An inline calibration method for a memory test apparatus

Abstract

The present application relates to the technical field of memory calibration, and specifically discloses an inline calibration method for a memory test device, comprising the following steps: in the initialization stage of a test program, defining a calibration object, a calibration trigger condition, and establishing a calibration parameter table in the memory, the calibration parameter table being used for storing the latest calibration value of each test parameter; the test machine tests the memory device according to a normal test flow; in the idle gap or specific node of the test flow, whether the calibration trigger condition is satisfied is monitored in real time, if not, the normal test flow is continued to be executed; if yes, the calibration flow is entered; the calibration subprogram is automatically called by the test program to perform calibration; the next or next batch of memory devices are continued to be executed by the test flow by using the updated calibration parameter. The present application does not need to interrupt production, avoids the long downtime of traditional offline calibration, and greatly improves the utilization rate of the test device and the production efficiency.

Description

Technical Field

[0001] This invention relates to the field of memory calibration technology, and more specifically to an inline calibration method for memory testing equipment. Background Technology

[0002] In large-scale production testing of semiconductor memories, automated test equipment (ATE) needs to apply precise power supply voltage, reference voltage, timing signals (such as clock cycle, setup / hold time), and input signal voltages (VIH / VIL) to the memory devices (DUTs). Due to thermal drift and aging of components within the AAE, as well as changes in the testing environment (such as temperature), these test parameters can drift slightly over time. Without intervention, this drift can lead to inaccurate test results, resulting in misclassification (classifying good products as defective) or missed classification (classifying defective products as good), causing losses in both yield and quality.

[0003] Traditional calibration methods are typically "offline calibration," which involves periodically shutting down the testing machine and using high-precision external instruments (such as digital multimeters and oscilloscopes) to measure and calibrate various parameters of the test channels. However, this existing technology requires stopping the test, reinstalling and reinstalling pin clips, and flipping the test head, with each shutdown calibration taking more than 8 hours, reducing equipment utilization and production efficiency; furthermore, it cannot respond in real time to changes in the internal state of the testing machine (such as thermal drift). Therefore, there is an urgent need for an online calibration method that can be performed seamlessly during the testing process without interrupting the testing flow. Summary of the Invention

[0004] The purpose of this invention is to provide an inline calibration method for a memory testing device to solve the above-mentioned technical problems.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] An inline calibration method for a memory testing device includes the following steps:

[0007] S1: Calibration strategy configuration: During the test program initialization phase, define the calibration object and calibration trigger conditions, and establish a calibration parameter table in memory. The calibration parameter table is used to store the latest calibration values ​​of each test parameter.

[0008] S2: Execute the test procedure: The test machine tests the memory device according to the normal test procedure;

[0009] S3: Calibration Trigger Judgment: During idle intervals or specific nodes in the test process, monitor in real time whether the calibration trigger condition is met. If not, return to S2 to continue the normal test process; if yes, proceed to the S4 calibration process.

[0010] S4: Inline calibration execution: The test program automatically calls the calibration subroutine to perform calibration;

[0011] S5: Seamlessly continue testing: Using the updated calibration parameters, return to S2 to continue the test process for the next or next batch of memory devices.

[0012] As a further aspect of the present invention: In step S4, the test program automatically calls the calibration subroutine to perform the following operations:

[0013] S4.1: Channel switching: The test channel to be calibrated is switched from the state of being connected to the memory device to the state of being connected to the internal measurement unit of the test machine through the switch matrix inside the test machine;

[0014] S4.2: Parameter Measurement: The tester controls its signal generation unit to apply the target excitation signal to the channel, and at the same time, it samples and measures the actual output signal of the channel through the internal measurement unit to obtain the actual measured value of the parameter being measured.

[0015] S4.3: Error Calculation and Compensation: Compare the actual measured value obtained in step S4.2 with the preset target standard value, calculate the error value Δ = actual value - target value, calculate the compensation value based on the error value, compensation value = -Δ × compensation coefficient, and update and compensate the corresponding parameter configuration of the channel in real time;

[0016] S4.4: Update the calibration parameter table: Update the calibration parameter table with the latest calculated compensation value or the calibrated parameter value;

[0017] S4.5: Channel Recovery: After calibration is complete, switch the test channel from the state of being connected to the measurement unit back to the state of being connected to the memory device.

[0018] As a further aspect of the present invention: the calibration object in step S1 includes one or more of the following: power supply voltage Vdd, input high level VIH, input low level VIL, offset error, and gain error.

[0019] As a further aspect of the present invention: the calibration triggering conditions in step S1 include one or more of periodic triggering, time triggering, temperature change triggering, or statistical triggering based on test results; the periodic triggering is triggered after every N devices are tested, the time triggering is triggered every time interval T, the temperature change triggering is triggered when the temperature change of the test environment exceeds ΔT, and the statistical triggering based on test results is triggered when abnormal test results occur continuously, where N is the preset number of tests, T is the preset interval time, and ΔT is the preset temperature change value.

[0020] As a further aspect of the present invention: a specific node in the test process in step S3 includes changing the test Lot or Wafer.

[0021] As a further aspect of the present invention: after applying the target excitation signal in step S4.2, compensation-related parameters are calculated using offset compensation or offset plus gain compensation, wherein:

[0022] Offset compensation only: Set the excitation signal to Vi1, the actual measured value to Vo1, and calculate the offset error Offset using the formula Offset=Vo1-Vi1;

[0023] Offset plus gain compensation is used: set the excitation signals as Vi1 and Vi2, and the corresponding actual measured values ​​are Vo1 and Vo2 respectively. The gain Gain is calculated by the formula Gain=(Vo2-Vo1) / (Vi2-Vi1), and the offset error Offset is calculated by the formula Offset=Vo1-(Vo2-Vo1) / (Vi2-Vi1)×Vi1.

[0024] As a further aspect of the present invention: in steps S4.2 and S4.3, when calibrating multiple test parameters, a time-division multiplexing method is used to measure and compensate each parameter sequentially.

[0025] As a further aspect of the present invention, the compensation coefficient is obtained in advance based on the hardware characteristics of the testing machine and historical calibration data.

[0026] The beneficial effects of this invention are as follows: The calibration process is embedded in the idle gaps of the test process or when changing Lot / Wafer nodes, without interrupting production, avoiding the long downtime of traditional offline calibration, and greatly improving the utilization rate of test equipment and production efficiency; it can respond in real time to changes in the internal state of the test machine (such as thermal drift) and fluctuations in ambient temperature, and immediately perform calibration when the trigger conditions are met, compensating for parameter deviations in real time, and ensuring the accuracy of test yield from the source; it supports two methods: offset compensation alone or offset + gain combined compensation, which can be flexibly selected according to test requirements, and accurately eliminates errors caused by parameter drift. Attached Figure Description

[0027] The invention will now be further described with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of the overall process of an inline calibration method for a memory testing device according to the present invention;

[0029] Figure 2 This is a schematic diagram of test channel switching in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Please see Figure 1 As shown, the present invention provides an inline calibration method for a memory testing device, the method comprising the following steps:

[0032] S1: Calibration Strategy Configuration: Define the following during the test program initialization phase:

[0033] Calibration target: Determine the test parameters that need to be calibrated, including but not limited to power supply voltage Vdd, input high / low level VIH / VIL, offset / gain error, etc.

[0034] Calibration trigger conditions: Set the event that triggers calibration, including periodic trigger (after testing N devices), time trigger (every time interval T), temperature change trigger (when the test environment temperature changes by more than ΔT), or statistical trigger based on test results (such as consecutive abnormal test results).

[0035] Calibration parameter table: A calibration parameter table is created in memory to store the latest calibration values ​​of each test parameter.

[0036] S2: Execute the test procedure: The test machine tests the memory device according to the normal test procedure.

[0037] S3: Calibration Trigger Judgment: During idle intervals or specific nodes in the test process (such as when changing test Lots or Wafers; specific nodes can be selected when changing several Lots or Wafers, as Prober takes some time when changing Lots, which can be used for Inline calibration to avoid affecting overall test efficiency), monitor in real time whether the calibration trigger condition is met. If not, continue with the normal test process (return to S2); if yes, proceed to the next calibration step.

[0038] S4: Inline Calibration Execution: Once the triggering condition is met, the test program automatically calls the calibration subroutine to perform the following operations:

[0039] S4.1: Channel Switching: The test channel to be calibrated is switched from the state of being connected to the memory device (DUT) to the state of being connected to the measurement unit inside the test machine via the switch matrix inside the test machine.

[0040] S4.2: Parameter Measurement: The tester controls its signal generation unit to apply the target excitation signal to the channel, and at the same time uses its internal measurement unit to sample and measure the actual output signal of the channel to obtain the actual measured value of the parameter being measured (such as the actual voltage value and the actual time value).

[0041] Applying an excitation essentially involves applying a theoretical value, then using a measurement unit to verify the deviation between the actual and theoretical values, thereby calculating the compensation coefficient. Compensation can be performed using only Offset compensation, or a combination of Offset and GainError compensation can be used.

[0042] Using only the Offset algorithm, the following is true:

[0043] The excitation signal is set to Vi1, and the actual measurement is Vo1;

[0044] Vi1 + Offset = Vo1;

[0045] Then Offset = Vo1 - Vi1.

[0046] The offset plus gain compensation algorithm is as follows:

[0047] The excitation signal is set to Vi1, and the actual measurement is Vo1;

[0048] The excitation signal is set to Vi2, and the actual measurement is Vo2;

[0049] Vi1*Gain+Offset=Vo1;

[0050] Vi2*Gain+Offset=Vo2;

[0051] From the above two equations, we get:

[0052] Then Gain = (Vo2 - Vo1) / (Vi2 - Vi1);

[0053] Offset=Vo1-(Vo2-Vo1) / (Vi2-Vi1)*Vi1.

[0054] S4.3: Error Calculation and Compensation: Compare the actual measured value obtained in step S4.2 with the preset target standard value, and calculate the error value (Δ = actual value - target value). Based on this error value, calculate the compensation value (compensation value = -Δ × compensation coefficient), and update and compensate the corresponding parameter configuration of the channel in real time.

[0055] S4.4: Update the calibration parameter table: Update the calculated latest compensation value or calibrated parameter value to the calibration parameter table.

[0056] S4.5: Channel Recovery: After calibration is complete, switch the test channel from the state of being connected to the measurement unit back to the state of being connected to the memory DUT.

[0057] S5: Seamlessly continue testing: Using the updated calibration parameters, continue the test process for the next or next batch of memory devices (return to S2) without pausing the test machine.

[0058] In steps S4.2 and S4.3, when calibrating multiple test parameters, a time-division multiplexing method is used to measure and compensate each parameter sequentially.

[0059] The compensation coefficient is pre-calibrated based on the hardware characteristics of the testing machine and historical calibration data to achieve optimal closed-loop control performance.

[0060] The method also includes a calibration recording and traceability step: the time, channel, parameters, error value, and compensation value of each calibration are recorded in a log file for subsequent statistical analysis, equipment health status monitoring, and fault diagnosis.

[0061] Taking the calibration of the VDD power supply voltage on a certain type of DRAM tester as an example:

[0062] S1: Calibration strategy configuration:

[0063] Calibration target: VDD Power Supply (DR chip power supply voltage), target standard value is 1.2V.

[0064] Triggering condition: Calibration is triggered once after every 500 devices are tested.

[0065] Initialize the calibration parameter table, and set the initial calibration value of VDD to 1.2V.

[0066] S2: Execute the test procedure: The test machine normally tests the DRAM device.

[0067] S3: Calibration trigger judgment: The test counter shows that 500 Wafers have been tested, and the trigger condition is met.

[0068] S4: Inline calibration execution:

[0069] S4.1: Channel Switching: The Zdown pin card disconnects the VDD channel that powers the DUT from the DUT end, controls the switch matrix, and connects to the high-precision ADC (DMM) measurement terminal inside the test machine.

[0070] S4.2: Parameter Measurement: The tester commands the power supply unit to output a voltage of 1.2V, and measures the actual voltage value on this channel through the internal DMM, which is 1.198V.

[0071] S4.3: Error Calculation and Compensation:

[0072] Error ΔV = 1.198V - 1.200V = -0.002V;

[0073] Calculate the compensation value: The compensation coefficient is pre-calibrated to 1.0 (i.e., direct compensation error), then the new voltage setting value = original setting value - ΔV = 1.2V - (-0.002V) = 1.202V. The power supply unit of the test machine updates the output voltage setting value of this channel to 1.202V.

[0074] S4.4: Update calibration parameter table: Update the calibration value of VDD to 1.202V.

[0075] S4.5: Channel Restoration: Switch the VDD channel back and reconnect it to the DUT under test.

[0076] S5: Zup pin, seamless continuation of testing: Testing begins on the 501st wafer, at which point the VDD voltage it obtains is a calibrated voltage closer to the accurate 1.2V (approximately 1.200V). Testing continues in cycles S2-S5.

[0077] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. An inline calibration method for a memory testing device, characterized in that, Includes the following steps: S1: Calibration strategy configuration: During the test program initialization phase, define the calibration object and calibration trigger conditions, and establish a calibration parameter table in memory. The calibration parameter table is used to store the latest calibration values ​​of each test parameter. S2: Execute the test procedure: The test machine tests the memory device according to the normal test procedure; S3: Calibration Trigger Judgment: During idle intervals or specific nodes in the test process, monitor in real time whether the calibration trigger condition is met. If not, return to S2 to continue the normal test process; if yes, proceed to the S4 calibration process. S4: Inline calibration execution: The test program automatically calls the calibration subroutine to perform calibration; S5: Seamlessly continue testing: Using the updated calibration parameters, return to S2 to continue the test process for the next or next batch of memory devices; In step S4, the test program automatically calls the calibration subroutine to perform the following operations: S4.1: Channel switching: The test channel to be calibrated is switched from the state of being connected to the memory device to the state of being connected to the internal measurement unit of the test machine through the switch matrix inside the test machine; S4.2: Parameter Measurement: The tester controls its signal generation unit to apply the target excitation signal to the channel, and at the same time, it samples and measures the actual output signal of the channel through the internal measurement unit to obtain the actual measured value of the parameter being measured. S4.3: Error Calculation and Compensation: Compare the actual measured value obtained in step S4.2 with the preset target standard value, calculate the error value Δ = actual value - target value, calculate the compensation value based on the error value, compensation value = -Δ × compensation coefficient, and update and compensate the corresponding parameter configuration of the channel in real time; S4.4: Update the calibration parameter table: Update the calibration parameter table with the latest calculated compensation value or the calibrated parameter value; S4.5: Channel Recovery: After calibration is complete, switch the test channel from the state of being connected to the measurement unit back to the state of being connected to the memory device.

2. The inline calibration method for a memory testing device according to claim 1, characterized in that, The calibration objects in step S1 include one or more of the following: power supply voltage Vdd, input high level VIH, input low level VIL, offset error, and gain error.

3. The inline calibration method for a memory testing device according to claim 1, characterized in that, The calibration triggering conditions in step S1 include one or more of the following: periodic triggering, time triggering, temperature change triggering, or statistical triggering based on test results; the periodic triggering is triggered after every N devices are tested, the time triggering is triggered every time interval T, the temperature change triggering is triggered when the temperature change of the test environment exceeds ΔT, and the statistical triggering based on test results is triggered when abnormal test results occur consecutively, where N is the preset number of tests, T is the preset interval time, and ΔT is the preset temperature change value.

4. The inline calibration method for a memory testing device according to claim 1, characterized in that, Specific nodes in the testing process in step S3 include when changing the test lot or wafer.

5. The inline calibration method for a memory testing device according to claim 1, characterized in that, In step S4.2, after applying the target excitation signal, the compensation-related parameters are calculated using offset compensation or offset plus gain compensation, wherein: Offset compensation only: Set the excitation signal to Vi1, the actual measured value to Vo1, and calculate the offset error Offset using the formula Offset=Vo1-Vi1; Offset plus gain compensation is used: set the excitation signals as Vi1 and Vi2, and the corresponding actual measured values ​​are Vo1 and Vo2 respectively. The gain Gain is calculated by the formula Gain=(Vo2-Vo1) / (Vi2-Vi1), and the offset error Offset is calculated by the formula Offset=Vo1-(Vo2-Vo1) / (Vi2-Vi1)×Vi1.

6. The inline calibration method for a memory testing device according to claim 2, characterized in that, In steps S4.2 and S4.3, when calibrating multiple test parameters, a time-division multiplexing method is used to measure and compensate each parameter sequentially.

7. The inline calibration method for a memory testing device according to claim 2, characterized in that, The compensation coefficient is obtained in advance based on the hardware characteristics of the testing machine and historical calibration data.

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