An eye diagram calibration method and system

Abstract

This invention relates to the field of communication signal or integrated circuit manufacturing technology, and discloses an eye diagram calibration method and system, comprising: calculating a clock phase adjustment and a voltage threshold adjustment based on offset information; setting a clock phase compensation value and a voltage threshold compensation value based on the clock phase adjustment and voltage threshold adjustment respectively; correcting the clock phase of a clock generation module based on the clock phase compensation value to obtain a corrected clock phase; correcting the voltage threshold of a DAC module based on the voltage threshold compensation value to obtain a corrected voltage threshold; sampling a data signal based on the corrected clock phase and the corrected voltage threshold to obtain D-channel data; determining whether the eye diagram calibration has converged; if not converged, updating the offset information using the D-channel data and recalculating the clock phase adjustment and voltage threshold adjustment; if converged, completing the eye diagram calibration. This invention can improve the feedback calibration and adjustment capability of eye diagrams.

Description

Technical Field

[0001] This invention relates to the field of communication signal or integrated circuit manufacturing technology, and in particular to an eye diagram calibration method and system. Background Technology

[0002] In the field of integrated circuit manufacturing and testing, the performance of signal recovery and sampling is crucial. In traditional signal processing architectures, signal recovery and sampling mainly rely on two core modules: equalization algorithms (such as Continuous Time Linear Equalization (CTLE) and Decision Feedback Equalization (DFE)) and Clock Data Recovery (CDR) circuits. No specific calibration algorithm is designed for the eye diagram center position. However, in real-world applications, systems are susceptible to eye diagram shifts due to multiple interferences, ultimately leading to insufficient eye diagram center stability in traditional signal transmission systems and affecting data transmission bit error rate performance.

[0003] The invention with publication number CN116775389A, entitled "Testing Device, Signal Eye Diagram Calibration System and Method," is the closest prior art to this invention. However, this invention does not disclose a method for eliminating signal offset in the signal eye diagram calibration system. Traditional eye-scanning systems operate by using the eye diagram center sampling point as a reference center, precisely adjusting the sampling clock phase and decision threshold voltage, and scanning the signal state point by point to obtain overall eye diagram information. However, traditional eye-scanning systems have not yet established a closed-loop feedback adjustment mechanism; they can only detect the eye diagram opening during the testing phase, and cannot generate and extract eye diagram offset information. They also lack the ability to actively calibrate the eye diagram center position. Therefore, current eye diagram calibration methods suffer from an imperfect calibration feedback adjustment mechanism. Summary of the Invention

[0004] This invention provides an eye diagram calibration method and system, the main purpose of which is to improve the feedback calibration and adjustment capability of the eye diagram.

[0005] To achieve the above objectives, the present invention provides an eye diagram calibration method, comprising:

[0006] The preset receiver signal is scanned using a pre-built eye diagram scanning module to obtain offset information;

[0007] The clock phase adjustment and voltage threshold adjustment are calculated based on the offset information. The clock phase adjustment includes the adjustment magnitude and direction of the clock phase, and the voltage threshold adjustment includes the adjustment magnitude and direction of the voltage threshold.

[0008] The clock phase compensation value and the voltage threshold compensation value are set according to the clock phase adjustment amount and the voltage threshold adjustment amount, respectively, wherein the clock phase compensation value is Trim Code_CDR and the voltage threshold compensation value is Trim Code_DAC;

[0009] The clock phase of the pre-built clock generation module is corrected according to the clock phase compensation value to obtain the corrected clock phase; the voltage threshold of the pre-built DAC module is corrected according to the voltage threshold compensation value to obtain the corrected voltage threshold.

[0010] The data signal processed by the equalization circuit is acquired, and the data signal is sampled according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data.

[0011] Based on the D-path data, determine whether the preset eye diagram calibration has converged;

[0012] If the eye diagram calibration fails to converge, the offset information is updated using the D-path data, and the steps described above for calculating the clock phase adjustment and voltage threshold adjustment based on the offset information are returned.

[0013] If the eye diagram calibration converges, the eye diagram calibration is complete.

[0014] Optionally, the step of scanning a preset receiving signal using a pre-built eye diagram scanning module to obtain offset information includes:

[0015] The eye diagram scanning module is used to scan the receiver signal to obtain the current scanned eye diagram;

[0016] Offset information is extracted from the current scanned eye diagram. The offset information includes: signal clock phase and signal voltage threshold.

[0017] Optionally, calculating the clock phase adjustment and voltage threshold adjustment based on the offset information includes:

[0018] Identify the horizontal offset position of the eye diagram in the offset information, and determine the extreme offset positions of the left and right halves of the eye based on the horizontal offset position of the eye diagram.

[0019] Identify the vertical offset position of the eye diagram in the offset information, and determine the upper half-eye limit offset position and the lower half-eye limit offset position based on the vertical offset position of the eye diagram.

[0020] Calculate the clock phase adjustment amount based on the left and right hemi-eye extreme offset positions;

[0021] The voltage threshold adjustment amount is calculated based on the upper half-eye limit offset position and the lower half-eye limit offset position.

[0022] Optionally, calculating the clock phase adjustment based on the left and right hemi-eye extreme offset positions includes:

[0023] The extreme offset of the left and right eyes is determined based on the extreme offset positions of the left and right eyes, respectively.

[0024] The clock phase sampling boundary is adjusted based on the left and right half-eye limit offsets to obtain a horizontally calibrated eye diagram.

[0025] Identify the clock phase adjustment amount of the horizontal calibration eye diagram.

[0026] Optionally, the step of calculating the voltage threshold adjustment based on the upper half-eye limit offset position and the lower half-eye limit offset position includes:

[0027] The extreme offset of the upper eye and the extreme offset of the lower eye are determined based on the extreme offset positions of the upper and lower eye respectively.

[0028] The voltage threshold is adjusted based on the upper half-eye limit offset and the lower half-eye limit offset to obtain a vertically calibrated eye diagram;

[0029] Identify the voltage threshold adjustment amount of the vertical calibration eye diagram.

[0030] Optionally, setting the clock phase compensation value and the voltage threshold compensation value according to the clock phase adjustment amount and the voltage threshold adjustment amount respectively includes:

[0031] The calibration algorithm module built into the pre-built eye diagram calibration algorithm module identifies the clock phase compensation value and voltage threshold compensation value based on the clock phase adjustment amount and voltage threshold adjustment amount. The calibration algorithm module identifies the clock phase compensation value and voltage threshold compensation value based on the clock phase adjustment amount and voltage threshold adjustment amount and uses the pre-built code mapping relationship.

[0032] Optionally, the step of sampling the data signal according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data includes:

[0033] A sampling voltage threshold is generated in a pre-built DAC module based on a corrected voltage threshold in the DAC calibration module. The corrected voltage threshold is used to adjust the comparison threshold level of the decision unit in the data recovery module.

[0034] The sampled clock phase is generated in the pre-built clock generation module based on the corrected clock phase in the CDR module;

[0035] Using the data recovery module, the data signal is sampled according to the sampling voltage threshold and the sampling clock phase to obtain D-channel data.

[0036] Optionally, determining whether the preset eye diagram calibration has converged based on the D-path data includes:

[0037] Based on the D-channel data and the preset O-channel data, the left limit offset code, right limit offset code, upper limit offset code and lower limit offset code are identified;

[0038] Determine whether the left limit offset code and the upper limit offset are equal to the right limit offset code and the lower limit offset, respectively;

[0039] If the left limit offset code and the upper limit offset are not equal to the right limit offset code and the lower limit offset, respectively, then the eye diagram calibration has not converged.

[0040] If the left limit offset code and the upper limit offset are equal to the right limit offset code and the lower limit offset, respectively, then the eye diagram calibration converges.

[0041] The eye diagram calibration determination process involves implementing clock phase correction and voltage threshold correction through Trim Code_CDR and Trim Code_DAC, respectively. The D-channel data is adjusted according to the clock phase correction and voltage threshold correction. By comparing the adjusted D-channel data with the preset O-channel data, it is determined whether the left limit offset code and the right limit offset code are equal, and whether the upper limit offset code and the lower limit offset code are equal. If the limit offset code and the right limit offset code are equal, and the upper limit offset code and the lower limit offset code are equal, then the eye diagram calibration converges.

[0042] Optionally, the clock phase compensation value is used to adjust the correction code of the CDR module, thereby adjusting the clock phase of the clock generation module. The voltage threshold compensation value is used to adjust the correction code of the DAC calibration module, thereby adjusting the voltage threshold of the DAC module.

[0043] To achieve the above objectives, the present invention also provides an eye diagram calibration system, comprising:

[0044] The offset information acquisition module is used to scan the preset receiving end signal using a pre-built eye diagram scanning module to obtain offset information;

[0045] A phase voltage compensation value setting module is used to calculate a clock phase adjustment amount and a voltage threshold adjustment amount based on the offset information. The clock phase adjustment amount includes the adjustment amplitude and adjustment direction of the clock phase, and the voltage threshold adjustment amount includes the adjustment amplitude and adjustment direction of the voltage threshold. The module sets a clock phase compensation value and a voltage threshold compensation value based on the clock phase adjustment amount and the voltage threshold adjustment amount, respectively. The clock phase compensation value is Trim Code_CDR, and the voltage threshold compensation value is Trim Code_DAC.

[0046] The phase voltage correction module is used to correct the clock phase of the pre-built clock generation module according to the clock phase compensation value to obtain the corrected clock phase, and to correct the voltage threshold of the pre-built DAC module according to the voltage threshold compensation value to obtain the corrected voltage threshold.

[0047] The eye diagram calibration convergence judgment module is used to acquire the data signal after processing by the equalization circuit, sample the data signal according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data; determine whether the preset eye diagram calibration has converged based on the D-channel data; if the eye diagram calibration has not converged, update the offset information using the D-channel data and return to the steps of calculating the clock phase adjustment and voltage threshold adjustment based on the offset information; if the eye diagram calibration has converged, the eye diagram calibration is completed.

[0048] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0049] A memory that stores at least one instruction; and a processor that executes the instructions stored in the memory to implement the eye diagram calibration method described above.

[0050] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the eye diagram calibration method described above.

[0051] To address the problems described in the background art, this invention first requires clock phase correction and voltage threshold correction to the clock generation module and DAC module respectively based on offset information. Then, the corrected data signals from the clock generation module and DAC module are used for signal sampling to obtain D-channel data. The D-channel data is then used to determine whether the preset eye diagram calibration has converged. When obtaining offset information, the receiving end signal needs to be scanned using an eye diagram scanning module. Before performing clock phase correction and voltage threshold correction on the clock generation module and DAC module respectively, the clock phase adjustment amount and voltage threshold adjustment amount need to be calculated based on the offset information. The clock phase adjustment amount includes the adjustment amplitude and direction of the clock phase, and the voltage threshold adjustment amount includes the adjustment amplitude and direction of the voltage threshold. At this point, clock phase compensation values ​​and voltage threshold compensation values ​​can be set according to the clock phase adjustment amount and voltage threshold adjustment amount respectively. The clock phase compensation value is Trim Code_CDR, and the voltage threshold compensation value is Trim Code_CDR. When the clock phase compensation value and voltage threshold compensation value are obtained, the clock generation module can be corrected based on the clock phase compensation value to obtain a corrected clock phase. Simultaneously, the DAC module can be corrected based on the voltage threshold compensation value to obtain a corrected voltage threshold. At this point, the data signal processed by the equalization circuit can be acquired. Then, the data signal is sampled based on the corrected clock phase and corrected voltage threshold to obtain D-channel data. The convergence of the eye diagram calibration can be determined based on the D-channel data. If the eye diagram calibration has not converged, the offset information is updated using the D-channel data, and a new clock phase adjustment and voltage threshold adjustment are recalculated based on the offset information. If the eye diagram calibration has converged, the eye diagram calibration is complete. Therefore, this invention can improve the feedback calibration adjustment capability of the eye diagram. Attached Figure Description

[0052] Figure 1 This is a schematic flowchart of an eye diagram calibration method provided in an embodiment of the present invention;

[0053] Figure 2 This is an overall structural diagram of analog and digital circuits provided in an embodiment of the present invention;

[0054] Figure 3 This is a horizontal offset eye diagram provided in an embodiment of the present invention;

[0055] Figure 4 This is a vertical offset eye diagram provided in an embodiment of the present invention;

[0056] Figure 5 This is an eye diagram after eye diagram algorithm calibration provided in an embodiment of the present invention;

[0057] Figure 6 This is a flowchart of the eye diagram calibration algorithm provided in an embodiment of the present invention;

[0058] Figure 7 This is a functional block diagram of an eye diagram calibration system provided in an embodiment of the present invention;

[0059] Figure 8 This is a schematic diagram of the structure of an electronic device for implementing the eye diagram calibration method according to an embodiment of the present invention.

[0060] Explanation of reference numerals in the attached figures:

[0061] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0062] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0063] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0064] This application provides an eye diagram calibration method. The execution entity of the eye diagram calibration method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the eye diagram calibration method can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0065] Reference Figure 1 The diagram shown is a schematic flowchart of an eye diagram calibration method provided in an embodiment of the present invention. In this embodiment, the eye diagram calibration method includes:

[0066] S1. Use the pre-built eye diagram scanning module to scan the preset receiver signal to obtain offset information.

[0067] Understandably, the Eye Diagram scan module refers to the module that scans and analyzes the received signal to obtain and generate corresponding eye diagram offset information. (See also...) Figure 2As shown, the eye diagram scanning module receives offset data output from the analog circuit, calculates the bit error rate using this offset data, and thus determines the horizontal and vertical limit offset positions to obtain the eye diagram offset information. Finally, the offset information is output to the calibration algorithm module in the Eye Calibration Module for processing. The eye diagram scanning module can scan the received signal under different sampling phases and voltage thresholds and extract key parameters reflecting signal quality, thereby providing a basis for subsequent clock phase and voltage threshold calibration. The eye diagram calibration algorithm module includes an eye diagram scanning module and a calibration algorithm module. The received signal refers to the signal received by the eye diagram scanning module from the analog circuit. The offset information refers to the maximum offset of the eye diagram in the horizontal and vertical directions, and mainly includes the boundary information of the eye diagram.

[0068] Explainable, the eye diagram is a core test pattern in the field of communications that provides an intuitive and quantitative assessment of signal transmission quality. Its formation mechanism is through signal superposition. Multiple periodic digital signals collected by the receiving end (these periodic digital signals are randomly distorted due to factors such as additive noise, inter-symbol interference, clock offset, and channel attenuation during transmission) are superimposed in the time domain. Since the amplitude distribution of different periodic digital signals at the same symbol moment has statistical regularity, it will eventually present a pattern with an outline similar to the human eye.

[0069] Furthermore, the eye diagram includes key features such as the degree of eye opening (a larger opening indicates better signal quality), the eye crossover point (the symmetry of the eye crossover point reflects the clock synchronization accuracy), the thickness of the eyelid (related to the magnitude of noise), and the slope of the upper and lower edges. By observing and analyzing these features, problems such as inter-symbol interference, noise pollution, and clock synchronization deviation in the transmission system can be quickly located, thereby guiding equalizer parameter adjustment, channel optimization, clock circuit calibration, and other work, ultimately ensuring the reliable transmission of digital signals.

[0070] Further, see Figure 2 As shown, Figure 2The system includes analog and digital circuits. The analog circuits include: an equalization circuit, a DAC (Digital-to-Analog Converter) module, a clock generator (CLKGEN), a data recovery module (Slicer), and a serial-in-parallel-out (SIPO) conversion module. The equalization circuits include: a continuous-time linear equalizer (CTLE) and a decision feedback equalizer (DFE). The digital circuits include: a DAC calibration module, a clock data recovery (CRD) module, and an eye diagram calibration algorithm module.

[0071] In detail, the digital circuit calibrates and optimizes the quality of the transmitted signal through algorithm design. The eye diagram calibration algorithm module in the digital circuit can generate a Trim Code. The Trim Code is transmitted to the analog circuit through the digital circuit and adjusts the key circuits in the analog circuit, thereby achieving precise center calibration of the eye diagram.

[0072] In this embodiment of the invention, the step of scanning a preset receiving signal using a pre-constructed eye diagram scanning module to obtain offset information includes:

[0073] The eye diagram scanning module is used to scan the receiver signal to obtain the current scanned eye diagram;

[0074] Offset information is extracted from the current scanned eye diagram. The offset information includes: signal clock phase and signal voltage threshold.

[0075] Explained, the current scanned eye diagram refers to the scanned eye diagram of the receiving end signal obtained after sampling the data signal under the current signal clock phase and signal voltage threshold.

[0076] Understandably, the eye diagram scanning module can determine the limit offset, which is bit offset information. This bit offset information mainly includes time offset information and voltage offset information. The time offset information represents the adjustable limit range of the sampling clock phase, corresponding to the horizontal opening width of the eye diagram, i.e., the maximum sampling deviation the system can tolerate in the time domain. The voltage offset information represents the adjustable limit range of the receiver decision level (i.e., the voltage threshold), corresponding to the vertical opening height of the eye diagram, i.e., the range of variation the system can tolerate in the voltage domain. See also... Figure 2As shown, the offset information is input into the eye diagram calibration algorithm module. The eye diagram calibration algorithm module calculates the Trim Code based on the mapping relationship between the clock phase offset, voltage threshold offset, voltage threshold, and clock phase change. Before scanning the receiver signal, the system needs to be powered on or reset. Then the algorithm starts running, initializing relevant registers, control signals, and module states to prepare for the subsequent calibration process.

[0077] Furthermore, when reading offset information, the system scans the clock phase and voltage threshold of the receiving signal through the eye diagram scanning module to obtain bit error rate or data stability information under different sampling conditions. The result output by the eye diagram scanning module is used to determine the offset information of the current eye diagram (including the opening size, vertical and horizontal offset). The offset information is the basic input of the entire algorithm and determines the subsequent calibration direction.

[0078] S2. Calculate the clock phase adjustment amount and voltage threshold adjustment amount based on the offset information. The clock phase adjustment amount includes the adjustment magnitude and adjustment direction of the clock phase. The voltage threshold adjustment amount includes the adjustment magnitude and adjustment direction of the voltage threshold.

[0079] Specifically, the clock phase adjustment amount refers to the adjustment parameter of the clock phase when sampling the data signal, and the voltage threshold adjustment amount refers to the adjustment parameter of the voltage threshold when sampling the data signal. The clock phase adjustment magnitude refers to the adjustment size of the clock phase, and the clock phase adjustment direction refers to the direction of movement of the clock phase, which includes: moving forward (advancing) and moving backward (delaying). The voltage threshold adjustment magnitude refers to the adjustment size of the voltage threshold, and the voltage threshold adjustment direction refers to the adjustment direction of the voltage threshold, which includes: increasing the voltage threshold and decreasing the voltage threshold.

[0080] In this embodiment of the invention, calculating the clock phase adjustment and voltage threshold adjustment based on the offset information includes:

[0081] Identify the horizontal offset position of the eye diagram in the offset information, and determine the extreme offset positions of the left and right halves of the eye based on the horizontal offset position of the eye diagram.

[0082] Identify the vertical offset position of the eye diagram in the offset information, and determine the upper half-eye limit offset position and the lower half-eye limit offset position based on the vertical offset position of the eye diagram.

[0083] Calculate the clock phase adjustment amount based on the left and right hemi-eye extreme offset positions;

[0084] The voltage threshold adjustment amount is calculated based on the upper half-eye limit offset position and the lower half-eye limit offset position.

[0085] Furthermore, the horizontal offset position of the eye diagram refers to the extreme offset position of the eye diagram in the horizontal direction, the extreme offset position of the left half of the eye diagram refers to the extreme offset position of the left half of the eye diagram, the extreme offset position of the right half of the eye diagram refers to the extreme offset position of the right half of the eye diagram, the vertical offset position of the eye diagram refers to the extreme offset position of the eye diagram in the vertical direction, the extreme offset position of the upper half of the eye diagram refers to the extreme offset position of the upper half of the eye diagram, and the extreme offset position of the lower half of the eye diagram refers to the extreme offset position of the lower half of the eye diagram.

[0086] In this embodiment of the invention, calculating the clock phase adjustment based on the left hemi-eye limit offset position and the right hemi-eye limit offset position includes:

[0087] The extreme offset of the left and right eyes is determined based on the extreme offset positions of the left and right eyes, respectively.

[0088] The clock phase sampling boundary is adjusted based on the left and right half-eye limit offsets to obtain a horizontally calibrated eye diagram.

[0089] Identify the clock phase adjustment amount of the horizontal calibration eye diagram.

[0090] Further, the left half-eye limit offset refers to the clock phase limit offset of the left half of the eye diagram. The right half-eye limit offset refers to the clock phase limit offset of the right half of the eye diagram. The clock phase sampling boundary refers to the eye diagram boundary representing the clock phase. The horizontally calibrated eye diagram refers to the eye diagram after horizontal adjustment.

[0091] In detail, during the operation of the calibration algorithm module, the O-channel data (i.e., the biased data) needs to be biased, and combined with the logic calculation and eye diagram scanning functions of the serial-to-parallel conversion module (SIPO), the sampling status of the data signal can be detected in real time. If the calibration algorithm module is not enabled in the system, please refer to [link to documentation]. Figure 3 As shown, the eye diagram of D-channel data (i.e., normal data) may exhibit horizontal offset, meaning the left and right openings are asymmetrical. When this occurs (where is the left half-eye limit offset, is the right half-eye limit offset, and and both represent the horizontal limit offset), the left half of the eye diagram is smaller, indicating that the current CDR module has a deviation in adjusting the clock phase for sampling D-channel data. In this case, the calibration algorithm module needs to intervene to correct it. When the calibration algorithm module receives and , it will dynamically adjust the eye diagram sampling boundary according to the left and right half-eye limit offsets, thereby increasing the left boundary of the eye diagram and decreasing the right boundary of the eye diagram. Ultimately, this changes the position of the sampling clock center, causing the sampling clock phase to shift to the right, achieving the purpose of horizontal eye diagram calibration and restoring the optimal sampling window position.

[0092] Furthermore, the serial-to-parallel conversion module (SIPO) is used to convert serial data into parallel data and output the parallel data, which is then input into the eye diagram scan module to calculate the bit error rate and offset information.

[0093] In this embodiment of the invention, calculating the voltage threshold adjustment based on the upper half-eye limit offset position and the lower half-eye limit offset position includes:

[0094] The extreme offset of the upper eye and the extreme offset of the lower eye are determined based on the extreme offset positions of the upper and lower eye respectively.

[0095] The voltage threshold is adjusted based on the upper half-eye limit offset and the lower half-eye limit offset to obtain a vertically calibrated eye diagram;

[0096] Identify the voltage threshold adjustment amount of the vertical calibration eye diagram.

[0097] Furthermore, the upper half-eye limit offset refers to the voltage threshold offset of the upper half of the eye diagram, the lower half-eye limit offset refers to the voltage threshold offset of the lower half of the eye diagram, and the vertically calibrated eye diagram refers to the eye diagram after vertical adjustment.

[0098] In detail, in addition to horizontal calibration, the voltage threshold in the vertical direction also needs to be adjusted using a calibration algorithm module to ensure the stability of data decisions and minimize the bit error rate. See also... Figure 4 As shown, Figure 4 For an eye diagram with vertical offset, if the system does not enable the calibration algorithm module, when the situation occurs (the vertical offset limit), the upper half of the eye diagram is smaller, indicating that the current DAC module has an error in adjusting the sampled voltage threshold. During the calibration process, the calibration algorithm module will receive a small amount of information. At this time, the DAC module will receive the Trim Code_DAC generated by the calibration algorithm module. The Trim Code_DAC is used to dynamically adjust the comparison threshold level of the decision slicer. When the upper half of the eye diagram is smaller, the voltage threshold of the DAC module can be adjusted downward, that is, the center sampling point of the eye diagram is moved downward, thereby realizing the adaptive calibration of the vertical direction of the eye diagram.

[0099] The eye diagram calibration algorithm module of this invention uses multi-point limit offset information at the eye diagram edge position to accurately determine whether the sampling clock center is the center position of signal 1UI and whether the Slicer's decision threshold is accurate. This continuously adjusts the trim code in the horizontal and vertical directions of the eye diagram. The calibration algorithm module is a closed-loop calibration system that performs self-loop optimization between data detection, bit error feedback, and threshold adjustment until the sampling clock and decision threshold converge to the optimal state and the bit error rate meets the system requirements. (See also...) Figure 5 As shown, Figure 5 This is a schematic diagram of the calibrated eye diagram. At this time, the upper and lower boundaries of the eye diagram are equal ( ), the left and right boundaries are equal ( ), and the sampling point of the eye diagram is at the center position.

[0100] S3. Set the clock phase compensation value and voltage threshold compensation value according to the clock phase adjustment amount and voltage threshold adjustment amount respectively, wherein the clock phase compensation value is Trim Code_CDR and the voltage threshold compensation value is Trim Code_DAC.

[0101] Understandably, the clock phase compensation value refers to the configuration value used to adjust or calibrate the internal parameters of the clock generation module (CLKGEN), and the voltage threshold compensation value refers to the configuration value used to adjust or calibrate the internal parameters of the DAC module. The clock phase compensation value is used for clock phase adjustment of the CDR module; by adjusting the clock phase, eye diagram horizontal calibration is achieved. The voltage threshold compensation value is used for voltage threshold adjustment of the DAC module. Vertical calibration is achieved by adjusting the reference voltage of the data recovery module. The Trim Code is a digital compensation value calculated by an algorithm, used to drive the adjustment of the analog circuit.

[0102] In this embodiment of the invention, setting the clock phase compensation value and the voltage threshold compensation value according to the clock phase adjustment amount and the voltage threshold adjustment amount respectively includes:

[0103] The calibration algorithm module built into the pre-built eye diagram calibration algorithm module identifies the clock phase compensation value and voltage threshold compensation value based on the clock phase adjustment amount and voltage threshold adjustment amount. The calibration algorithm module identifies the clock phase compensation value and voltage threshold compensation value based on the clock phase adjustment amount and voltage threshold adjustment amount and uses the pre-built code mapping relationship.

[0104] Understandably, the calibration algorithm module can convert offset information into TrimCode based on the Code mapping relationship.

[0105] S4. Based on the clock phase compensation value, the clock phase of the pre-built clock generation module is corrected to obtain the corrected clock phase. Based on the voltage threshold compensation value, the voltage threshold of the pre-built DAC module is corrected to obtain the corrected voltage threshold.

[0106] Understandably, the clock generation module (CLKGEN) is used to control the horizontal offset of the eye diagram, see [link / reference]. Figure 2 As shown, the center sampling position of the clock phase is adjusted in real time by receiving the Code generated by the digital circuit, thereby calibrating the eye diagram center. The DAC module is used to control the vertical offset of the eye diagram. By receiving the Code generated by the digital circuit, it precisely adjusts the sampling voltage threshold of the data signal. This adjustment allows the DAC module to change the sampling position of the data signal on the vertical axis in real time, thereby effectively calibrating the position of the eye diagram center. The CDR module changes the sampling clock phase according to the clock phase compensation value to optimize the horizontal center of the eye diagram, and the DAC calibration module changes the voltage threshold according to the voltage threshold compensation value to optimize the vertical center of the eye diagram. The CDR module and the DAC calibration module work together in the data recovery module, ultimately affecting the data decision accuracy.

[0107] Specifically, the corrected clock phase refers to the sampled clock phase corrected based on the offset information, generated in the clock generation module (CLKGEN). The corrected voltage threshold refers to the sampled voltage threshold corrected based on the offset information, generated in the DAC module.

[0108] In this embodiment of the invention, the clock phase compensation value is used to adjust the correction code of the CDR module, thereby adjusting the clock phase of the clock generation module. The voltage threshold compensation value is used to adjust the correction code of the DAC calibration module, thereby adjusting the voltage threshold of the DAC module.

[0109] Understandably, the CDR module is a horizontal offset control module used to receive the TrimCode generated by the horizontal offset. By changing the Code value of the control clock phase through the CDR module, the center position of the sampling clock phase is changed, thereby achieving eye diagram center calibration. The DAC calibration module is used to receive and process the TrimCode of the vertical offset. Through precise processing of the TrimCode, the DAC calibration module can output a real-time updated Code value, and input the real-time updated Code value into the DAC module of the analog circuit, thereby dynamically adjusting the sampling voltage threshold.

[0110] S5. Obtain the data signal after it has been processed by the equalization circuit, and sample the data signal according to the corrected clock phase and the corrected voltage threshold to obtain D channels of data.

[0111] Understandably, the equalization circuit is a core module of the analog circuit. In high-speed serial data transmission systems, the integrity of the signal is often compromised after long-distance transmission or multiple signal reflections and attenuations, especially due to inter-symbol interference (ISI) and other non-ideal factors. The equalization circuit can be used to eliminate these interferences and effects. The D-channel data refers to normal data. The system in this embodiment includes D-channel data (i.e., normal data) and O-channel data (i.e., biased data). The eye diagram scanning module mainly samples and biases the O-channel data in the analog circuit by manually controlling the horizontal Code value (i.e., Trim Code_CDR) and vertical Code value (i.e., Trim Code_DAC) of the O-channel data. Finally, the O-channel data output by the serial-to-parallel conversion module (SIPO) is the biased data, which is compared with the D-channel data in the serial-to-parallel conversion module.

[0112] In this embodiment of the invention, the step of sampling the data signal according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data includes:

[0113] A sampling voltage threshold is generated in a pre-built DAC module based on a corrected voltage threshold in the DAC calibration module. The corrected voltage threshold is used to adjust the comparison threshold level of the decision unit in the data recovery module.

[0114] The sampled clock phase is generated in the pre-built clock generation module based on the corrected clock phase in the CDR module;

[0115] Using the data recovery module, the data signal is sampled according to the sampling voltage threshold and the sampling clock phase to obtain D-channel data.

[0116] Explained, the sampling voltage threshold refers to the corrected voltage threshold used for sampling the data signal, and the sampling clock phase refers to the corrected clock phase used for sampling the data signal. The data recovery module (Slicer) receives the corrected voltage threshold and corrected clock phase generated by the DAC module and the clock generation module. Simultaneously, it receives the data signal processed by the equalization circuit. The data recovery module uses the corrected voltage threshold and corrected clock phase to determine the sampling time and eye diagram center position of the data signal.

[0117] S6. Determine whether the preset eye diagram calibration has converged based on the D-path data.

[0118] In this embodiment of the invention, determining whether the preset eye diagram calibration has converged based on the D-path data includes:

[0119] Based on the D-channel data and the preset O-channel data, the left limit offset code, right limit offset code, upper limit offset code and lower limit offset code are identified;

[0120] Determine whether the left limit offset code and the upper limit offset are equal to the right limit offset code and the lower limit offset, respectively;

[0121] If the left limit offset code and the upper limit offset are not equal to the right limit offset code and the lower limit offset, respectively, then the eye diagram calibration has not converged.

[0122] If the left limit offset code and the upper limit offset are equal to the right limit offset code and the lower limit offset, respectively, then the eye diagram calibration converges.

[0123] The eye diagram calibration determination process involves implementing clock phase correction and voltage threshold correction through Trim Code_CDR and Trim Code_DAC, respectively. The D-channel data is adjusted according to the clock phase correction and voltage threshold correction. By comparing the adjusted D-channel data with the preset O-channel data, it is determined whether the left limit offset code and the right limit offset code are equal, and whether the upper limit offset code and the lower limit offset code are equal. If the limit offset code and the right limit offset code are equal, and the upper limit offset code and the lower limit offset code are equal, then the eye diagram calibration converges.

[0124] Furthermore, the left limit offset code refers to the rightmost phase control code value of the data that can still be correctly identified when the sampling clock phase is shifted to the left (i.e., sampled earlier), corresponding to the left boundary of the eye diagram; the right limit offset code refers to the rightmost phase control code value of the data that can still be correctly identified when the sampling clock phase is shifted to the right (i.e., sampled later), corresponding to the right boundary of the eye diagram; the upper limit offset code refers to the highest voltage control code value of the data that can still be correctly identified when the sampling voltage threshold is shifted upward (i.e., the voltage threshold is increased), corresponding to the upper boundary of the eye diagram; and the lower limit offset code refers to the lowest voltage control code value of the data that can still be correctly identified when the sampling voltage threshold is shifted downward (i.e., the voltage threshold is decreased), corresponding to the lower boundary of the eye diagram.

[0125] If the eye diagram calibration fails to converge, then execute S7 to update the offset information using the D-path data.

[0126] Understandably, when the eye diagram calibration fails to converge, the clock phase error and voltage threshold error can be calculated based on the D-channel and O-channel data. New clock phase and voltage threshold adjustments are then generated based on these errors, thereby achieving dynamic feedback control of the clock phase and voltage threshold. The voltage threshold and clock phase are adjusted using Trim Code (the voltage threshold and clock phase affect the decision unit in the data recovery module), thus adjusting the D-channel data. Then, the D-channel and O-channel data are compared again (i.e., the process of determining the limit offsets is repeated) to determine whether the left limit offset code and upper limit offset are equal to the right limit offset code and lower limit offset, respectively. That is, whether the upper and lower halves of the eye diagram, and the left and right halves, are equal. When the left and upper limit offset codes are equal to the right and lower limit offset codes, respectively, the eye diagram calibration converges; otherwise, the eye diagram calibration fails to converge, and the calibration algorithm needs to be repeated.

[0127] Return to the steps described above for calculating the clock phase adjustment and voltage threshold adjustment based on the offset information.

[0128] Understandably, if the center position of the eye diagram meets the preset criteria (i.e., the upper and lower halves of the eye diagram, and the left and right halves of the eye diagram are equal), the eye diagram calibration converges, and the process enters the final stage. If the center position of the eye diagram does not meet the preset criteria, the D-path data is fed back to the eye diagram calibration algorithm module to recalculate and generate a new Tirm Code, and then proceed to the next round of calculation. See [link / reference]. Figure 6 As shown, this loop structure ensures that the algorithm has adaptive adjustment capabilities.

[0129] If the eye diagram calibration converges, then execute S8 to complete the eye diagram calibration.

[0130] Furthermore, once the eye diagram calibration converges, the system obtains the optimal sampling clock phase and the optimal sampling voltage threshold, ensuring the maximum eye opening and minimum bit error rate of data recovery at the receiving end in the signal transmission system.

[0131] Explained, this invention can meet the signal transmission stability requirements of signal transmission systems in complex application scenarios, possessing broad environmental adaptability and precise calibration performance. In practical applications, signal transmission systems often need to cope with complex conditions such as switching between different operating modes, dynamic adjustment of data transmission rates (e.g., from low-speed hundreds of megabits to high-speed ten gigabits), and differences in signal link insertion loss (affected by factors such as transmission medium, distance, and environmental interference). This invention can stably adapt to the above-mentioned diverse scenarios without the need for repeated development and debugging for specific scenarios, greatly improving the flexibility and versatility of the technology application.

[0132] Furthermore, the accuracy of the eye diagram's center position is a key indicator for ensuring the bit error rate of data transmission in a signal transmission system. Eye diagram offset directly reduces the fault tolerance space for signal recognition and increases the risk of data transmission errors. This invention dynamically adjusts key parameters such as the sampling clock phase and sampling voltage threshold of the data signal by real-time acquisition of eye diagram feature parameters and an adaptive calibration model. This can efficiently and accurately calibrate the eye diagram's center position, effectively solving the eye diagram offset problem caused by factors such as link loss, timing deviation, and noise interference, and significantly improving the signal transmission quality and stability of the signal transmission system.

[0133] To address the problems described in the background art, this invention first requires clock phase correction and voltage threshold correction to the clock generation module and DAC module respectively based on offset information. Then, the corrected data signals from the clock generation module and DAC module are used for signal sampling to obtain D-channel data. The D-channel data is then used to determine whether the preset eye diagram calibration has converged. When obtaining offset information, the receiving end signal needs to be scanned using an eye diagram scanning module. Before performing clock phase correction and voltage threshold correction on the clock generation module and DAC module respectively, the clock phase adjustment amount and voltage threshold adjustment amount need to be calculated based on the offset information. The clock phase adjustment amount includes the adjustment amplitude and direction of the clock phase, and the voltage threshold adjustment amount includes the adjustment amplitude and direction of the voltage threshold. At this point, clock phase compensation values ​​and voltage threshold compensation values ​​can be set according to the clock phase adjustment amount and voltage threshold adjustment amount respectively. The clock phase compensation value is Trim Code_CDR, and the voltage threshold compensation value is Trim Code_CDR. When the clock phase compensation value and voltage threshold compensation value are obtained, the clock generation module can be corrected based on the clock phase compensation value to obtain a corrected clock phase. Simultaneously, the DAC module can be corrected based on the voltage threshold compensation value to obtain a corrected voltage threshold. At this point, the data signal processed by the equalization circuit can be acquired. Then, the data signal is sampled based on the corrected clock phase and corrected voltage threshold to obtain D-channel data. The convergence of the eye diagram calibration can be determined based on the D-channel data. If the eye diagram calibration has not converged, the offset information is updated using the D-channel data, and a new clock phase adjustment and voltage threshold adjustment are recalculated based on the offset information. If the eye diagram calibration has converged, the eye diagram calibration is complete. Therefore, this invention can improve the feedback calibration adjustment capability of the eye diagram.

[0134] like Figure 7 The diagram shown is a functional block diagram of an eye diagram calibration system provided in an embodiment of the present invention.

[0135] The eye diagram calibration system 100 of this invention can be installed in an electronic device. Depending on the functions implemented, the eye diagram calibration system 100 may include an offset information acquisition module 101, a phase voltage compensation value setting module 102, a phase voltage correction module 103, and an eye diagram calibration convergence judgment module 104. The module described in this invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0136] The offset information acquisition module 101 is used to scan a preset receiving end signal using a pre-constructed eye diagram scanning module to obtain offset information.

[0137] The phase voltage compensation value setting module 102 is used to calculate the clock phase adjustment amount and the voltage threshold adjustment amount according to the offset information. The clock phase adjustment amount includes the adjustment amplitude and adjustment direction of the clock phase, and the voltage threshold adjustment amount includes the adjustment amplitude and adjustment direction of the voltage threshold. The module sets the clock phase compensation value and the voltage threshold compensation value according to the clock phase adjustment amount and the voltage threshold adjustment amount, respectively. The clock phase compensation value is TrimCode_CDR, and the voltage threshold compensation value is TrimCode_DAC.

[0138] The phase voltage correction module 103 is used to correct the clock phase of the pre-built clock generation module according to the clock phase compensation value to obtain the corrected clock phase, and to correct the voltage threshold of the pre-built DAC module according to the voltage threshold compensation value to obtain the corrected voltage threshold.

[0139] The eye diagram calibration convergence judgment module 104 is used to acquire the data signal after being processed by the equalization circuit, sample the data signal according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data; determine whether the preset eye diagram calibration has converged based on the D-channel data; if the eye diagram calibration has not converged, update the offset information using the D-channel data and return to the steps of calculating the clock phase adjustment and voltage threshold adjustment based on the offset information; if the eye diagram calibration has converged, the eye diagram calibration is completed.

[0140] In detail, the modules in the eye diagram calibration system 100 described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The eye diagram calibration method described herein uses the same technical means and can produce the same technical effect, so it will not be repeated here.

[0141] like Figure 8 The diagram shown is a schematic diagram of an electronic device for implementing an eye diagram calibration method according to an embodiment of the present invention.

[0142] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program, such as an eye diagram calibration method program, stored in the memory 11 and executable on the processor 10.

[0143] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 1. Furthermore, the memory 11 includes both internal storage units and external storage devices of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as the code of an eye diagram calibration method program, but also to temporarily store data that has been output or will be output.

[0144] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules (such as eye diagram calibration methods) stored in the memory 11, and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0145] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0146] Figure 8 Only electronic devices with components are shown; those skilled in the art will understand that... Figure 8 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0147] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0148] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0149] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0150] The eye diagram calibration method program stored in the memory 11 of the electronic device 1 is a combination of multiple instructions, which, when run in the processor 10, can achieve the following:

[0151] The preset receiver signal is scanned using a pre-built eye diagram scanning module to obtain offset information;

[0152] The clock phase adjustment and voltage threshold adjustment are calculated based on the offset information. The clock phase adjustment includes the adjustment magnitude and direction of the clock phase, and the voltage threshold adjustment includes the adjustment magnitude and direction of the voltage threshold.

[0153] The clock phase compensation value and the voltage threshold compensation value are set according to the clock phase adjustment amount and the voltage threshold adjustment amount, respectively, wherein the clock phase compensation value is Trim Code_CDR and the voltage threshold compensation value is Trim Code_DAC;

[0154] The clock phase of the pre-built clock generation module is corrected according to the clock phase compensation value to obtain the corrected clock phase; the voltage threshold of the pre-built DAC module is corrected according to the voltage threshold compensation value to obtain the corrected voltage threshold.

[0155] The data signal processed by the equalization circuit is acquired, and the data signal is sampled according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data.

[0156] Based on the D-path data, determine whether the preset eye diagram calibration has converged;

[0157] If the eye diagram calibration fails to converge, the offset information is updated using the D-path data, and the steps described above for calculating the clock phase adjustment and voltage threshold adjustment based on the offset information are returned.

[0158] If the eye diagram calibration converges, the eye diagram calibration is complete.

[0159] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 8 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0160] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0161] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0162] The preset receiver signal is scanned using a pre-built eye diagram scanning module to obtain offset information;

[0163] The clock phase adjustment and voltage threshold adjustment are calculated based on the offset information. The clock phase adjustment includes the adjustment magnitude and direction of the clock phase, and the voltage threshold adjustment includes the adjustment magnitude and direction of the voltage threshold.

[0164] The clock phase compensation value and the voltage threshold compensation value are set according to the clock phase adjustment amount and the voltage threshold adjustment amount, respectively, wherein the clock phase compensation value is Trim Code_CDR and the voltage threshold compensation value is Trim Code_DAC;

[0165] The clock phase of the pre-built clock generation module is corrected according to the clock phase compensation value to obtain the corrected clock phase; the voltage threshold of the pre-built DAC module is corrected according to the voltage threshold compensation value to obtain the corrected voltage threshold.

[0166] The data signal processed by the equalization circuit is acquired, and the data signal is sampled according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data.

[0167] Based on the D-path data, determine whether the preset eye diagram calibration has converged;

[0168] If the eye diagram calibration fails to converge, the offset information is updated using the D-path data, and the steps described above for calculating the clock phase adjustment and voltage threshold adjustment based on the offset information are returned.

[0169] If the eye diagram calibration converges, the eye diagram calibration is complete.

[0170] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0171] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0172] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0173] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An eye diagram calibration method, characterized in that, The method includes: The preset receiver signal is scanned using a pre-built eye diagram scanning module to obtain offset information; The clock phase adjustment and voltage threshold adjustment are calculated based on the offset information. The clock phase adjustment includes the adjustment magnitude and direction of the clock phase, and the voltage threshold adjustment includes the adjustment magnitude and direction of the voltage threshold. The clock phase compensation value and the voltage threshold compensation value are set according to the clock phase adjustment amount and the voltage threshold adjustment amount, respectively, wherein the clock phase compensation value is Trim Code_CDR and the voltage threshold compensation value is Trim Code_DAC; The clock phase of the pre-built clock generation module is corrected according to the clock phase compensation value to obtain the corrected clock phase; the voltage threshold of the pre-built DAC module is corrected according to the voltage threshold compensation value to obtain the corrected voltage threshold. The data signal processed by the equalization circuit is acquired, and the data signal is sampled according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data. Based on the D-path data, determine whether the preset eye diagram calibration has converged; If the eye diagram calibration fails to converge, the offset information is updated using the D-path data, and the steps described above for calculating the clock phase adjustment and voltage threshold adjustment based on the offset information are returned. If the eye diagram calibration converges, the eye diagram calibration is complete.

2. The eye diagram calibration method as described in claim 1, characterized in that, The step of scanning the preset receiver signal using a pre-constructed eye diagram scanning module to obtain offset information includes: The eye diagram scanning module is used to scan the receiver signal to obtain the current scanned eye diagram; Offset information is extracted from the current scanned eye diagram. The offset information includes: signal clock phase and signal voltage threshold.

3. The eye diagram calibration method as described in claim 2, characterized in that, The calculation of clock phase adjustment and voltage threshold adjustment based on the offset information includes: Identify the horizontal offset position of the eye diagram in the offset information, and determine the extreme offset positions of the left and right halves of the eye based on the horizontal offset position of the eye diagram. Identify the vertical offset position of the eye diagram in the offset information, and determine the upper half-eye limit offset position and the lower half-eye limit offset position based on the vertical offset position of the eye diagram. Calculate the clock phase adjustment amount based on the left and right hemi-eye extreme offset positions; The voltage threshold adjustment amount is calculated based on the upper half-eye limit offset position and the lower half-eye limit offset position.

4. The eye diagram calibration method as described in claim 3, characterized in that, The calculation of the clock phase adjustment based on the left and right hemi-eye extreme offset positions includes: The extreme offset of the left and right eyes is determined based on the extreme offset positions of the left and right eyes, respectively. The clock phase sampling boundary is adjusted based on the left and right half-eye limit offsets to obtain a horizontally calibrated eye diagram. Identify the clock phase adjustment amount of the horizontal calibration eye diagram.

5. The eye diagram calibration method as described in claim 4, characterized in that, The calculation of the voltage threshold adjustment based on the upper half-eye limit offset position and the lower half-eye limit offset position includes: The extreme offset of the upper eye and the extreme offset of the lower eye are determined based on the extreme offset positions of the upper and lower eye respectively. The voltage threshold is adjusted based on the upper half-eye limit offset and the lower half-eye limit offset to obtain a vertically calibrated eye diagram; Identify the voltage threshold adjustment amount of the vertical calibration eye diagram.

6. The eye diagram calibration method as described in claim 5, characterized in that, The step of setting clock phase compensation values ​​and voltage threshold compensation values ​​according to the clock phase adjustment amount and voltage threshold adjustment amount respectively includes: The calibration algorithm module built into the pre-built eye diagram calibration algorithm module identifies the clock phase compensation value and voltage threshold compensation value based on the clock phase adjustment amount and voltage threshold adjustment amount. The calibration algorithm module identifies the clock phase compensation value and voltage threshold compensation value based on the clock phase adjustment amount and voltage threshold adjustment amount and uses the pre-built code mapping relationship.

7. The eye diagram calibration method as described in claim 6, characterized in that, The step of sampling the data signal according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data includes: A sampling voltage threshold is generated in a pre-built DAC module based on a corrected voltage threshold in the DAC calibration module. The corrected voltage threshold is used to adjust the comparison threshold level of the decision unit in the data recovery module. The sampled clock phase is generated in the pre-built clock generation module based on the corrected clock phase in the CDR module; Using the data recovery module, the data signal is sampled according to the sampling voltage threshold and the sampling clock phase to obtain D-channel data.

8. The eye diagram calibration method as described in claim 7, characterized in that, The step of determining whether the preset eye diagram calibration has converged based on the D-path data includes: Based on the D-channel data and the preset O-channel data, the left limit offset code, right limit offset code, upper limit offset code and lower limit offset code are identified; Determine whether the left limit offset code and the upper limit offset are equal to the right limit offset code and the lower limit offset, respectively; If the left limit offset code and the upper limit offset are not equal to the right limit offset code and the lower limit offset, respectively, then the eye diagram calibration has not converged. If the left limit offset code and the upper limit offset are equal to the right limit offset code and the lower limit offset, respectively, then the eye diagram calibration converges. The eye diagram calibration determination process involves implementing clock phase correction and voltage threshold correction through Trim Code_CDR and Trim Code_DAC, respectively. The D-channel data is adjusted according to the clock phase correction and voltage threshold correction. By comparing the adjusted D-channel data with the preset O-channel data, it is determined whether the left limit offset code and the right limit offset code are equal, and whether the upper limit offset code and the lower limit offset code are equal. If the limit offset code and the right limit offset code are equal, and the upper limit offset code and the lower limit offset code are equal, then the eye diagram calibration converges.

9. The eye diagram calibration method as described in claim 8, characterized in that, The clock phase compensation value is used to adjust the correction code of the CDR module, thereby adjusting the clock phase of the clock generation module. The voltage threshold compensation value is used to adjust the correction code of the DAC calibration module, thereby adjusting the voltage threshold of the DAC module.

10. An eye diagram calibration system, characterized in that, The system includes: The offset information acquisition module is used to scan the preset receiving end signal using a pre-built eye diagram scanning module to obtain offset information; A phase voltage compensation value setting module is used to calculate a clock phase adjustment amount and a voltage threshold adjustment amount based on the offset information. The clock phase adjustment amount includes the adjustment amplitude and adjustment direction of the clock phase, and the voltage threshold adjustment amount includes the adjustment amplitude and adjustment direction of the voltage threshold. The module sets a clock phase compensation value and a voltage threshold compensation value based on the clock phase adjustment amount and the voltage threshold adjustment amount, respectively. The clock phase compensation value is Trim Code_CDR, and the voltage threshold compensation value is Trim Code_DAC. The phase voltage correction module is used to correct the clock phase of the pre-built clock generation module according to the clock phase compensation value to obtain the corrected clock phase, and to correct the voltage threshold of the pre-built DAC module according to the voltage threshold compensation value to obtain the corrected voltage threshold. The eye diagram calibration convergence judgment module is used to acquire the data signal after processing by the equalization circuit, sample the data signal according to the corrected clock phase and the corrected voltage threshold to obtain D-channel data; determine whether the preset eye diagram calibration has converged based on the D-channel data; if the eye diagram calibration has not converged, update the offset information using the D-channel data and return to the steps of calculating the clock phase adjustment and voltage threshold adjustment based on the offset information; if the eye diagram calibration has converged, the eye diagram calibration is completed.

Images