Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, and belongs to the technical field of semiconductors, the semiconductor device comprises at least one storage unit, and the storage unit comprises a first transistor layer arranged on a substrate and a second transistor layer arranged on the side, away from the substrate, of the first transistor layer; the first transistor layer comprises a plurality of lower transistors arranged on the substrate, a semiconductor layer of each lower transistor comprises a vertical channel, a seed layer is arranged on one side, close to the substrate, of the semiconductor layer of each lower transistor, and the seed layer is in contact with the semiconductor layer of each lower transistor; the material of the semiconductor layer of the lower transistor comprises a single-crystal-like semiconductor or a single-crystal semiconductor; the second transistor layer comprises a plurality of upper transistors; the grid electrode of at least one upper transistor in the second transistor layer is connected with the grid electrode of the lower transistor; the structure is simple, and a preparation technology of a CMOS back-end process can be compatible.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a semiconductor device and its manufacturing method, as well as an electronic device, which has a simple structure and is compatible with CMOS back-end process fabrication technology.

[0006] This disclosure provides a semiconductor device including at least one memory cell, the memory cell including a first transistor layer disposed on a substrate and a second transistor layer disposed on the side of the first transistor layer away from the substrate;

[0007] The first transistor layer includes a plurality of lower transistors disposed on the substrate. The semiconductor layer of the lower transistor includes a vertical channel. A seed layer is disposed on the side of the semiconductor layer of the lower transistor near the substrate. The seed layer is in contact with the semiconductor layer of the lower transistor. The material of the semiconductor layer of the lower transistor includes a single-crystal semiconductor or a single-crystal semiconductor.

[0008] The second transistor layer includes a plurality of upper transistors; the gate of at least one upper transistor in the second transistor layer is connected to the gate of the lower transistor.

[0009] In some embodiments, the seed layer is made of a metallized semiconductor material.

[0010] In some embodiments, the seed layer is made of metal silicide.

[0011] In some embodiments, the semiconductor layer of the lower transistor is made of quasi-monocrystalline silicon or monocrystalline silicon.

[0012] In some embodiments, the first transistor layer includes a first lower transistor and a second lower transistor, which are spaced apart along a direction parallel to the substrate. The first lower transistor includes a first semiconductor layer, a first gate, and a first conductive contact region that contacts the periphery of the first semiconductor layer. The first gate extends along a direction perpendicular to the substrate. The first semiconductor layer surrounds the sidewall of the first gate. A first seed layer is disposed on the side of the first semiconductor layer near the substrate. The material of the first semiconductor layer includes a quasi-single-crystal semiconductor or a single-crystal semiconductor. The second lower transistor includes a second semiconductor layer, a second gate, and a second conductive contact region that contacts the periphery of the second semiconductor layer. The second gate extends along a direction perpendicular to the substrate. The second semiconductor layer surrounds the sidewall of the second gate. A second seed layer is disposed on the side of the second semiconductor layer near the substrate. The material of the second semiconductor layer includes a quasi-single-crystal semiconductor or a single-crystal semiconductor.

[0013] In some embodiments, the second transistor layer includes a first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor. The second upper transistor overlaps with the orthographic projection of the first lower transistor on the substrate, and the third upper transistor overlaps with the orthographic projection of the second lower transistor on the substrate. The first upper transistor does not overlap with the orthographic projections of the first lower transistor and the second lower transistor on the substrate, and the fourth upper transistor does not overlap with the orthographic projections of the first lower transistor and the second lower transistor on the substrate. The second upper transistor includes a fourth gate, a fourth semiconductor layer, a third electrode, and a fourth electrode. The fourth gate is located on the side of the fourth semiconductor layer near the substrate and is in contact with the first gate of the first lower transistor. The third electrode and the fourth electrode of the second upper transistor are respectively disposed on the fourth semiconductor layer and are spaced apart along a direction parallel to the substrate. The third upper transistor includes a fifth gate, a fifth semiconductor layer, a fifth electrode, and a sixth electrode. The fifth gate is located on the side of the fifth semiconductor layer near the substrate and is in contact with the second gate of the second lower transistor. The fifth electrode and the sixth electrode of the third upper transistor are respectively disposed on the fifth semiconductor layer and are spaced apart along a direction parallel to the substrate.

[0014] In some embodiments, the first upper transistor includes a third gate, a third semiconductor layer, a first electrode, and a second electrode. The third gate is located on the side of the third semiconductor layer near the substrate. The first electrode and the second electrode of the first upper transistor are respectively disposed on the third semiconductor layer and spaced apart along a direction parallel to the substrate. The fourth upper transistor includes a sixth gate, a sixth semiconductor layer, a seventh electrode, and an eighth electrode. The sixth gate is located on the side of the sixth semiconductor layer near the substrate. The seventh electrode and the eighth electrode of the fourth upper transistor are respectively disposed on the sixth semiconductor layer and spaced apart along a direction parallel to the substrate.

[0015] In some embodiments, the system further includes a first bit line, a second bit line, a word line, a power signal line, and a ground line. The first conductive contact area of ​​the first lower transistor is connected to the third terminal of the second upper transistor, and the first gate of the first lower transistor is connected to the seventh terminal of the fourth upper transistor. The second conductive contact area of ​​the second lower transistor is connected to the sixth terminal of the third upper transistor, and the second gate of the second lower transistor is connected to the second terminal of the first upper transistor. The third gate of the first upper transistor is connected to the word line, and the first terminal of the first upper transistor is connected to the first bit line. The fourth terminal of the second upper transistor is connected to the ground line, and the fifth terminal of the third upper transistor is connected to the ground line. The sixth gate of the fourth upper transistor is connected to the word line, and the eighth terminal of the fourth upper transistor is connected to the second bit line. Both the first seed layer and the second seed layer are connected to the power signal line.

[0016] In some embodiments, the lower transistor is a p-channel field-effect transistor.

[0017] In some embodiments, the upper transistor is an N-channel metal-oxide-semiconductor field-effect transistor.

[0018] In some embodiments, the semiconductor layer of the upper transistor includes a horizontal channel.

[0019] This application also provides a method for manufacturing a semiconductor device, including:

[0020] A first seed layer and a second seed layer are formed on a substrate at intervals;

[0021] A first via and a second via are formed extending along the direction perpendicular to the substrate, wherein the first via exposes the first seed layer and the second via exposes the second seed layer;

[0022] A doped amorphous semiconductor thin film is formed on the inner wall of the first via and the second via. The doped amorphous semiconductor thin film is in contact with the exposed first seed layer through the first via and the doped amorphous semiconductor thin film is in contact with the exposed second seed layer through the second via.

[0023] The first and second seed layers are used as induction layers to induce crystallization annealing of doped amorphous semiconductor films to form quasi-single crystal semiconductor or single crystal semiconductor films.

[0024] Etching a single-crystal semiconductor or a single-crystal semiconductor thin film to form a first semiconductor layer disposed on the inner wall of the first via and a second semiconductor layer disposed on the inner wall of the second via;

[0025] A first gate insulating layer and a first gate are sequentially formed in the first via, and a second gate insulating layer and a second gate are sequentially formed in the second via;

[0026] A first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor are formed on the side of the first gate and the second gate away from the substrate, wherein the gate of the second upper transistor is in contact with the first gate, and the gate of the third upper transistor is in contact with the second gate.

[0027] In some embodiments, forming a first seed layer and a second seed layer spaced apart on the substrate includes:

[0028] An amorphous semiconductor thin film is formed on the substrate;

[0029] The amorphous semiconductor thin film is patterned to form a first amorphous semiconductor pattern and a second amorphous semiconductor pattern spaced apart along a direction parallel to the substrate.

[0030] A metal thin film is deposited covering the first amorphous semiconductor pattern and the second amorphous semiconductor pattern;

[0031] The metal thin film, the first amorphous semiconductor pattern, and the second amorphous semiconductor pattern are annealed to cause the first amorphous semiconductor pattern to react with the metal thin film to form a first seed layer; the second amorphous semiconductor pattern is then reacted with the metal thin film to form a second seed layer.

[0032] In some embodiments, the first seed layer and the second seed layer are used as induction layers to induce crystallization annealing of the doped amorphous semiconductor thin film to form a quasi-single crystal semiconductor or a single crystal semiconductor thin film. The induced crystallization annealing temperature is 500°C to 575°C, and the induced crystallization annealing time is 12 hours to 24 hours.

[0033] In some embodiments, the metal thin film, the first amorphous semiconductor pattern, and the second amorphous semiconductor pattern are annealed to cause the first amorphous semiconductor pattern to react with the metal thin film to form a first seed layer; and the second amorphous semiconductor pattern to react with the metal thin film to form a second seed layer. The annealing temperature is 350°C to 450°C, and the annealing time is 10 minutes to 60 minutes.

[0034] In some embodiments, forming a first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor on the side of the first gate and the second gate away from the substrate includes:

[0035] A third gate, a fourth gate, a fifth gate, and a sixth gate are formed on the side of the first gate and the second gate away from the substrate, and are spaced apart along a direction parallel to the substrate. The fourth gate is in contact with the side of the first gate away from the substrate, and the fifth gate is in contact with the side of the second gate away from the substrate.

[0036] A third gate insulating layer is deposited covering the third gate, fourth gate, fifth gate, and sixth gate on the side away from the substrate;

[0037] A third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer are formed on the third gate insulating layer at intervals along a direction parallel to the substrate. The third semiconductor layer overlaps with the orthogonal projection of the third gate on the substrate, the fourth semiconductor layer overlaps with the orthogonal projection of the fourth gate on the substrate, the fifth semiconductor layer overlaps with the orthogonal projection of the fifth gate on the substrate, and the sixth semiconductor layer overlaps with the orthogonal projection of the sixth gate on the substrate.

[0038] A first electrode and a second electrode are formed on the third semiconductor layer, spaced apart along a direction parallel to the substrate. The third gate, the third semiconductor layer, the first electrode, and the second electrode form a first upper transistor. A third electrode and a fourth electrode are formed on the fourth semiconductor layer, spaced apart along a direction parallel to the substrate. The fourth gate, the fourth semiconductor layer, the third electrode, and the fourth electrode form a second upper transistor. A fifth electrode and a sixth electrode are formed on the fifth semiconductor layer, spaced apart along a direction parallel to the substrate. The fifth gate, the fifth semiconductor layer, the fifth electrode, and the sixth electrode form a third upper transistor. A seventh electrode and an eighth electrode are formed on the sixth semiconductor layer, spaced apart along a direction parallel to the substrate. The sixth gate, the sixth semiconductor layer, the seventh electrode, and the eighth electrode form a fourth upper transistor.

[0039] This application also provides an electronic device comprising the semiconductor device described in any of the above embodiments, or a semiconductor device formed by a manufacturing method of the semiconductor device described in any of the above embodiments.

[0040] The semiconductor device of this disclosure has a simple structure and is easy to manufacture because the gate of the lower transistor is in contact with the gate of the upper transistor, so that the lower transistor and the upper transistor share a gate.

[0041] The semiconductor device disclosed herein achieves a three-dimensional device by stacking upper and lower transistors in the direction perpendicular to the substrate and making the orthogonal projections of the upper and lower transistors on the substrate overlap, thereby reducing the area of ​​the memory cell.

[0042] The semiconductor device manufacturing method in this embodiment induces the formation of the semiconductor layer of the lower transistor through a seed layer. The process is simple to implement, has low process cost, and is compatible with the fabrication process of CMOS back-end process.

[0043] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings.

[0044] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0045] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions.

[0046] Figure 1a This is an equivalent circuit diagram of the semiconductor device according to an embodiment of the present disclosure;

[0047] Figure 1b This is a longitudinal cross-sectional view of a semiconductor device according to an embodiment of this disclosure;

[0048] Figure 2 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first amorphous semiconductor pattern and the second amorphous semiconductor pattern;

[0049] Figure 3 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after a metal thin film has been formed.

[0050] Figure 4 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure, showing the formation of the first seed layer and the subsequent formation of the first seed layer.

[0051] Figure 5 This is a longitudinal cross-sectional view of the semiconductor device according to an embodiment of the present disclosure after the formation of the first insulating layer, the isolation layer, and the second insulating layer;

[0052] Figure 6This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first via and the second via;

[0053] Figure 7 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after forming a thin film of a quasi-single-crystal semiconductor or a single-crystal semiconductor.

[0054] Figure 8 This is a longitudinal cross-sectional view of the semiconductor device according to an embodiment of the present disclosure after the formation of the first conductive contact region and the second conductive contact region during the manufacturing process;

[0055] Figure 9 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first lower transistor and the second lower transistor;

[0056] Figure 10 This is a longitudinal cross-sectional view of the semiconductor device according to an embodiment of the present disclosure after the third gate, fourth gate, fifth gate and sixth gate are formed during the manufacturing process;

[0057] Figure 11 This is a longitudinal cross-sectional view of the semiconductor device according to an embodiment of the present disclosure after the formation of the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer. Detailed Implementation

[0058] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0060] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0061] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0062] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0063] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0064] In this disclosure, the terms "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating film".

[0065] This disclosure provides a semiconductor device and its manufacturing method, as well as an electronic device, which has a simple structure and is compatible with CMOS back-end process fabrication technology.

[0066] This disclosure provides a semiconductor device including at least one memory cell, the memory cell including a first transistor layer disposed on a substrate and a second transistor layer disposed on the side of the first transistor layer away from the substrate;

[0067] The first transistor layer includes a plurality of lower transistors disposed on the substrate. The semiconductor layer of the lower transistor includes a vertical channel. A seed layer is disposed on the side of the semiconductor layer of the lower transistor near the substrate. The seed layer is in contact with the semiconductor layer of the lower transistor. The material of the semiconductor layer of the lower transistor includes a single-crystal semiconductor or a single-crystal semiconductor.

[0068] The second transistor layer includes a plurality of upper transistors; the gate of at least one upper transistor in the second transistor layer is connected to the gate of the lower transistor.

[0069] Figure 1a This is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present disclosure. In an exemplary embodiment, as shown... Figure 1aAs shown, the semiconductor device in this embodiment includes at least one memory cell. The memory cell includes a first transistor layer disposed on a substrate and a second transistor layer disposed on the side of the first transistor layer away from the substrate. The first transistor layer includes a first lower transistor T1 and a second lower transistor T2. The second transistor layer includes a first upper transistor T3, a second upper transistor T4, a third upper transistor T5, and a fourth upper transistor T6. The first terminal of the first lower transistor T1 is connected to the power signal line VDD, the second terminal of the first lower transistor T1 is connected to the first terminal of the second upper transistor T4, and the gate of the first lower transistor T1 is connected to the first terminal of the fourth upper transistor T6 and the gate of the second upper transistor T4, respectively. The first terminal of the second lower transistor T2 is connected to the power signal line VDD, the second terminal of the second lower transistor T2 is connected to the second terminal of the third upper transistor T5, and the gate of the second lower transistor T2 is connected to the second terminal of the first upper transistor T3 and the gate of the third upper transistor T5, respectively. The first terminal of the first upper transistor T3 is connected to the first bit line BL1, the second terminal of the first upper transistor T3 is connected to the gate of the second lower transistor T2 and the gate of the third upper transistor T5, respectively. The gate of transistor T3 is connected to the word line WL; the first terminal of the second upper transistor T4 is connected to the second terminal of the first lower transistor T1, the second terminal of the second upper transistor T4 is connected to ground GND, and the gate of the second upper transistor T4 is connected to the gate of the first lower transistor T1 and the first terminal of the fourth upper transistor T6, respectively; the first terminal of the third upper transistor T5 is connected to the second terminal of the second lower transistor T2, the second terminal of the third upper transistor T5 is connected to ground GND, and the gate of the third upper transistor T5 is connected to the gate of the second lower transistor T2 and the second terminal of the first upper transistor T3, respectively; the first terminal of the fourth upper transistor T6 is connected to the gate of the first lower transistor T1 and the gate of the second upper transistor T4, respectively, and the second terminal of the fourth upper transistor T6 is connected to the second bit line BL2.

[0070] In one exemplary embodiment, at least one memory cell in the semiconductor device of this disclosure may be an SRAM memory cell.

[0071] Figure 1b This is a longitudinal cross-sectional view of a semiconductor device according to an embodiment of this disclosure. In an exemplary embodiment, as shown... Figure 1b As shown, the memory cell of the semiconductor device in this embodiment includes a buffer layer 102 disposed on a substrate 101, a first transistor layer disposed on the side of the buffer layer 102 away from the substrate 101, and a second transistor layer disposed on the side of the first transistor layer away from the substrate.

[0072] In an exemplary embodiment, the first transistor layer includes a first lower transistor and a second lower transistor disposed on the side of the buffer layer 102 away from the substrate and spaced apart along a direction parallel to the substrate. The first lower transistor includes a first semiconductor layer 51, a first gate 71, a first conductive contact region 41, and a first gate insulating layer 61 disposed on the side of the buffer layer 102 away from the substrate. The first gate 71 has a T-shaped cross-section perpendicular to the substrate direction, and a portion of the first gate 71 is columnar extending along the direction perpendicular to the substrate. The first semiconductor layer 51 includes sidewalls extending along the direction perpendicular to the substrate and a bottom wall extending along the direction parallel to the substrate. The sidewalls of the first semiconductor layer 51 surround the sidewalls of the first gate 71, forming a ring gate structure. The bottom wall of the first semiconductor layer 51 is located at the bottom of the first gate 71 near the substrate. The first conductive contact region 41 contacts the outer side of the sidewalls of the first semiconductor layer 51. The first gate insulating layer 61 is disposed between the first semiconductor layer 51 and the first gate 71.

[0073] In an exemplary embodiment, a first seed layer 11 is disposed on the bottom wall of the first semiconductor layer 51 near the substrate, and the first seed layer 11 is in contact with the bottom wall of the first semiconductor layer 51.

[0074] In an exemplary embodiment, the material of the first semiconductor layer 51 includes a quasi-monocrystalline semiconductor or a monocrystalline semiconductor, and the first seed layer 11 is used to induce the formation of the first semiconductor layer 51 from a polycrystalline semiconductor thin film. For example, the material of the first seed layer 11 is a metallide semiconductor material, such as a metal silicide, for example, nickel silicide. An amorphous silicon thin film can form the first semiconductor layer 51 under the induction of the first seed layer 11, and the material of the first semiconductor layer 51 is quasi-monocrystalline silicon or monocrystalline silicon.

[0075] In an exemplary embodiment, the second lower transistor includes a second semiconductor layer 52, a second gate 72, a second conductive contact region 42, and a second gate insulating layer 62 disposed on the side of the buffer layer 102 away from the substrate. The second gate 72 has a T-shaped cross-section perpendicular to the substrate direction, and a portion of the second gate 72 is columnar extending perpendicular to the substrate direction. The second semiconductor layer 52 includes sidewalls extending perpendicular to the substrate direction and a bottom wall extending parallel to the substrate direction. The sidewalls of the second semiconductor layer 52 surround the sidewalls of the second gate 72, forming a ring gate structure. The bottom wall of the second semiconductor layer 52 is located at the bottom of the second gate 72 near the substrate. The second conductive contact region 42 contacts the outer side of the sidewall of the second semiconductor layer 52. The second gate insulating layer 62 is disposed between the second semiconductor layer 52 and the second gate 72.

[0076] In an exemplary embodiment, a second seed layer 12 is disposed on the bottom wall of the second semiconductor layer 52 near the substrate, and the second seed layer 12 is in contact with the bottom wall of the second semiconductor layer 52.

[0077] In an exemplary embodiment, the material of the second semiconductor layer 52 includes a quasi-single-crystal semiconductor or a single-crystal semiconductor, and the second seed layer 12 is used to induce the formation of the second semiconductor layer 52 from a polycrystalline semiconductor thin film. For example, the material of the second seed layer 12 is a metallide semiconductor material, such as a metal silicide, for example, nickel silicide. An amorphous silicon thin film can be induced by the second seed layer 12 to form the second semiconductor layer 52, and the material of the second semiconductor layer 52 is quasi-single-crystal silicon or single-crystal silicon.

[0078] In one exemplary embodiment, both the first lower transistor and the second lower transistor are p-channel field-effect transistors.

[0079] In an exemplary embodiment, both the first semiconductor layer 51 of the first lower transistor and the second semiconductor layer 52 of the second lower transistor include a vertical channel.

[0080] In an exemplary embodiment, the semiconductor device of this disclosure further includes a first insulating layer 104 disposed on the side of the first seed layer 11 and the second seed layer 12 away from the substrate, a first isolation layer 105 disposed on the side of the first insulating layer 104 away from the substrate, and a second insulating layer 106 disposed on the side of the first isolation layer 105 away from the substrate. The first isolation layer 105, the first conductive contact region 41, and the second conductive contact region 42 are disposed in the same layer, and the first isolation layer 105 is located between the first conductive contact region 41 and the second conductive contact region 42, isolating the first conductive contact region 41 and the second conductive contact region 42.

[0081] In one exemplary embodiment, the second transistor layer includes a first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor. The first upper transistors do not overlap with the orthographic projections of the first lower transistor and the second lower transistor onto the substrate. Each first upper transistor includes a third gate 73, a third semiconductor layer 53, a first electrode 81, and a second electrode 82. The third gate 73 and the third semiconductor layer 53 extend in a direction parallel to the substrate. The third gate 73 is located on the side of the third semiconductor layer 53 closest to the substrate. The first electrode 81 and the second electrode 82 are respectively disposed on the third semiconductor layer 53 and spaced apart in a direction parallel to the substrate. The first upper transistor is an N-channel metal-oxide-semiconductor field-effect transistor, and the third semiconductor layer 53 includes a horizontal channel.

[0082] In one exemplary embodiment, the orthographic projections of the second upper transistor and the first lower transistor onto the substrate overlap. The second upper transistor includes a fourth gate 74, a fourth semiconductor layer 54, a third electrode 83, and a fourth electrode 84. The fourth gate 74 and the fourth semiconductor layer 54 extend in a direction parallel to the substrate. The fourth gate 74 is located on the side of the fourth semiconductor layer 54 closest to the substrate. The third electrode 83 and the fourth electrode 84 are respectively disposed on the fourth semiconductor layer 54 and spaced apart in a direction parallel to the substrate. The second upper transistor is an N-channel metal-oxide-semiconductor field-effect transistor, and the fourth semiconductor layer 54 includes a horizontal channel.

[0083] In an exemplary embodiment, the orthographic projections of the fourth gate 74 and the first gate 71 on the substrate overlap, the fourth gate 74 is located on the side of the first gate 71 away from the substrate, and the fourth gate 74 is in contact with the first gate 71.

[0084] In one exemplary embodiment, the orthographic projections of the third upper transistor and the second lower transistor onto the substrate overlap. The third upper transistor includes a fifth gate 75, a fifth semiconductor layer 55, a fifth electrode 85, and a sixth electrode 86. The fifth gate 75 and the fifth semiconductor layer 55 extend along a direction parallel to the substrate. The fifth gate 75 is located on the side of the fifth semiconductor layer 55 closest to the substrate. The fifth electrode 85 and the sixth electrode 86 are respectively disposed on the fifth semiconductor layer 55 and spaced apart along a direction parallel to the substrate. The third upper transistor is an N-channel metal-oxide-semiconductor field-effect transistor, and the fifth semiconductor layer 55 includes a horizontal channel.

[0085] In an exemplary embodiment, the orthographic projections of the fifth gate 75 and the second gate 72 on the substrate overlap, the fifth gate 75 is located on the side of the second gate 72 away from the substrate, and the fifth gate 75 is in contact with the second gate 72.

[0086] In an exemplary embodiment, the fourth upper transistor does not overlap with the orthographic projections of the first and second lower transistors onto the substrate. The fourth upper transistor includes a sixth gate 76, a sixth semiconductor layer 56, a seventh electrode 87, and an eighth electrode 88. The sixth gate 76 and the sixth semiconductor layer 56 extend parallel to the substrate. The sixth gate 76 is located on the side of the sixth semiconductor layer 56 closest to the substrate. The seventh electrode 87 and the eighth electrode 88 are respectively disposed on the sixth semiconductor layer 56 and spaced apart along the direction parallel to the substrate. The fourth upper transistor is an N-channel metal-oxide-semiconductor field-effect transistor, and the sixth semiconductor layer 56 includes a horizontal channel.

[0087] In an exemplary embodiment, the semiconductor device of this disclosure further includes a third insulating layer 107 disposed on the side of the second insulating layer 106 away from the substrate, a second isolation layer 108 disposed on the side of the third insulating layer 107 away from the substrate, a third gate insulating layer 63 disposed on the side of the second isolation layer 108 away from the substrate, and a fourth insulating layer 109 disposed on the side of the third gate insulating layer 63 away from the substrate.

[0088] In an exemplary embodiment, the third gate 73, the fourth gate 74, the fifth gate 75, and the sixth gate 76 are disposed in the same layer, the third semiconductor layer 53, the fourth semiconductor layer 54, the fifth semiconductor layer 55, and the sixth semiconductor layer 56 are disposed in the same layer, and the third gate insulating layer 63 is located between the third gate 73, the fourth gate 74, the fifth gate 75, and the sixth gate 76 disposed in the same layer and the third semiconductor layer 53, the fourth semiconductor layer 54, the fifth semiconductor layer 55, and the sixth semiconductor layer 56 disposed in the same layer.

[0089] In an exemplary embodiment, the second isolation layer 108, the third gate 73, the fourth gate 74, the fifth gate 75 and the sixth gate 76 are disposed on the same layer, and the second isolation layer 108 isolates the third gate 73, the fourth gate 74, the fifth gate 75 and the sixth gate 76 from each other.

[0090] In an exemplary embodiment, the semiconductor device of this disclosure further includes a first bit line, a second bit line, a word line, a power signal line, and a ground line. A first conductive contact region of the first lower transistor is connected to the third terminal of the second upper transistor, and a first gate of the first lower transistor is connected to the seventh terminal of the fourth upper transistor. A second conductive contact region of the second lower transistor is connected to the sixth terminal of the third upper transistor, and a second gate of the second lower transistor is connected to the second terminal of the first upper transistor. The third gate of the first upper transistor is connected to the word line, and a first terminal of the first upper transistor is connected to the first bit line. A fourth terminal of the second upper transistor is connected to the ground line, and a fifth terminal of the third upper transistor is connected to the ground line. A sixth gate of the fourth upper transistor is connected to the word line, and an eighth terminal of the fourth upper transistor is connected to the second bit line. Both the first seed layer and the second seed layer are connected to the power signal line.

[0091] The semiconductor device of this disclosure has a simple structure and is easy to manufacture because the gate of the lower transistor is in contact with the gate of the upper transistor, so that the lower transistor and the upper transistor share a gate.

[0092] The semiconductor device disclosed herein achieves a three-dimensional device by stacking upper and lower transistors in the direction perpendicular to the substrate and making the orthogonal projections of the upper and lower transistors on the substrate overlap, thereby reducing the area of ​​the memory cell.

[0093] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layers, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0094] In one exemplary embodiment, the manufacturing process of a semiconductor device may include:

[0095] Step 101: Form the first amorphous semiconductor pattern and the second amorphous semiconductor pattern.

[0096] Figure 2 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first amorphous semiconductor pattern and the second amorphous semiconductor pattern.

[0097] In an exemplary embodiment, forming a first amorphous semiconductor pattern and a second amorphous semiconductor pattern includes: as follows Figure 2 As shown, a buffer layer 102 and an amorphous semiconductor thin film are first formed sequentially on a substrate 101; then, the amorphous semiconductor thin film is patterned to form a first amorphous semiconductor pattern 31 and a second amorphous semiconductor pattern 32 that are spaced apart along a direction parallel to the substrate.

[0098] In an exemplary embodiment, the substrate 101 can be a semiconductor substrate, such as a silicon substrate, or any substrate that serves as a support, not just a substrate, but a substrate formed by peripheral circuits on the substrate.

[0099] In one exemplary embodiment, the material of the buffer layer 102 may include oxides or nitrides.

[0100] In one exemplary embodiment, the material of the amorphous semiconductor thin film may include N-type doped amorphous silicon. For example, N-type doped amorphous silicon can be formed by implanting an N-type dopant, such as arsenic (As), into the amorphous silicon. For example, the doping concentration of arsenic (As) may be 1E20 to 5E20 / cm³. -3 .

[0101] In one exemplary embodiment, the amorphous semiconductor thin film can be grown using a low-temperature epitaxial process, with a growth temperature below 900°C to avoid impurity diffusion. In other embodiments, other doping methods, such as implantation or vapor diffusion techniques, can also be used.

[0102] Step 102: Form a metal thin film.

[0103] Figure 3 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after a metal thin film has been formed.

[0104] In one exemplary embodiment, forming a metal thin film includes: Figure 3 As shown, a metal thin film 201 covering a first amorphous semiconductor pattern 31 and a second amorphous semiconductor pattern 32 is deposited on a substrate 101.

[0105] In one exemplary embodiment, the material of the metal thin film 201 may include nickel.

[0106] In other embodiments of this application, the material of the metal thin film may also include other metal materials such as aluminum (Al), copper (Cu) or cobalt (Co).

[0107] In an exemplary embodiment, the thicknesses of both the first amorphous semiconductor pattern 31 and the second amorphous semiconductor pattern 32 are greater than or equal to twice the thickness of the metal thin film 201. For example, the ratio of the thickness of the first amorphous semiconductor pattern 31 to the thickness of the metal thin film 201 is 2:1, and the ratio of the thickness of the second amorphous semiconductor pattern 32 to the thickness of the metal thin film 201 is also 2:1.

[0108] Step 103: Form the first seed layer and the second seed layer.

[0109] Figure 4 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first seed layer and the second seed layer.

[0110] In one exemplary embodiment, forming the first seed layer and the second seed layer includes: Figure 4As shown, the metal thin film, the first amorphous semiconductor pattern 31, and the second amorphous semiconductor pattern 32 are first annealed. For example, the annealing temperature can be 350°C to 450°C, and the annealing time can be 10 minutes to 60 minutes, so that the first amorphous semiconductor pattern and the metal thin film react chemically to form the first seed layer 11; the second amorphous semiconductor pattern and the metal thin film react chemically to form the second seed layer 12; then, the unreacted metal thin film is removed to expose the first seed layer 11 and the second seed layer 12.

[0111] In an exemplary embodiment, when the material of the metal thin film 104 includes nickel (Ni) and the material of the first amorphous semiconductor pattern includes amorphous silicon, the material of the first seed layer 11 may include nickel silicide; when the material of the metal thin film 104 includes nickel (Ni) and the material of the second amorphous semiconductor pattern includes amorphous silicon, the material of the second seed layer 12 may include nickel silicide.

[0112] In other embodiments of this application, when the material of the metal thin film includes other metal materials such as aluminum (Al), copper (Cu) or cobalt (Co), after the annealing process, the metal thin film forms corresponding metal silicides with the first amorphous semiconductor pattern and the second amorphous semiconductor pattern, respectively. This application does not limit this.

[0113] Step 104: Form the first insulating layer, the isolation layer, and the second insulating layer.

[0114] Figure 5 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first insulating layer, the isolation layer, and the second insulating layer.

[0115] In an exemplary embodiment, forming the first insulating layer, the insulating layer, and the second insulating layer includes: as follows Figure 5 As shown, a first insulating layer 104, a first isolation layer 105, and a second insulating layer 106 covering the first seed layer and the second seed layer are sequentially deposited on the substrate 101.

[0116] In one exemplary embodiment, the first insulating layer 104 and the second insulating layer 106 are made of silicon oxide. The first insulating layer 105 is made of silicon nitride.

[0117] Step 105: Form the first via and the second via.

[0118] Figure 6 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first via and the second via.

[0119] In an exemplary embodiment, forming the first via and the second via includes: Figure 6As shown, a first via 21 and a second via 22 extending along a direction perpendicular to the substrate are formed in the stacked structure formed by the first insulating layer 104, the first isolation layer 105 and the second insulating layer 106. The first via 21 sequentially penetrates the second insulating layer 106, the first isolation layer 105 and the first insulating layer 104, exposing the first seed layer 11; the second via 22 sequentially penetrates the second insulating layer 106, the first isolation layer 105 and the first insulating layer 104, exposing the second seed layer 12.

[0120] Step 106: Form a quasi-single-crystal semiconductor or single-crystal semiconductor thin film.

[0121] Figure 7 This is a longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present disclosure after a thin film of a quasi-monocrystalline semiconductor or a monocrystalline semiconductor is formed during the manufacturing process.

[0122] In one exemplary embodiment, forming a quasi-single-crystal semiconductor or single-crystal semiconductor thin film includes: as Figure 7 As shown, a doped amorphous semiconductor film is first deposited on a stacked structure formed by a first insulating layer 104, a first isolation layer 105, and a second insulating layer 106. The doped amorphous semiconductor film covers the sidewalls and bottom walls of the first via 21 and the second via 22. Subsequently, the first seed layer 11 and the second seed layer 12 are used as induction layers to perform metal-induced crystallization annealing on the doped amorphous semiconductor film. For example, the induction crystallization annealing temperature can be 500°C to 575°C, and the induction crystallization annealing time can be 12 hours to 24 hours, so that the doped amorphous semiconductor film forms a metal-induced near-single-crystal semiconductor or single-crystal semiconductor film 202. Furthermore, during this crystallization annealing process, impurities in the doped amorphous semiconductor film are activated.

[0123] In some embodiments, the first seed layer and the second seed layer are used as induction layers, and laser induction is used to form a doped amorphous semiconductor thin film into a quasi-single crystal semiconductor thin film or a single crystal semiconductor thin film.

[0124] In one exemplary embodiment, the material used to dope the amorphous semiconductor thin film may include p-type doped amorphous silicon. For example, p-type doped amorphous silicon can be formed by implanting a p-type dopant, such as boron (P), into the amorphous silicon. For example, the doping concentration of boron (P) may be 1E18 to 1E19 / cm³. -3 .

[0125] In an exemplary embodiment, taking the materials of the first seed layer 11 and the second seed layer 12 as nickel silicide and the material of the doped amorphous semiconductor thin film as p-type doped amorphous silicon as an example, nickel silicide has a face-centered cubic (FCC) structure and a lattice mismatch of approximately 0.4%, which is close to the lattice structure of single-crystal silicon. During the crystallization annealing process, the first seed layer 11 and the second seed layer 12 are used as inducing layers to form a metal-induced quasi-single-crystal silicon thin film in the doped amorphous semiconductor thin film.

[0126] Step 107: Form the first conductive contact area and the second conductive contact area.

[0127] Figure 8 This is a longitudinal cross-sectional view of the semiconductor device according to an embodiment of the present disclosure after the formation of the first conductive contact region and the second conductive contact region during the manufacturing process.

[0128] In an exemplary embodiment, forming the first conductive contact region and the second conductive contact region includes: as follows Figure 8 As shown, the material of the first isolation layer 105 around the first via 21 and the material of the first isolation layer 105 around the second via 22 are first etched away to form a first channel exposing the outer wall of the single-crystal semiconductor or single-crystal semiconductor thin film 202 in the first via 21 and a second channel exposing the outer wall of the single-crystal semiconductor or single-crystal semiconductor thin film 202 in the second via 22; then, a first conductive contact area 41 and a second conductive contact area 42 are formed in the first channel and the second channel, respectively.

[0129] In an exemplary embodiment, the first conductive contact region 41 is made of a conductive material, such as titanium nitride. The first conductive contact region 41 is in contact with the outer wall of the single-crystal semiconductor or single-crystal semiconductor thin film 202 in the first via 21. The second conductive contact region 42 is made of a conductive material, such as titanium nitride. The second conductive contact region 42 is in contact with the outer wall of the single-crystal semiconductor or single-crystal semiconductor thin film 202 in the second via 22.

[0130] Step 108: Form the first lower transistor and the second lower transistor.

[0131] Figure 9 This is a longitudinal cross-sectional view of the semiconductor device manufactured according to an embodiment of the present disclosure after the formation of the first lower transistor and the second lower transistor.

[0132] In one exemplary embodiment, forming the first lower transistor and the second lower transistor includes: as follows Figure 9As shown, a single-crystal semiconductor or single-crystal semiconductor thin film is first etched to form a first semiconductor layer 51 disposed on the sidewall and bottom wall of the first via 21, and a second semiconductor layer 52 disposed on the sidewall and bottom wall of the second via 22. Subsequently, an atomic deposition process is used to form a first gate insulating layer 61 and a second gate insulating layer 62 in the first via 21 and the second via 22, respectively. Subsequently, a first gate 71 and a second gate 72 are filled in the first via 21 and the second via 22, respectively. The first semiconductor layer 51, the first gate insulating layer 61, and the first gate 71 form a first lower transistor, and the second semiconductor layer 52, the second gate insulating layer 62, and the second gate 72 form a second lower transistor.

[0133] In an exemplary embodiment, the first semiconductor layer 51 includes a bottom wall that contacts the first seed layer 11 and extends in a direction parallel to the substrate, a side wall that extends in a direction perpendicular to the substrate and contacts the first conductive contact region 41 on the side wall of the first via 21, and an extension portion located around the opening of the first via 21 and extending in a direction parallel to the substrate. The side wall of the first semiconductor layer 51 surrounds the side wall of the first gate 71. The second semiconductor layer 52 includes a bottom wall that contacts the second seed layer 12 and extends in a direction parallel to the substrate, a side wall that extends in a direction perpendicular to the substrate and contacts the second conductive contact region 42 on the side wall of the second via 22, and an extension portion located around the opening of the second via 22 and extending in a direction parallel to the substrate. The side wall of the second semiconductor layer 52 surrounds the side wall of the second gate 72.

[0134] In an exemplary embodiment, the first seed layer 11 and the second seed layer 12 serve as the first source / drain of the first lower transistor and the second lower transistor, respectively; the first conductive contact region 41 and the second conductive contact region 42 serve as the second source / drain of the first lower transistor and the second lower transistor, respectively.

[0135] In an exemplary embodiment, the first semiconductor layer 51 of the first lower transistor is a vertical annular channel (CAA channel), and the sidewalls of the first semiconductor layer 51 are disposed around the sidewalls of the first gate 71. The second semiconductor layer 52 of the second lower transistor is a vertical annular channel (CAA channel), and the sidewalls of the second semiconductor layer 52 are disposed around the sidewalls of the second gate 72.

[0136] In an exemplary embodiment, both the first gate insulating layer 61 and the second gate insulating layer 62 are made of high-K dielectric materials, i.e., dielectric materials with a dielectric constant K ≥ 3.9. The high-K dielectric material may include, but is not limited to, at least one of the following: aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0137] In an exemplary embodiment, both the first gate 71 and the second gate 72 can be a single-layer structure or a multi-layer stacked structure. For example, the materials of both the first gate 71 and the second gate 72 can be titanium nitride, or a multi-layer structure formed of titanium nitride and tungsten (W) or other conductive materials.

[0138] Step 109: Form the third gate, the fourth gate, the fifth gate, and the sixth gate.

[0139] Figure 10 This is a longitudinal cross-sectional view of the semiconductor device according to an embodiment of the present disclosure after the third gate, fourth gate, fifth gate and sixth gate are formed during the manufacturing process.

[0140] In an exemplary embodiment, forming the third gate, the fourth gate, the fifth gate, and the sixth gate includes: Figure 10 As shown, a third insulating layer 107 is first deposited on the first gate 71 and the second gate 72, and the third insulating layer 107 is polished to expose the side of the first gate 71 away from the substrate and the side of the second gate 72 away from the substrate. Subsequently, a third gate 73, a fourth gate 74, a fifth gate 75 and a sixth gate 76 are formed on the third insulating layer 107 at intervals along a direction parallel to the substrate. The side of the fourth gate 74 near the substrate contacts the exposed side of the first gate 71 away from the substrate, and the side of the fifth gate 75 near the substrate contacts the exposed side of the second gate 72 away from the substrate.

[0141] Step 110: Form the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer.

[0142] Figure 11 This is a longitudinal cross-sectional view of the semiconductor device according to an embodiment of the present disclosure after the formation of the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer.

[0143] In one exemplary embodiment, forming the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer includes: Figure 11 As shown, a second isolation layer 108 is first deposited on the third gate 73, the fourth gate 74, the fifth gate 75, and the sixth gate 76. The second isolation layer 108 is then polished to expose the side of the third gate 73, the fourth gate 74, the fifth gate 75, and the sixth gate 76 away from the substrate. Subsequently, a third gate insulating layer 63 is deposited on the second isolation layer 108 to cover the side of the third gate 73, the fourth gate 74, the fifth gate 75, and the sixth gate 76 away from the substrate. Subsequently, a third semiconductor layer 53, a fourth semiconductor layer 54, a fifth semiconductor layer 55, and a sixth semiconductor layer 56 are formed on the third gate insulating layer 63, spaced apart along a direction parallel to the substrate.

[0144] In one exemplary embodiment, the material of the third gate insulating layer 63 includes a Low-K dielectric material and / or a High-K dielectric material, wherein the High-K dielectric material is a dielectric material with a dielectric constant K ≥ 3.9. The Low-K dielectric material may include, but is not limited to, silicon oxide. The High-K dielectric material may include, but is not limited to, at least one of the following: aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0145] In an exemplary embodiment, the materials of the third semiconductor layer 53, the fourth semiconductor layer 54, the fifth semiconductor layer 55, and the sixth semiconductor layer 56 all include metal oxide semiconductors. The metal oxide semiconductor can be indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, metal oxides containing In and / or Sn, etc. When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 1E). -15 A to 1E -10 A), where 1E -15 A refers to 10 to the power of negative 15 amperes, 1E -10 A refers to 10 to the power of negative 10 amperes, thus ensuring the low refresh rate of the dynamic memory. It should be noted that the metal oxide material can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the transistor leakage current meets the requirements. Specific adjustments can be made according to the actual situation.

[0146] Step 111: Form the first and second terminals of the first upper transistor, the third and fourth terminals of the second upper transistor, the fifth and sixth terminals of the third upper transistor, and the seventh and eighth terminals of the fourth upper transistor.

[0147] The first and second terminals of the first upper transistor, the third and fourth terminals of the second upper transistor, the fifth and sixth terminals of the third upper transistor, and the seventh and eighth terminals of the fourth upper transistor include: Figure 1bAs shown, a first electrode 81 and a second electrode 82 are formed on the third semiconductor layer 53 at intervals along the direction parallel to the substrate; a third electrode 83 and a fourth electrode 84 are formed on the fourth semiconductor layer 54 at intervals along the direction parallel to the substrate; a fifth electrode 85 and a sixth electrode 86 are formed on the fifth semiconductor layer 55 at intervals along the direction parallel to the substrate; a seventh electrode 87 and an eighth electrode 88 are formed on the sixth semiconductor layer 56 at intervals along the direction parallel to the substrate; subsequently, various signal lines, such as word lines, first bit lines, second bit lines, power signal lines, and ground lines, are formed.

[0148] The semiconductor device manufacturing method in this embodiment induces the formation of the semiconductor layer of the lower transistor through a seed layer. The process is simple to implement, has low process cost, and is compatible with the fabrication process of CMOS back-end process.

[0149] This application also provides a method for manufacturing a semiconductor device, including:

[0150] A first seed layer and a second seed layer are formed on a substrate at intervals;

[0151] A first via and a second via are formed extending along the direction perpendicular to the substrate, wherein the first via exposes the first seed layer and the second via exposes the second seed layer;

[0152] A doped amorphous semiconductor thin film is formed on the inner wall of the first via and the second via. The doped amorphous semiconductor thin film is in contact with the exposed first seed layer through the first via and the doped amorphous semiconductor thin film is in contact with the exposed second seed layer through the second via.

[0153] The first and second seed layers are used as induction layers to induce crystallization annealing of doped amorphous semiconductor films to form quasi-single crystal semiconductor or single crystal semiconductor films.

[0154] Etching a single-crystal semiconductor or a single-crystal semiconductor thin film to form a first semiconductor layer disposed on the inner wall of the first via and a second semiconductor layer disposed on the inner wall of the second via;

[0155] A first gate insulating layer and a first gate are sequentially formed in the first via, and a second gate insulating layer and a second gate are sequentially formed in the second via;

[0156] A first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor are formed on the side of the first gate and the second gate away from the substrate, wherein the gate of the second upper transistor is in contact with the first gate, and the gate of the third upper transistor is in contact with the second gate.

[0157] In some embodiments, forming a first seed layer and a second seed layer spaced apart on the substrate includes:

[0158] An amorphous semiconductor thin film is formed on the substrate;

[0159] The amorphous semiconductor thin film is patterned to form a first amorphous semiconductor pattern and a second amorphous semiconductor pattern spaced apart along a direction parallel to the substrate.

[0160] A metal thin film is deposited covering the first amorphous semiconductor pattern and the second amorphous semiconductor pattern;

[0161] The metal thin film, the first amorphous semiconductor pattern, and the second amorphous semiconductor pattern are annealed to cause the first amorphous semiconductor pattern to react with the metal thin film to form a first seed layer; the second amorphous semiconductor pattern is then reacted with the metal thin film to form a second seed layer.

[0162] In some embodiments, the first seed layer and the second seed layer are used as induction layers to induce crystallization annealing of the doped amorphous semiconductor thin film to form a quasi-single crystal semiconductor or a single crystal semiconductor thin film. The induced crystallization annealing temperature is 500°C to 575°C, and the induced crystallization annealing time is 12 hours to 24 hours.

[0163] In some embodiments, the metal thin film, the first amorphous semiconductor pattern, and the second amorphous semiconductor pattern are annealed to cause the first amorphous semiconductor pattern to react with the metal thin film to form a first seed layer; and the second amorphous semiconductor pattern to react with the metal thin film to form a second seed layer. The annealing temperature is 350°C to 450°C, and the annealing time is 10 minutes to 60 minutes.

[0164] In some embodiments, forming a first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor on the side of the first gate and the second gate away from the substrate includes:

[0165] A third gate, a fourth gate, a fifth gate, and a sixth gate are formed on the side of the first gate and the second gate away from the substrate, and are spaced apart along a direction parallel to the substrate. The fourth gate is in contact with the side of the first gate away from the substrate, and the fifth gate is in contact with the side of the second gate away from the substrate.

[0166] A third gate insulating layer is deposited covering the third gate, fourth gate, fifth gate, and sixth gate on the side away from the substrate;

[0167] A third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer are formed on the third gate insulating layer at intervals along a direction parallel to the substrate. The third semiconductor layer overlaps with the orthogonal projection of the third gate on the substrate, the fourth semiconductor layer overlaps with the orthogonal projection of the fourth gate on the substrate, the fifth semiconductor layer overlaps with the orthogonal projection of the fifth gate on the substrate, and the sixth semiconductor layer overlaps with the orthogonal projection of the sixth gate on the substrate.

[0168] A first electrode and a second electrode are formed on the third semiconductor layer, spaced apart along a direction parallel to the substrate. The third gate, the third semiconductor layer, the first electrode, and the second electrode form a first upper transistor. A third electrode and a fourth electrode are formed on the fourth semiconductor layer, spaced apart along a direction parallel to the substrate. The fourth gate, the fourth semiconductor layer, the third electrode, and the fourth electrode form a second upper transistor. A fifth electrode and a sixth electrode are formed on the fifth semiconductor layer, spaced apart along a direction parallel to the substrate. The fifth gate, the fifth semiconductor layer, the fifth electrode, and the sixth electrode form a third upper transistor. A seventh electrode and an eighth electrode are formed on the sixth semiconductor layer, spaced apart along a direction parallel to the substrate. The sixth gate, the sixth semiconductor layer, the seventh electrode, and the eighth electrode form a fourth upper transistor.

[0169] This application also provides an electronic device comprising the semiconductor device described in any of the above embodiments, or a semiconductor device formed by a manufacturing method of the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0170] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, It includes at least one memory cell, the memory cell including a first transistor layer disposed on a substrate, and a second transistor layer disposed on the side of the first transistor layer away from the substrate; The first transistor layer includes a plurality of lower transistors disposed on the substrate. The semiconductor layer of the lower transistor includes a vertical channel. A seed layer is disposed on the side of the semiconductor layer of the lower transistor near the substrate. The seed layer is in contact with the semiconductor layer of the lower transistor. The material of the semiconductor layer of the lower transistor includes a single-crystal semiconductor or a single-crystal semiconductor. The second transistor layer includes a plurality of upper transistors; the gate of at least one upper transistor in the second transistor layer is connected to the gate of the lower transistor.

2. The semiconductor device according to claim 1, characterized in that, The seed layer is made of a metallized semiconductor material.

3. The semiconductor device according to claim 2, characterized in that, The seed layer is made of metal silicide.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor layer of the lower transistor is made of quasi-monocrystalline silicon or monocrystalline silicon.

5. The semiconductor device according to claim 1, characterized in that, The first transistor layer includes a first lower transistor and a second lower transistor, which are spaced apart along a direction parallel to the substrate. The first lower transistor includes a first semiconductor layer, a first gate, and a first conductive contact region that contacts the periphery of the first semiconductor layer. The first gate extends along a direction perpendicular to the substrate. The first semiconductor layer surrounds the sidewall of the first gate. A first seed layer is disposed on the side of the first semiconductor layer near the substrate. The material of the first semiconductor layer includes a quasi-single-crystal semiconductor or a single-crystal semiconductor. The second lower transistor includes a second semiconductor layer, a second gate, and a second conductive contact region that contacts the periphery of the second semiconductor layer. The second gate extends along a direction perpendicular to the substrate. The second semiconductor layer surrounds the sidewall of the second gate. A second seed layer is disposed on the side of the second semiconductor layer near the substrate. The material of the second semiconductor layer includes a quasi-single-crystal semiconductor or a single-crystal semiconductor.

6. The semiconductor device according to claim 5, characterized in that, The second transistor layer includes a first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor. The orthographic projections of the second upper transistor and the first lower transistor on the substrate overlap. The orthographic projections of the third upper transistor and the second lower transistor on the substrate overlap. The orthographic projections of the first upper transistor and the second lower transistor on the substrate do not overlap. The orthographic projections of the fourth upper transistor and the first lower transistor on the substrate do not overlap. The second upper transistor includes a fourth gate, a fourth semiconductor layer, a third electrode, and a fourth electrode. The fourth gate is located on the side of the fourth semiconductor layer near the substrate and is in contact with the first gate of the first lower transistor. The third electrode and the fourth electrode of the second upper transistor are respectively disposed on the fourth semiconductor layer and are spaced apart along a direction parallel to the substrate. The third upper transistor includes a fifth gate, a fifth semiconductor layer, a fifth electrode, and a sixth electrode. The fifth gate is located on the side of the fifth semiconductor layer near the substrate and is in contact with the second gate of the second lower transistor. The fifth electrode and the sixth electrode of the third upper transistor are respectively disposed on the fifth semiconductor layer and are spaced apart along a direction parallel to the substrate.

7. The semiconductor device according to claim 6, characterized in that, The first upper transistor includes a third gate, a third semiconductor layer, a first electrode, and a second electrode. The third gate is located on the side of the third semiconductor layer near the substrate. The first electrode and the second electrode of the first upper transistor are respectively disposed on the third semiconductor layer and are spaced apart along a direction parallel to the substrate. The fourth upper transistor includes a sixth gate, a sixth semiconductor layer, a seventh electrode, and an eighth electrode. The sixth gate is located on the side of the sixth semiconductor layer near the substrate. The seventh electrode and the eighth electrode of the fourth upper transistor are respectively disposed on the sixth semiconductor layer and are spaced apart along a direction parallel to the substrate.

8. The semiconductor device according to claim 7, characterized in that, It also includes a first bit line, a second bit line, a word line, a power signal line, and a ground line. The first conductive contact area of ​​the first lower transistor is connected to the third terminal of the second upper transistor, and the first gate of the first lower transistor is connected to the seventh terminal of the fourth upper transistor. The second conductive contact area of ​​the second lower transistor is connected to the sixth terminal of the third upper transistor, and the second gate of the second lower transistor is connected to the second terminal of the first upper transistor. The third gate of the first upper transistor is connected to the word line, and the first terminal of the first upper transistor is connected to the first bit line. The fourth terminal of the second upper transistor is connected to the ground line, and the fifth terminal of the third upper transistor is connected to the ground line; the sixth gate of the fourth upper transistor is connected to the word line, and the eighth terminal of the fourth upper transistor is connected to the second bit line; both the first seed layer and the second seed layer are connected to the power signal line.

9. The semiconductor device according to claim 1, characterized in that, The lower transistor is a p-channel field-effect transistor.

10. The semiconductor device according to claim 1, characterized in that, The upper transistor is an N-channel metal-oxide-semiconductor field-effect transistor.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor layer of the upper transistor includes a horizontal channel.

12. A method for manufacturing a semiconductor device, characterized in that, include: A first seed layer and a second seed layer are formed on a substrate at intervals; A first via and a second via are formed extending along the direction perpendicular to the substrate, wherein the first via exposes the first seed layer and the second via exposes the second seed layer; A doped amorphous semiconductor thin film is formed on the inner wall of the first via and the second via. The doped amorphous semiconductor thin film is in contact with the exposed first seed layer through the first via and the doped amorphous semiconductor thin film is in contact with the exposed second seed layer through the second via. The first and second seed layers are used as induction layers to induce crystallization annealing of doped amorphous semiconductor films to form quasi-single crystal semiconductor or single crystal semiconductor films. Etching a single-crystal semiconductor or a single-crystal semiconductor thin film to form a first semiconductor layer disposed on the inner wall of the first via and a second semiconductor layer disposed on the inner wall of the second via; A first gate insulating layer and a first gate are sequentially formed in the first via, and a second gate insulating layer and a second gate are sequentially formed in the second via; A first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor are formed on the side of the first gate and the second gate away from the substrate, wherein the gate of the second upper transistor is in contact with the first gate, and the gate of the third upper transistor is in contact with the second gate.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, Forming a first seed layer and a second seed layer spaced apart on a substrate includes: An amorphous semiconductor thin film is formed on the substrate; The amorphous semiconductor thin film is patterned to form a first amorphous semiconductor pattern and a second amorphous semiconductor pattern spaced apart along a direction parallel to the substrate. A metal thin film is deposited covering the first amorphous semiconductor pattern and the second amorphous semiconductor pattern; The metal thin film, the first amorphous semiconductor pattern, and the second amorphous semiconductor pattern are annealed to cause the first amorphous semiconductor pattern to react with the metal thin film to form a first seed layer; the second amorphous semiconductor pattern is then reacted with the metal thin film to form a second seed layer.

14. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The first and second seed layers are used as induction layers to induce crystallization annealing of doped amorphous semiconductor thin films to form quasi-single crystal semiconductor or single crystal semiconductor thin films. The induced crystallization annealing temperature is 500°C to 575°C, and the induced crystallization annealing time is 12 hours to 24 hours.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The metal thin film, the first amorphous semiconductor pattern, and the second amorphous semiconductor pattern are annealed to allow the first amorphous semiconductor pattern to react with the metal thin film to form a first seed layer; the second amorphous semiconductor pattern is then reacted with the metal thin film to form a second seed layer. The annealing temperature is 350°C to 450°C, and the annealing time is 10 minutes to 60 minutes.

16. The method for manufacturing a semiconductor device according to claim 12, characterized in that, Forming a first upper transistor, a second upper transistor, a third upper transistor, and a fourth upper transistor on the side of the first gate and the second gate away from the substrate includes: A third gate, a fourth gate, a fifth gate, and a sixth gate are formed on the side of the first gate and the second gate away from the substrate, and are spaced apart along a direction parallel to the substrate. The fourth gate is in contact with the side of the first gate away from the substrate, and the fifth gate is in contact with the side of the second gate away from the substrate. A third gate insulating layer is deposited covering the third gate, fourth gate, fifth gate, and sixth gate on the side away from the substrate; A third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer are formed on the third gate insulating layer at intervals along a direction parallel to the substrate. The third semiconductor layer overlaps with the orthogonal projection of the third gate on the substrate, the fourth semiconductor layer overlaps with the orthogonal projection of the fourth gate on the substrate, the fifth semiconductor layer overlaps with the orthogonal projection of the fifth gate on the substrate, and the sixth semiconductor layer overlaps with the orthogonal projection of the sixth gate on the substrate. A first electrode and a second electrode are formed on the third semiconductor layer, spaced apart along a direction parallel to the substrate. The third gate, the third semiconductor layer, the first electrode, and the second electrode form a first upper transistor. A third electrode and a fourth electrode are formed on the fourth semiconductor layer, spaced apart along a direction parallel to the substrate. The fourth gate, the fourth semiconductor layer, the third electrode, and the fourth electrode form a second upper transistor. A fifth electrode and a sixth electrode are formed on the fifth semiconductor layer, spaced apart along a direction parallel to the substrate. The fifth gate, the fifth semiconductor layer, the fifth electrode, and the sixth electrode form a third upper transistor. A seventh electrode and an eighth electrode are formed on the sixth semiconductor layer, spaced apart along a direction parallel to the substrate. The sixth gate, the sixth semiconductor layer, the seventh electrode, and the eighth electrode form a fourth upper transistor.

17. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 11, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 12 to 16.

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