An adapter device for chip testing and a chip testing system

Abstract

The application discloses an adapter device and a chip testing system for chip testing, and relates to the technical field of semiconductor testing. The adapter device comprises an adapter plate, a first fixing member, a second fixing member and a locking mechanism. The first and second adapter surfaces of the adapter plate are respectively provided with pin structures corresponding to the arrangement of the first and second chip pins, and are connected through internal lines according to a mapping rule. The first and second fixing members are respectively used for mounting the chips. The locking mechanism is used for detachably pressing and fixing the stacked chips and the adapter plate to establish electrical connection. The application realizes signal switching between different packaged chips through heterogeneous pin mapping, realizes efficient multiplexing of the test master chip through a detachable pressing structure, and guarantees the connection reliability through optional pressure self-adaptive design, thereby effectively solving the technical problems of difficult test adaptation of special-shaped packages, low equipment utilization and low test efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to an adapter and a chip testing system for chip testing. Background Technology

[0002] In the R&D, verification, production testing, and fault analysis phases of memory chips, especially LPDDR chips, a high-performance SOC chip (System-on-a-Chip) is typically used as a tester to apply test vectors to the memory chip under test (DUT) and verify its response. However, in actual testing scenarios, the following technical challenges are often encountered: high-end SOC chip resources with sufficient performance are often scarce and expensive; while the DUT may exist in various different package forms (such as 496-ball, 315-ball, 245-ball, etc.). Traditional solutions mainly rely on two methods: one is to customize a dedicated test board for each DUT package, soldering the SOC chip and the DUT onto the same board. This method results in the SOC chip being permanently bound, unable to be reused, with extremely low equipment utilization and high costs; the other is to use a simple adapter board, but traditional adapter boards usually have the same pin layout on both sides, which can only realize the connection between chips of the same model and cannot adapt to the signal conversion needs between irregularly shaped packages with completely different pin definitions and numbers.

[0003] When a high-performance SoC chip of the same model with pin compatibility with the memory chip under test is unavailable, engineers are often forced to use flying wires or temporary soldering for connections. This method not only results in poor test reliability and signal integrity, but is also cumbersome and inefficient, failing to meet the needs of batch testing or rapid verification. Therefore, existing technologies suffer from technical problems such as insufficient test system flexibility, low utilization of high-value SoC chips, difficulty in test compatibility between irregularly packaged chips, and low test efficiency. Summary of the Invention

[0004] This invention provides an adapter and a chip testing system for chip testing, in order to solve the problems that high-performance test master control chips cannot be reused among chips under test with different package types, and the resulting low testing efficiency, low equipment utilization, and high testing cost.

[0005] In a first aspect, an adapter for chip testing is provided, comprising:

[0006] The adapter board has a first adapter surface and a second adapter surface arranged opposite to each other. The first adapter surface is provided with a first pin structure corresponding to the pin arrangement of the first chip, and the second adapter surface is provided with at least one second pin structure corresponding to the pin arrangement of the second chip. The first pin structure is electrically connected to the corresponding second pin structure through the internal circuit of the adapter board.

[0007] A first fixing member is disposed on the first adapter surface and is used to install the first chip;

[0008] The second fastener is disposed on the second adapter surface and is used to install at least one second chip;

[0009] A locking mechanism is provided on the second fixing member to detachably press and fix the first chip, the adapter board and the second chip along the thickness direction of the adapter board, so that the first chip is electrically connected to the first pin structure and the second chip is electrically connected to the second pin structure.

[0010] In a second aspect, a chip testing system is provided, comprising a test circuit board and an adapter for chip testing as described above, wherein the test circuit board is fixedly connected to a first fixing member of the adapter for chip testing, a first chip is disposed between the first fixing member and the test circuit board, and the first chip is electrically connected to the test circuit board.

[0011] The aforementioned chip testing adapter and chip testing system utilizes an adapter board with a first pin structure and at least one second pin structure, internally connected to form a signal conversion channel. This allows first and second chips with different pin configurations to communicate electrically, solving the fundamental problem of incompatibility between irregularly packaged chips. Secondly, the layered layout of "first fixing component - adapter board - second fixing component" and a detachable locking mechanism enables mechanically detachable pressing and fixing of the entire connection interface. This replaces the soldering process required in traditional testing, allowing high-value first chips (such as test SOCs) to be safely and quickly reused for testing different second chips, significantly improving the utilization rate and flexibility of critical testing resources. Finally, the device's integrated compact design combines signal conversion, chip fixing, and electrical connection functions into a quickly detachable module, significantly simplifying the test preparation process, reducing operational complexity, and providing an efficient and universal hardware solution for chip R&D verification and production testing. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a converter device for chip testing according to an embodiment of the present invention.

[0014] Figure 2This is a schematic diagram of the structure of an adapter board for a chip testing adapter device according to an embodiment of the present invention.

[0015] Figure 3 This is another schematic diagram of the adapter board of the adapter device for chip testing in one embodiment of the present invention.

[0016] Figure 4 This is a schematic diagram of the structure of the first fixing member of the adapter device for chip testing in one embodiment of the present invention.

[0017] Figure 5 This is another structural schematic diagram of the first fixing member of the adapter device for chip testing in one embodiment of the present invention.

[0018] Figure 6 This is a schematic diagram of the structure of the second fixing member of the adapter device for chip testing in one embodiment of the present invention.

[0019] Figure 7 This is a schematic diagram of the clamping part of an adapter for chip testing in one embodiment of the present invention.

[0020] Figure 8 This is a schematic diagram of a chip testing system according to an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Please see Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of an adapter device for chip testing provided in an embodiment of the present invention. The adapter device for chip testing includes: an adapter plate 100, a first fixing member 200, a second fixing member 300, and a locking mechanism 400.

[0023] like Figure 2 and Figure 3As shown, the adapter board 100 has a first adapter surface 110 and a second adapter surface 120 facing each other. A first pin structure 111 is formed on the first adapter surface 110. The specific arrangement of the first pin structure 111 (such as the position, spacing, and number of pads or contacts) completely mirrors the pin (or solder ball) arrangement of the selected first chip (which is a test controller chip, such as a high-performance 496-ball BGA packaged system-on-a-chip). At least one second pin structure 121 is formed on the second adapter surface 120. Its arrangement completely mirrors the pin arrangement of the second chip under test (which is a chip under test, such as a 315-ball packaged LPDDR memory chip). The first pin structure 111 and the second pin structure 121 are connected according to pre-designed electrical rules via conductive lines (such as copper traces, vias, blind / buried vias, etc.) fabricated inside the adapter board 100, thereby "translating" the signal from the first chip and routing it to the second chip. For example, the high-current power supply pins (VDD, VDDQ) of the first chip are simultaneously connected to multiple power supply pins of two second chips in a star or mesh topology through the wide power plane inside the adapter board 100, ensuring power sharing and low impedance. This complex, asymmetrical pin-to-pin mapping enables a single physical adapter board 100 to perform logical "protocol conversion" and "signal routing" functions, which is the foundation for a single SoC to drive different packages or multiple memory chips.

[0024] The first fixing member 200 is made of an insulating material (such as PEEK engineering plastic) and is disposed on one side of the first adapter surface 110 of the adapter plate 100. The main function of the first fixing member 200 is to support and position the first chip. For example, it can be a base with a positioning frame to ensure that the first chip can be placed at a predetermined position relative to the first adapter surface 110.

[0025] The second fixing member 300, also made of insulating material, is disposed on one side of the second adapter surface 120 of the adapter plate 100. Its function is to support and position at least one second chip. For example, it can be a bracket with a receiving slot, allowing the second chip to be stably placed and aligned with the second pin structure 121 on the second adapter surface 120.

[0026] A locking mechanism 400 is mounted on the second fixing member 300. Its core function is to provide an operable and releasable mechanical clamping force. During operation, the locking mechanism 400 actuates, pressing and temporarily fixing the sequentially stacked first chip, adapter plate 100, and second chip along the thickness direction (i.e., the stacking direction) of the adapter plate 100. This clamping force forces the pins of the first chip into close contact with the first pin structure 111 on the first adapter surface 110, and simultaneously forces the pins of the second chip into close contact with the second pin structure 121 on the second adapter surface 120, thereby establishing a complete electrical connection path between the two originally independent chips. After testing, the locking mechanism 400 is operated to release the pressure, allowing the components to be separated without damage, achieving complete reuse of the first chip and the adapter.

[0027] This embodiment establishes a signal conversion channel by setting up an adapter board 100 with a first pin structure 111 and at least one second pin structure 121, and connecting the circuitry within it. This heterogeneous pin structure enables direct electrical communication between first and second chips with different pin arrangements, solving the fundamental problem of incompatibility testing between irregularly packaged chips. Secondly, the stacked layout of "first fixing component 200 - adapter board 100 - second fixing component 300" and a detachable locking mechanism 400 achieves mechanically detachable pressing and fixing of the entire connection interface. This replaces the soldering process required in traditional testing, allowing high-value first chips (such as test SOCs) to be safely and quickly reused for testing different second chips, greatly improving the utilization rate and testing flexibility of critical testing resources. Finally, the device, through its integrated and compact design, integrates signal conversion, chip fixing, and electrical connection functions into a quickly detachable module, significantly simplifying the test preparation process, reducing operational complexity, and providing an efficient and universal hardware solution for chip R&D verification and production testing.

[0028] Furthermore, based on the above embodiments, in other embodiments, such as Figure 2 and Figure 4 As shown, the first adapter surface 110 is provided with a protrusion 112, and the first pin structure 111 is provided on the protrusion 112. The side of the first fixing member 200 facing the adapter plate 100 is provided with a first groove 210 that matches the protrusion 112. The first groove 210 is provided with a through hole 220. The through hole 220 is directly opposite the pin of the first chip. When the protrusion 112 is inserted into the first groove 210, the first pin structure 111 passes through the through hole 220 and abuts against the pin of the first chip.

[0029] Specifically, a protrusion 112 is specially formed on the first adapter surface 110 of the adapter board 100. This protrusion 112 can be a stepped area formed by controlling the PCB lamination thickness, or it can be an additionally soldered rigid frame. The first pin structure 111 is disposed on the top surface of this protrusion 112. Correspondingly, a first groove 210 is machined on the side of the first fixing member 200 facing the adapter board 100 (i.e., the upper surface). The shape and size of the first groove 210 are precisely matched with the protrusion 112, like a "mortise and tenon" structure. At the bottom of the first groove 210, a plurality of through holes 220 are provided. The positions of these through holes 220 are precisely designed to correspond one-to-one with the positions of the key pin clusters (or all pins) placed on the first chip pin surface below. During assembly, the protrusion 112 is aligned and snapped into the first groove 210. This action not only completes the precise horizontal alignment of the adapter plate 100 and the first fixing member 200, but more importantly, it enables the first pin structure 111 on the top surface of the protrusion 112 to pass through the through hole 220 and directly approach or contact the corresponding pin of the first chip located below the first fixing member 200.

[0030] This embodiment achieves mechanical pre-alignment between the adapter plate 100 and the first fixing member 200 through the cooperation of the "protrusion 112-first groove 210", avoiding blind assembly. The design of the "through hole 220" provides a precise "contact channel" for the first pin structure and the chip pin. This triple positioning structure (groove to protrusion 112, through hole 220 to chip pin) greatly improves the alignment accuracy and first-time assembly success rate between the high-density BGA packaged chip and the adapter plate 100, effectively preventing poor contact or short circuits caused by misalignment, and is a key mechanical design to ensure the reliability of the device.

[0031] Furthermore, based on the above embodiments, in other embodiments, such as Figure 5 As shown, the side of the first fixing member 200 facing away from the adapter plate 100 is provided with a second groove 230 that matches the first chip, and the through hole 220 passes through the first groove 210 and the second groove 230.

[0032] Specifically, a second groove 230 is machined on the side of the first fixing member 200 facing away from the adapter plate 100 (i.e., the lower surface). The shape and size of the second groove 230 match the package outline of the first chip, and are used to accommodate and limit the first chip. Crucially, the through hole 220 described in the above embodiment does not end at the bottom of the first groove 210, but extends downwards through the entire first fixing member 200, that is, it simultaneously penetrates the bottoms of the first groove 210 and the second groove 230. This allows the first groove 210 and the second groove 230 to communicate through the through hole 220. During assembly, the first chip is placed in the second groove 230. At this time, the pin surface of the first chip (the side facing the adapter plate 100) is exposed through the through hole 220. When the protrusion 112 of the adapter plate 100 (carrying the first pin structure 111) engages with the first groove 210 of the first fixing member 200, the first pin structure 111 can directly achieve spatial alignment and physical contact with the corresponding pins on the pin surface of the first chip below through these through holes 220.

[0033] This embodiment provides stable and precise primary positioning of the first chip through the second recess 230. The through hole 220 connects the dual recesses, creating a "vertical unobstructed contact channel" from the pin structure of the adapter board 100 to the chip pins. This structure ensures that regardless of the thickness of the first chip, as long as it is placed within the second recess 230, its pins can be accurately aligned with the upper first pin structure 111 through the through hole 220, simplifying assembly requirements and improving the adaptability of the device.

[0034] Furthermore, based on the above embodiments, in other embodiments, such as Figure 6 As shown, the second fixing member 300 is provided with at least one through slot 310 for mounting the second chip, and each through slot 310 is directly opposite a second pin structure 121.

[0035] Specifically, the second fixing member 300 is provided with at least one through slot 310. This through slot 310 is a through-hole extending vertically, and its horizontal cross-sectional shape and size are slightly larger than the package outline of the second chip, facilitating chip insertion and removal. The vertical projection of each through slot 310 completely coincides with or is included within the projection of a second pin structure 121 on the second adapter surface 120 of the adapter plate 100. That is, each through slot 310 faces an independent second pin structure 121 on the lower adapter plate 100. When testing is required, the second chip is placed into the corresponding through slot 310 with its pin face down. Due to the guiding and limiting effect of the through slot 310, the second chip is quickly placed in the correct position, with its pin face facing and approximately aligned with the lower second pin structure 121.

[0036] This embodiment provides an extremely simple and quick installation method for the second chip through the through-slot 310 structure, allowing operators to place the chip without precise alignment. Simultaneously, this structure clearly defines the correspondence between each second chip and a specific second pin structure 121 on the adapter board 100, making it particularly suitable for scenarios involving parallel testing of multiple identical or dissimilar chips (by setting multiple through-slots 310 and corresponding second pin structures 121), laying a physical foundation for improving test throughput.

[0037] Furthermore, based on the above embodiments, in other embodiments, such as Figure 1 As shown, the locking mechanism 400 includes a base 410 and a cover 420. One end of the base 410 is hinged to one end of the cover 420. The base 410 is disposed on the second fixing member 300. The base 410 is provided with a through hole facing the receiving area of ​​the second fixing member 300 for mounting the second chip. The cover 420 is provided with a pressing part 421. When the cover 420 is closed on the base 410, the pressing part 421 passes through the through hole and presses the second chip.

[0038] Specifically, the locking mechanism 400 includes a base 410 and a cover 420. The base 410 is fixedly mounted on the upper surface of the second fixing member 300 (the side facing away from the adapter plate 100). One end of the cover 420 is connected to one end of the base 410 via a hinge, allowing the cover 420 to open and close like a door. Through holes 411 are provided on the base 410. The positions of these through holes 411 correspond vertically to the receiving areas (e.g., the through slot 310 in embodiment four) on the second fixing member 300 for mounting the second chip. A pressing part 421 is provided on the inner side of the cover 420 (the side facing the base 410). In the basic form, this pressing part 421 can be a rigid pressure block that matches the shape of the back of the chip. During operation, after the second chip is placed into the second fixing member 300, the cover 420 is closed. The cover 420 rotates around the hinge until it covers the base 410. At this time, the pressing part 421 (pressing block) on the cover 420 passes through the through hole 411 on the base 410, extends into the receiving area (through groove 310) of the second fixing member 300, and directly presses against the back side (non-pin side) of the second chip. A set locking force can be applied and maintained by the locking mechanism 400 (such as a buckle or knob provided on the other side of the cover 420). This force is transmitted through the stacked components, ultimately ensuring that all electrical contact interfaces are stable and reliable.

[0039] This embodiment utilizes a hinged flip-top design, making the locking operation very intuitive and quick, similar to closing a box, greatly simplifying the testing personnel's workflow. The through-hole design provides a precise operating channel for the clamping part 421, avoiding interference with other components. This locking method is simple in structure, low in cost, and highly reliable, making it ideal for testing environments that require frequent chip replacements.

[0040] Furthermore, based on the above embodiments, in other embodiments, such as Figure 7 As shown, the pressing part 421 includes a pressing block 4210 and a plurality of independently movable pressing needles 4211. The pressing block 4210 is provided with a plurality of guide holes 4212 that match the pressing needles 4211. Each guide hole 4212 is provided with an elastic element 4213. The top end of the pressing needle 4211 is disposed in the guide hole 4212 and connected to the elastic element 4213. The bottom end of the pressing needle 4211 passes through the through hole and presses the second chip when the cover 420 is closed on the base 410.

[0041] Specifically, the clamping part 421 on the cover 420 is designed as a pressure-adaptive clamping assembly. This assembly includes a clamping block 4210 fixed to the cover 420 and multiple independently movable pressure pins 4211. Multiple guide holes 4212 are machined on the clamping block 4210, their arrangement corresponding to the back region of the second chip. An elastic element 4213, such as a miniature compression spring, is placed within each guide hole 4212. The upper end of each pressure pin 4211 is positioned within the corresponding guide hole 4212 and rests on or is connected to the lower end of the elastic element 4213. The pressure pins 4211 can slide independently in the vertical direction (clamping direction) under the constraint of the guide holes 4212. When the cover 420 is closed, the bottom ends of all pressure pins 4211 simultaneously contact the back of the second chip. If the back of the chip is uneven or has thickness variations, each pressure pin 4211 will independently compress its corresponding elastic element 4213 according to the height of its local area, resulting in different compression amounts. According to Hooke's Law (F=k·x), the pressure applied to the chip by each pressure pin 4211 is proportional to the compression amount of its corresponding spring. By designing a suitable spring stiffness (k value), the pressure applied by each pressure pin 4211 can be kept within a relatively uniform range within a certain range of compression variation.

[0042] Traditional monolithic pressure blocks can cause stress concentration at high points on the chip, while insufficient pressure may occur at low points. In this embodiment, multiple independent floating pressure pins 4211, in conjunction with elastic elements 4213, constitute a "distributed micro-pressure servo system" that can automatically adapt to and compensate for microscopic unevenness and macroscopic thickness differences in the chip, ensuring that the entire back surface of the second chip receives uniformly distributed positive pressure. This directly translates to uniformity of contact pressure between the chip pin surface and the adapter board 100, greatly improving the stability and consistency of the electrical connection. It is particularly suitable for long-term testing or multi-chip parallel testing where contact reliability requirements are extremely high.

[0043] Furthermore, based on the above embodiments, in other embodiments, the bottom end of the pressure needle 4211 is provided with a flexible contact head.

[0044] Specifically, a flexible contact head is provided at the bottom end of the pressure pin 4211, that is, the end that directly contacts the back side of the second chip. This flexible contact head can be made of silicone rubber, polyurethane, or other materials with appropriate elasticity and insulation properties.

[0045] The flexible contact head in this embodiment provides multiple layers of protection. First, its soft texture prevents the hard pressure pins from scratching or damaging the packaging material on the back of the chip. Second, the flexible material better conforms to the minute undulations of the chip surface, further improving the uniformity of pressure distribution. Finally, it provides additional cushioning to prevent damage to the chip from impacts caused by excessively rapid operation or overload during the locking process. This small improvement significantly enhances the safety and durability of the device.

[0046] Furthermore, based on the above embodiments, in other embodiments, a first conductive element (not shown in the figure) is provided between the first pin structure 111 and the first chip, and a second conductive element (not shown in the figure) is provided between the second pin structure 121 and the second chip.

[0047] In this embodiment, to ensure a good and stable electrical connection under compressed conditions, a first conductive element is sandwiched between the pins of the first chip and the first pin structure 111 on the first transition surface 110 of the adapter plate 100. Similarly, a second conductive element is sandwiched between the pins of the second chip and the second pin structure 121 on the second transition surface 120 of the adapter plate 100.

[0048] This embodiment offers a key advantage by introducing a specialized conductive component as the connection medium. It fills the microscopic gap between the chip pins and the pads of the adapter board 100, ensuring full contact even on surfaces that are not perfectly flat. The conductive component typically possesses a degree of elasticity or plasticity, capable of absorbing mechanical stress and dimensional changes caused by thermal expansion and contraction, maintaining connection stability. Most importantly, it enables a detachable electrical connection, a fundamental characteristic that distinguishes it from permanent soldering (such as reflow soldering), and forms the technological basis for enabling rapid chip replacement and device reuse.

[0049] Furthermore, based on the above embodiments, in other embodiments, both the first conductive element and the second conductive element are conductive adhesives.

[0050] Specifically, both the first and second conductive components are preferably conductive adhesives, and more specifically, anisotropic conductive adhesive films. The anisotropic conductive adhesive film contains uniformly dispersed micron-sized conductive particles, which are separated from each other in an uncompressed state. When placed between the chip pins and the pin structure of the adapter board 100 and subjected to appropriate heat and pressure, the adhesive softens and flows upon heating, and the conductive particles are compressed together in the vertical direction (Z-axis) to form a conductive path, thereby achieving electrical connection in this direction. In the horizontal direction (XY-axis), since the particles are not directionally compressed, the adhesive remains insulating, effectively preventing short circuits between adjacent pins.

[0051] This embodiment utilizes anisotropic conductive adhesive, a perfect material for solving high-density, detachable interconnects. Its "vertical conduction and lateral insulation" characteristics perfectly suit the connection requirements of array packages such as BGA. The connection achieved through thermoforming has advantages such as low contact resistance, high reliability, and good consistency. Furthermore, this connection is reversible under certain conditions (such as reheating), making chip removal possible. Therefore, the use of conductive adhesive not only achieves excellent electrical performance but also thoroughly implements the core design concept of "detachable" in this invention.

[0052] Figure 8 A schematic diagram of the chip testing system according to an embodiment of the present invention is shown. Figure 8 As shown, the chip testing system includes a test circuit board 10 and an adapter 20 for chip testing according to any of the above embodiments. The test circuit board 10 is fixedly connected to a first fixing member of the adapter 20 for chip testing. A first chip is disposed between the first fixing member and the test circuit board 10, and the first chip is electrically connected to the test circuit board 10.

[0053] Specifically, the test circuit board 10 is a motherboard that integrates power supply circuitry, a controller (such as an MCU or FPGA), communication interfaces (such as USB or Ethernet), a clock source, etc., providing all the necessary power, control, and low-speed signals for testing. The adapter is mechanically fixed to a predetermined position on the test circuit board 10 via its first fixing member 200. A first chip (test SOC) is mounted between the first fixing member 200 and the test circuit board 10, and the back side of the first chip (the non-pin side, or another set of pins) is electrically connected (e.g., via soldering or a socket) to a corresponding circuit on the test circuit board 10, thereby enabling it to obtain all the resources required for operation from and be controlled by the test circuit board 10.

[0054] The host computer sends test commands and programs to the first chip via the test circuit board 10. The first chip, acting as the test execution engine, initiates high-speed read and write operations to the second chip (the memory chip under test) installed on the adapter device through the bridge connected inside the adapter board. The response data from the second chip is then returned via the original path, captured by the first chip, and uploaded to the host computer via the test circuit board 10 for result analysis and judgment.

[0055] This embodiment combines an innovative adapter with a universal test motherboard to construct a complete, efficient, and modular testing solution. The test circuit board 10 carries stable and universal basic functions, while the adapter becomes a "quick-change smart fixture" for specific chips under test. This architecture maximizes the utilization and extends the lifespan of the core resources of the test system (expensive high-performance SOCs and test motherboards). By adapting to new chip packages simply by replacing or adjusting the adapter, it significantly reduces the total cost of ownership and maintenance complexity of the test system, demonstrating outstanding industrial application value and economic efficiency.

[0056] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An adapter for chip testing, characterized in that, include: The adapter board has a first adapter surface and a second adapter surface arranged opposite to each other. The first adapter surface is provided with a first pin structure corresponding to the pin arrangement of the first chip, and the second adapter surface is provided with at least one second pin structure corresponding to the pin arrangement of the second chip. The first pin structure is electrically connected to the corresponding second pin structure through the internal circuit of the adapter board. A first fixing member is disposed on the first adapter surface and is used to install the first chip; A second fastener is disposed on the second adapter surface and is used to mount at least one of the second chips. A locking mechanism is provided on the second fixing member for detachably pressing and fixing the first chip, the adapter plate and the second chip along the thickness direction of the adapter plate, so that the first chip is electrically connected to the first pin structure and the second chip is electrically connected to the second pin structure. A locking mechanism is provided on the second fixing member for detachably pressing and fixing the first chip, the adapter plate and the second chip along the thickness direction of the adapter plate, so that the first chip is electrically connected to the first pin structure and the second chip is electrically connected to the second pin structure. The first adapter surface is provided with a protrusion, the first pin structure is provided on the protrusion, the side of the first fixing member facing the adapter plate is provided with a first groove that matches the protrusion, the first groove is provided with a through hole, the through hole is directly opposite the pin of the first chip, when the protrusion is inserted into the first groove, the first pin structure passes through the through hole and abuts against the pin of the first chip. The side of the first fixing member facing away from the adapter plate is provided with a second groove that matches the first chip, and the through hole passes through the first groove and the second groove; The second fastener is provided with at least one through slot for mounting the second chip, and each through slot is directly opposite a second pin structure. The locking mechanism includes a base and a cover. One end of the base is hinged to one end of the cover. The base is disposed on the second fixing member. The base is provided with a through hole facing the receiving area of ​​the second fixing member for mounting the second chip. The cover is provided with a pressing part. When the cover is closed on the base, the pressing part passes through the through hole and presses the second chip.

2. The adapter for chip testing according to claim 1, characterized in that, The pressing part includes a pressing block and multiple independently movable pressing needles. The pressing block is provided with multiple guide holes that match the pressing needles. Each guide hole is provided with an elastic element. The top end of the pressing needle is disposed in the guide hole and connected to the elastic element. When the cover is closed on the base, the bottom end of the pressing needle passes through the through hole and presses the second chip.

3. The adapter for chip testing according to claim 2, characterized in that, The bottom end of the pressure needle is provided with a flexible contact head.

4. The adapter for chip testing according to claim 1, characterized in that, A first conductive element is disposed between the first pin structure and the first chip, and a second conductive element is disposed between the second pin structure and the second chip.

5. The adapter for chip testing according to claim 4, characterized in that, Both the first conductive component and the second conductive component are conductive adhesives.

6. A chip testing system, characterized in that, It includes a test circuit board and an adapter for chip testing as described in any one of claims 1-4, wherein the test circuit board is fixedly connected to a first fixing member of the adapter for chip testing, the first chip is disposed between the first fixing member and the test circuit board, and the first chip is electrically connected to the test circuit board.

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