Analysis method and device for chip

Abstract

The invention relates to an analysis method and device for a chip. The method comprises the steps that data capture is conducted on latest results of a target chip by different analysis tools to obtain target data, the number of the analysis tools is at least two, and analysis conducted on the target chip by the analysis tools is different; taking the target data corresponding to each analysis tool as an analysis basis and sending the analysis basis to other analysis tools; performing anomaly evaluation based on the target data to obtain an evaluation result; under the condition that the evaluation result is abnormal, the abnormal evaluation result serves as an analysis basis for optimization and is sent to a first tool in the analysis tools, and all the analysis tools are controlled to end analysis until an end condition is met; the end condition is that the evaluation result is normal. The accuracy and speed of chip analysis are remarkably improved, multi-dimensional linkage analysis is achieved, and the method is suitable for multiple research and development stages of chip development and wide in application range.

Description

Technical Field

[0001] This disclosure relates to the field of chip development technology, and in particular to an analysis method and apparatus for chips. Background Technology

[0002] In the chip development process, continuous problem analysis and design optimization are necessary to ensure chip yield, lifespan, and stability. In related technologies, different tools can be used for different types of chip analysis and testing. However, individual tools can only perform their specific type of analysis, providing researchers with limited results. Furthermore, sequential analysis between tools can lead to inaccuracies and potential risks. Therefore, improving the accuracy of chip analysis, avoiding potential risks, and expanding the analytical dimensions are urgent technical challenges that need to be addressed. Summary of the Invention

[0003] In view of this, this disclosure proposes an analysis method and apparatus for chips.

[0004] According to one aspect of this disclosure, an analysis method for a chip is provided, the method comprising:

[0005] The latest results of different analysis tools on the target chip are captured separately to obtain the target data corresponding to each analysis tool. The analysis tools include at least two types, and each analysis tool performs different analyses on the target chip.

[0006] The target data corresponding to each of the aforementioned analysis tools is sent to other analysis tools as the basis for analysis.

[0007] An evaluation result is obtained by performing anomaly assessment based on the target data, and the evaluation result is either normal or abnormal.

[0008] If the evaluation result is abnormal, the abnormal evaluation result is sent to the first tool in the analysis tool as the basis for optimization analysis, until the termination condition is met, then each analysis tool is controlled to end the analysis.

[0009] The termination condition is that the evaluation result is normal.

[0010] In one possible implementation, the analysis tool includes at least two of a physical implementation tool, a timing analysis tool, and a voltage drop analysis tool; the first tool is the physical implementation tool.

[0011] The target data includes at least one of the following: first data obtained by capturing the physical implementation results output by the physical implementation tool, second data obtained by capturing the timing analysis results output by the timing analysis tool, and third data obtained by capturing the power network analysis results output by the voltage drop analysis tool.

[0012] In one possible implementation, the latest results of different analysis tools on the target chip are captured separately to obtain the target data corresponding to each analysis tool, including:

[0013] Based on the respective data collection criteria of each analysis tool, the latest results of the target chip obtained by different analysis tools are collected to obtain the target data corresponding to each analysis tool.

[0014] In one possible implementation, the method further includes:

[0015] Based on the current development stage of the target chip and / or the data requirements of each of the analysis tools, determine the different target data requirements that each analysis tool needs to capture;

[0016] The development phase includes at least one of the following: layout planning phase, routing phase, final approval phase, and initial tape-out and debugging phase;

[0017] The crawling criteria corresponding to the analysis tool include the corresponding requirement attributes.

[0018] In one possible implementation, the target data corresponding to each of the aforementioned analysis tools is sent as the basis for analysis to other analysis tools, including:

[0019] Based on the required attributes indicated by the crawling criteria of each of the aforementioned analysis tools, the data in the target data is sent to the matching analysis tool according to the attributes.

[0020] In one possible implementation, the method further includes:

[0021] The window size for data capture for the second tool is determined based on the preset capture range;

[0022] The second tool includes the time series analysis tool and / or the voltage drop analysis tool;

[0023] The crawling criteria corresponding to the analysis tool include the window size of the analysis tool.

[0024] According to another aspect of this disclosure, an analysis apparatus for a chip is provided, the apparatus comprising:

[0025] The data capture module is used to capture the latest results of different analysis tools on the target chip to obtain the target data corresponding to each analysis tool. The analysis tools include at least two types, and each analysis tool performs different analyses on the target chip.

[0026] The data distribution module is used to send the target data corresponding to each of the aforementioned analysis tools as the basis for analysis to other analysis tools;

[0027] An anomaly assessment module is used to perform anomaly assessment based on the target data to obtain an assessment result, wherein the assessment result is normal or abnormal.

[0028] The analysis control module is used to send the abnormal evaluation result as the basis for optimization analysis to the first tool in the analysis tools when the evaluation result is abnormal, and to control each analysis tool to end the analysis when the termination condition is met.

[0029] The termination condition includes the evaluation result being normal.

[0030] In one possible implementation, the analysis tool includes at least two of a physical implementation tool, a timing analysis tool, and a voltage drop analysis tool; the first tool is the physical implementation tool.

[0031] The target data includes at least one of the following: first data obtained by capturing the physical implementation results output by the physical implementation tool, second data obtained by capturing the timing analysis results output by the timing analysis tool, and third data obtained by capturing the power network analysis results output by the voltage drop analysis tool.

[0032] In one possible implementation, the anomaly assessment module includes:

[0033] The evaluation submodule is used to extract data from the latest results of the target chip by different analysis tools according to the extraction criteria corresponding to each analysis tool, so as to obtain the target data corresponding to each analysis tool.

[0034] In one possible implementation, the device further includes:

[0035] The attribute determination module is used to determine the required attributes of different target data that each of the analysis tools needs to capture, based on the current development stage of the target chip and / or the data requirements of each analysis tool.

[0036] The development phase includes at least one of the following: layout planning phase, routing phase, final approval phase, and initial tape-out and debugging phase;

[0037] The crawling criteria corresponding to the analysis tool include the corresponding requirement attributes.

[0038] In one possible implementation, the data distribution module includes:

[0039] The distribution submodule is used to send the data in the target data to the matching analysis tool according to the required attributes indicated by the crawling criteria of each analysis tool.

[0040] In one possible implementation, the device further includes:

[0041] The window determination module is used to determine the window size for data capture by the second tool based on a preset capture range.

[0042] The second tool includes the time series analysis tool and / or the voltage drop analysis tool;

[0043] The crawling criteria corresponding to the analysis tool include the window size of the analysis tool.

[0044] According to another aspect of this disclosure, an analysis apparatus for a chip is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method described above.

[0045] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0046] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0047] The analysis method and device for a chip provided by an embodiment of the present disclosure. Data scraping is respectively performed on the latest results output by each analysis tool for analyzing a target chip to obtain target data corresponding to each analysis tool. There are at least two analysis tools, and the analyses performed by each analysis tool on the target chip are different; the target data corresponding to each analysis tool is sent to other analysis tools as an analysis basis; an anomaly assessment for the target chip is performed based on the target data to obtain an assessment result; in the case where the assessment result is abnormal, the abnormal assessment result is sent to the first tool among the analysis tools as an analysis basis for optimization until the end condition is met, and then each analysis tool is controlled to end the analysis; where the end condition includes that the assessment result is normal. This significantly improves the accuracy and speed of the analysis for the chip, and due to expanding the dimension of the analysis basis of each analysis tool and performing result cross-verification, multi-dimensional linkage analysis is achieved, which is applicable to multiple R & D stages of chip development and has a wide range of applications.

[0048] Other features and aspects of the present disclosure will become clear from the following detailed description of the exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings, which are included in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the present disclosure together with the specification and are used to explain the principles of the present disclosure.

[0050] Figure 1 The flowchart showing the analysis method for a chip according to an embodiment of the present disclosure.

[0051] Figure 2 s The block diagram showing a device 1900 for analyzing a chip according to an exemplary embodiment. DETAILED DESCRIPTION

[0052] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0053] As used herein, the terms "comprising," "including," "having," or variations thereof are open-ended and include one or more stated features, wholes, elements, steps, components, or functions, but do not exclude the existence or addition of one or more other features, wholes, elements, steps, components, functions, or groups thereof.

[0054] When an element is referred to as being "connected," "coupled," "responsive," or variations thereof to another element, it can be directly connected, coupled, or responsive to the other element, or there may be intervening elements.

[0055] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Thus, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0056] As used herein, the word "exemplary" means "serving as an example, embodiment, or illustration". Any embodiment illustrated herein as "exemplary" should not necessarily be construed as superior or better than other embodiments.

[0057] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0058] To solve the above technical problems, embodiments of the present disclosure provide an analysis method and apparatus for a chip. Data capture is respectively performed on the latest results output by each analysis tool for analyzing a target chip to obtain target data corresponding to each analysis tool. There are at least two analysis tools, and the analyses performed by each analysis tool on the target chip are different; the target data corresponding to each analysis tool is sent to other analysis tools as an analysis basis; an anomaly assessment for the target chip is performed based on the target data to obtain an assessment result; in the case where the assessment result is abnormal, the abnormal assessment result is sent to the first tool among the analysis tools as an analysis basis for optimization until the end condition is met, and then each analysis tool is controlled to end the analysis; wherein, the end condition includes that the assessment result is normal. This significantly improves the accuracy and speed of the analysis of the chip, and due to expanding the dimension of the analysis basis of each analysis tool and performing result cross-verification, multi-dimensional联动 analysis is achieved, which is applicable to multiple R & D stages of chip development and has a wide application range.

[0059] Embodiments of the present disclosure provide an analysis method for a chip, as Figure 1 shown, the method includes steps S101-step S106. The method can be applied to the process of analyzing a target chip and can be applied to a device capable of executing the method. In some embodiments, the device can run and / or control analysis tool 10.

[0060] Among them, the analysis tool 10 used in the process of analyzing the target chip can include at least two, for example, Figure 1The analysis tool 10 includes analysis tool 1, analysis tool 2, ..., analysis tool n. Each analysis tool 10 can perform pre-set analysis processing based on the received analysis data. The analysis performed by each analysis tool 10 on the target chip is different.

[0061] For example, the analysis tool 10 may include at least two of the following: a Physical Implementation Tool (PR), a Static Timing Analysis Tool (STA), and an Inverse Voltage Drop Analysis Tool (IR). The PR tool is used to implement the entire physical implementation process from the netlist of the target chip to GDSII (Graphic Data System II), including floorplanning, cell placement, clock tree synthesis (CTS), and routing. The STA tool can be used for timing constraints (setup time / hold time) of the target chip, identifying critical path timing margins and timing violations. The IR drop analysis tool is used to simulate voltage fluctuations (IR drop) and electromigration (EM) risks in the power network, generating voltage hotspot maps and current density reports.

[0062] In step S101, as Figure 1 As shown, data is captured from the latest results (i.e., the latest output analysis results for the target chip) of different analysis tools 10 to obtain the target data corresponding to each analysis tool 10. Potential problems can be discovered through the target data, allowing for earlier problem analysis and resolution, saving development costs and shortening the development cycle.

[0063] In step S102, the target data corresponding to each analysis tool 10 is sent to other analysis tools as the basis for analysis. This expands the basis for analysis performed by each analysis tool 10, enriches the dimensions of the basis for analysis performed by each analysis tool 10, and enables the current analysis tool to verify the results of other analysis tools based on the received target data, as well as to achieve mutual verification of results.

[0064] In the case where the analysis tools include physical implementation tools, timing analysis tools, and voltage drop analysis tools, the target data may include at least one of the following: first data obtained by capturing the latest physical implementation results output by the physical implementation tools, second data obtained by capturing the latest timing analysis results output by the timing analysis tools, and third data obtained by capturing the latest power network analysis results output by the voltage drop analysis tools.

[0065] In step S103, an anomaly assessment is performed based on the target data to obtain an assessment result, which is either normal or abnormal.

[0066] Specifically, an anomaly assessment of the target chip can be performed based on at least one of the target data corresponding to each of the analysis tools to obtain the assessment result.

[0067] In step S104, it is determined whether the evaluation result is abnormal. If the evaluation result is abnormal, the first tool in the analysis tool 10 is executed to send the evaluation result as the basis for optimization analysis. If the evaluation result is normal, step S105 is executed. Sending the abnormal evaluation result to the first tool allows for real-time optimization and adjustment of chip design layout, routing, etc., based on the anomaly. This enables early analysis and resolution of potential problems, shortens the number of analysis rounds, reduces iteration cycles, and saves R&D costs. In some embodiments, the first tool may include at least a physical implementation tool.

[0068] In step S105, it is determined whether the termination condition is met. If it is, step S106 is executed to control each of the analysis tools 10 to end the analysis. The termination condition may include an evaluation result of "normal". In some embodiments, the termination condition may also include the current analysis round being greater than or equal to a preset round, etc., which is not limited in this disclosure. In step S106, a termination command may be sent to each analysis tool to stop the analysis. Each analysis tool, after receiving target data captured from other analysis tools, if no termination command is received, can perform the next round of analysis based on the current analysis criteria, iterating cyclically until it stops.

[0069] In this embodiment, the analysis of each analysis tool 10 can be monitored. After determining that any analysis tool 10 has finished its analysis and output its analysis result, data is captured from the analysis result output by that analysis tool 10 to obtain the target data corresponding to that analysis tool 10. In some embodiments, the method may also include: receiving the analysis results output by each analysis tool 10, and after receiving the analysis result of any analysis tool 10, using that analysis result as the latest result to capture the target data corresponding to that analysis tool 10. In this way, the target data of each analysis tool 10 can be captured through multiple data captures. Where multiple analysis results are output simultaneously by monitoring and / or receiving analysis results, data capture for each analysis result can also be performed in parallel, and this disclosure does not limit this.

[0070] In some embodiments, step 101 may include: according to the capture criteria corresponding to each of the analysis tools 10, capturing the latest results of different analysis tools 10 for the target chip, and obtaining the target data corresponding to each analysis tool 10. This is because different analysis tools 10 have different functions, and the analysis results they produce also differ. Furthermore, since the target data will be used as the analysis criteria by other analysis tools 10 in the future, it is necessary to predetermine the capture criteria for each analysis tool 10, and then capture data based on the capture criteria to ensure that the target data can meet the analysis and usage requirements of other analysis tools 10.

[0071] In one possible implementation, the method may further include: determining the required attributes of the target data to be captured by each of the analysis tools 10, based on the current development stage of the target chip and / or the data requirements for analysis by each of the analysis tools 10. The capturing criteria corresponding to each analysis tool 10 may include the required attributes of the target data to be captured by the analysis tool 10.

[0072] The attributes of the data can be characteristic information that distinguishes different data, such as the type of data, purpose, name, and attributes of the cell to which it belongs; this disclosure does not impose any restrictions on this. Requirement attributes can include one or more of the attributes of the data; this disclosure does not impose any restrictions on this.

[0073] The development phase can include at least one of the following: Floorplan (FP), Routing (R0), Final Sign-Off (FSO), and First Tape-out Debug (T0 debug). The required attributes of the target data to be captured can be set according to the focus of R&D personnel at different development stages, thus meeting the analytical needs of different development stages and expanding the applicability of the method.

[0074] In one possible implementation, the method may further include: determining the window size for data capture by the second tool based on a preset capture range. The second tool may include the time series analysis tool and / or the voltage drop analysis tool. The capture criteria corresponding to the analysis tool 10 may further include the window size corresponding to the analysis tool 10.

[0075] The window size can refer to the area within the target chip's layout corresponding to the data being captured. The window size can be defined by physical coordinates, or it can be limited based on the range of associated cells of a specific functional cell; this disclosure does not impose such limitations. For example, the window size for data capture can be all cells governed by a PSO (Power Shut-Off cell).

[0076] In some embodiments, after determining the data scraping criteria, including the window size and requirement attributes corresponding to each analysis tool, the method may further include determining a corresponding scraping script for each analysis tool 10, and then controlling the corresponding scraping script to scrape data from each analysis tool 10. Specifically, a general script can be pre-designed, and the criteria for data scraping by each general script can be marked. Then, after determining the scraping criteria for the analysis tools, scripts in the general scripts whose criteria match the scraping criteria are identified as candidate scripts, and these candidate scripts are displayed for users, such as developers, to select a scraping script from among them. Alternatively, user-uploaded scraping scripts can be received; this disclosure does not limit this.

[0077] In one possible implementation, since the required attributes of the data for analysis by the analysis tools 10 differ, step S102 may include: sending the data in each target data set to the matching analysis tool according to the required attributes indicated by the capture criteria of each analysis tool 10. In this way, selectively distributing the captured target data according to the actual required attributes of the analysis tools 10 improves the speed and efficiency of target data transmission compared to sending all target data. Furthermore, because the target data is sent on demand, the analysis tools 10 can directly utilize the target data, eliminating the time spent extracting the data they need from the target data, thereby also improving the overall speed and efficiency of the analysis.

[0078] In one possible implementation, in step S103, different anomaly evaluation rules can be set for different target data selections to perform anomaly evaluation based on these rules. For example, a single anomaly evaluation rule can be set for the target data corresponding to each analysis tool 10, M anomaly evaluation rules can be set for the target data corresponding to M analysis tools 10 (M can be a positive integer greater than or equal to 2), and a full-item anomaly evaluation rule can be set for the target data corresponding to all analysis tools 10. This allows for anomaly evaluation from different dimensions, achieving multi-dimensional, interconnected, and mutually verifiable accurate evaluation of the target chip.

[0079] For example, when the analysis tools include physical implementation tools, timing analysis tools, and voltage drop analysis tools, the large logic cone structure can be extracted as target data from the analysis results of the physical implementation tool. Timing violations can be extracted from the analysis results of the timing analysis tool, and electrical characteristics can be extracted from the analysis results of the voltage drop analysis tool as target data. If anomalies are found based on these three types of target data, they can be fed back to the physical implementation tool (the first tool) for routing and layout optimization. Interlocking optimization adjustments can also be performed between the timing analysis tool and the voltage drop analysis tool. For instance, if the target data corresponding to the voltage drop analysis tool is abnormal but the timing violations are not critical, the anomaly can be resolved by moving the position in the layout of the physical implementation tool. Conversely, if the timing violations are critical and the electrical characteristics are problematic, they can be addressed by enhancing the power network in the physical implementation tool.

[0080] In this embodiment, the analysis basis of the analysis tool 10 includes not only the target data from other analysis tools 10 (the analysis basis of some analysis tools 10 also includes abnormal evaluation results), but also other information depending on the type of analysis tool 10.

[0081] For example, the analysis basis for physical implementation tools may also include: design constraints for the target chip, such as RTL (Register-Transfer Level) code, SDC (Synopsys DesignConstraints) timing constraints (such as clock frequency, multi-cycle paths), and physical constraints (such as macrocell locations, forbidden routing regions). Process data for the target chip, such as LEF (Library Exchange Format, used to define cell physical attributes) and TECH (Technology File) files (including process rules, such as minimum linewidth). Target data received from other analysis tools may include critical path reports output by timing analysis tools and IR hotspot regions (used for iterative optimization) from voltage drop analysis tools. Analysis results output by physical implementation tools may include: physical layout files for the target chip, such as DEF (Design Exchange Format, containing cell locations and routing information) and GDSII (layout data for tape-out). Parasitic parameters of the target chip, such as SPEF files (Standard Parasitic Exchange Format, recording net resistance and capacitance). The physical analysis report for the target chip includes: cell density (e.g., cell density in a 100-site window), routing congestion diagram, and power network topology. Data extracted from the physical implementation tool may include the netlist corresponding to the target chip (containing cell connectivity), parasitic parameters, cell layout in the DEF file, and power network topology in GDSII or DEF.

[0082] The analysis basis for timing analysis tools can also include: library files, such as .db (timing library, containing delay data of cells under different PVT (Process, Voltage, Temperature) conditions). Target data received from other analysis tools can include netlists, parasitic parameters, and cell layouts in DEF files from physical implementation tools. The analysis results output by timing analysis tools can include: timing reports, including a critical path list, setup / hold violations, and timing slack; path attributes, including cell composition, fanout, and transition time for each path; multi-scenario analysis results, including timing performance under different process corners, voltages, and temperatures; and SAIF (Switching Activity Interchange Format, a standard file used to describe signal switching activity) files. The target data captured by timing analysis tools can include SAIF files, critical path topology information, timing margin distribution, clock tree structure information (clock skew and jitter data from STA analysis, which help physical tools optimize buffer positions and drive strength during the clock tree synthesis (CTS) stage to ensure that clock signals arrive at the triggers synchronously), etc.

[0083] The analysis basis for voltage drop analysis tools may also include: process parameters, such as metal layer resistivity and power supply voltage standards (e.g., VDD=1.0V); timing constraints, such as the clock frequency of the critical path, used to calculate peak current. Target data captured from other analysis tools may include power network topology in GDSII or DEF, SAIF files, etc. Analysis results output by voltage drop analysis tools may include: IR Drop hotspot maps, regions with voltages below thresholds (e.g., regions with VDD<0.9V); electromigration reports, metal lines with excessive current density (e.g., power rail current >1mA / μm); power network recommendations, such as decoupling capacitor (DECAP) requirements (e.g., DECAP type and total value for a specific window size), and power rail width adjustment schemes. Target data captured by voltage drop analysis tools may include regional current density distribution, IR Drop hotspot coordinates, electromigration (EM) risk reports, etc., for physical implementation tools; and lists of voltage-sensitive cells, path voltage fluctuation curves, PSO cell power states, etc., for timing analysis tools.

[0084] For example, during the debugging and analysis of product A in the x development phase, it was found that the registers (bits) would have problems during the "spatial pattern generation" test. The fail points (i.e., the registers that malfunctioned) have the following characteristics:

[0085] Feature 1: Low-order bits do not fail, but some high-order bits fail. For example, bits [7:0] are normal, but some bits in bits [15:8] fail.

[0086] Feature 2: The cell corresponding to the fail bit is clustered (not randomly scattered) in the chip layout, that is, the faulty bit is physically clustered on the chip.

[0087] In related technologies, because PR, STA, and IR each perform single-dimensional detection and analysis, the following analytical situations arise in the detection of the above-mentioned anomalies:

[0088] PR analysis can only determine the cell density for 100 sites. STA analysis can only determine if there are setup / hold violations. IR analysis can only guarantee that the IR drop does not exceed the threshold.

[0089] However, single-dimensional analysis of the relevant technologies for product A cannot yield accurate analysis results for the PSO unit in product A, and cannot determine the cause of the register problem. Based on the method provided in this disclosure, "multi-tool linkage + dynamic feedback" can be achieved, enabling the following analysis process: identifying PSO units near the fail bit's timing path; identifying the worst-performing PSO unit with the worst current based on IR analysis results; further determining all units governed by the worst-performing PSO unit; calculating the unit density within a specified window size; statistically analyzing the DECAP unit types and calculating the total DECAP value within a specified window size; statistically analyzing the number of registers controlled by the clock gating unit (ICG) within a specified window size; and finally, determining the cause of the register error based on the above process, thereby resolving the problem.

[0090] As can be seen, compared to the serial process of "physical design → timing analysis → power analysis", the chip analysis method based on the embodiment of this disclosure, which includes "analysis tools including physical implementation tools, timing analysis tools and voltage drop analysis tools", provides the R&D design team with a cross-tool, full-process collaborative optimization analysis method in the form of "multi-tool linkage + dynamic feedback", which ensures the balance of chip performance, reliability and cost under advanced process technology.

[0091] This disclosure also provides an analysis apparatus for a chip, the apparatus comprising:

[0092] The data capture module is used to capture the latest results of different analysis tools on the target chip, and obtain the target data corresponding to each analysis tool. There are at least two analysis tools, and each analysis tool performs different analyses on the target chip.

[0093] The data distribution module is used to send the target data corresponding to each analysis tool to other analysis tools as the basis for analysis.

[0094] The anomaly assessment module is used to perform anomaly assessment based on target data and obtain assessment results, which are either normal or abnormal.

[0095] The analysis and control module is used to send the abnormal evaluation results as the basis for optimization analysis to the first tool in the analysis tools when the evaluation results are abnormal, and to control each analysis tool to end the analysis when the termination condition is met.

[0096] The termination condition includes an evaluation result that is normal.

[0097] In one possible implementation, the analysis tools include at least two of the following: physical implementation tools, timing analysis tools, and voltage drop analysis tools; the first tool is a physical implementation tool.

[0098] The target data includes at least one of the following: first data obtained by capturing the physical implementation results output by the physical implementation tool, second data obtained by capturing the timing analysis results output by the timing analysis tool, and third data obtained by capturing the power network analysis results output by the voltage drop analysis tool.

[0099] In one possible implementation, the anomaly assessment module includes:

[0100] The evaluation submodule is used to extract the latest results of different analysis tools on the target chip according to the extraction criteria of each analysis tool, and obtain the target data corresponding to each analysis tool.

[0101] In one possible implementation, the device further includes:

[0102] The attribute determination module is used to determine the required attributes of the different target data that each analysis tool needs to capture, based on the current development stage of the target chip and / or the data requirements of each analysis tool.

[0103] The development phase includes at least one of the following: layout planning phase, routing phase, final approval phase, and initial tape-out and debugging phase;

[0104] The data scraping criteria for the analysis tools include the corresponding requirement attributes.

[0105] In one possible implementation, the data distribution module includes:

[0106] The distribution submodule is used to send data from the target data to the matching analysis tools according to the required attributes indicated by the crawling criteria of each analysis tool.

[0107] In one possible implementation, the device further includes:

[0108] The window determination module is used to determine the window size for data capture by the second tool based on a preset capture range.

[0109] The second tool includes time series analysis tools and / or voltage drop analysis tools;

[0110] The crawling criteria for the analysis tool include the window size of the analysis tool.

[0111] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0112] It should be noted that although the above embodiments have been used as examples to illustrate the analysis method and apparatus for chips, those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly set each step and module according to their personal preferences and / or actual application scenarios, as long as it conforms to the technical solution of this disclosure.

[0113] This disclosure also provides an analysis apparatus for a chip, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0114] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0115] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0116] Figure 2 This is a block diagram illustrating an apparatus 1900 for analyzing a chip according to an exemplary embodiment. For example, apparatus 1900 can be provided as a terminal device. (Refer to...) Figure 2The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0117] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0118] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0119] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0120] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0121] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0122] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0123] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0124] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0126] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method of analysis for a chip, characterized by, The method comprises: respectively performing data grabbing on latest results of a target chip by different analysis tools to obtain target data corresponding to each analysis tool, wherein the analysis tools include at least two kinds, and each analysis tool performs different analysis on the target chip; sending the target data corresponding to each analysis tool as analysis basis to other analysis tools; performing abnormality evaluation based on the target data to obtain an evaluation result, wherein the evaluation result is normal or abnormal; in a case where the evaluation result is abnormal, sending the abnormal evaluation result as analysis basis for optimization to a first tool among the analysis tools, and ending the analysis of each analysis tool until a termination condition is met; wherein the termination condition is that the evaluation result is normal.

2. The method of claim 1, wherein, The analysis tools include at least two of a physical implementation tool, a timing analysis tool and a voltage drop analysis tool; and the first tool is the physical implementation tool. The target data includes at least one of first data obtained by grabbing physical implementation results output by the physical implementation tool, second data obtained by grabbing timing analysis results output by the timing analysis tool, and third data obtained by grabbing power network analysis results output by the voltage drop analysis tool.

3. The method of claim 2, wherein, Respectively performing data grabbing on latest results of a target chip by different analysis tools to obtain target data corresponding to each analysis tool, comprises: According to the grabbing basis corresponding to each analysis tool, respectively performing data grabbing on latest results of a target chip by different analysis tools to obtain target data corresponding to each analysis tool.

4. The method of claim 3, wherein, The method further comprises: According to the requirements of each analysis tool for data required by the current development stage of the target chip and / or the demand attribute of different target data required to be grabbed by each analysis tool, determining the demand attribute of different target data required to be grabbed by each analysis tool; The development stage includes at least one of the following: layout planning stage, routing stage, final sign-off stage, and first tape-out debugging stage; The grabbing basis corresponding to each analysis tool includes the corresponding demand attribute.

5. The method according to claim 1 or 4, characterized in that, Sending the target data corresponding to each analysis tool as analysis basis to other analysis tools, comprises: According to the demand attribute indicated by the grabbing basis of each analysis tool, sending data in the target data to the matched analysis tool according to the data attribute.

6. The method of claim 3, wherein, The method further comprises: According to a preset grabbing range, determining a window size of data grabbing performed by a second tool; The second tool includes the timing analysis tool and / or the voltage drop analysis tool; The grabbing basis corresponding to each analysis tool includes the window size corresponding to the analysis tool.

7. An analysis device for a chip, characterized by The device comprises: A data grabbing module for respectively performing data grabbing on latest results of a target chip by different analysis tools to obtain target data corresponding to each analysis tool, wherein the analysis tools include at least two kinds, and each analysis tool performs different analysis on the target chip; A data distribution module for sending the target data corresponding to each analysis tool as analysis basis to other analysis tools; anomaly evaluation module, configured to perform anomaly evaluation based on the target data to obtain an evaluation result, the evaluation result being normal or abnormal; an analysis control module, configured to, in a case where the evaluation result is abnormal, send the abnormal evaluation result as an analysis basis for optimization to a first tool in the analysis tools, and control each of the analysis tools to end analysis until a termination condition is met; wherein the termination condition comprises the evaluation result being normal.

8. An analysis apparatus for a chip, comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the steps of the method of any one of claims 1 to 6.

9. A non-transitory computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program or a non-transitory computer-readable storage medium bearing a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

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