Chip layout method and device based on reinforcement learning network, equipment and medium

Abstract

The invention provides a chip layout method and device based on a reinforcement learning network, equipment and a medium, and the method comprises the steps: determining layout evaluation data of a current layout scheme, solving a comprehensive evaluation model through employing a boundary intersection algorithm for the current layout scheme, and obtaining a layout evaluation compromise solution, and according to the difference between the layout evaluation data and the reference layout evaluation data, guiding the reinforcement learning network to determine a target unit which is not laid out and a corresponding layout strategy according to the circuit netlist characteristics, and then adding the target unit to the current layout scheme according to the layout strategy until all the units are laid out. According to the embodiment of the invention, the balance among a plurality of mutually constrained layout evaluation indexes (such as area, time delay, power consumption and the like) in the chip layout process can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip layout, in particular, to a chip layout method and device based on a reinforcement learning network, equipment and a storage medium. BACKGROUND

[0002] Chip layout is a very important link in integrated circuit design, which refers to the process of laying out each circuit unit (such as logic unit, storage unit, input and output port, clock circuit, etc.) of a chip in the physical space of the chip.

[0003] The layout target of chip layout is to optimize performance, power consumption, area and other design constraints on the basis of meeting the functional requirements of the chip, so as to achieve the optimal chip design effect. That is, the chip not only needs to realize the functional requirements, but also needs to achieve a balance in area, performance, power consumption, manufacturability, etc., which is a key problem faced in integrated circuit design and manufacturing. SUMMARY

[0004] Therefore, the present application provides a chip layout method and device based on a reinforcement learning network, equipment and a storage medium to at least solve the problems in the related art.

[0005] Specifically, the present application is realized by the following technical solutions: The present application provides a chip layout method based on a reinforcement learning network, comprising: Obtaining a circuit netlist of a target chip, the circuit netlist comprising laid-out units and un-laid-out units; Performing feature extraction on the circuit netlist to obtain circuit netlist features; the circuit netlist features comprising position features of the laid-out units; Determining a current layout scheme based on the position features of the laid-out units, and determining layout evaluation data of the current layout scheme; Solving a comprehensive evaluation model using a boundary intersection algorithm to obtain a layout evaluation compromise solution; wherein the comprehensive evaluation model is used to represent the constraint relationship between a comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution comprises reference layout evaluation data of the current layout scheme; According to the difference between the layout evaluation data and the reference layout evaluation data, guiding the reinforcement learning network to determine un-laid-out target units and their corresponding layout strategies based on the circuit netlist features; Adding the target units to the current layout scheme according to the layout strategies, returning to the step of determining the layout evaluation data of the current layout scheme until all units are laid out to obtain a target layout scheme, and performing physical layout on the target chip based on the target layout scheme.

[0006] In some embodiments, the layout evaluation compromise solution is obtained by solving the comprehensive evaluation model using a boundary intersection algorithm, comprising: obtaining layout constraint conditions and boundary values corresponding to each of the layout evaluation indexes; constructing a target space based on each of the layout evaluation indexes; the target space is used to represent the correlation between the layout evaluation indexes; solving the comprehensive evaluation model in the target space based on the layout constraint conditions and each boundary value to obtain the layout evaluation compromise solution.

[0007] In some embodiments, the solving of the comprehensive evaluation model in the target space based on the layout constraint conditions and each boundary value to obtain the layout evaluation compromise solution comprises: solving the comprehensive evaluation model in the target space based on the layout constraint conditions and each boundary value to obtain a compromise solution; adjusting the layout constraint conditions and model coefficients of the comprehensive evaluation model based on the compromise solution, and returning to the step of solving the comprehensive evaluation model in the target space until a preset iteration requirement is met to obtain a plurality of compromise solutions; determining the layout evaluation compromise solution from the plurality of compromise solutions.

[0008] In some embodiments, the layout constraint conditions include at least one of physical constraint conditions, electrical constraint conditions, and design process constraint conditions.

[0009] In some embodiments, the circuit netlist features are extracted from the circuit netlist features by a feature extraction network, wherein the feature extraction network is obtained by self-supervised training of an initial feature extraction network, and the initial feature extraction network includes a feature extraction module, an encoder, and a decoder; the feature extraction network is trained in the following way: obtaining a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas includes a laid-out sample unit in the circuit netlist sample; inputting the circuit netlist sample into the feature extraction module to obtain circuit netlist sample features; partially covering the initial layout canvas to obtain a covered layout canvas; encoding the covered layout canvas by the encoder to obtain encoded features, and fusing the circuit netlist sample features and the encoded features to obtain fused features; decoding the fused features by the decoder to obtain a restored layout canvas; Based on the recovered layout canvas and the initial layout canvas, the initial feature extraction network is self-supervised trained to obtain the feature extraction network.

[0010] In some embodiments, the self-supervised training of the initial feature extraction network based on the recovered layout canvas and the initial layout canvas to obtain the feature extraction network comprises: A first loss is determined according to the pixel difference between the recovered layout canvas and the initial layout canvas. A plurality of cell pairs are obtained by matching cells in the recovered layout canvas and the initial layout canvas, an intersection-over-union of each cell pair is determined respectively, and a second loss is determined based on the intersection-over-union of each cell pair respectively. Based on the first loss and the second loss, a target loss is determined, and the network parameters of the initial feature extraction network are adjusted based on the target loss until a preset training condition is reached to obtain the feature extraction network.

[0011] In some embodiments, the circuit netlist sample features include sample cell features of each sample cell; and the feature fusion of the circuit netlist sample features and the encoded features to obtain the fused features comprises: Target sample cell features corresponding to the occluded sample cells are screened from the circuit netlist sample features. The target sample cell features are subjected to dimension conversion processing to obtain target sample cell features with a target dimension; the target dimension is the same as the dimension of the encoded features. The target sample cell features with the target dimension and the encoded features are subjected to feature fusion to obtain the fused features.

[0012] The application also provides a chip layout device based on a reinforcement learning network, comprising: A netlist acquisition module is configured to acquire a circuit netlist of a target chip, the circuit netlist comprising laid-out cells and un-laid-out cells. A feature extraction module is configured to extract features of the circuit netlist by a feature extraction network to obtain circuit netlist features; the circuit netlist features comprising position features of the laid-out cells. A data determination module is configured to determine a current layout scheme based on the position features of the laid-out cells, and determine layout evaluation data of the current layout scheme. A model solving module is configured to solve a comprehensive evaluation model by a boundary intersection point algorithm to obtain a layout evaluation trade-off solution; wherein the comprehensive evaluation model is configured to represent a constraint relationship between a comprehensive evaluation index and each layout evaluation index, and the layout evaluation trade-off solution comprises reference layout evaluation data of the current layout scheme. a unit determination module configured to determine, according to the difference between the layout evaluation data and the reference layout evaluation data, a target unit and a corresponding layout strategy of the target unit based on the circuit netlist features by using the reinforcement learning network; a physical layout module configured to add the target unit to the current layout scheme according to the layout strategy, return to the step of determining the layout evaluation data of the current layout scheme until all units are completed to obtain a target layout scheme, and perform physical layout of the target chip based on the target layout scheme.

[0013] The application further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the chip layout method based on the reinforcement learning network according to any one of the preceding embodiments when executing the program.

[0014] The application further provides a computer readable storage medium, which stores a computer program, wherein the program implements the steps of the chip layout method based on the reinforcement learning network according to any one of the preceding embodiments when executed by a processor.

[0015] The application further provides a computer program product, which includes a computer program, wherein the computer program executes the steps of the chip layout method based on the reinforcement learning network according to any one of the preceding embodiments when executed by a processor.

[0016] The technical scheme provided by the embodiments of the application can have the following beneficial effects: In the embodiments of the application, the boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain a layout evaluation compromise solution for the current layout scheme, and the layout evaluation compromise solution includes reference layout evaluation data of the current layout scheme, so that the reinforcement learning network can be guided to perform layout of a target unit according to the difference between the layout evaluation data and the reference layout evaluation data. Since the comprehensive evaluation model represents the constraint relationship between the comprehensive evaluation index and each layout evaluation index, the layout evaluation compromise solution obtained by solving can balance multiple layout evaluation indexes (such as area, time delay, power consumption, etc.), thereby avoiding the overall performance loss caused by single index optimization.

[0017] Secondly, the layout method of step-by-step layout (determining a target unit and updating a layout scheme each time) in the application combines dynamic evaluation feedback, which can correct deviations in time during the layout process and avoid the cost of large-scale adjustment in the later period.

[0018] Furthermore, the reinforcement learning network obtains reward values ​​by comparing the placement evaluation data with the compromise solution of the placement evaluation, realizing a closed-loop learning mechanism of "evaluation-feedback-optimization". As the placement process progresses, the network can continuously optimize the placement strategy to adapt to different circuit structures (such as differences in complexity and cell type), improving the versatility and intelligence of the placement.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a chip layout method based on a reinforcement learning network, as shown in an exemplary embodiment of this application. Figure 2 This is a flowchart illustrating another chip layout method based on reinforcement learning networks, as shown in an exemplary embodiment of this application; Figure 3 This is a flowchart illustrating the training process of a feature extraction network according to an exemplary embodiment of this application; Figure 4 This is a flowchart illustrating the training process of a feature extraction network according to an exemplary embodiment of this application; Figure 5 This is a schematic diagram of the structure of a chip layout device based on a reinforcement learning network, as illustrated in an exemplary embodiment of this application. Figure 6 This is a schematic diagram of another chip layout device based on a reinforcement learning network, as illustrated in an exemplary embodiment of this application. Figure 7 This is a hardware structure diagram of an electronic device illustrated in an exemplary embodiment of this application. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0023] It should be understood that, although the terms first, second, third, etc. can be employed in this application to describe various information, these information should not be limited to these terms. These terms are only used to differentiate one piece of information from another piece of information of the same type. For example, without departing from the scope of the application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon determination" or "in response to determining".

[0024] Chip layout is an important link in integrated circuit design, which refers to the process of laying out various circuit units (such as logic units, storage units, input / output ports, clock circuits, etc.) of a chip in the physical space of the chip.

[0025] The layout target of chip layout is to optimize performance, power consumption, area and other design constraints (such as bus length, process) on the basis of meeting the functional requirements of the chip, so as to achieve the optimal chip design effect. That is, the chip not only needs to achieve the functional requirements, but also needs to achieve a balance in terms of area, performance, power consumption, manufacturability, etc., which is a key problem faced in integrated circuit design and manufacturing.

[0026] Based on the above research, the present disclosure provides a chip layout method based on a reinforcement learning network. The method first acquires a circuit netlist of a target chip; the circuit netlist includes laid-out units and un-laid-out units; secondly, feature extraction is performed on the circuit netlist to obtain circuit netlist features; the circuit netlist features include position features of the laid-out units; then, a current layout scheme is determined based on the position features of the laid-out units, and layout evaluation data of the current layout scheme is determined; and a boundary intersection algorithm is used to solve a comprehensive evaluation model to obtain a layout evaluation compromise solution; the comprehensive evaluation model is used to represent the constraint relationship between a comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes reference layout evaluation data of the current layout scheme; then, according to the difference between the layout evaluation data and the reference layout evaluation data, the reinforcement learning network is guided to determine a target unit that has not been laid out and a corresponding layout strategy according to the circuit netlist features; finally, the target unit is added to the current layout scheme according to the layout strategy, and the step of determining the layout evaluation data of the current layout scheme is executed until all units are laid out to obtain a target layout scheme, and the target chip is physically laid out based on the target layout scheme.

[0027] In the embodiment of the present application, for the current layout scheme, the boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain a layout evaluation compromise solution, which includes the reference layout evaluation data of the current layout scheme, so that the difference between the layout evaluation data and the reference layout evaluation data can be used to guide the reinforcement learning network to perform the layout of the target unit. Since the comprehensive evaluation model represents the constraint relationship between the comprehensive evaluation index and each layout evaluation index, the layout evaluation compromise solution obtained by solving can achieve the balance between multiple layout evaluation indexes (such as area, time delay, power consumption, etc.), avoiding the overall performance loss caused by single index optimization.

[0028] Secondly, the step-by-step layout method (determining one target unit and updating the layout scheme each time) in the present application combines dynamic evaluation feedback, which can correct deviations in the layout process in time and avoid the cost of large-scale adjustment in the later period.

[0029] Further, the reinforcement learning network obtains the reward value through the difference between the layout evaluation data and the layout evaluation compromise solution, realizing the closed-loop learning mechanism of “evaluation-feedback-optimization”. With the advancement of the layout process, the network can continuously optimize the layout strategy, adapt to different circuit structures (such as complexity, unit type difference), and improve the generality and intelligent level of the layout.

[0030] To facilitate the understanding of the present embodiment, first, a chip layout method based on a reinforcement learning network disclosed by the present embodiment is introduced in detail. The execution subject of the chip layout method based on the reinforcement learning network provided by the present embodiment is generally an electronic device. The electronic device can be a server, which can be a physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud service, cloud database, cloud computing, cloud storage, big data and artificial intelligence platform. In other embodiments, the electronic device can also be a terminal device, which can be a mobile device, a terminal, a handheld device, a computing device, etc.

[0031] In other embodiments, the method can also be applied to an implementation environment composed of an electronic device and a server. In addition, the chip layout method based on the reinforcement learning network can also be realized by calling the computer readable instructions stored in the memory through the processor.

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0033] Please refer to the drawings Figure 1 A flowchart of a chip layout method based on a reinforcement learning network is shown for an exemplary embodiment of the present application. As shown in Figure 1As shown, the chip layout method based on the reinforcement learning network in the embodiments of the present disclosure can include the following steps S101-S106: S101: Obtain a circuit netlist of a target chip, the circuit netlist including laid-out cells and un-laid-out cells.

[0034] The circuit netlist is a text file or data structure describing the components (or cells) in an electronic circuit and their connection relationships, and is a very core basic data in the chip design process. It is equivalent to the "blueprint" of the circuit, which clearly records the composition of the cells, the properties of the cells, and the electrical connection relationships between the cells.

[0035] In chip design, the main content of the circuit netlist usually includes: component / cell information: such as the model number or attribute parameters of transistors, resistors, capacitors, logic gates, macro cells, etc.; connection relationship: the connection between the pins of each cell is identified by a node (Net), which clearly records the transmission path of the signal from one cell to another cell; port information: input / output port definition of the circuit, used for interaction with external circuits or systems.

[0036] There are many formats for circuit netlists, such as SPICE format (commonly used for analog circuits), Verilog netlist (commonly used for digital circuits), EDIF format, etc. In the chip layout and routing (Place and Route) stage, the physical location and connection routing of each cell are determined, and finally the logical design is converted into a physical entity layout.

[0037] Among them, the laid-out cell refers to a cell with a fixed layout position in the target chip, such as an input / output interface, and the un-laid-out cell refers to a cell that needs to be laid out.

[0038] In some embodiments, the circuit netlist can include a plurality of sub-netlists, each sub-netlist including a plurality of cells. For example, the circuit netlist can be represented as N1: A, B; N2: B, C, D; N3: A, D, where N1, N2, and N3 represent sub-netlists, A, B, C, and D represent cells, A, B represent a connection relationship between cell A and cell B, and B, C, D represent a connection relationship between cell B, cell C, and cell D.

[0039] S102: Feature extraction is performed on the circuit netlist to obtain circuit netlist features; the circuit netlist features include position features of the laid-out cells.

[0040] In the embodiments of the present application, the circuit netlist features are extracted by a feature extraction network, which can include various types of graph neural networks, such as graph convolutional neural networks, graph attention networks, and graph perceptron hybrid networks. The feature extraction network is obtained by self-supervised training of an initial feature extraction network. For the training process of the feature extraction network, please refer to the following.

[0041] The feature extraction network can map the complex cell information in the circuit netlist to a lower dimension to obtain the circuit netlist features, wherein the circuit netlist features include cell features of each cell, connection relationship features between each cell, and position features of the laid-out cells. The cell features can include cell size features, cell pin layout features, and cell electrical features, etc.

[0042] S103: Determine a current layout scheme based on the position features of the laid-out cells, and determine layout evaluation data of the current layout scheme.

[0043] Here, since the laid-out cells are cells with fixed layout positions, the current layout scheme can be determined based on the position features of the laid-out cells, that is, the laid-out cells are laid out.

[0044] In the present embodiment, after determining the current layout scheme, the layout evaluation data of the current layout scheme can be determined based on a preset evaluation algorithm. The layout evaluation indicators include index data corresponding to each of the plurality of layout evaluation indicators. For example, if the layout evaluation indicators include area, bus length, and power consumption, the layout evaluation data can include area index data, bus length index data, and power consumption index data.

[0045] The preset evaluation algorithm can include bus length evaluation algorithm, layout density evaluation algorithm, and congestion degree evaluation algorithm, etc. for bus length, layout density, and congestion degree.

[0046] For the bus length evaluation algorithm, it should be understood that the line length has a direct impact on signal delay and clock frequency. Excessive line length increases parasitic reactance and parasitic capacitance, resulting in higher signal delay. Longer line length often brings more clock skew in the clock network and reduces the maximum clock frequency. At the same time, excessive line length also leads to higher circuit power consumption and leakage rate, which has a negative impact on the performance of semiconductor devices. In addition, bus length also affects signal integrity, processing difficulty, processing cost, thermal management, etc., so bus length is used as an evaluation algorithm indicator.

[0047] There are many methods to calculate the bus length, such as half-perimeter bus length model, Steiner tree length model, square bus length model and smooth bus length model. Taking the half-perimeter bus length as an example, for any netlist, the bus length is the sum of the x coordinate range and the y coordinate range of the components in the netlist. In order to avoid the bus length being zero, the expression is shown in formula (1): (1) Wherein, x is the horizontal coordinate of the component, and y is the vertical coordinate of the component.

[0048] For layout density, it should be understood that the layout density will directly affect the wiring difficulty, whether the chip has overlap, whether the chip area is wasted, and the like. Therefore, the layout density needs to be controlled in a proper interval, neither too large to affect wiring, nor too small to waste chip area.

[0049] The method for evaluating the layout density includes grid-based evaluation, diffusion model-based evaluation and electrostatic model-based evaluation. The common grid-based evaluation method divides the chip into equal grids and calculates the proportion of the component area in the entire chip.

[0050] For congestion degree, it should be understood that the congestion degree is used to measure whether the capacity of wiring is sufficient for all netlists in the same region. The congestion degree has a significant impact on wiring difficulty, timing violation, DRC error and the like. Severe congestion can lead to no wiring. The congestion degree must be considered in advance in the layout process to avoid failure in later wiring. Common models include global routing-based estimation method, probability model method and RUDY. Here, taking the global routing-based estimation method as an example, a global routing algorithm is executed after the preliminary layout is completed, and the congestion degree is judged by comparing the wiring overhead and the wiring capacity target in the fast routing result.

[0051] S104: a boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain a layout evaluation compromise solution; wherein the comprehensive evaluation model is used to represent the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes reference layout evaluation data of the current layout scheme.

[0052] Wherein, the comprehensive evaluation model is used to represent the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and each layout evaluation index can include any multiple of the indexes of power consumption, performance, area, bus length, congestion degree, signal integrity and thermal management.

[0053] Please refer to formula (1) for the expression of the comprehensive evaluation model: (1) Wherein, is the comprehensive evaluation index, a model coefficient corresponding to the layout evaluation index, a layout evaluation index function, i representing a layout evaluation index.

[0054] In some embodiments, when a layout evaluation compromise solution is obtained by solving the comprehensive evaluation model based on the layout evaluation data using a boundary intersection algorithm, the following steps (A)~(C) can be included: (A) Obtain layout constraint conditions and boundary values corresponding to each layout evaluation index.

[0055] The layout constraint conditions include at least one of a physical constraint condition, an electrical constraint condition, and a design process constraint condition.

[0056] The physical constraint condition can refer to a constraint on physical space, geometric size, i.e., structural characteristics. For example, the physical constraint condition can include a cell spacing constraint, a region constraint, a density constraint, etc. For example, the cell spacing constraint can mean that a minimum distance (e.g., 2 μm) must be maintained between two adjacent cells (e.g., logic gates) to prevent physical overlap or interference. The region constraint can mean that a specific functional unit needs to be placed in a designated region, for example, a power management module needs to be placed at the edge of a chip close to a power pin to facilitate power distribution. The density constraint can mean that the layout density of cells in a certain region of the chip cannot exceed a threshold (e.g., a maximum of 100 cells per square millimeter) to avoid wiring difficulties or heat dissipation problems.

[0057] The electrical constraint condition can refer to a constraint on the electrical characteristics of the circuit to ensure that the layout scheme meets the electrical performance requirements such as signal transmission, power consumption, timing, etc. For example, the electrical constraint condition can include a timing constraint, a signal interference constraint, and a load constraint, etc. For example, the timing constraint can mean that the delay of a critical path (e.g., the path from the adder to the register of the CPU) must be less than a specified value (e.g., 2 ns), and the physical distance needs to be shortened through layout optimization to reduce transmission delay. The signal interference constraint can mean that the wiring area of a high-speed signal (e.g., a clock signal) and a sensitive signal (e.g., an analog signal) needs to maintain a minimum distance (e.g., 5 μm) to avoid electromagnetic interference (EMI). The load constraint can mean that the number of load cells connected to a certain driving cell (e.g., a buffer) cannot exceed an upper limit (e.g., a maximum of 8 cells), to prevent signal driving capacity from being insufficient to cause waveform distortion.

[0058] The design process constraint condition can refer to a chip manufacturing process level and a process constraint, to ensure that the chip layout result meets the process specification. The design process constraint condition can include a minimum line width constraint, a minimum via size, a direction constraint, and a density uniformity constraint. For example, the minimum line width constraint can include that the width of a pin connection or internal metal line of a unit cannot be less than the minimum value allowed by the process (e.g., the minimum line width is 7 nm under a 7 nm process). The density uniformity constraint can include that the distribution of units on the surface of the chip needs to maintain a certain uniformity to avoid local areas being too dense or too sparse.

[0059] The boundary value corresponding to each layout evaluation index in the target space can be a reasonable range or threshold set for each layout evaluation index (such as area, delay, power consumption, etc.) in the chip layout design. These boundary values are quantitative standards for determining whether a layout scheme is feasible and meets design requirements. The boundary value can include a "lower limit value" (minimum value) and / or an "upper limit value" (maximum value). Some layout evaluation indexes only need one-way constraint (such as area, which usually only has an upper limit, and delay, which only has an upper limit).

[0060] (B) Based on the layout evaluation indexes, a target space is constructed. The target space is used to represent the correlation between the layout evaluation indexes.

[0061] Here, each point in the target space represents a layout scheme, and the coordinate value of each point is composed of the evaluation data of the corresponding layout scheme on each evaluation index (such as area 5 mm², delay 1.2 ns, and power consumption 80 mW). In this way, the correlation between multiple layout evaluation indexes can be determined.

[0062] As known from the foregoing, the layout evaluation data includes index data corresponding to multiple layout evaluation indexes, and therefore, the target space can be constructed based on the index data corresponding to the multiple layout evaluation indexes.

[0063] Optionally, the layout evaluation compromise solution can be determined based on the index data corresponding to the multiple layout evaluation indexes.

[0064] (C) In the target space, the layout constraint condition and the boundary value of each layout evaluation index are used to solve the comprehensive evaluation model to obtain the layout evaluation compromise solution.

[0065] Here, since the target space represents the correlation between the layout evaluation indexes, and the layout constraint condition and the boundary value of each layout evaluation index limit the solution range, the layout evaluation compromise solution can be obtained by solving the comprehensive evaluation model under the above conditions.

[0066] Optionally, when the layout evaluation compromise solution is obtained by solving the comprehensive evaluation model based on the layout constraint conditions and the boundary values in the target space, the following steps (1)-(3) can be used to determine the layout evaluation compromise solution: (1) solving the comprehensive evaluation model based on the layout constraint conditions and the boundary values in the target space to obtain a compromise solution.

[0067] (2) adjusting the layout constraint conditions and the model coefficients of the comprehensive evaluation model based on the compromise solution, and returning to the step of solving the comprehensive evaluation model in the target space until a preset iteration requirement is met to obtain a plurality of compromise solutions.

[0068] (3) determining the layout evaluation compromise solution from the plurality of compromise solutions.

[0069] It can be understood that, in theory, only one compromise solution can be obtained when the comprehensive evaluation model is solved. However, since the layout constraint conditions and the model coefficients of the comprehensive evaluation model in the present application are manually set values, the layout constraint conditions and the model coefficients of the comprehensive evaluation model can be adjusted according to the compromise solution. Specifically, as known from the foregoing, the layout constraint conditions include at least one of the physical constraint conditions, the electrical constraint conditions, and the design process constraint conditions. Therefore, the adjustment of the plurality of layout constraint conditions can refer to the adjustment of at least one of the above three constraint conditions. In addition, as known from formula (1), each layout evaluation index corresponds to a model coefficient. Therefore, the model coefficients of each layout evaluation index can be adjusted respectively. In this way, the step of solving the comprehensive evaluation model based on the layout constraint conditions and the boundary values in the target space to obtain a compromise solution can be returned to perform iteration until a preset iteration requirement is met to obtain a plurality of compromise solutions.

[0070] The preset iteration requirement can include a preset number of times or a compromise solution meeting a preset requirement.

[0071] Optionally, after obtaining a plurality of compromise solutions, the index data of each layout evaluation index in each compromise solution can be evaluated, for example, for each compromise solution, determining a corresponding comprehensive evaluation index value, and determining a layout evaluation compromise solution from the plurality of compromise solutions according to the comprehensive evaluation index value.

[0072] In this way, the accuracy of the layout evaluation compromise solution can be improved through the iteration calculation of the last compromise solution.

[0073] Optionally, when the layout constraint condition and the model coefficient of the comprehensive evaluation model are adjusted respectively according to the compromise solution, the layout constraint condition and the model coefficient of the comprehensive evaluation model can be adjusted based on the differences between the index data in the reference layout evaluation data included in the compromise solution.

[0074] For example, if the comprehensive evaluation model is a model for two evaluation indexes of delay and bus length, the model coefficient is 1:2, and a compromise solution of delay 1.5 and line length 2.4 is obtained, at this time, it can be considered that the delay is small, and the weight of the delay can be increased to make the delay larger, at this time, the model coefficient can be adjusted to 1:1, and the next iteration is performed based on the coefficient 1:1.

[0075] S105: According to the difference between the layout evaluation data and the reference layout evaluation data, guiding the reinforcement learning network to determine the target unit not laid out and the layout strategy corresponding thereto according to the circuit netlist features.

[0076] Here, after obtaining the layout evaluation compromise solution of the current layout scheme, the reinforcement learning network can be guided to determine the target unit not laid out and the layout strategy corresponding thereto according to the circuit netlist features according to the difference between the layout evaluation data and the reference layout evaluation data.

[0077] Specifically, the reward value of the reinforcement learning network can be determined according to the difference between the layout evaluation data and the reference layout evaluation data, and the reinforcement learning network can be guided to determine the target unit and the layout strategy corresponding thereto based on the reward value.

[0078] Here, it can be understood that the difference between the layout evaluation data and the reference layout evaluation data can be used to represent the pros and cons of the current layout scheme, so as to determine the reward value, and combine the circuit netlist features (used to provide a reference for global layout) to guide the reinforcement learning network to determine the target unit not laid out and the layout strategy corresponding thereto, wherein the layout strategy can include the placement position and the placement orientation of the target unit.

[0079] S106: Adding the target unit to the current layout scheme according to the layout strategy, returning to the step of determining the layout evaluation data of the current layout scheme until all units are laid out to obtain a target layout scheme, and performing physical layout of the target chip based on the target layout scheme.

[0080] It can be understood that after the reinforcement learning network determines the target unit and the layout strategy corresponding thereto, the target unit can be added to the current layout scheme according to the layout strategy to generate a new current layout scheme.

[0081] Furthermore, after the current layout scheme is updated, the process can return to the step of determining the layout evaluation data of the current layout scheme. In this way, a target cell and its corresponding layout strategy can be determined in each iteration. The target cell is added to the current layout scheme each time until all cells are placed, and the target layout scheme is obtained.

[0082] Finally, after determining the target layout scheme, the target chip can be physically laid out according to the target layout scheme. That is, each physical unit is laid out according to the target layout scheme to obtain the target chip. Here, the target chip is the physical chip. In this way, a balanced design of the target chip in various evaluation indicators can be achieved, which is conducive to improving the chip performance.

[0083] Optionally, the target chip type may include, but is not limited to, digital chips, analog chips, mixed-signal chips, etc.

[0084] The following is combined Figure 2 The complete process of the chip layout generation method described above will be explained.

[0085] Figure 2 A flowchart illustrating another chip layout generation method provided for an exemplary embodiment of this application. (See flowchart for example.) Figure 2 As shown, the method includes steps S201 to S212: S201: Obtain the circuit netlist of the target chip, and extract features from the circuit netlist to obtain circuit netlist features. The circuit netlist features include the cell features of each cell, the connection relationship features between each cell, and the position features of the laid-out cells.

[0086] S202: Determine the current layout scheme based on the location characteristics of the already laid-out units.

[0087] S203: Determine whether all units have been laid out. If yes, proceed to step S212; otherwise, proceed to step S204.

[0088] S204: Determine the layout evaluation data for the current layout scheme; S205: Obtain the layout constraints and the boundary values ​​corresponding to each layout evaluation index, and construct the target space.

[0089] S206: In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain a compromise solution.

[0090] S207: Determine whether the preset iteration requirements have been met. If yes, proceed to step S209; otherwise, proceed to step S208.

[0091] S208: Adjust the model coefficients of the layout constraints and the comprehensive evaluation model according to the compromise solution, and return to step S206.

[0092] S209: Obtain multiple compromise solutions and determine the layout evaluation compromise solution from among the multiple compromise solutions. The layout evaluation compromise solution includes reference layout evaluation data for the current layout scheme.

[0093] S210: Based on the difference between the layout evaluation data and the reference layout evaluation data, determine the reward value of the reinforcement learning network, and guide the reinforcement learning network to determine the unplaced target cells and their corresponding placement strategies based on the circuit netlist characteristics.

[0094] S211: Add the target cell to the current layout scheme according to the layout strategy, and execute step S203.

[0095] S212: Obtain the target layout scheme and perform physical layout of the target chip based on the target layout scheme.

[0096] The following is combined Figure 3 and Figure 4 The training process of the feature extraction network in this application is described in detail. Figure 3 A flowchart illustrating the training process of a feature extraction network provided in an exemplary embodiment of this application. Figure 4 A flowchart illustrating the training process of a feature extraction network provided for an exemplary embodiment of this application.

[0097] In this embodiment, the feature extraction network is obtained by self-supervised training of an initial feature extraction network. The initial feature extraction network includes a feature extraction module, an encoder, and a decoder. The feature extraction module can use a preset neural network to implement the feature extraction function. The preset neural network can be a graph convolutional neural network, a graph attention network, or a graph perceptron hybrid network, etc., which is not limited here.

[0098] like Figure 3 As shown, the training process of the feature extraction network includes S301~S306: S301: Obtain a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas includes at least some sample cells from the circuit netlist sample.

[0099] The circuit netlist sample here can include multiple sample cells and the connection relationships between the sample cells.

[0100] The initial layout canvas can refer to an image based on the layout of at least some of the sample cells among a plurality of sample cells. For example, a circuit netlist sample may include 100 cells, while the initial layout canvas may include 50 cells.

[0101] Optionally, when generating the initial layout canvas, an empty canvas can be first constructed, and each sample cell and the connection relationship therebetween are drawn in the empty canvas according to the size and position of each sample cell indicated in the circuit netlist sample, to obtain the initial layout canvas.

[0102] S302: input the circuit netlist sample into a feature extraction module to obtain circuit netlist sample features.

[0103] The feature extraction module can be a graph convolutional neural network, a graph attention network, or a graph perception machine hybrid network, without limitation.

[0104] Here, the circuit netlist sample is input into the feature extraction module to obtain circuit netlist sample features, which are similar to the contents of the circuit netlist features in the foregoing embodiments, and will not be described here.

[0105] As shown in Figure 4 , the circuit netlist sample 10 can be input into the feature extraction module 20 to obtain circuit netlist sample features 30, including cell features 31 and connection relationship features 32 of each cell.

[0106] S303: partially mask the initial layout canvas to obtain a masked layout canvas.

[0107] Specifically, the initial layout canvas can be divided into a plurality of grids of the same size, and a target grid is selected from the plurality of grids for masking according to a preset grid ratio, to obtain the masked layout canvas.

[0108] It can be understood that the masking in this step is a pixel-level mask masking (i.e., all-0 masking), as shown in Figure 4 , where 40 is the initial layout canvas and 50 is the masked layout canvas.

[0109] Optionally, if the size of the initial layout canvas cannot be evenly divided by the side length of the grid, blank filling is performed at the edge. Alternatively, if the size of the initial layout canvas is greater than a first preset size or smaller than a second preset size, a scaling operation can be performed on the initial layout canvas by a certain ratio before grid division to obtain a preprocessed canvas, and the preprocessed canvas is partially masked to obtain the masked layout canvas.

[0110] S304: encode the masked layout canvas by the encoder to obtain an encoded feature, and perform feature fusion on the circuit netlist sample features and the encoded feature to obtain a fused feature.

[0111] Further, please continue to refer to Figure 4The cover layout canvas 50 can be input into an encoder to obtain an encoded feature corresponding to the cover layout canvas, that is, the cover layout canvas is taken as a label of an initial feature extraction network.

[0112] Meanwhile, the circuit netlist sample feature and the encoded feature are fused to obtain a fused feature. In this way, the feature extracted by the network and the visual feature obtained by encoding can be fused.

[0113] S305: Decoding the fused feature by the decoder to obtain a restored layout canvas.

[0114] Further, the fused feature is decoded by the decoder to obtain the restored layout canvas 60. Here, the restored layout canvas can be understood as predicted data.

[0115] S306: Based on the restored layout canvas and the initial layout canvas, the initial feature extraction network is self-supervised trained to obtain the feature extraction network.

[0116] In this way, after the restored layout canvas is obtained, the initial feature extraction network can be self-supervised trained based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network.

[0117] Here, the self-supervised training of the initial feature extraction network can mean that the network parameters of the feature extraction module, the encoder and the decoder are adjusted respectively, and based on the parameter-adjusted feature extraction module, the parameter-adjusted encoder and the parameter-adjusted decoder, the feature extraction network is obtained.

[0118] Optionally, the parameter-adjusted feature extraction module can also be taken as the feature extraction network.

[0119] In some embodiments, when the initial feature extraction network is self-supervised trained based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network, the following steps (I)-(III) can be included: (I) According to the pixel difference between the restored layout canvas and the initial layout canvas, a first loss is determined.

[0120] Here, the pixel mean square error can be determined according to the pixels of the restored layout canvas and the initial layout canvas, and the pixel mean square error is taken as the first loss.

[0121] (II) The units in the restored layout canvas and the initial layout canvas are matched to obtain a plurality of unit pairs, the intersection over union of each unit pair is determined respectively, and the second loss is determined based on the intersection over union respectively corresponding to each unit pair.

[0122] Among them, the unit intersection-over-union (IoU) quantifies the degree of overlap between the restored layout canvas and the initial layout canvas.

[0123] (III) Based on the first loss and the second loss, determine the target loss, and adjust the network parameters of the initial feature extraction network based on the target loss until a preset training condition is reached to obtain the feature extraction network.

[0124] After determining the first loss and the second loss, the target loss can be determined based on the first loss and the second loss. Here, the target loss can be obtained by weighted summing the first loss and the second loss, so that the network parameters of the initial feature extraction network (such as the feature extraction module, the encoder, and the decoder) are adjusted according to the target loss, until a preset iteration number is reached or the target loss meets a preset loss requirement (such as the target loss being less than a preset loss), to obtain the feature extraction network.

[0125] Corresponding to the foregoing embodiments of the chip layout method based on the reinforcement learning network, the present application also provides a hardware accelerator, which includes a processor unit, a computing unit, a policy inference unit, a storage unit, and a scheduling unit. The processor unit is configured to receive a training result of a neural network model, and generate a comprehensive evaluation model in combination with a reinforcement learning network. The computing unit includes a parallel computing unit, and the parallel computing unit includes a tensor computing core configured to perform parallel cost function calculation and gradient update on a plurality of compromise solutions. The parallel computing unit further includes a matrix multiplication array and a sparse computing module to support efficient operation of sparse graph convolution and attention mechanism. The policy inference unit is configured to perform forward inference of a policy network and a value function in a reinforcement learning process to generate a layout strategy. The storage unit is configured to store an intermediate training state of the network, a layout scheme, and circuit netlist features extracted by the feature extraction network. The scheduling unit is configured to perform task allocation and data flow scheduling on the parallel computing unit and the storage unit in a layout optimization iteration process.

[0126] In some embodiments, the storage unit includes an on-chip high-bandwidth memory configured to store netlist graph structures and layout state information of the compromise solutions. The processor unit can be programmably configured with weights to support weighted optimization among wire length, congestion, latency, and power consumption.

[0127] The hardware accelerator described above can be independently deployed, or can be cooperated with a CPU, a GPU, and an FPGA to provide a scalable platform.

[0128] Corresponding to the foregoing embodiments of the chip layout method based on the reinforcement learning network, the present application also provides an embodiment of a chip layout device based on the reinforcement learning network.

[0129] Please refer to Figure 5FIG. 1 shows a schematic diagram of a chip layout device based on a reinforcement learning network according to an example embodiment of the present application. As shown in FIG. 1, the chip layout device 500 based on the reinforcement learning network includes: Figure 5 a netlist obtaining module 510, configured to obtain a circuit netlist of a target chip, the circuit netlist including laid-out cells and un-laid-out cells; the netlist obtaining module 510, configured to obtain a circuit netlist of a target chip, the circuit netlist including laid-out cells and un-laid-out cells; a feature extraction module 520, configured to perform feature extraction on the circuit netlist to obtain circuit netlist features; the circuit netlist features including position features of the laid-out cells; a data determining module 530, configured to determine a current layout scheme based on the position features of the laid-out cells, and determine layout evaluation data of the current layout scheme; a model solving module 540, configured to solve a comprehensive evaluation model using a boundary intersection algorithm to obtain a layout evaluation compromise solution; wherein the comprehensive evaluation model is used to represent a constraint relationship between a comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes reference layout evaluation data of the current layout scheme; a cell determining module 550, configured to guide the reinforcement learning network to determine a target cell that is un-laid-out and a corresponding layout strategy of the target cell based on the circuit netlist features according to a difference between the layout evaluation data and the reference layout evaluation data; a physical layout module 560, configured to add the target cell to the current layout scheme according to the layout strategy, return to perform the step of determining the layout evaluation data of the current layout scheme, until all cells are laid out to obtain a target layout scheme, and perform physical layout on the target chip based on the target layout scheme.

[0130] In some embodiments, the model solving module 540 is specifically configured to: obtain layout constraint conditions and boundary values corresponding to each layout evaluation index respectively; construct a target space based on each layout evaluation index; the target space is used to represent a correlation between the layout evaluation indexes; solve the comprehensive evaluation model in the target space based on the layout constraint conditions and each boundary value to obtain the layout evaluation compromise solution.

[0131] In some embodiments, the model solving module 540 is specifically configured to: solve the comprehensive evaluation model in the target space based on the layout constraint conditions and each boundary value to obtain a compromise solution; Based on the compromise solution, the layout constraint condition and the model coefficient of the comprehensive evaluation model are adjusted respectively, and the step of solving the comprehensive evaluation model in the target space is returned to execute until a preset iteration requirement is reached, and a plurality of compromise solutions are obtained; The layout evaluation compromise solution is determined from the plurality of compromise solutions.

[0132] In some embodiments, the layout constraint condition includes at least one of a physical constraint condition, an electrical constraint condition, and a design process constraint condition.

[0133] See Figure 6 Another structure schematic diagram of a chip layout device based on a reinforcement learning network is provided for an exemplary embodiment of the present application. As shown in Figure 6 The chip layout device based on the reinforcement learning network 500 further includes a network training module 570, and the circuit netlist features are extracted from the circuit netlist features by a feature extraction network, wherein the feature extraction network is obtained by self-supervised training of an initial feature extraction network, and the initial feature extraction network includes a feature extraction module, an encoder, and a decoder; the network training module 570 is used for: obtaining a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas includes a laid-out sample unit in the circuit netlist sample; inputting the circuit netlist sample into the feature extraction module to obtain circuit netlist sample features; partially covering the initial layout canvas to obtain a covered layout canvas; encoding the covered layout canvas by the encoder to obtain encoded features, and performing feature fusion on the circuit netlist sample features and the encoded features to obtain fused features; decoding the fused features by the decoder to obtain a restored layout canvas; based on the restored layout canvas and the initial layout canvas, performing self-supervised training on the initial feature extraction network to obtain the feature extraction network.

[0134] In some embodiments, the network training module 570 is specifically used for: determining a first loss according to a pixel difference between the restored layout canvas and the initial layout canvas; matching units in the restored layout canvas and the initial layout canvas to obtain a plurality of unit pairs, respectively determining an intersection over union of each unit pair, and determining a second loss based on the intersection over union respectively corresponding to each unit pair; Based on the first loss and the second loss, a target loss is determined, and network parameters of the initial feature extraction network are adjusted based on the target loss until a preset training condition is reached, to obtain the feature extraction network.

[0135] In some embodiments, the circuit netlist sample features include sample unit features of respective sample units; and the network training module 570 is specifically configured to: filter target sample unit features corresponding to the covered sample units from the circuit netlist sample features; perform dimension conversion processing on the target sample unit features to obtain target sample unit features with a target dimension; the target dimension is the same as the dimension of the encoded features; perform feature fusion on the target sample unit features with the target dimension and the encoded features to obtain the fused features.

[0136] The implementation process of the functions and roles of each unit in the above apparatus is specifically described in the implementation process of the corresponding steps in the above method, which will not be repeated here.

[0137] For the device embodiment, since it basically corresponds to the method embodiment, the relevant part can be referred to the part of the method embodiment. The above described device embodiment is only illustrative, and the units described as separate components can be or can not be physically separated, and the components displayed as units can be or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. According to the actual needs, part or all of the modules can be selected to achieve the purpose of the present application. Those skilled in the art can understand and implement without creative labor.

[0138] Corresponding to the above chip layout method based on the reinforcement learning network, the embodiment of the present disclosure also provides an electronic device, as shown in Figure 7 The structure of the electronic device provided by the embodiment of the present disclosure is shown in the figure, which includes: The electronic device 700 includes a processor 710, an internal bus 720, a memory 730, a network interface 740, and a non-volatile memory 750, and of course can also include other hardware required by functions. One or more embodiments of the present specification can be implemented in a software manner, such as reading the corresponding computer program from the non-volatile memory 750 into the memory 730 by the processor 710 and then running. Of course, in addition to the software implementation, one or more embodiments of the present specification do not exclude other implementation manners, such as logic devices or a combination of software and hardware, and the like, that is, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0139] The memory 730, also referred to as a main memory, is used to temporarily store data for processing by the processor 710, and exchange data with the non-volatile memory 750 such as a hard disk. The processor 710 exchanges data with the non-volatile memory 750 through the memory 730.

[0140] In the embodiments of the present application, the memory 730 is specifically used to store application program codes for executing the scheme of the present application, and is controlled to execute by the processor 710. That is, when the electronic device is running, the processor 710 communicates with the network interface 740, the memory 730 and the non-volatile memory 750 through the internal bus 720 respectively, so that the processor 710 executes the application program codes stored in the memory 730 and the non-volatile memory 750, and further executes the chip layout method based on the reinforcement learning network described in the above method embodiments.

[0141] The processor 710 can be an integrated circuit chip having a processing capability of signals. The processor described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; or can be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general processor can be a microprocessor or the processor can also be any conventional processor or the like.

[0142] It can be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device 700. In some other embodiments of the present application, the electronic device 700 can include more or fewer components than those illustrated, or combine certain components, or split certain components, or different arrangement of components. The illustrated components can be implemented in hardware, software or a combination of software and hardware.

[0143] The embodiments of the present disclosure also provide a computer readable storage medium, which stores a computer program. When the computer program is run by a processor, the steps of the chip layout method based on the reinforcement learning network in the above method embodiments are executed. The storage medium can be a volatile or non-volatile computer readable storage medium.

[0144] The embodiment of the present disclosure further provides a computer program product carrying program codes, the program codes comprising instructions for executing the steps of the chip layout method based on the reinforcement learning network in the above method embodiment, which can be specifically referred to the above method embodiment and will not be described here.

[0145] The computer program product can be specifically implemented by hardware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0146] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0147] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), and the apparatus can be specifically constructed to perform the processes and logic flows. The processes and logic flows can also be performed by, and apparatus can also be implemented as, a programmable computer coupled to receive data and instructions from, and coupled to transmit data and instructions to, one or more remotely located computers or other programmable devices.

[0148] Computers suitable for the execution of a computer program include, by way of example, general and / or special purpose microprocessors, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory and / or a random access memory. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.

[0149] Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0150] While this specification contains many specifics, these should not be construed as limitations on the scope of any invention or on the required scope of patent protection. Certain features outside the scope of the claimed invention are described in order to provide a clearer understanding of the features of the particular inventions. Some features described in multiple embodiments can be combined in a single embodiment. Conversely, various features described in a single embodiment can be divided among several embodiments. Moreover, no component or structure of the described embodiment is intended to be essential to the practice of the claimed invention unless the component or structure is directly numbered and described as an essential element of the invention in the claims. It is intended that additional modifications and variations to these specific implementation be considered as coming within the scope of the claimed invention. It is intended that only such limitations as two-fully described and clearly induced the patent and / or industrial property office be placed upon the invention and any inventions defined by the following claims. These claims should be construed to cover any alternatives falling within the equivalent of the recited elements.

[0151] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such an order, nor that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products.

[0152] Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0153] The above-described embodiments are merely possible implementations of the present application, and do not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the present application.

Claims

1. A chip layout method based on a reinforcement learning network, characterized by, The method comprises the following steps: obtaining a circuit netlist of a target chip; the circuit netlist comprises laid-out cells and non-laid-out cells; performing feature extraction on the circuit netlist to obtain circuit netlist features; the circuit netlist features comprise position features of the laid-out cells; determining a current layout scheme based on the position features of the laid-out cells, and determining layout evaluation data of the current layout scheme; solving a comprehensive evaluation model by using a boundary intersection point algorithm to obtain a layout evaluation compromise solution; the comprehensive evaluation model is used to represent a constraint relationship between a comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution comprises reference layout evaluation data of the current layout scheme; based on a difference between the layout evaluation data and the reference layout evaluation data, guiding a reinforcement learning network to determine a target cell that has not been laid out and a layout strategy corresponding to the target cell according to the circuit netlist features; adding the target cell to the current layout scheme according to the layout strategy, and returning to the step of determining the layout evaluation data of the current layout scheme until all cells are laid out to obtain a target layout scheme, and performing physical layout on the target chip based on the target layout scheme.

2. The method of claim 1, wherein, The step of solving the comprehensive evaluation model by using the boundary intersection point algorithm to obtain the layout evaluation compromise solution comprises the following steps: obtaining layout constraint conditions and boundary values corresponding to each layout evaluation index; based on each layout evaluation index, constructing a target space; the target space is used to represent a correlation between the layout evaluation indexes; in the target space, solving the comprehensive evaluation model based on the layout constraint conditions and the boundary values to obtain the layout evaluation compromise solution.

3. The method of claim 2, wherein, The step of solving the comprehensive evaluation model based on the layout constraint conditions and the boundary values in the target space to obtain the layout evaluation compromise solution comprises the following steps: in the target space, solving the comprehensive evaluation model based on the layout constraint conditions and the boundary values to obtain a compromise solution; based on the compromise solution, adjusting the layout constraint conditions and model coefficients of the comprehensive evaluation model respectively, and returning to the step of solving the comprehensive evaluation model in the target space until a preset iteration requirement is met to obtain a plurality of compromise solutions; determining the layout evaluation compromise solution from the plurality of compromise solutions.

4. The method of claim 3, wherein, The layout constraint conditions comprise at least one of a physical constraint condition, an electrical constraint condition and a design process constraint condition.

5. The method of claim 1, wherein, The circuit netlist features are obtained by performing feature extraction on the circuit netlist by using a feature extraction network, wherein the feature extraction network is obtained by performing self-supervised training on an initial feature extraction network, the initial feature extraction network comprises a feature extraction module, an encoder and a decoder; and the feature extraction network is trained in the following manner: obtaining a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas comprises laid-out sample cells in the circuit netlist sample; inputting the circuit netlist sample into the feature extraction module to obtain circuit netlist sample features; Partially cover the initial layout canvas to obtain a covered layout canvas; Encode the covered layout canvas by the encoder to obtain encoded features, and perform feature fusion on the circuit netlist sample features and the encoded features to obtain fused features; Decode the fused features by the decoder to obtain a restored layout canvas; Perform self-supervised training on the initial feature extraction network based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network.

6. The method of claim 5, wherein, The self-supervised training of the initial feature extraction network based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network comprises: Determine a first loss according to the pixel difference between the restored layout canvas and the initial layout canvas; Match the cells in the restored layout canvas and the initial layout canvas to obtain a plurality of cell pairs, respectively determine the intersection over union of each cell pair, and determine a second loss based on the intersection over union of each cell pair respectively corresponding; Determine a target loss based on the first loss and the second loss, and adjust the network parameters of the initial feature extraction network based on the target loss until a preset training condition is reached to obtain the feature extraction network.

7. The method of claim 6, wherein, The circuit netlist sample features include sample cell features of each sample cell; the feature fusion of the circuit netlist sample features and the encoded features to obtain the fused features comprises: Screen target sample cell features corresponding to the covered sample cells from the circuit netlist sample features; Perform dimension conversion processing on the target sample cell features to obtain target sample cell features with a target dimension; the target dimension is the same as the dimension of the encoded features; Perform feature fusion on the target sample cell features with the target dimension and the encoded features to obtain the fused features.

8. A chip placement apparatus based on a reinforcement learning network, characterized by, Comprise: The netlist acquisition module is used for acquiring the circuit netlist of the target chip, and the circuit netlist comprises laid-out cells and un-laid-out cells; The feature extraction module is used for extracting features from the circuit netlist to obtain circuit netlist features; the circuit netlist features comprise position features of the laid-out cells; The data determination module is used for determining a current layout scheme based on the position features of the laid-out cells, and determining layout evaluation data of the current layout scheme; The model solving module is used for solving a comprehensive evaluation model by a boundary intersection point algorithm to obtain a layout evaluation trade-off solution; wherein, the comprehensive evaluation model is used for representing a constraint relationship between a comprehensive evaluation index and each layout evaluation index, and the layout evaluation trade-off solution comprises reference layout evaluation data of the current layout scheme; The cell determination module is used for guiding the reinforcement learning network to determine un-laid-out target cells and corresponding layout strategies based on the circuit netlist features according to the difference between the layout evaluation data and the reference layout evaluation data. An entity placement module is configured to add the target cell to the current placement scheme according to the placement strategy, return to performing the step of determining the layout evaluation data of the current placement scheme until all cells are completed to obtain a target placement scheme, and perform entity placement on the target chip based on the target placement scheme.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the steps of the chip placement method based on the reinforcement learning network according to any one of claims 1-7 when executing the program.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The processor implements the steps of the chip placement method based on the reinforcement learning network according to any one of claims 1-7 when executing the program.

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