Chip mounting method

Abstract

The application provides a chip patching method, relates to the technical field of semiconductor packaging, and through a complete process of "initial alignment-precise alignment-positioning-patching", relies on a chip alignment system to synchronously collect a top pattern area and a bottom front cutting edge of a chip and establishes a position correlation, combines a positioning system with synchronous up-down collection capability, realizes linkage of the chip alignment system and the positioning system, the chip alignment system identifies a cutting edge inspection area and records a deviation for a chip with an inclined cutting edge, the positioning system synchronously collects chip and target patching position information, matches the cutting edge features, accurately compensates for the position error caused by the inclined cutting edge, solves the problem that traditional technologies cannot accurately compensate for abnormal cutting edges, stably realizes high-precision patching, and improves the yield and adaptability of high-end semiconductor packaging.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip mounting method. Background Technology

[0002] In the semiconductor packaging field, chip mounting is the core process connecting bare chips to substrates / PCBs, and its precision directly determines the performance and reliability of semiconductor devices. With the upgrading of integrated circuit technology, high-end packaging has raised the precision requirements for chip mounters to the 3μm level, and this high-precision standard has become the key to ensuring device yield.

[0003] However, after the chips are diced, due to factors such as fluctuations in the dicing process and uneven material, the diced edges of each chip will have individual differences such as size deviation, tilting and twisting. At the same time, the chip is also prone to posture deviation during the chip picking and transfer process. These problems make it difficult for traditional mounting technology to achieve the high precision requirement of 3μm.

[0004] Existing placement technologies have significant shortcomings: relying solely on top visual recognition of the chip's front pattern without compensating for positional differences between the cut edge and the pattern can easily lead to placement alignment deviations; placement machines that omit the precise alignment step of the platform cannot eliminate the attitude offset of chip transport; solutions using transparent nozzles are prone to deformation and contamination, making it difficult to achieve stable high-precision placement; and existing technologies cannot adapt to chips with abnormal cut edges, further reducing packaging yield.

[0005] The aforementioned problems make it difficult to achieve high-precision mounting, limiting the yield and efficiency of high-end semiconductor packaging and failing to meet the market's demand for high-precision and high-reliability devices. Therefore, there is an urgent need for a chip mounting method that is compatible with individual chip differences and can stably achieve high-precision mounting. Summary of the Invention

[0006] This invention proposes a chip mounting method that solves the problem of low mounting accuracy caused by chip cutting differences, effectively improving the accuracy and yield of chip mounting.

[0007] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0008] This invention provides a chip mounting method, comprising the following steps:

[0009] S1. Initial alignment: The vision module that comes with the placement head obtains the preset position of the cut chip, and the placement head picks up the chip according to the preset position;

[0010] S2. Precision Alignment: The placement head transfers the chip to the stage. The chip alignment system acquires the reference feature image and edge feature image of the chip, and after processing and analysis, obtains the chip's compensation parameters. The stage performs position compensation on the chip according to the compensation parameters.

[0011] S3. Positioning: The placement head moves the chip processed in step S2 to the positioning area above the target placement position; the positioning system simultaneously acquires image information of the chip and the target placement position, and performs feature matching with the reference feature image and edge feature image analyzed and processed in step S2 to determine the real-time position of the chip; then, combined with the compensation parameters obtained in step S2, the placement head moves the chip to perform position compensation; the relative height between the chip and the target placement position is identified.

[0012] S4. Chip Placement: The placement head obtains the relative height according to step S3, moves the chip vertically to the corresponding position, and releases the chip after descending the relative height, thus completing chip placement.

[0013] Furthermore, in step S2, when the chip is placed on the stage, the cutting portion at the front end of the chip is exposed. The cutting portion includes at least the front cutting edge and the rectangular outlines on the left and right sides, and the exposed range meets the visual recognition requirements of the chip alignment system.

[0014] Furthermore, in step S2, the chip alignment system includes an upper alignment system and a lower alignment system; the upper alignment system uses a downward vision method to acquire a reference feature image, which is the upper pattern area of ​​the chip; the lower alignment system uses an upward vision method to acquire an edge feature image, which is the front cutting edge of the bottom of the chip.

[0015] Furthermore, in step S3, the relative height is the vertical distance between the upper surface of the upper pattern area and the upper surface of the target patch position.

[0016] Furthermore, step S2 specifically includes:

[0017] S2A: The chip alignment system synchronously acquires reference feature image and edge feature image information, establishes the relative positional relationship between the upper pattern area and the front cutting edge, and generates a first image containing the reference feature image and the edge feature image.

[0018] S2B: The chip alignment system calculates the chip's angular offset value based on the first image;

[0019] S2C: The stage rotates the chip according to the angle offset value in step S2B to complete the angle offset correction;

[0020] S2D: The placement head moves above the stage, picks up the chip that has been angle-corrected again, and moves it above the positioning area.

[0021] Furthermore, step S3 specifically includes:

[0022] S3A: Pre-enter the standard chip template into the chip alignment system. The chip alignment system calculates and stores the first distance from its inspection baseline to the front cutting edge based on the standard chip template.

[0023] S3B: The chip alignment system calculates a second distance from the chip inspection baseline to the front cutting edge based on the first image, and determines the chip category based on the difference between the second distance and the first distance.

[0024] S3C: By comparing the first distance with the second distance, the position compensation amount of the chip is calculated;

[0025] S3D: The positioning system acquires the front-end cutting edge image of the chip located in the positioning area, and the mounting head moves longitudinally according to the position compensation amount to complete the position compensation;

[0026] S3E: The placement head descends vertically to the position corresponding to the relative height, completing the chip placement.

[0027] Furthermore, the inspection baseline is the bottom edge of the upper pattern area in the first image; when the second distance is shorter than the first distance, and the front cutting edge is parallel to the inspection baseline, the chip is of the first type, and the placement head moves in the positive longitudinal direction with a position compensation amount; when the second distance is longer than the first distance, and the front cutting edge is parallel to the inspection baseline, the chip is of the second type, and the placement head moves in the negative longitudinal direction with a position compensation amount.

[0028] Furthermore, when the front-end cutting edge is not parallel to the inspection baseline, the chip is of the third type; the lower alignment system identifies the front-end cutting edge and delineates the cutting edge inspection area, generates a second image containing the cutting edge inspection area, and records the third distance from the inspection baseline to the cutting edge inspection area.

[0029] Furthermore, the positioning system moves within the positioning area to acquire the cutting edge inspection area, i.e., the third image, and performs shape matching between the third image and the second image to determine the real-time position of the chip.

[0030] Furthermore, the cutting edge inspection area is a rectangular region that includes all features of the front-end cutting edge.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] This invention provides a chip mounting method that, through a complete process of "initial alignment - fine alignment - positioning - mounting", relies on a chip alignment system to synchronously acquire the upper pattern area of ​​the chip and the bottom front cutting edge and establish a positional association. Combined with a positioning system with the ability to acquire data simultaneously from both the upper and lower edges, the chip alignment system and the positioning system are linked. For chips with tilted cutting edges, the chip alignment system first identifies the cutting edge inspection area and records the deviation. Then, the positioning system synchronously acquires the chip and target mounting position information and matches the cutting edge features to accurately compensate for the positional error caused by the tilted cutting edge. This solves the problem of inaccurate compensation for abnormal cutting edges in traditional technologies, stably achieves high-precision mounting, and improves the yield and compatibility of high-end semiconductor packaging. Attached Figure Description

[0033] To more clearly illustrate the technical solution proposed by the present invention, a detailed description is provided below in conjunction with the embodiments and accompanying drawings. It should be understood that the accompanying drawings described below are merely some embodiments of the present invention, and those skilled in the art can make changes to these drawings under the concept of the present invention.

[0034] Figure 1 An assembly perspective view of an embodiment of the platform provided by the present invention;

[0035] Figure 2 An assembly perspective view of an embodiment of the chip alignment system provided by the present invention;

[0036] Figure 3 An assembly perspective view of an embodiment of the positioning system provided by the present invention;

[0037] Figure 4 An assembly perspective view of an embodiment of the cutting part provided by the present invention;

[0038] Figure 5 An assembly perspective view of an embodiment of the standard chip template provided by the present invention;

[0039] Figure 6 A schematic diagram of the structure of the first type of chip provided by the present invention;

[0040] Figure 7 This is a schematic diagram of the structure of the second type of chip provided by the present invention;

[0041] Figure 8 This is a schematic diagram of the structure of the third type of chip provided by the present invention.

[0042] 1. Chip; 2. Stage; 3. Positioning system; 4. Upper alignment camera; 5. Lower alignment camera; 6. Target placement position; 7. Placement head; 8. Cutting section; 9. Inspection baseline; 10. Front cutting edge; 11. Cutting edge inspection area; 12. Upper pattern area. Detailed Implementation

[0043] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0044] For the surface mount of the first type of chip 1

[0045] S1, Initial Alignment:

[0046] The placement head 7 moves above the wafer, and the outline of the chip 1 is identified by the vision module set on the placement head 7. With the center of the chip 1 as the picking reference, the vacuum nozzle of the placement head 7 descends and starts the adsorption function to complete the stable picking of the chip 1.

[0047] S2, precise alignment:

[0048] S2A: The mounting head 7 transfers the chip 1 to the precision alignment stage 2 and adjusts the chip 1 so that the cutting part 8 at the front end of the chip 1 is exposed. The cutting part 8 includes the front cutting edge 10 and the rectangular outlines on the left and right sides to meet the visual recognition requirements of the chip alignment system.

[0049] S2B: Synchronous Acquisition of Chip Alignment System: The chip alignment system includes an upper alignment camera 4 and a lower alignment camera 5. The upper alignment camera 4 is located above the chip 1 and captures the upper pattern area 12; the lower alignment camera 5 is located below the chip 1 and captures the cutting edge 10 at the bottom front end of the chip 1. This step also includes determining whether the front cutting edge 10 is parallel to the inspection baseline 9. If they are parallel, proceed to the next step. It should be noted that the parallel state here can be set to be considered parallel within a certain deflection error range. The specific error parameters are assigned adaptively based on actual production test data.

[0050] S2C: The chip alignment system combines the image of the pattern area 12 obtained by the upper alignment camera 4 and the image of the cutting edge 10 obtained by the lower alignment camera 5 in step S2B to generate a first image containing the features of the two images. The bottom edge of the upper pattern area 12 is the inspection baseline 9. By analyzing and processing the first image, the relative distance between the inspection baseline 9 and the front cutting edge 10 is obtained and defined as the second distance L2.

[0051] S2D: Set the relative distance between the inspection baseline 9 of the standard chip template and the front cutting edge 10 as the first distance L1; for example, set the first distance L1 to 100µm, and according to the relative distance L2 = 90µm between the inspection baseline 9 and the front cutting edge 10 obtained in step S2C, calculate the deviation ΔL = L2 - L1 = -10µm by comparing it with the first distance L1 of the standard chip template.

[0052] S2E: If the deviation ΔL = -10 µm is negative, it is determined as the first type of chip 1 (see the structure shown in Figure 6 ), at this time L2 < L1, and the cutting edge 10 is parallel to the inspection reference line 9;

[0053] S2F: The chip alignment system calculates the angular offset value of chip 1 based on the first image; specifically, by comparing the first image with the standard chip template, the angular offset value of the first image relative to the standard chip template is obtained, and the stage 2 rotates through the θ-axis to complete the angular correction of chip 1;

[0054] S2G: The placement head 7 moves above the stage 2, restarts the vacuum adsorption, and picks up chip 1 after the angular correction is completed.

[0055] S3. Chip 1 positioning:

[0056] S3A: The placement head 7 carries chip 1 and transfers it above the positioning area of the target placement position 6;

[0057] S3B: The positioning system 3 is located between chip 1 and the target placement position 6, and the positioning system 3 synchronously acquires the images of chip 1 and the target placement position 6;

[0058] S3C: From below chip 1, the positioning system 3 acquires the image of the cutting edge 10 of chip 1 as a reference to confirm feature matching;

[0059] S3D: The control system uses the deviation ΔL calculated in step S2D as the position compensation amount. Since the deviation ΔL is negative, the compensation direction is the longitudinal positive direction (away from the cutting edge 10 direction); thus, the placement head 7 moves 10 µm in the longitudinal positive direction to complete the position compensation;

[0060] S3E: The positioning system 3 measures the vertical relative height between the upper surface of the upper pattern area 12 and the surface of the target placement position 6 through image depth of field analysis.

[0061] S4. Chip placement:

[0062] The placement head 7 precisely moves in the vertical direction according to the measured relative height, so that the lower surface of chip 1 contacts the target placement position 6, and the placement head 7 releases the vacuum to complete the placement.

[0063] Chip placement for the second type of chip 1:

[0064] S1. Initial alignment:

[0065] The placement head 7 moves above the wafer, identifies the contour of chip 1 through the vision module set on the placement head 7, takes the center of chip 1 as the pickup reference, and the vacuum nozzle of the placement head 7 descends and starts the adsorption function to complete the stable pickup of chip 1.

[0066] S2. Fine alignment:

[0067] S2A: The mounting head 7 transfers the chip 1 to the precision alignment stage 2 and adjusts the chip 1 so that the cutting part 8 at the front end of the chip 1 is exposed. The cutting part 8 includes the front cutting edge 10 and the rectangular outlines on the left and right sides to meet the visual recognition requirements of the chip alignment system.

[0068] S2B: Synchronous Acquisition of Chip Alignment System: The chip alignment system includes an upper alignment camera 4 and a lower alignment camera 5. The upper alignment camera 4 is located above the chip 1 and captures the upper pattern area 12 of the chip; the lower alignment camera 5 is located below the chip 1 and captures the cutting edge 10 at the bottom front end of the chip 1. This step also includes determining whether the front cutting edge 10 is parallel to the inspection baseline 9; if they are parallel, proceed to the next step. It should be noted that the parallel state here can be set to be considered parallel within a certain deflection error range, and the specific error parameters are adaptively assigned based on actual production test data.

[0069] S2C: The chip alignment system combines the image of the pattern area 12 obtained by the upper alignment camera 4 and the image of the cutting edge 10 obtained by the lower alignment camera 5 in step S2B to generate a first image containing the features of the two images. The bottom edge of the upper pattern area 12 is the inspection baseline 9. By analyzing and processing the first image, the relative distance between the inspection baseline 9 and the front cutting edge 10 is obtained and defined as the second distance L2.

[0070] S2D: Set the relative distance between the inspection baseline 9 of the standard chip template and the front cutting edge 10 as the first distance L1; for example, set the first distance L1 to 100µm. According to the relative distance between the inspection baseline 9 and the front cutting edge 10 obtained in step S2C, that is, the second distance L2=110µm, the deviation ΔL=L2-L1=+10µm is calculated by comparing it with the first distance L1 of the standard chip template.

[0071] S2E: If the deviation ΔL = +10µm is positive, it is determined to be chip type 1 (see...). Figure 7 (as shown in the structure), where L2>L1, and the cutting edge 10 is parallel to the inspection baseline 9;

[0072] S2F: The chip alignment system calculates the angle offset value of chip 1 based on the first image; specifically, by comparing the first image with the standard chip template, the angle offset value of the first image relative to the standard chip template is obtained, and the stage 2 completes the angle correction of chip 1 by rotating along the θ axis;

[0073] S2G: The mounting head 7 moves above the stage 2, restarts vacuum adsorption, and picks up the chip 1 after angle correction.

[0074] S3, Positioning:

[0075] S3A: The placement head 7 carries the chip 1 and moves it above the positioning area of ​​the target placement position 6;

[0076] S3B: Positioning system 3 is located between chip 1 and target patch 6. Positioning system 3 synchronously acquires images of chip 1 and target patch 6.

[0077] S3C: Positioning system 3 uses the image of the cut edge 10 of chip 1 from below as a reference to confirm feature matching;

[0078] S3D: The control system uses the deviation ΔL calculated in step S2D as the position compensation amount. Since the deviation ΔL is a positive number, the compensation direction is the negative longitudinal direction (closer to the cutting edge 10). As a result, the mounting head 7 moves 10µm in the negative longitudinal direction to complete the position compensation.

[0079] S3E: Positioning system 3 measures the vertical relative height between the upper surface of the upper pattern area 12 and the surface of the target patch position 6 through image depth analysis;

[0080] S4, Patch Panel:

[0081] The mounting head 7 moves precisely in the vertical direction according to the measured relative height, so that the lower surface of the chip 1 contacts the target mounting position 6, and the mounting head 7 releases the vacuum to complete the mounting.

[0082] For the third type of chip 1 (tilted cut edge) patch

[0083] S1, Initial Alignment

[0084] The placement head 7 moves above the wafer, and the outline of the chip 1 is identified by the vision module set on the placement head 7. With the center of the chip 1 as the picking reference, the vacuum nozzle of the placement head 7 descends and starts the adsorption function to complete the stable picking of the chip 1.

[0085] S2, precise alignment:

[0086] S2A: The mounting head 7 transfers the chip 1 to the precision alignment stage 2 and adjusts the chip 1 so that the inclined cutting edge 10 of the chip 1 is fully exposed. The cutting part 8 includes the front cutting edge 10 and the rectangular outlines on the left and right sides to meet the visual recognition requirements of the chip alignment system.

[0087] S2B: Synchronous Acquisition of Chip Alignment System: The chip alignment system includes an upper alignment camera 4 and a lower alignment camera 5. The upper alignment camera 4 is located above the chip 1 and captures the upper pattern area 12; the lower alignment camera 5 is located below the chip 1 and captures the cutting edge 10 at the bottom front end of the chip 1; when the chip alignment system acquires images, it identifies that the cutting edge at the front end is not parallel to the inspection baseline 9.

[0088] S2C: The chip alignment system selects a rectangular area containing all features of the inclined cutting edge in the image acquired by the lower alignment camera 5, merges the processed image with the image acquired by the upper alignment camera 4 to form a second image, and sets a position of the rectangular area as the reference point of the cutting edge inspection area 11; and analyzes and obtains the relative distance from the inspection baseline 9 to the reference point of the cutting edge inspection area 11, and sets it as the third distance L3.

[0089] S2D: Set the relative distance between the inspection baseline 9 of the standard chip template and the front cutting edge 10 as the first distance L1; for example, set the first distance L1 to 100µm. According to the relative distance between the inspection baseline 9 and the front cutting edge 10 obtained in step S2C, that is, the third distance L3 = 110µm, the deviation ΔL = L3 - L1 = +10µm is calculated by comparing it with the first distance L1 of the standard chip template.

[0090] S2E: If the deviation ΔL = +10µm is positive, and the cutting edge 10 is not parallel to the inspection baseline 9, then it is determined to be a third type chip 1 (see...). Figure 8 (as shown in the diagram), where L3 > L1;

[0091] S2F: The chip alignment system calculates the angle offset value of chip 1 based on the second image; specifically, by comparing the second image with the standard chip template, the angle offset value of the second image relative to the standard chip template is obtained, and the stage 2 completes the angle correction of chip 1 by rotating along the θ axis;

[0092] S2G: The mounting head 7 moves above the stage 2, restarts vacuum adsorption, and picks up the chip 1 after angle correction.

[0093] S3. Positioning (Shape Matching Compensation):

[0094] S3A: The placement head 7 carries the chip 1 and moves it above the positioning area of ​​the target placement position 6;

[0095] S3B: Positioning system 3 is located between chip 1 and target patch 6. Positioning system 3 synchronously acquires images of chip 1 and target patch 6.

[0096] S3C: The positioning system 3 is located below the chip 1 and acquires a third image of the chip 1 containing the real-time features of the cutting edge 10. The positioning system 3 performs high-precision shape matching between the third image and the second image.

[0097] S3D: The control system uses the deviation ΔL calculated in step S2D as the position compensation amount. Since the deviation ΔL is a positive number, the compensation direction is the negative longitudinal direction (towards the cutting edge 10). Thus, the placement head 7 moves 10 µm in the negative longitudinal direction to complete the position compensation. Of course, it should be noted that in step S2D of this embodiment, only the case where L3 > L1 is listed. However, in actual operation, there may also be a case where L3 < L1. At this time, the deviation ΔL is a negative number, and the compensation direction is the positive longitudinal direction (away from the cutting edge 10). Thus, the placement head 7 moves 10 µm in the positive longitudinal direction to complete the position compensation.

[0098] S3E: The positioning system 3 measures the vertical relative height between the upper surface of the upper pattern area 12 and the surface of the target placement position 6 through image depth-of-field analysis.

[0099] S4. Chip placement

[0100] The placement head 7 accurately moves in the vertical direction according to the measured relative height, so that the lower surface of the chip 1 contacts the target placement position 6, and the placement head 7 releases the vacuum to complete the placement. Through the above shape matching compensation, even if the cutting edge 10 is inclined, the upper pattern area 12 is still accurately aligned with the target placement position 6, and the placement accuracy meets the requirements of high-end packaging.

[0101] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0102] The above is the specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A chip mounting method, characterized in that, Includes the following steps: S1. Initial alignment: The vision module matched with the mounting head (7) obtains the preset position of the cut chip (1), and the mounting head (7) obtains the chip (1) according to the preset position. S2, fine alignment: The mounting head (7) transfers the chip (1) to the stage (2). When the chip (1) is placed on the stage (2), the cutting part exposed at the front end of the chip (1) includes at least the front cutting edge (10) and the rectangular outline on the left and right sides. The chip alignment system includes an upper alignment system and a lower alignment system. The upper alignment system uses a downward vision method to collect the upper pattern area (12) of the chip (1) as a reference feature image. The lower alignment system uses an upward vision method to collect the front cutting edge (10) at the bottom of the chip (1) as an edge feature image. The reference feature image and the edge feature image are collected simultaneously and the relative positional relationship between the upper pattern area (12) and the front cutting edge (10) is established. After processing and analysis, the compensation parameters of the chip are obtained. The stage (2) performs position compensation on the chip (1) according to the compensation parameters. S3, Positioning: The mounting head (7) moves the chip (1) processed in step S2 to the positioning area above the target patch position (6); the positioning system (3) synchronously collects image information of the chip (1) and the target patch position (6), and performs feature matching with the baseline feature image and edge feature image processed in step S2 to determine the real-time position of the chip (1); then, combined with the compensation parameters obtained in step S2, the mounting head (7) drives the chip (1) to perform position compensation; the relative height between the chip (1) and the target patch position is identified; the relative height is the vertical distance between the upper surface of the upper pattern area (12) and the upper surface of the target patch position (6); S4, Placement: The placement head (7) obtains the relative height according to step S3, moves the chip (1) to the corresponding position in the vertical direction and releases the chip (1) after lowering the relative height, thus completing the placement of the chip (1).

2. The chip mounting method as described in claim 1, characterized in that, Step S2 specifically includes: S2A: The chip alignment system synchronously acquires the reference feature image and the edge feature image information, establishes the relative positional relationship between the upper pattern area (12) and the front cutting edge (10), and generates a first image containing the reference feature image and the edge feature image; S2B: The chip alignment system calculates the angular offset value of the chip (1) based on the first image; S2C: The stage (2) drives the chip (1) to rotate according to the angle offset value in step S2B, thereby completing the correction of the angle offset; S2D: The mounting head (7) moves above the stage (2), picks up the chip (1) that has completed angle correction, and moves it above the positioning area.

3. The chip mounting method as described in claim 2, characterized in that, Step S3 specifically includes: S3A: A standard chip template is pre-entered into the chip alignment system. Based on the standard chip template, the chip alignment system calculates and stores the first distance from its inspection baseline (9) to the front cutting edge (10). S3B: The chip alignment system calculates the second distance from the inspection baseline (9) to the front cutting edge (10) based on the first image, and determines the category of the chip (1) based on the difference between the second distance and the first distance; S3C: Compare the first distance with the second distance to calculate the position compensation amount of the chip (1); S3D: The positioning system (3) acquires the image of the front cutting edge (10) of the chip (1) located in the positioning area, and the mounting head (7) moves longitudinally according to the position compensation amount to complete the position compensation; S3E: The mounting head (7) descends vertically to the position corresponding to the relative height to complete the mounting of the chip (1).

4. The chip mounting method as described in claim 3, characterized in that, The inspection baseline (9) is the bottom edge of the upper pattern area (12) in the first image; when the second distance is shorter than the first distance, and the front cutting edge (10) is parallel to the inspection baseline (9), the chip (1) is of the first type, and the mounting head (7) moves the position compensation amount in the positive longitudinal direction; when the second distance is longer than the first distance, and the front cutting edge (10) is parallel to the inspection baseline (9), the chip (1) is of the second type, and the mounting head (7) moves the position compensation amount in the negative longitudinal direction.

5. The chip mounting method as described in claim 3, characterized in that, When the front-end cutting edge (10) is not parallel to the inspection baseline (9), the chip (1) is of the third type; the lower alignment system identifies the front-end cutting edge (10) and delineates the cutting edge inspection area (11), generates a second image containing the cutting edge inspection area (11), and records the third distance from the inspection baseline (9) to the cutting edge inspection area (11).

6. The chip mounting method as described in claim 5, characterized in that, The positioning system (3) moves in the positioning area to collect the cutting edge inspection area, i.e., the third image, and performs shape matching between the third image and the second image to determine the real-time position of the chip (1).

Images