A directory update method, device, medium and program product for maintaining cache consistency

Abstract

The present application belongs to the technical field of maintaining cache consistency, and particularly relates to a directory updating method, device, medium and program product for maintaining cache consistency. The present application provides a directory updating method for maintaining cache consistency, which comprises the following steps: in response to a cache consistency maintenance operation initiated by a current processor core, obtaining a target cache block to which the cache consistency maintenance operation is directed and first target core information of the current processor core; determining a target directory table entry corresponding to the target cache block; obtaining a current recording mode of shared information of the target directory table entry; and updating the target directory table entry according to the first target core information and the current recording mode. The present application provides a more efficient method for determining cache blocks that need to maintain cache consistency when cache consistency is executed, which greatly improves the efficiency of data sharing and interaction.

Description

Technical Field

[0001] This invention belongs to the technical field of maintaining cache consistency, and specifically relates to a directory update method, device, medium, and program product for maintaining cache consistency. Background Technology

[0002] Each processor core on a modern many-core CPU has a cache to improve data access speed and ensure ease of program writing. When running a parallel program, multiple processes or threads running on multiple processor cores may read and write data in the same memory region. To ensure the correct execution of parallel programs, cache coherence is required between different processor cores of the same CPU and between different CPUs within the same compute node. This ensures that the same data remains consistent across the private caches of multiple processor cores within the same compute node.

[0003] There are two main cache coherence protocols: bus-based snooping coherence protocols (snooping protocols) and directory-based coherence protocols (directory protocols). Currently, a single CPU has over a hundred processor cores, and this number will soon reach hundreds or even thousands, posing significant challenges to both snooping and directory protocols. Snooping protocols incur substantial overhead for snooping across hundreds or thousands of cores on a single bus-based operation; while directory protocols require maintaining increasingly large directories, and each directory entry struggles to accurately record the sharing status of a shared cache block across all processor cores (to ensure accurate recording, each directory entry would need to be a bitmap with a width of tens or even hundreds of bytes). A commonly used method for non-precisely recording cache block sharing (called the fuzzy sharing record method) involves each directory entry recording the current number of valid copies of the corresponding memory region (a cache block or several consecutive cache blocks) and the core number of the primary owner. The fuzzy sharing record method often results in a cache coherence operation requiring snooping across all processor cores, leading to significant overhead. For example, if a cache block has valid copies on three processing cores, and another processor core is about to modify this cache block, since the directory entry doesn't know which three processor cores have valid copies of the cache block, it can only listen on almost all processor cores in the compute node. This leads to significant overhead and a huge consumption of on-chip network resources. Another commonly used fuzzy sharing record method is for each directory entry to correspond to a valid cache block copy. Each directory entry records the sharing state of the corresponding cache block copy and the core number of the primary owner, where the sharing state is a state such as the MESI or MEOSI protocol. When a cache block has multiple copies, the directory entries of these copies are the same or consistent.

[0004] When writing parallel programs, developing only process-level parallelism can lead to numerous processes running on the same computing node, resulting in severe contention for communication ports. Therefore, to efficiently utilize a CPU or the numerous processor cores within a computing node, it's often necessary to use parallel programming libraries or languages ​​such as MPI and OpenMP to collaboratively develop a hybrid process-level and thread-level parallelism. Furthermore, as the number of processor cores on a CPU increases, the number of threads needing to run collaboratively within a process typically increases as well. Since all threads belonging to a process share the process's shared memory space, multiple threads within the same process often experience data sharing and interaction based on cache coherency. However, fuzzy shared record methods make data sharing and interaction highly inefficient. Summary of the Invention

[0005] This invention provides a directory update method for maintaining cache consistency, comprising: responding to a cache consistency maintenance operation initiated by the current processor core; obtaining the target cache block targeted by the cache consistency maintenance operation and first target core information of the current processor core; determining the target directory entry corresponding to the target cache block; obtaining the current recording method of the target directory entry for shared information; and updating the target directory entry according to the first target core information and the current recording method. This application provides multiple recording methods for shared information, with different recording methods matching the different distribution patterns of multiple valid copies of the cache block among processor cores. This allows for a more efficient method to determine the processor cores requiring attention when maintaining cache consistency, greatly improving the efficiency of data sharing and interaction, and solving the problem that using only fuzzy shared recording methods in the prior art makes data sharing and interaction very inefficient.

[0006] To address the aforementioned technical problems, this application proposes four aspects.

[0007] In a first aspect, this application provides a directory update method for maintaining cache consistency, comprising: responding to a cache consistency maintenance operation initiated by the current processor core, obtaining the target cache block targeted by the cache consistency maintenance operation and the first target core information of the current processor core; determining the target directory entry corresponding to the target cache block; obtaining the current recording method of the target directory entry for shared information; and updating the target directory entry according to the first target core information and the current recording method.

[0008] In some embodiments, the current recording method includes: local bitmap information; when the current recording method is local bitmap information, updating the target directory entry according to the first target core information and the current recording method includes: obtaining the local bitmap information of the target directory entry, wherein the local bitmap information is used to record the sharing status of the target cache block within the directory entry core group; determining whether the first target core information and the local bitmap information can correspond to the same core group; when the first target core information and the local bitmap information can correspond to the same core group, updating the local bitmap information of the target directory entry according to the cache block operation type corresponding to the cache consistency maintenance operation.

[0009] In some embodiments, when the current recording method is local bitmap information, updating the target directory entry based on the first target core information and the current recording method further includes: when the first target core information and the local bitmap information do not correspond to the same core group, obtaining the number of valid copies of the target cache block and the core number of the processor core where each valid copy is located through the local bitmap information; switching the current recording method of the target directory entry from local bitmap information to fuzzy shared information; determining the sharing count information or protocol status information in the fuzzy shared information based on the number of valid copies; and determining the owner core information in the fuzzy shared information based on the core number of the processor core where each valid copy is located and the first target core information.

[0010] In some embodiments, the current recording method further includes: fuzzy shared information; when the current recording method is the fuzzy shared information, updating the target directory entry according to the first target core information and the current recording method further includes: obtaining the cache block operation type corresponding to the cache consistency maintenance operation; updating the sharing count information or protocol status information of the fuzzy shared information according to the cache block operation type and the first target core information.

[0011] In some embodiments, updating the sharing count information or protocol status information of the fuzzy shared information according to the cache block operation type and the first target core information includes: updating the sharing count information or protocol status information of the fuzzy shared information according to the cache block operation type; determining whether to update the owner core information of the fuzzy shared information according to the cache block operation type; wherein, when the cache block operation type is modifying data, the owner core information is updated according to the first target core information.

[0012] In some embodiments, the cache block operation type further includes: reading data and discarding replicas; determining whether to update the owner core information of the fuzzy shared information based on the cache block operation type includes: obtaining the record status of the owner core information; determining whether to update the owner core information based on the record status; wherein, when the cache block operation type is reading data, the record status includes: whether the owner core information is full or whether there is a meaningless owner core number in the owner core information; when the owner core information is not full or whether there is a meaningless owner core number in the owner core information, updating the owner core information based on the first target core information; when the cache block operation type is discarding replicas, the record status includes: whether the owner core information contains the first target core information; when the owner core information contains the first target core information, updating the owner core information based on the first target core information.

[0013] In some embodiments, when the current recording mode is the fuzzy shared information, updating the target directory entry based on the first target core information and the current recording mode further includes: determining second target core information based on the owner core information when the shared count information is updated to 1 or the protocol status information is updated to exclusive status, and the owner core information of the fuzzy shared information is meaningful; updating the current recording mode of the target directory entry from the fuzzy shared information to local bitmap information; determining the current target core group corresponding to the second target core information; setting the directory entry core group of the local bitmap information as the current target core group; and generating a shared bitmap of the local bitmap information based on the second target core information and the current target core group.

[0014] In some embodiments, the current recording mode further includes: a coexistence mode; when the current recording mode is the coexistence mode, updating the target directory entry according to the first target core information and the current recording mode further includes: obtaining local bitmap information of the target directory entry, wherein the local bitmap information is used to record the sharing status of the target cache block within the directory entry core group; determining whether the first target core information and the local bitmap information can correspond to the same core group; when the first target core information and the local bitmap information cannot correspond to the same core group, updating the fuzzy sharing information of the target directory entry according to the cache block operation type corresponding to the cache consistency maintenance operation; when the first target core information and the local bitmap information can correspond to the same core group, updating the local bitmap information of the target directory entry according to the cache block operation type corresponding to the cache consistency maintenance operation.

[0015] In some embodiments, obtaining the current recording method of the target directory entry for shared information includes: determining whether there is a target directory entry in the directory corresponding to the target cache block; when there is no target directory entry in the directory corresponding to the target cache block, generating a target directory entry based on the target cache block; wherein, the current recording method of the target directory entry is set to a preset initial recording method, the preset initial recording method being one of local bitmap information or coexistence method; and initializing the shared bitmap of the local bitmap information of the target directory entry and the corresponding directory entry core group based on the first target core information.

[0016] In some embodiments, determining whether the first target core information and the local bitmap information correspond to the same core group includes: obtaining the processor core grouping rule corresponding to the target directory entry, wherein the processor core grouping rule is a uniform grouping rule or a dynamic grouping rule; the uniform grouping rule divides all processor cores into multiple core groups evenly according to the core group size, and the starting core number of the core group is an integer multiple of the core group size; when updating the local bitmap information of the target directory entry, the uniform grouping rule requires the core group of the directory entry to remain unchanged; the dynamic grouping rule does not restrict the starting core number of the core group, and when updating the local bitmap information of the target directory entry, the dynamic grouping rule allows the core group of the directory entry to be changed; when the cache block operation type is data modification, confirming that the first target core information and the local bitmap information correspond to the same core group; when the cache block operation type is not data modification, determining whether the first target core information and the local bitmap information correspond to the same core group according to the processor core grouping rule.

[0017] In some embodiments, when the processor core grouping rule is the dynamic grouping rule, determining whether the first target core information and the local bitmap information can correspond to the same core group according to the processor core grouping rule includes: obtaining the directory entry core group of the local bitmap information; determining whether the first target core information belongs to the directory entry core group; when the first target core information belongs to the directory entry core group, confirming that the first target core information and the local bitmap information correspond to the same core group; when the first target core information does not belong to the directory entry core group, obtaining the shared bitmap of the local bitmap information; determining the target processor core that has a valid copy of the target cache block according to the shared bitmap, the directory entry core group, and the first target core information; and determining whether the target processor cores with each valid copy can belong to the same core group.

[0018] In some embodiments, determining whether the target processor cores of each valid copy belong to the same core group includes: obtaining a preset shared bitmap width threshold for the local bitmap information; determining the number difference between the maximum and minimum numbers based on the numbers of each target processor core; determining whether the target processor cores of each valid copy are in the same core group based on the numerical relationship between the number difference and the shared bitmap width threshold; wherein when the number difference is less than the shared bitmap width threshold, it is determined that the first target core information and the local bitmap information correspond to the same core group.

[0019] In some embodiments, when the processor core grouping rule is the uniform grouping rule, determining whether the first target core information and the local bitmap information can correspond to the same core group according to the processor core grouping rule includes: obtaining the directory entry core group of the local bitmap information; determining whether the first target core information belongs to the directory entry core group; when the first target core information belongs to the directory entry core group, confirming that the first target core information and the local bitmap information correspond to the same core group; when the first target core information does not belong to the directory entry core group, confirming that the first target core information and the local bitmap information cannot correspond to the same core group.

[0020] In some embodiments, the uniform grouping rule includes: a fixed uniform core uniform grouping rule, a dynamic uniform core uniform grouping rule, and a single-core uniform grouping rule; the fixed uniform core uniform grouping rule cannot be changed after the operating system starts, while the dynamic uniform core uniform grouping rule can be changed by the operating system or an application after the operating system starts; the single-core uniform grouping rule is set as the processor core grouping rule when the target directory entry is initialized; when the processor core grouping rule is the uniform grouping rule, obtaining the processor core grouping rule corresponding to the target directory entry includes: when the uniform grouping rule is the fixed uniform core uniform grouping rule, obtaining the fixed uniform core uniform grouping rule for all processor cores; when the uniform grouping rule is the dynamic uniform core uniform grouping rule or the single-core uniform grouping rule, obtaining the single-core uniform grouping rule for the target directory entry.

[0021] In a second aspect, this application proposes a computer electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any of the methods described in the first aspect.

[0022] Thirdly, this application proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the first aspects.

[0023] Fourthly, this application proposes a computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any of the first aspects.

[0024] This invention provides a directory update method for maintaining cache consistency, comprising: responding to a cache consistency maintenance operation initiated by the current processor core; obtaining the target cache block targeted by the cache consistency maintenance operation and first target core information of the current processor core; determining the target directory entry corresponding to the target cache block; obtaining the current recording method of the target directory entry for shared information; and updating the target directory entry according to the first target core information and the current recording method. This application provides multiple recording methods for shared information, with different recording methods matching different cache block distribution patterns. This allows for a more efficient method to determine the cache blocks requiring cache consistency maintenance during cache consistency execution, greatly improving the efficiency of data sharing and interaction, and solving the problem that using only fuzzy shared recording methods in the prior art makes data sharing and interaction very inefficient. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, and these illustrative descriptions do not constitute a limitation on the embodiments.

[0026] Figure 1 The main flowchart of a directory update method for maintaining cache consistency is provided in an embodiment of this application;

[0027] Figure 2 This is a structural block diagram of a computer electronic production equipment provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0029] Each processor core on a modern many-core CPU has a cache to improve data access speed and ensure ease of program writing. When running a parallel program, multiple processes or threads running on multiple processor cores may read and write data in the same memory region. To ensure the correct execution of parallel programs, cache coherence is required between different processor cores of the same CPU and between different CPUs within the same compute node. This ensures that the same data remains consistent across the private caches of multiple processor cores within the same compute node.

[0030] There are two main cache coherence protocols: bus-based snooping coherence protocols (snooping protocols) and directory-based coherence protocols (directory protocols). Currently, the number of processor cores on a single CPU has exceeded one hundred, and will soon reach several hundred or even thousands, posing significant challenges to both snooping and directory protocols. Snooping protocols incur huge overhead for conducting a single bus-based snooping of hundreds or thousands of cores; while directory protocols require maintaining increasingly large directories, and each directory entry struggles to accurately record the sharing status of a shared cache block across all processor cores (to ensure accurate recording, each directory entry would need to record a bitmap with a width of tens or even hundreds of bytes). A commonly used method for non-precisely recording cache block sharing (called the fuzzy sharing record method) involves each directory entry recording the current number of valid copies of the corresponding memory region (a cache block or several consecutive cache blocks) and the core number of the primary owner. Another commonly used fuzzy shared record method is to have each directory entry correspond to a valid cache block copy. Each directory entry records the sharing state of the corresponding cache block copy and the core number of the primary owner, where the sharing state is a state such as that in the MESI or MEOSI protocols. When a cache block has multiple copies, the directory entries for these copies are identical or consistent. The fuzzy shared record method often leads to a cache coherence operation requiring monitoring of all processor cores, resulting in significant overhead. For example, if a cache block has valid copies on three processor cores, and another processor core is about to modify this cache block, since the directory entries do not know which three processor cores have valid copies of the cache block, they must monitor almost all processor cores in the compute node. This leads to significant overhead and a huge consumption of on-chip network resources.

[0031] When writing parallel programs, developing only process-level parallelism can lead to numerous processes running on the same computing node, resulting in severe contention for communication ports. Therefore, to efficiently utilize a CPU or the numerous processor cores within a computing node, it's often necessary to use parallel programming libraries or languages ​​such as MPI and OpenMP to collaboratively develop a hybrid process-level and thread-level parallelism. Furthermore, as the number of processor cores on a CPU increases, the number of threads needing to run collaboratively within a process typically increases as well. Since all threads belonging to a process share the process's shared memory space, multiple threads within the same process often experience data sharing and interaction based on cache coherency. However, fuzzy shared record methods make data sharing and interaction highly inefficient.

[0032] To address the aforementioned technical problems, this invention proposes a directory update method for maintaining cache consistency. The implementation details of the directory update method for maintaining cache consistency in this embodiment are described below. The following content is only for ease of understanding and is not necessary for implementing this solution.

[0033] Example 1:

[0034] like Figure 1 As shown, this application provides a directory update method for maintaining cache consistency. The method is applicable to electronic production equipment, which can be a server, mobile terminal, computer, cloud platform, etc. The functions implemented by the production equipment data processing provided in this application embodiment can be implemented by the processor of the electronic production equipment calling program code, wherein the program code can be stored in a computer storage medium. The directory update method for maintaining cache consistency includes:

[0035] Step S1: In response to the cache coherence maintenance operation initiated by the current processor core, obtain the target cache block targeted by the cache coherence maintenance operation and the first target core information of the current processor core.

[0036] Modern CPUs typically use the MESI or MOESI protocols, with their states and transitions (states within cache blocks), to achieve cache coherency. In the MOESI protocol, the I state (invalid) indicates that the data in the current cache block is invalid; the E state indicates that the current cache block is the only valid copy across all processor cores and is a read-only copy; the M state indicates that the current cache block is the only valid copy across all processor cores and is a rewritten copy; the S state indicates that the current cache block is a valid copy and is a read-only copy, and other processor cores also have valid copies; the O state indicates that the current cache block is a valid copy and is a rewritten copy, and other processor cores also have valid copies. When a memory access instruction changes the state of a cache block, the current processor core (the processor core corresponding to the cache whose state changed (the target cache block)) initiates a cache coherency maintenance operation. Since the directory entries store the sharing information of valid copies of the target cache block, the directory needs to be queried, used, and modified. The sharing information of valid copies of the target cache block is recorded through the core information of the processor cores. Therefore, this application needs to obtain the target cache block and the first target core information of the current processor. The first target core information is usually the number of the current processor core.

[0037] Step S2: Determine the target directory entry corresponding to the target cache block.

[0038] The main task of step S2 in this application is to search for a directory entry in the directory based on the memory address corresponding to the memory access instruction. The directory entry to be searched is the target directory entry. However, this search has two possible results: either the target directory entry exists in the directory, or it does not exist. When using a directory protocol, the number of target directory entries will not exceed one. When using a bus-based listening protocol, which combines protocols such as MOESI, each cache block copy may have one directory entry. Therefore, there may be multiple target directory entries, which are also referred to as target directory entries (maintaining consistency among multiple target directory entries is easy to achieve and will not be described in detail in this application).

[0039] Step S3: Obtain the current recording method of the target directory entry for shared information.

[0040] If the target directory entry can be found, the current recording method for the shared information can be obtained directly from the found target directory entry. If the target directory entry cannot be found, a new target directory entry needs to be allocated first, and then the current recording method of the newly allocated target directory entry can be obtained.

[0041] Therefore, in some embodiments, step S3, "obtaining the current recording method of the target directory entry for shared information," includes:

[0042] Step S31: Determine whether there is a target directory entry in the directory that corresponds to the target cache block.

[0043] Step S32: When there is no target directory entry corresponding to the target cache block in the directory, generate a target directory entry based on the target cache block.

[0044] Step S33: Initialize the directory entry core group and shared bitmap of the local bitmap information of the target directory entry according to the first target core information.

[0045] Since the target directory entry may not exist in the directory, this application first needs to determine if the target directory entry exists in the directory. If the target directory entry does not exist, a new target directory entry needs to be allocated for the target cache block. Because the directory entry needs to record the sharing status of each valid copy of the target cache block among the processor cores, the issue of recording sharing information needs to be considered when allocating a new target directory entry.

[0046] When a processor has a large number of cores, accurately recording the distribution of valid copies of a target cache block across all cores requires reserving space in the cache table entries matching the number of cores to record whether each core has a valid copy of the target cache block. This results in significant resource consumption. To reduce the resources required for recording shared cache information, a fuzzy recording method is needed. However, this fuzzy recording method often leads to a cache coherence operation requiring monitoring of all cores, resulting in substantial overhead. Therefore, an improvement to the method of recording shared cache information is needed.

[0047] Therefore, this application does not employ a single recording method for recording shared information. The overall recording method in this application can be divided into two types: a switching method and a coexistence method. Regardless of whether it is a switching or coexistence method, the recording of shared information is based on two basic recording methods: local bitmap information and fuzzy shared information.

[0048] Switching refers to selecting an appropriate recording method to record sharing information based on the distribution of valid copies of the target cache block across processor cores. In this method, at least one bit in the directory table entry indicates whether the entry records local bitmap information or fuzzy shared information; that is, local bitmap information and fuzzy shared information use overlapping space in the directory table entry, or share a single recording space. Coexistence, on the other hand, uses both local bitmap information and fuzzy shared information simultaneously to record the distribution of valid copies of the target cache block across processor cores. Because coexistence uses both local bitmap information and fuzzy shared information to record the sharing of valid copies of the target cache block, these two types of information use non-overlapping space in the directory table entry. Therefore, coexistence incurs greater hardware overhead than switching. Typically, switching and coexistence are determined by the CPU hardware as a whole: some CPUs use switching for all directory table entries, while others use coexistence.

[0049] When a target directory entry uses a switching method to record shared information, its current recording method may be local bitmap information or fuzzy shared information as the program runs. Therefore, the current recording methods in this application include: local bitmap information, fuzzy shared information, and coexistence.

[0050] Therefore, in this application, when allocating a new target directory entry, the current recording method of the target directory entry is set to a preset initial recording method. For switching methods, the preferred initial recording method is local bitmap information. Therefore, the preset initial recording method is either local bitmap information or a coexistence method. When generating a directory entry, if it is a coexistence method, both local bitmap information and fuzzy sharing information are generated simultaneously. Since there is only one valid copy of the target cache block at this time, it can be accurately recorded using local bitmap information, so local bitmap information is used first to record the sharing situation.

[0051] Therefore, in some embodiments, step S33, "initializing the directory entry kernel group and shared bitmap of the local bitmap information of the target directory entry according to the first target kernel information," includes:

[0052] Step S331: Obtain the preset processor core grouping rules for the target cache block.

[0053] Step S332: When the initial recording method is local bitmap information, determine the directory entry core group of the local bitmap information according to the processor core grouping rules and the first target core information.

[0054] Step S333: Initialize the shared bitmap of the local bitmap information according to the directory entry core group and the first target core information.

[0055] Bitmaps are a convenient method for accurately recording cache block sharing. They assign consecutive integer numbers to all processor cores on a CPU or compute node, with each bit in the bitmap corresponding to a processor core. However, when there are many processor cores, the bitmap for a single directory entry can have many bits, resulting in significant hardware overhead. This application considers that it's rare for every processor core to have a valid copy of the target cache block; more often, only a few processor cores have valid copies. Therefore, this application proposes using a narrower local bitmap to accurately record cache block sharing among a subset of processor cores. For example, when a compute node has 1024 processor cores, the global bitmap requires 1024 bits, while the local bitmap can be 8, 10, or 16 bits. Typically, the processor cores corresponding to a local bitmap are numbered consecutively. More complex situations may arise, such as a local bitmap corresponding to multiple processor cores with consecutive even numbers. The set of processor cores corresponding to a local bitmap is called the directory entry core group, used to record the core group corresponding to the local bitmap of a directory entry.

[0056] Local bitmap information is used to record the precise sharing of cache blocks among all processor cores within a core group. It consists of a directory entry core group and a shared bitmap. The directory entry core group records the unique core group corresponding to the local bitmap information and can use various marking methods, such as using the core group number or the number representing the core within the group (e.g., the core with the smallest number). The maximum width threshold (i.e., the maximum number of bits) of the shared bitmap cannot be infinitely large and is limited by hardware capacity, determined by the size of the directory entry (the number of bits it occupies). When the directory entry core group is marked with a core group number, the shared bitmap also has a minimum width threshold, determined by the minimum number of processor cores in the core group. The smaller the minimum number of processor cores threshold, the more bits need to be reserved to record the core group number, resulting in higher hardware costs.

[0057] The concept of core groups implicitly introduces the grouping of all processor cores. Processor core grouping rules include at least two categories: uniform grouping rules and dynamic grouping rules. Uniform grouping rules divide all processor cores evenly into multiple core groups based on the core group size (i.e., the number of cores in different core groups is roughly the same), and no two core groups share a common processor core. Under uniform grouping rules, the core group in the directory entry can be identified by the core group number or by the number representing the core within the core group; the starting core number of a core group is usually an integer multiple of the core group size.

[0058] Dynamic grouping rules do not require the starting core number of a core group to be an integer multiple of the core group size, meaning the starting core number can be any processor core number. Therefore, under dynamic grouping rules, a directory entry core group can only be identified using the number representing the core within the core group. Furthermore, under dynamic grouping rules, the directory entry core group of a directory entry's local bitmap information can dynamically change with access to the directory entry. For example, given a maximum shared bitmap width threshold of 8, when a target directory entry is created due to access to the target cache block by core 113, the local bitmap information of the target directory entry can be initialized to <core group flag = 113, shared bitmap = 10000000>. At this time, the shared bitmap can be used to record the sharing of cache blocks between cores 113 and 120. Subsequently, when core 116 accesses the target cache block, the local bitmap information is updated to <core group flag = 113, shared bitmap = 10010000>. Next, if core 111 accesses the target cache block, the local bitmap information is updated to <core group flag=111, shared bitmap=10100100>, meaning the core group of the directory entry has changed from cores 113-120 to cores 111-118, and the shared bitmap also changes (it can be understood as shifting 2 bits to the right). However, if core 107 accesses the target cache block, the shared core set of the shared target cache block is {107, 113, 116}, which cannot be recorded using an 8-bit wide shared bitmap. In this case, the local bitmap information needs to be converted into fuzzy shared information. When the local bitmap corresponds to multiple consecutively numbered processor cores, as long as the difference between the largest and smallest core numbers of the shared cache block does not exceed the maximum width threshold of the shared bitmap, the local bitmap information can be used to record the sharing status. Dynamic grouping rules are more flexible than uniform grouping rules, but the hardware requirements for implementation are higher. Therefore, some CPUs use uniform grouping rules, while others use dynamic grouping rules. When a CPU's shared information recording method is coexistence mode, the CPU can only use uniform grouping rules because the flexible changes in the directory table entry core group will conflict with the fuzzy shared information.

[0059] Therefore, if valid copies of the target cache block are distributed across multiple processor cores within a single core group, they can be recorded using local bitmap information. However, when the target cache block is shared across core groups, fuzzy sharing information is needed to record the sharing status. This fuzzy sharing information includes: 1) owner core information; and 2) sharing count information or protocol status information. Owner core information records the core number of the processor core that owns the valid copies of the target cache block. Sharing count information records the total number of valid copies of the target cache block. Protocol status information corresponds to states in protocols such as MESI or MOESI (e.g., I, E, O, M, S). Both sharing count information and protocol status information can be used to record the sharing status of cache blocks, with sharing count information being more accurate but also incurring greater overhead. Therefore, if valid copies of the target cache block are distributed across different core groups, fuzzy sharing information can be used to record this information.

[0060] Because the number of threads required for efficient parallel execution may vary across different programs, some CPUs, to improve flexibility and versatility, allow the operating system or other system software to uniformly set or modify the core group size for uniform grouping rules. Some CPUs even support different core group sizes for different directory entries. Conversely, some CPUs do not support this. Therefore, the processor core grouping rules in this application include a uniform core grouping rule for all processor cores. This uniform core grouping rule can be a fixed or dynamic rule. The fixed rule cannot be changed after the operating system starts, while the dynamic rule can be changed by the operating system or applications after startup. There are also differences in CPUs that support uniform setting or modification of the core group size by the operating system or other system software. Some CPUs only support uniform setting or modification of the core group size before system startup, while others support it after system startup. These two methods of modifying the core group size supported by CPUs are referred to as fixed uniform and dynamic uniform in this application, while the core group size is referred to as the core grouping rule in this application. Therefore, the fixed uniform core grouping rule in this application is proposed for CPUs that only support uniform setting or modification of the core group size before system startup, while the dynamic uniform core grouping rule is proposed for CPUs that support uniform setting or modification of the core group size after system startup. During program execution, since the fixed uniform core grouping rule remains unchanged, the directory entry does not need to record the grouping rule; these fixed uniform core grouping rules can be uniformly recorded in the common information of all processor cores.

[0061] For dynamic uniform core grouping rules, changing the core group size during program execution affects all entries in the directory, thus impacting all processor cores. However, changing the core group size doesn't necessarily require an operating system restart. There are at least two ways to change the core group size: a global abrupt change and a gradual change. A global abrupt change involves centrally changing the core group size of all directory entries' local bitmaps. During this process, the entire directory is no longer accessible to individual processor cores, thus pausing the operation of all processor cores. Only after the core group size change for all directory entries' local bitmaps is complete can the processor cores resume operation. The advantage of this method is that only the entire directory needs to record the core group size, rather than each individual directory entry. However, implementing the function of pausing all processor cores under directory-driven operation presents both hardware design and development challenges and reduces system responsiveness to applications.

[0062] The gradual adjustment method refers to progressively adjusting each directory entry to the target core group size. In this method, it's possible for two valid directory entries to have different core group sizes. Therefore, the gradual adjustment method requires each directory entry to record its current core group size. One potential implementation is to adjust the core group size corresponding to a directory entry as a processor core accesses it. This implementation would lead to frequent checks whether to adjust the core group size.

[0063] Therefore, the processor core grouping rules in this application also include: individual core uniform grouping rules, that is, each directory entry must record its individual core uniform grouping rules. The individual core uniform grouping rules in this application are proposed for CPUs that support dynamic unified core uniform grouping rules. Generally, when a new directory entry is allocated, the core group corresponding to that directory entry needs to be determined. Subsequently, when accessing a directory entry, it is necessary to determine whether the unified grouping rule of the core group to which the current processor core that initiated the cache coherence maintenance operation belongs is the same as the core group to which the directory entry belongs. It is possible that the current unified grouping rule differs from the unified grouping rule used when previously allocating directory entries; in this case, the core group to which the current processor core belongs cannot be determined according to the current unified grouping rule, but only the past unified grouping rule can be used. The individual core uniform grouping rule for each directory entry is used to record the "past unified grouping rule," that is, to record the dynamic unified uniform grouping rule used when a new directory entry is allocated.

[0064] In coexistence mode, directory entries simultaneously contain local bitmap information and fuzzy sharing information. Therefore, local bitmap information can be prioritized for recording sharing details; that is, the core group of directory entries with local bitmap information is set during target directory entry initialization. The coexistence of local bitmap information and fuzzy sharing information allows for precise recording of a small portion of a cache block, while the remaining portion is recorded fuzzily.

[0065] Step S334: When the initial recording method is coexistence mode, determine the directory entry core group of the local bitmap information of the target directory entry according to the processing core grouping rules and the first target core information.

[0066] Step S335: Initialize the local bitmap information and fuzzy sharing information of the target directory entry according to the directory entry core group and the first target core information.

[0067] After obtaining the processor core grouping rules and the first target core information, the target directory entry can be generated. Further, the core group information where the target cache block resides is determined based on the first target core information and the processor core grouping rules, and local bitmap information of the target directory entry is generated based on the core group information and the first target core information.

[0068] Step S4: Update the target directory entries according to the first target core information and the current recording method.

[0069] When using a switching method to record shared information, the way the shared information is recorded may change. The current recording method may be partial bitmap information or fuzzy shared information. Therefore, updating the target directory entry involves not only updating the specific shared information but also updating the recording method.

[0070] Therefore, if the current record information is the local bitmap information, in some embodiments, step S4 "updating the target directory entry according to the first target kernel information and the current record method" includes:

[0071] Step S411: Obtain the local bitmap information of the target directory entry.

[0072] Step S412: Determine whether the first target kernel information and the local bitmap information correspond to the same kernel group.

[0073] Step S413: When the first target core information and the local bitmap information can correspond to the same core group, update the local bitmap information of the target directory table entry according to the cache block operation type corresponding to the cache consistency maintenance operation.

[0074] The cache block operations related to cache consistency mainly include reading data, discarding replicas, and modifying data. Reading data typically involves reading data from memory or a valid cache replica, increasing the number of valid replicas of the target cache block. Discarding replicas invalidates a valid cache replica, reducing the number of valid replicas of the target cache block. Modifying data modifies a cache block with multiple valid replicas, requiring invalidation of valid cache block replicas in other cores, leaving only one valid replica of the cache block. If the current recording method is local bitmap information, it means that the existing valid replicas of the target cache block corresponding to the target directory entry are distributed among processor cores within the same core group. If a processor core initiates a cache consistency operation, it is necessary to first determine whether the current processor core initiating the cache consistency operation corresponds to the same core group as the local bitmap information. If so, it means that regardless of the cache consistency maintenance operation performed on the target cache block, it will not affect the recording method of shared information. In this case, only the shared information needs to be updated, i.e., the shared bitmap or directory entry core group in the local bitmap information needs to be updated. For example, if the operation type is reading data, the bit marker corresponding to the current processor core in the shared bitmap is updated from 0 to 1; if the operation type is discarding a copy, the bit marker corresponding to the current processor core in the shared bitmap is updated from 1 to 0; if the operation type is modifying data, the bit markers of all processor cores in the shared bitmap except the current processor core are updated to 0 (0 indicates no valid copy). The bit marker corresponding to the current processor core in the shared bitmap can be determined based on the first target core information of the current processor core. Of course, it is also possible that all bit markers in the updated shared bitmap are 0, indicating that the target cache block has completed its task, and the target directory entry can then be deleted from the directory.

[0075] When the processor core grouping rule is a uniform grouping rule, updating the local bitmap information does not involve updating the directory entry core group. When the processor core grouping rule is a dynamic grouping rule, if the first target core information belongs to the directory entry core group of the local bitmap information, updating the local bitmap information also does not require modifying the directory entry core group. When the first target core information does not belong to the directory entry core group of the local bitmap information, it is also possible to construct a new core group that can contain the first target core information and all shared cores (processor cores with valid copies of cache blocks) in the local bitmap information, and this new core group can be used as the same core group. For example, the local bitmap information before the update is <core group tag=113, shared bitmap=10010000>, where 113 represents the starting core number of the directory entry core group. When core 111 reads the target cache block, core 111 does not belong to the directory entry core group before the update. However, all shared cores (113 and 116) corresponding to the local bitmap information belong to the same new core group starting with core number 111 as the 111th core. Therefore, it can be confirmed that the first target core information and the local bitmap information correspond to the same core group. Under the dynamic grouping rule, when the core group of the directory entry before the update is different from the same core group, the update of the local bitmap information includes the update of the directory entry core group and the shared bitmap, which specifically includes the shift operation of the shared bitmap, the recording of the first target core information in the shared bitmap, and updating the directory entry core group to the same core group.

[0076] In some embodiments, step S4, "updating the target directory entry based on the first target kernel information and the current recording method," further includes:

[0077] Step S415: When the first target core information and the local bitmap information do not correspond to the same core group, obtain the number of valid copies of the target cache block and the core number of the processor core where each valid copy is located through the local bitmap information.

[0078] Step S416: Switch the current recording mode of the target directory entry from local bitmap information to fuzzy shared information.

[0079] Step S417: Determine the sharing count information or protocol status information in the fuzzy sharing information based on the number of valid copies.

[0080] Step S418: Determine the owner core information in the fuzzy shared information based on the core number of the processor core where each valid copy is located and the first target core information.

[0081] Of course, in some cases, the first target core information and the local bitmap information may not correspond to the same core group. In this case, since the current recording method is local bitmap information, it indicates that no other processor core besides the directory entry core group has a valid copy of the target cache block. When the cache coherence operation initiated by a processor core outside the directory entry core group is a data read operation, the data read operation will increase the number of valid copies of the target cache block, and the newly added valid copies make it impossible to accurately describe the sharing situation of the target cache block using only local bitmap information. Therefore, it is necessary to update the recording method of sharing information from local bitmap information to fuzzy sharing information. When the cache coherence operation initiated by a processor core outside the directory entry core group is a data modification operation, since there will only be one valid copy in the end (i.e., the copy corresponding to the current processor core), the local bitmap information method can still be retained.

[0082] When updating local bitmap information to fuzzy shared information, it is necessary to specify the share count information (or protocol status information) and the owner core information within the fuzzy shared information. Since the local bitmap information explicitly records the distribution of each valid copy of the target cache block, the share count information (or protocol status information) and the owner core information of the updated fuzzy shared information can be determined based on the local bitmap information and the first target core information. Because the fuzzy shared information and local bitmap information share the same storage space in the switching mode, the space for recording the fuzzy shared information is limited. It may not be possible to record the core numbers of all processor cores possessing valid copies of the target cache block. Therefore, in this application, a portion of the core numbers of processor cores possessing valid copies of the target cache block can be selected as the owner core information. This owner core information can be used to determine which processor core to retrieve data from when other processor cores need to read data from the target cache block. When protocol status information is used, the updated protocol status information is a shared state, such as the O and S states under the MEOSI protocol.

[0083] If the current recording method is fuzzy shared information, in some embodiments, step S4, "updating the target directory entry based on the first target kernel information and the current recording method," further includes:

[0084] Step S421: Obtain the cache block operation type corresponding to the cache consistency maintenance operation.

[0085] Step S422: Update the sharing count information or protocol status information of the fuzzy sharing information according to the cache block operation type and the first target kernel information.

[0086] Since the fuzzy sharing information indicates that multiple valid copies of the target cache block are not necessarily in the same core group, it is not necessary to determine the core group to which the current processor core belongs. The sharing count or protocol status information in the fuzzy sharing information can be updated directly based on the operation type and the first target core information. However, due to limited storage space for the owner core information, updates will occur in some cases and not in others. Therefore, this section only describes the updating of the sharing count and protocol status information; the updating of the owner core information will be explained in detail below.

[0087] In some embodiments, step S422, "updating the sharing count information or protocol status information of the fuzzy sharing information according to the cache block operation type and the first target kernel information," includes:

[0088] Step S4221: Update the sharing count information or protocol status information of the fuzzy shared information according to the cache block operation type.

[0089] Step S4222: Determine whether to update the owner kernel information of the fuzzy shared information based on the cache block operation type.

[0090] Step S4223: When the cache block operation type is data modification, the owner core information is updated according to the first target core information.

[0091] Cache coherence operations that cause updates to shared count information or protocol state information may also trigger updates to the owner core information. Specifically, the cache block modification operation type invalidates all cache blocks except those in the currently processing core. This will cause the shared count information to become 1 or the protocol state information to become exclusive (indicating that there is only one valid copy of the cache block). Generally, this will necessarily update the owner core information, except in one special case: if the owner core information only records the core number of the current processor core, then updating the owner core information is unnecessary. Updating the owner core information can be done in several ways. One way is to update the owner core information with the current processor core's core number as the unique core number when the owner core information does not contain the current processor core's core number. Another way is to delete the other core numbers when the owner core information contains multiple core numbers, including the current processor core's core number, making the current processor core's core number the unique core number in the owner core information.

[0092] In some embodiments, step S4222, "determining whether to update the owner kernel information of the fuzzy shared information based on the cache block operation type," includes:

[0093] Step S42221: Obtain the record of the owner's core information.

[0094] Step S42222: Determine whether to update the owner core information based on the recorded information.

[0095] Step S42223: Wherein, when the cache block operation type is reading data, the recording status includes: whether the owner core information is full or whether there is a meaningless owner core number in the owner core information.

[0096] Step S42224: When the owner core information is not fully recorded or when there is a meaningless owner core number in the owner core information, update the owner core information according to the first target core information.

[0097] Data read operations create new valid copies of cache blocks. However, the storage space for the owner core information is limited. Therefore, whether to update the owner core information requires determining if there is sufficient storage space within the owner core information to store the new cache block copy. One way to determine if there is storage space is whether the owner core information is full or if there are any meaningless core IDs. If the owner core information can only store the core ID of one valid copy, and the processor core relinquishes the valid copy, theoretically the core ID in the owner core information would be deleted. However, since the core ID in the owner core information is recorded in hardware, it cannot be truly deleted. In this case, the core ID can be marked as meaningless, meaning there may be meaningless core IDs. Therefore, if the owner core information is not full or if there are meaningless core IDs, it means that the owner core information can record the new valid copy of the core information. In this case, the owner core information will be updated based on the first target core information.

[0098] Therefore, if the operation type is read data, the shared count information is incremented by 1 (when shared count information is used). If the owner core information is still meaningful or the owner core signal is full, the owner core information is not updated. If the owner core information is meaningless (e.g., the content in the owner core information is meaningless), or the owner core information is not full, the core number of the current processor core is added to the owner core information (the owner core information then becomes meaningful).

[0099] When protocol state information is used instead of shared count information, the protocol state information undergoes state transitions according to protocols such as MESI or MOESI adopted by the CPU. The protocol state information can determine whether a cache block has one valid copy or multiple valid copies. When there are multiple valid copies, the exact number of valid copies cannot be determined.

[0100] Step S42225: When the cache block operation type is "discard copy", the record status includes: whether the owner core information contains the first target core information.

[0101] Step S42226: When the owner core information contains the first target core information, update the owner core information according to the first target core information.

[0102] If the operation type is "discard replica," the number of valid replicas will decrease, and the share count in the fuzzy shared information will be decremented by 1 (if protocol state information is used, it usually remains unchanged). Whether to update the owner core information depends on whether the owner core information contains the core number of the current processor core. If not, the owner core information does not need to be updated; otherwise, it does. During the update process, if the owner core information includes multiple core numbers, the core number of the current processor core is directly deleted from the owner core information. If the owner core information only contains the core number of the current processor core, this core number can be marked as meaningless (if it is not marked as meaningless, there may be situations where data is retrieved according to the owner core information but the owner core cannot provide it).

[0103] For fuzzy shared information, when the updated fuzzy shared information meets preset conditions, the current recording method of the target directory entry is switched from fuzzy shared information to local bitmap information. Specifically, in some embodiments, step S4, "updating the target directory entry according to the first target kernel information and the current recording method," further includes:

[0104] Step S423: When the shared count information is updated to 1 or the protocol status information is updated to exclusive status, and the owner core information is meaningful, determine the second target core information based on the owner core information.

[0105] Step S424: Update the current recording method of the target directory entry from the fuzzy shared information to the local bitmap information.

[0106] Step S425: Determine the second current target core group corresponding to the second target core information.

[0107] Step S426: Set the directory entry core group of the local bitmap information as the second current target core group.

[0108] Step S427: Generate a shared bitmap of the local bitmap information based on the second target kernel information and the second current target kernel group.

[0109] When the updated shared count information is 1 or the protocol status information is in an exclusive state (in cache coherence protocols, this indicates a state with only one valid copy, such as the E or M state in the MOESI protocol), and the owner core information is meaningful, it means that the target cache block has only one unique copy and there is no cross-core group sharing of the cache block. At this time, the core number recorded in the owner core information is the processor core where the unique copy is located. Therefore, the second target core information can be determined based on the core number information at this time, and the core group of the processor core where the target cache block is located can be determined based on the second target core information, that is, the second current target core group. At this time, the second current target core group can be used as the core group corresponding to the target directory table entry. A shared bitmap of local bitmap information can be generated based on the second target core information and the core group information of the second current target core group, and the local bitmap information can be used as the current recording method of the target directory table entry.

[0110] Because in the coexistence mode, the target directory entry uses both local bitmap information and fuzzy shared information to record shared information, it is necessary to determine which recording method will be updated by the cache consistency maintenance operation. For fuzzy shared information in the coexistence mode, it may not overwrite the shared information in the local bitmap information. Since the local bitmap information records the distribution of the target cache block within the directory entry core group, if the first target core information and the local bitmap information do not correspond to the same core group, the local bitmap information will not be updated. However, if the first target core information and the local bitmap information correspond to the same core group, the local bitmap information will be updated. If the fuzzy shared information does not record the sharing situation within the directory entry core group, then an update to the fuzzy shared information will only be triggered if the current processor core is outside the directory entry core group. However, if the fuzzy shared information also records the sharing situation within the directory entry core group, then an update to the fuzzy shared information will be triggered regardless of whether the current processor core is within the directory entry core group.

[0111] Therefore, if the current recording method is a coexistence mode, in some embodiments, step S4 "updating the target directory entry according to the first target kernel information and the current recording method" further includes:

[0112] Step S431: Obtain the local bitmap information of the target directory entry.

[0113] Step S432: Determine whether the first target kernel information and the local bitmap information correspond to the same kernel group.

[0114] Step S433: When the first target core information and the local bitmap information do not correspond to the same core group, update the fuzzy shared information of the target directory table entry according to the cache block operation type corresponding to the cache consistency maintenance operation.

[0115] Step S434: When the first target core information and the local bitmap information can correspond to the same core group, update the local bitmap information of the target directory table entry according to the cache block operation type corresponding to the cache consistency maintenance operation.

[0116] Because CPUs with different performance levels support different core grouping rules, this application, in determining whether the current processor core and the local bitmap information correspond to the same core group, first needs to obtain the processor core grouping rule corresponding to the target directory entry, and then determine whether the current processor core and the local bitmap information belong to the same core group based on the processor core grouping rule. The processor core grouping rules in this application include: uniform grouping rules and dynamic grouping rules.

[0117] Therefore, in some embodiments, step S432, "determining whether the first target kernel information and the local bitmap information correspond to the same kernel group," includes:

[0118] Step S4321: Obtain the processor core grouping rule corresponding to the target directory entry, wherein the processor core grouping rule is a uniform grouping rule or a dynamic grouping rule.

[0119] Step S4322: The uniform grouping rule divides all processor cores into multiple core groups evenly according to the core group size, and the starting core number of the core group is an integer multiple of the core group size. When updating the local bitmap information of the target directory entry, the uniform grouping rule requires that the core group of the directory entry remain unchanged.

[0120] Step S4323: The dynamic grouping rule does not restrict the starting core number of the core group, and when updating the local bitmap information of the target directory entry, the dynamic grouping rule allows changes to the core group of the directory entry.

[0121] Step S4324: When the cache block operation type is data modification, confirm that the first target core information and the local bitmap information can correspond to the same core group;

[0122] Step S4325: When the cache block operation type is not data modification, determine whether the first target core information and the local bitmap information can correspond to the same core group according to the processor core grouping rules.

[0123] In some embodiments, when the cache block operation type is data modification, all valid copies of processor cores other than the current processor core will be invalidated, so that there will only be one valid copy in the end. The local bitmap information can continue to be used to record the sharing situation. Therefore, it can be confirmed that the first target core information and the local bitmap information correspond to the same core group, and the same core group is the corresponding core group determined by the current processor core according to the processor core grouping rules.

[0124] In some embodiments, when the processor core grouping rule is the dynamic grouping rule, step S4325, "determining whether the first target core information and the local bitmap information can correspond to the same core group according to the processor core grouping rule," includes:

[0125] Step SC1: Obtain the core group of the directory table entries for the local bitmap information.

[0126] Step SC2: Determine whether the first target core information belongs to the directory table entry core group.

[0127] Step SC3: When the first target kernel information belongs to the directory table entry kernel group, confirm that the first target kernel information and the local bitmap information correspond to the same kernel group.

[0128] Step SC4: When the first target kernel information does not belong to the directory table entry kernel group, obtain the shared bitmap of the local bitmap information.

[0129] Step SC5: Determine the target processor core that has a valid copy of the target cache block based on the shared bitmap, the directory entry core group, and the first target core information.

[0130] Step SC6: Determine whether the target processor cores of each valid copy belong to the same core group.

[0131] In some embodiments, step SC6, "determining whether the target processor cores of each valid copy belong to the same core group," includes:

[0132] Step SE1: Obtain the preset shared bitmap width threshold for the local bitmap information.

[0133] Step SE2: Determine the number difference between the maximum number and the minimum number based on the number of each of the target processor cores.

[0134] Step SE3: Determine whether the target processor cores of each valid copy can be in the same core group based on the numerical relationship between the number difference and the shared bitmap width threshold.

[0135] Step SE4: When the difference in the number is less than the shared bitmap width threshold, it is determined that the first target core information and the local bitmap information correspond to the same core group.

[0136] Because dynamic grouping rules do not require the starting core number of a core group to be an integer multiple of the core group size, allowing any processor core number as the starting core number, directory entry core groups under dynamic grouping rules can only be identified using the core number representing the core within the core group. Furthermore, under dynamic grouping rules, the directory entry core group of a directory entry's local bitmap information can dynamically change with access to the directory entry. For example, given a maximum shared bitmap width threshold of 8, when a target directory entry is created due to access to the target cache block by core 113, the local bitmap information of the target directory entry can be initialized to <core group flag = 113, shared bitmap = 10000000>. At this time, the shared bitmap can be used to record the sharing status of the cache block between cores 113 and 120. Subsequently, when core 116 accesses the target cache block, the local bitmap information is updated to <core group flag = 113, shared bitmap = 10010000>. Next, if the 111th core accesses the target cache block, the local bitmap information is updated to <core group flag=111, shared bitmap=10100100>, that is, the core group of the directory entry has changed, from cores 113-120 to cores 111-118, and the shared bitmap has also changed (which can be understood as shifting 2 bits to the right).

[0137] Therefore, when the current processing core grouping rule is a dynamic grouping rule, in order to determine whether the first target core information and the local bitmap information can correspond to the same core group, in addition to directly determining whether the current processor core belongs to the current target entry core group of the local bitmap information, it is also necessary to consider whether the current processor core can form a new core group that satisfies the preset rules with other valid copy processor cores. If the current processor core does not belong to the current target entry core group, but can form a new target entry core group with other valid copy processor cores, then it is also considered that the current processor core and the core group corresponding to the local bitmap information are the same core group.

[0138] In some embodiments, when the processor core grouping rule is the uniform grouping rule, step S4325, "determining whether the first target core information and the local bitmap information can correspond to the same core group according to the processor core grouping rule," further includes:

[0139] Step SD1: Obtain the core group of the directory table entries for the local bitmap information.

[0140] Step SD2: Determine whether the first target core information belongs to the directory table entry core group.

[0141] Step SD3: When the first target kernel information belongs to the directory table entry kernel group, confirm that the first target kernel information and the local bitmap information correspond to the same kernel group.

[0142] Step SD4: When the first target kernel information does not belong to the directory table entry kernel group, confirm that the first target kernel information and the local bitmap information cannot correspond to the same kernel group.

[0143] Because the uniform grouping rule divides all processor cores evenly into multiple core groups based on the core group size (i.e., the number of cores in different core groups is basically the same), and no two core groups share a common processor core. Under the uniform grouping rule, the core group of the directory entry can be identified by the core group number or by the number representing the core in the core group; the starting core number of a core group is usually an integer multiple of the core group size. Therefore, when the processor core grouping rule is uniform, it is possible to directly determine whether the first target core information and the local bitmap information correspond to the same core group based on the core number of the current processor core and the core number of the directory entry core group.

[0144] The uniform grouping rules in this application include: fixed uniform kernel uniform grouping rule, dynamic uniform kernel uniform grouping rule, and individual kernel uniform grouping rule.

[0145] If the processor core grouping rule is a fixed, uniform core grouping rule, the processor core grouping rule is consistent across all directory entries, and such core grouping rules will be stored uniformly in the directory or system. However, if the processor core grouping rule is an individual core grouping rule or a dynamic grouping rule, then such grouping rules will be stored in the core group of the directory entry's local bitmap information.

[0146] Therefore, the method for obtaining processor core grouping rules differs for CPUs with different performance levels. In some embodiments, when the processor core grouping rule is a uniform grouping rule for individual cores, step S4321, "obtaining the processor core grouping rule corresponding to the target directory entry," includes:

[0147] Step S43211: When the uniform grouping rule is the fixed uniform core uniform grouping rule, obtain the fixed uniform core uniform grouping rule for all processor cores.

[0148] Step S43212: When the uniform grouping rule is the dynamic unified kernel uniform grouping rule or the individual kernel uniform grouping rule, obtain the individual kernel uniform grouping rule of the target directory table entry.

[0149] Individual core uniform grouping rules and dynamic unified core uniform grouping rules coexist; that is, individual core uniform grouping rules are only needed under dynamic unified core uniform grouping rules. For CPUs that support individual core uniform grouping rules, since the processor core grouping rules can be changed during program execution, different directory entries may be initialized using different unified core uniform grouping rules. For the process of allocating new target directory entries, such as in steps S33-S335, the core group corresponding to the newly allocated target directory entry can be generated based on the specifically set grouping rules, i.e., the unified core uniform grouping rules at that time, thereby initializing the local bitmap information. Of course, when switching modes, and the current recording mode of a target directory entry changes from fuzzy shared information to local bitmap information, since there is only one valid copy of the target cache block at this time, the copies in other processor cores have been invalidated or released. There is no impact of processor cores and directory entries on the implementation of new grouping rules. Therefore, when switching to local bitmap information, the core group of the directory entry for the local bitmap information can be re-determined based on the individual core uniform grouping rules and the second target core information.

[0150] The updates to the target directory entries in this application can be summarized as follows:

[0151] 1) When allocating a new directory entry, in the switching mode, mark the directory entry as recording local bitmap information and determine the directory entry core group for local bitmap information; or in the coexistence mode, determine the directory entry core group for local bitmap information.

[0152] 2) In switching mode, convert local bitmap information into fuzzy shared information. This update operation typically occurs when local bitmap information is used before the directory entry, but the current processor core has read the data and the current processor core and the local bitmap information do not correspond to the same core group.

[0153] 3) Record the current processor core in the local bitmap information of the catalog entry. This update operation usually occurs when the catalog entry can record local bitmap information, the current processor core has read or modified data, and the current processor core and the local bitmap information correspond to the same core group.

[0154] 4) Remove the current processor core from the local bitmap information of the directory entry. This update operation typically occurs when the directory entry can record local bitmap information, the current processor core has discarded its cache block copy, and the current processor core is within the core group corresponding to the local bitmap information.

[0155] 5) Record the current processor core in the fuzzy shared information. This update operation usually occurs when the current processor core has read data and the catalog entry only records fuzzy shared information (using a switching method), or when the current processor core is not within the catalog entry core group of the local bitmap information (using a coexistence method).

[0156] 6) Remove the current processor core from the fuzzy shared information. This update operation typically occurs when the current processor core loses its cache block copy, the directory entry only records fuzzy shared information (using a switching method), or the current processor core is not within the directory entry core group of the local bitmap information (using a coexistence method).

[0157] 7) Delete the directory entry. This update operation typically occurs when the current processor core loses its cache block copy, and then all processor cores no longer have valid cache block copies.

[0158] Therefore, updating the target directory entry includes not only updating the content of local bitmap information or fuzzy shared information, but also the conversion between local bitmap information and fuzzy shared information. When converting local bitmap information to fuzzy shared information, it is necessary to add the number of valid cache block replicas corresponding to the local bitmap information to the sharing count information of the fuzzy shared information, or set the protocol status information of the fuzzy shared information to the corresponding sharing status, and also update the owner core information (core number) in the fuzzy shared information.

[0159] The core idea of ​​this application is to improve the accuracy of recording cache block sharing information through local bitmap information. When it is necessary to invalidate cache block copies based on directory entries, if a switching method is used and the directory entry records local bitmap information, or a coexistence method is used and the fuzzy sharing information records precise sharing information (share count is 0 or share count is 1 and owner core information is valid; or the protocol status information is exclusive, corresponding to a single valid copy and owner core information is valid), then all cache copies will be invalidated point-to-point using the content in the local bitmap information. If a switching method is used and the directory entry records fuzzy sharing information, or a coexistence method is used and the fuzzy sharing information records fuzzy sharing information (share count is 1 and owner core information is invalid, or share count is greater than 1; or protocol status information corresponds to multiple valid copies or owner core information is invalid), then only a broadcast listening method can be used to invalidate cache block copies.

[0160] In addition to the method of this application, those skilled in the art may think of using a two-level directory approach to solve the problem that in the prior art, when there are many processor cores, the bitmap covering all processor cores is very wide, resulting in a large hardware overhead for accurately maintaining cache consistency.

[0161] The two-level directory structure works as follows: the first-level directory is divided into several sections. Each section's directory entries precisely record the sharing of cache blocks within a processor core group based on a bitmap (the bitmap width is the number of cores in the core group). The second-level directory entries record the sharing of cache blocks between core groups based on a bitmap (the bitmap width is the number of core groups). Compared to a single-level directory method based on a complete bitmap, this method effectively reduces the hardware space occupied by the directory, but increases directory lookup latency (usually requiring a lookup of the first-level directory first, followed by the second-level directory). Compared to a single-level directory method based on fuzzy sharing information, this method ensures the accuracy of the shared information recording, but increases hardware capacity overhead by more than double and increases directory lookup latency.

[0162] The method proposed in this application incurs almost no hardware overhead (using a switching approach) or only a small hardware overhead (using a coexistence approach), and virtually no increase in directory lookup latency. When well-integrated with applications, it can significantly increase the accuracy of shared information records. Therefore, the technology in this application is more promising for application than the two-level directory method.

[0163] Therefore, the method of this application provides a directory update method for maintaining cache consistency, comprising: responding to a cache consistency maintenance operation initiated by the current processor core, obtaining the target cache block targeted by the cache consistency maintenance operation and the first target core information of the current processor core; determining the target directory entry corresponding to the target cache block; obtaining the current recording method of the target directory entry for shared information; and updating the target directory entry according to the first target core information and the current recording method. This application provides multiple recording methods for shared information, with different recording methods matching different cache block distribution methods. This allows for a more efficient method to determine the cache blocks that need cache consistency maintenance when performing cache consistency operations, greatly improving the efficiency of data sharing and interaction. It solves the problem that using only fuzzy shared record methods in the prior art makes data sharing and interaction very inefficient. Furthermore, it does not increase the latency of directory lookups and can be combined with programs to improve the accuracy of shared information recording.

[0164] Example 2:

[0165] Secondly, this application provides a computer electronic production device, such as... Figure 2As shown, it includes: at least one processor 901; and a memory 902 communicatively connected to the at least one processor 901; wherein the memory 902 stores instructions executable by the at least one processor 901, the instructions being executed by the at least one processor 901 to enable the at least one processor 901 to execute a drilling early warning method in the above embodiments.

[0166] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0167] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0168] In addition, the computer device may include (but is not limited to) a data bus, an input / output (I / O) bus, a display, and input / output devices (e.g., keyboard, mouse, speakers, etc.).

[0169] The processor can communicate with external devices via the I / O bus through wired or wireless networks.

[0170] In one embodiment, the at least one computer-executable instruction may also be compiled into or comprise a software product / computer program product, wherein one or more computer-executable instructions are executed by a processor to perform the steps of the various functions and / or methods in the embodiments described herein.

[0171] Example 3:

[0172] Thirdly, this application proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the first aspects.

[0173] Computer-readable storage media can be implemented by any type of volatile or non-volatile storage device or a combination thereof. Computer-readable storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, and computer storage media (e.g., hard disks, floppy disks, solid-state drives, removable disks, CD-ROMs, DVD-ROMs, Blu-ray discs, etc.).

[0174] Computer-readable storage media may also store at least one computer-executable program / instruction, such as computer-readable instructions. Computer-readable storage media include, but are not limited to, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Computer-readable storage media may include, for example, read-only memory (ROM), hard disk, flash memory, etc. For example, a non-transitory computer-readable storage medium may be connected to a computing device such as a computer, and then, when the computing device executes the computer-readable instructions stored on the computer-readable storage medium, the various methods described above can be performed.

[0175] Example 4:

[0176] Fourthly, this application proposes a computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the method described in any of the first aspects.

[0177] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0178] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0179] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0180] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0181] In the embodiments provided in this disclosure, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0182] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a controller to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0183] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0184] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A directory update method for maintaining cache consistency, characterized in that, include: In response to a cache coherence maintenance operation initiated by the current processor core, the target cache block targeted by the cache coherence maintenance operation and the first target core information of the current processor core are obtained, wherein the first target core information includes the number of the current processor core; Determine the target directory entry corresponding to the target cache block; Obtain the current recording method of the target directory entry for shared information, wherein the current recording method is one of local bitmap information, fuzzy shared information, or coexistence mode; Update the target directory entries based on the first target core information and the current recording method; When the current recording method is local bitmap information, updating the target directory entry based on the first target kernel information and the current recording method includes: Obtain the local bitmap information of the target directory entry, wherein the local bitmap information is used to record the sharing status of the target cache block within the directory entry core group; Determine whether the first target kernel information and the local bitmap information correspond to the same kernel group; When the first target core information and the local bitmap information correspond to the same core group, the local bitmap information of the target directory table entry is updated according to the cache block operation type corresponding to the cache consistency maintenance operation.

2. The method according to claim 1, characterized in that, When the current recording method is the fuzzy shared information, updating the target directory entry based on the first target kernel information and the current recording method further includes: Obtain the cache block operation type corresponding to the cache consistency maintenance operation; The fuzzy shared information is updated based on the cache block operation type and the first target kernel information.

3. The method of claim 1, wherein, When the current recording method is local bitmap information, updating the target directory entry based on the first target kernel information and the current recording method further includes: When the first target core information and the local bitmap information do not correspond to the same core group, the number of valid copies of the target cache block and the core number of the processor core where each valid copy is located are obtained through the local bitmap information. Switch the current recording method of the target directory entry from local bitmap information to fuzzy shared information; The sharing count information or protocol status information in the fuzzy sharing information is determined based on the number of valid copies. The owner core information in the fuzzy shared information is determined based on the core number of the processor core where each valid copy is located and the first target core information.

4. The method according to claim 2, characterized in that, The step of updating the fuzzy shared information according to the cache block operation type and the first target kernel information includes: Update the sharing count information or protocol status information of the fuzzy shared information according to the cache block operation type; Determine whether to update the owner kernel information of the fuzzy shared information based on the cache block operation type; Specifically, when the cache block operation type is data modification, the owner core information is updated according to the first target core information.

5. The method according to claim 2, characterized in that, When the current recording method is the fuzzy sharing information, the fuzzy sharing information includes: sharing count information or protocol status information; updating the target directory entry according to the first target kernel information and the current recording method further includes: When the shared count information is updated to 1 or the protocol status information is updated to exclusive status, and the owner core information of the fuzzy shared information is meaningful, the second target core information is determined based on the owner core information; Update the current recording method of the target directory entry from the fuzzy shared information to local bitmap information; Determine the current target core group corresponding to the second target core information; Set the directory entry core group of the local bitmap information as the current target core group; A shared bitmap of the local bitmap information is generated based on the second target kernel information and the current target kernel group.

6. The method according to claim 1, characterized in that, When the current recording mode is the coexistence mode, updating the target directory entry based on the first target core information and the current recording mode further includes: Obtain the local bitmap information of the target directory entry, wherein the local bitmap information is used to record the sharing status of the target cache block within the directory entry core group; Determine whether the first target kernel information and the local bitmap information correspond to the same kernel group; When the first target core information and the local bitmap information do not correspond to the same core group, the fuzzy shared information of the target directory table entry is updated according to the cache block operation type corresponding to the cache consistency maintenance operation. When the first target core information and the local bitmap information correspond to the same core group, the local bitmap information of the target directory table entry is updated according to the cache block operation type corresponding to the cache consistency maintenance operation.

7. The method according to claim 1, characterized in that, The method for obtaining the current record of the shared information in the target directory entry includes: Determine whether a target directory entry corresponding to the target cache block exists in the directory; When there is no target directory entry corresponding to the target cache block in the directory, a target directory entry is generated based on the target cache block; wherein, the current recording mode of the target directory entry is set to a preset initial recording mode, and the preset initial recording mode is one of local bitmap information or coexistence mode; The shared bitmap and directory entry core group of the local bitmap information of the target directory entry are initialized based on the first target core information.

8. The method according to any one of claims 1 or 6, characterized in that, The step of determining whether the first target kernel information and the local bitmap information correspond to the same kernel group includes: Obtain the processor core grouping rule corresponding to the target directory entry, wherein the processor core grouping rule is a uniform grouping rule or a dynamic grouping rule; The uniform grouping rule divides all processor cores into multiple core groups evenly according to the core group size, and the starting core number of the core group is an integer multiple of the core group size; when updating the local bitmap information of the target directory entry, the uniform grouping rule requires that the core group of the directory entry remain unchanged; The dynamic grouping rule does not restrict the starting core number of the core group, and when updating the local bitmap information of the target directory entry, the dynamic grouping rule allows changes to the core group of the directory entry; When the cache block operation type is data modification, it is confirmed that the first target core information and the local bitmap information can correspond to the same core group. When the cache block operation type is not data modification, the processor core grouping rules are used to determine whether the first target core information and the local bitmap information can correspond to the same core group.

9. The method according to claim 8, characterized in that, When the processor core grouping rule is the dynamic grouping rule, the step of determining whether the first target core information and the local bitmap information can correspond to the same core group according to the processor core grouping rule includes: The core group of the directory table entries for obtaining the local bitmap information; Determine whether the first target core information belongs to the directory table entry core group; When the first target kernel information belongs to the directory entry kernel group, it is confirmed that the first target kernel information and the local bitmap information correspond to the same kernel group. When the first target kernel information does not belong to the directory table entry kernel group, obtain the shared bitmap of the local bitmap information; The target processor core that has a valid copy of the target cache block is determined based on the shared bitmap, the directory entry core group, and the first target core information; Determine whether the target processor cores of each valid copy belong to the same core group.

10. The method according to claim 9, characterized in that, The step of determining whether the target processor cores of each valid copy belong to the same core group includes: Obtain a preset shared bitmap width threshold for the local bitmap information; The number difference between the maximum and minimum numbers is determined based on the number of the target processor core of each valid copy; Based on the numerical relationship between the number difference and the shared bitmap width threshold, it is determined whether the target processor cores of each valid copy can be in the same core group; When the difference in the number is less than the shared bitmap width threshold, it is determined that the first target kernel information and the local bitmap information correspond to the same kernel group.

11. The method according to claim 8, characterized in that, When the processor core grouping rule is the uniform grouping rule, the step of determining whether the first target core information and the local bitmap information can correspond to the same core group according to the processor core grouping rule includes: The core group of the directory table entries for obtaining the local bitmap information; Determine whether the first target core information belongs to the directory table entry core group; When the first target kernel information belongs to the directory entry kernel group, it is confirmed that the first target kernel information and the local bitmap information correspond to the same kernel group. When the first target kernel information does not belong to the directory table entry kernel group, it is confirmed that the first target kernel information and the local bitmap information cannot correspond to the same kernel group.

12. The method according to claim 8, characterized in that, The uniform grouping rules include: fixed uniform kernel uniform grouping rules, dynamic uniform kernel uniform grouping rules, and individual kernel uniform grouping rules; The fixed uniform core uniform grouping rule cannot be changed after the operating system is started, while the dynamic uniform core uniform grouping rule can be changed by the operating system or application after the operating system is started. The individual core uniform grouping rule is set as the processor core grouping rule when initializing the target directory table entry; When the processor core grouping rule is the uniform grouping rule, obtaining the processor core grouping rule corresponding to the target directory entry includes: When the uniform grouping rule is the fixed uniform core uniform grouping rule, obtain the fixed uniform core uniform grouping rule for all processor cores; When the uniform grouping rule is the dynamic unified kernel uniform grouping rule or the individual kernel uniform grouping rule, obtain the individual kernel uniform grouping rule of the target directory table entry.

13. A computer electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method according to any one of claims 1-12.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 12.

15. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-12.

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