Self-aligned isolation method

Abstract

The invention provides a self-aligned isolation method. The method comprises the following steps: forming a sacrificial layer on a substrate, and sequentially forming an isolation wall and a functional layer on the side wall of the sacrificial layer; and then the isolation wall is removed to form a groove, and the groove is filled with an insulating material, so that a self-aligned isolation structure is formed between the sacrificial layer and the functional layer. When the sacrificial layer is subsequently etched by using a mask to form a cavity, the self-aligned isolation structure serves as a vertical etching stop layer, and effective lateral protection is provided for the functional layer. The method solves the problems that an etching process window is narrow and a functional area is easy to damage due to lack of lateral protection in the prior art, and has the beneficial effects that the process window is obviously expanded, the etching defect is effectively prevented, and the manufacturing yield and the performance of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a self-aligned isolation method. BACKGROUND

[0002] In the manufacturing process of high-performance semiconductor devices, such as silicon germanium (SiGe) heterojunction bipolar transistor (HBT), in order to reduce the parasitic capacitance of the device and improve its high-frequency performance, it is usually necessary to make a cavity structure in a specific area of the device (for example, between the base and the collector).

[0003] A conventional method for realizing such a cavity structure is to first deposit a sacrificial layer (for example, sacrificial polysilicon), and then remove it by etching, thereby leaving a desired cavity at its original position. In the process of etching the sacrificial layer, in order to protect the adjacent functional area (for example, the base area) from being damaged, an etching stop layer is usually provided at the bottom of the sacrificial layer.

[0004] However, the etching stop layer in the prior art usually only exists at the bottom of the sacrificial layer, and its lateral size is limited. This results in a very narrow process window when etching the sacrificial layer. If there is a slight mask alignment offset in the etching process or process fluctuation causes over-etching, the etching will laterally erode into the adjacent functional area, thereby causing defects and seriously affecting the performance and manufacturing yield of the device. Therefore, how to provide effective lateral protection for the etching of the sacrificial layer and thereby expand the process window is a technical problem to be solved in the field. SUMMARY

[0005] The technical problem to be solved by the present application is that in the prior art, in the process of forming a cavity by etching a sacrificial layer, an etching stop layer is usually only provided at the bottom of the sacrificial layer, and there is a lack of effective lateral protection for the adjacent functional area. This results in a very narrow etching process window, and when alignment offset or over-etching occurs, the functional area is easily damaged, resulting in defects such as pitting, thereby affecting the performance and manufacturing yield of the device.

[0006] To solve the above technical problems, the present application provides a self-aligned isolation method, comprising the following steps:

[0007] Step one, forming a sacrificial layer on a substrate;

[0008] Step two, forming an isolation wall on the sidewall of the sacrificial layer;

[0009]

[0009] Step three, forming a functional layer beside the sidewall of the isolation wall;

[0010] Step four, removing the isolation wall to form a trench between the sacrificial layer and the functional layer;

[0011] Step five, filling the trench with an insulating material to form a self-aligned isolation structure; and

[0012] Step six, etching the sacrificial layer with a mask to form a cavity, wherein the isolation structure provides lateral protection for the functional layer during the etching process.

[0013] Preferably, before the step one, the method further comprises forming a liner layer on the substrate.

[0014] Preferably, the liner layer comprises an oxide layer.

[0015] Preferably, in the step one, the sacrificial layer comprises a polysilicon layer.

[0016] Preferably, in the step two, the spacer wall comprises a nitride layer.

[0017] Preferably, the nitride layer is a silicon nitride layer.

[0018] Preferably, in the step three, the functional layer is an epitaxial layer.

[0019] Preferably, before the step three, the method further comprises removing the exposed liner layer on the substrate.

[0020] Preferably, the epitaxial layer comprises a silicon layer or a silicon germanium layer.

[0021] Preferably, in the step four, the spacer wall is removed by a wet etching process.

[0022] Preferably, in the step five, the insulating material is an oxide.

[0023] Preferably, the oxide is an oxide formed by a high-density plasma chemical vapor deposition process.

[0024] Preferably, in the step six, the mask comprises a photoresist layer and a bottom anti-reflective coating layer.

[0025] Preferably, the method is used for manufacturing a silicon germanium device.

[0026] Preferably, the method is used for manufacturing a silicon germanium device. As mentioned above, the self-aligned isolation method of the present application has the following beneficial effects:

[0027] The present application forms an isolation structure between the sacrificial layer and the functional layer by using a self-alignment process of "spacer formation-spacer removal-filling", which does not need additional photolithography alignment steps, simplifies the process flow and avoids overlay alignment errors. The self-alignment isolation structure formed acts as an etching stop layer in the vertical direction in the subsequent step of etching the sacrificial layer to form a cavity, thereby providing reliable and effective lateral protection for the adjacent functional layer. Due to the lateral protection, even if over-etching occurs due to mask alignment deviation or process fluctuations during etching, lateral etching to the functional area is effectively prevented, thereby avoiding the generation of etching defects and protecting the integrity of the functional area. Finally, by providing effective lateral protection, the present application significantly expands the process window of the cavity etching process, improves the stability and fault tolerance of the process, and has important significance for improving the manufacturing yield and electrical performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 a flowchart of a self-alignment isolation method according to an embodiment of the present application;

[0029] Figure 2 a cross-sectional structure diagram of a self-alignment isolation method according to an embodiment of the present application after forming an isolation wall;

[0030] Figure 3 a cross-sectional structure diagram of a self-alignment isolation method according to an embodiment of the present application after forming a functional layer;

[0031] Figure 4 a cross-sectional structure diagram of a self-alignment isolation method according to an embodiment of the present application after removing the isolation wall;

[0032] Figure 5 a cross-sectional structure diagram of a self-alignment isolation method according to an embodiment of the present application after filling insulating material;

[0033] Figure 6 a cross-sectional structure diagram of a self-alignment isolation method according to an embodiment of the present application after forming a cavity. DETAILED DESCRIPTION

[0034] The embodiments of the present application will be described in detail with specific reference to particular examples. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied in other different embodiments, and the details in this specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0035] Figure 1 a flowchart of a self-alignment isolation method according to an embodiment of the present application; Figures 2 to 6are cross-sectional structural schematic diagrams of the method according to some embodiments of the present application at various manufacturing stages. The following will be described in detail in conjunction with Figures 2 to 6 The method steps in Figure 1 will be described in detail.

[0036] Embodiments of the present application provide a self-aligned isolation method. The method can be implemented on different types of substrates. The substrate can include but is not limited to bulk semiconductor substrates such as silicon substrates, germanium substrates or substrates made of other III-V or II-VI semiconductor materials; it can also be a silicon-on-insulator (SOI) substrate which can include a buried oxide layer (BOX) and a semiconductor layer on the buried oxide layer; in addition, the substrate can also be a structure containing multiple epitaxial layers or a structure with other functional layers or devices formed on a semiconductor substrate. In some preferred embodiments, the substrate is a doped or undoped silicon substrate. In the drawings, reference numeral 101 schematically represents a substrate.

[0037] In some embodiments, before step one, it further includes forming a liner layer 102 on the substrate 101. The liner layer can serve to buffer the stress between the substrate and the subsequently deposited layers, and protect the substrate surface from damage in subsequent processes.

[0038] In some embodiments, the liner layer 102 includes an oxide layer. For example, a layer of silicon dioxide can be grown on a silicon substrate as the liner layer by a thermal oxidation process. Alternatively, the oxide layer can also be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) and the like. In addition to oxide, the liner layer can also be a nitride layer (such as silicon nitride) or a multilayer structure of oxide / nitride / oxide (ONO), the specific choice depends on the compatibility of subsequent processes and the requirements on device performance.

[0039] In step one, a sacrificial layer 103 is formed on the substrate 101. The sacrificial layer is a temporary structure, and its main function is to reserve a position for the subsequent formation of a cavity in the space it occupies.

[0040] In some embodiments, in step one, the sacrificial layer 103 includes a polysilicon layer (dummy poly). The method of forming the polysilicon layer can include low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In addition to polysilicon, the sacrificial layer can also be selected from other materials that can be removed with high selectivity, such as amorphous silicon, germanium, silicon-germanium alloy, or even certain specific organic polymers or amorphous carbon layers, as long as there is a large enough etching selectivity between the material and the functional layer and the isolation structure material.

[0041] In step two, an isolation wall 104 is formed on the sidewall of the sacrificial layer 103. This isolation wall serves as a spacer for the subsequent formation of a self-isolating quasi-isolation structure. After completing steps one and two, the resulting structure is as follows: Figure 2 As shown. A pad layer 102 is formed on the substrate 101, a sacrificial layer 103 is formed on the pad layer 102, and isolation walls 104 are covered on the sidewalls of the sacrificial layer 103. In some embodiments, such as... Figure 2 As shown, the isolation wall 104 not only covers the sidewalls of the sacrificial layer 103, but some isolation wall material may also remain on its top, forming a cap structure covering the top of the sacrificial layer 103. This depends on the specific parameters of the anisotropic etching process, and this cap structure may also play a role in protecting the top of the sacrificial layer from erosion in some subsequent processes.

[0042] In some embodiments, in step two, the isolation wall 104 includes a nitride layer. This nitride layer has good etch selectivity relative to the insulating material (e.g., oxide) to be subsequently filled and the sacrificial layer (e.g., polysilicon), which allows it to be precisely removed without damaging adjacent structures.

[0043] In some embodiments, the nitride layer is a silicon nitride (SiN) layer. The specific process for forming the silicon nitride spacer typically involves: first, conformally depositing a silicon nitride thin film across the entire wafer surface using methods such as LPCVD or PECVD; then, vertically etching the silicon nitride film downwards using an anisotropic dry etching process (e.g., reactive ion etching, RIE) without a mask. Due to the anisotropy of the etching, the silicon nitride on the horizontal surfaces (the top of the sacrificial layer and the substrate surface) is removed, while the silicon nitride on the vertical sidewalls is retained, thus forming the spacer structure. Besides silicon nitride, other dielectric materials such as silicon oxynitride (SiON), silicon carbide (SiC), or certain low-k materials can also be used to form the spacer, chosen based on their chemoselectivity with subsequent removal processes.

[0044] In step three, a functional layer 105 is formed next to the sidewall of the isolation wall 104. This functional layer is the core working region in the semiconductor device, such as the base or emitter of a transistor. The structure at this point is as follows: Figure 3 As shown, the functional layer 105 is formed next to the sidewall of the isolation wall 104 and is in contact with the substrate 101.

[0045] In some embodiments, in step three, the functional layer 105 is an epitaxial layer (EPI). Epitaxial growth is a technique to grow a thin film of single crystal on a crystalline substrate with the same crystal orientation as the substrate. This process can be achieved in various ways, including vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD). By precisely controlling the gas flow, temperature, and pressure during the growth process, a high-quality crystalline layer with specific doping concentration and composition can be obtained.

[0046] In some embodiments, prior to step three, the exposed pad layer 102 on the substrate 101 is removed. This step is to expose the underlying substrate surface, providing a clean growth interface for the subsequent high-quality epitaxial growth. For example, if the pad layer is an oxide, it can be removed by a wet clean using diluted hydrofluoric acid (DHF) solution; if the pad layer is a nitride, it can be removed using hot phosphoric acid.

[0047] In some embodiments, the epitaxial layer includes a silicon layer or a silicon-germanium layer (SiGe). By introducing a germanium source (such as germane GeH4) during the epitaxial growth, a silicon-germanium alloy layer can be grown on a silicon substrate. For HBT devices, the device performance can be optimized by adjusting the concentration gradient of germanium. In addition to silicon and silicon-germanium, the functional layer can also be other semiconductor materials, such as III-V materials (such as gallium arsenide GaAs, indium phosphide InP, etc.), depending on the type of device being manufactured.

[0048] In step four, the isolation wall 104 is removed to form a trench between the sacrificial layer 103 and the functional layer 105. Since the isolation wall is removed, the space it originally occupied forms a precisely aligned narrow trench, with a structure as shown in Figure 4 .

[0049] In some embodiments, in step four, the isolation wall is removed by a wet etching process. Wet etching has very high selectivity. For example, when the isolation wall is silicon nitride, and the surrounding materials are polysilicon and oxide, hot phosphoric acid is an ideal etchant. Depending on the material of the isolation wall, other etchants can also be selected, for example, for some dielectric materials, specific chemical solvents or fluoride-based aqueous solutions can be used for removal. The core principle of selecting an etchant is that its etching rate for the isolation wall material is much greater than that for the sacrificial layer, functional layer, and pad layer.

[0050] In step five, the trench is filled with insulating material 106 to form a self-aligned isolation structure. Since this isolation structure is formed using the space left by the previous isolation wall (spacer), its position is self-aligned relative to the sacrificial layer and the functional layer, without the need for additional photolithography alignment steps, thereby improving process accuracy and reducing cost. The structure after completing this step is shown in Figure 5 .

[0051] In some embodiments, the insulating material is an oxide.

[0052] In some embodiments, the oxide is an oxide formed by a high-density plasma chemical vapor deposition (HDP-CVD) process (HDP OX). In addition to HDP-CVD, other deposition techniques with good trench-filling capability can also be used, such as sub-atmospheric chemical vapor deposition (SACVD) or spin-on dielectric (SOD) techniques. The insulating material is not limited to silicon oxide, but can also be a doped silicate glass (e.g., phosphorus-doped silicon glass PSG, boron-doped phosphorus-silicon glass BPSG), or a material with a lower dielectric constant (low-k material), such as carbon-doped silicon oxide (SiOC), etc., to further reduce the parasitic capacitance. After filling, a chemical mechanical polishing (CMP) or etch-back process is usually needed to remove the excess insulating material and planarize the surface, in preparation for subsequent processes.

[0053] In step six, the sacrificial layer 103 is etched using a mask to form cavities. In this step, the self-aligned isolation structure 106 formed in step five plays a key role. The final cavity structure is shown in FIG. 6. Figure 6

[0054] In some embodiments, in step six, the mask includes a photoresist layer (PR) 108 and a bottom anti-reflective coating (BARC) 107. The formation of the mask itself is a standard photolithography process, including spin-coating BARC and photoresist, exposure by a photolithography machine, and development, etc.

[0055] The isolation structure 106 formed on the side wall of the sacrificial layer serves as a vertical etching stop layer during the etching of the sacrificial layer 103. The etching process of the sacrificial layer can be dry etching or wet etching. For example, for a polysilicon sacrificial layer, dry etching based on fluorine or chlorine plasma (such as SF6 or Cl2) or wet etching using an alkaline solution such as tetramethylammonium hydroxide (TMAH) can be used. The conventional stop layer is only located at the bottom of the sacrificial layer and cannot provide lateral protection. The self-aligned isolation structure 106 in the present application is immediately adjacent to the sacrificial layer, and even if there is a mask alignment offset or over-etching, the lateral spread of etching will be effectively blocked by the isolation structure 106 when etching occurs. This provides effective lateral protection for the adjacent functional layer 105, avoiding the erosion of the functional layer by etching gas or plasma, thereby effectively preventing the occurrence of etching defects. Finally, by providing such lateral protection, the present method significantly expands the process window for etching the sacrificial layer, improves the stability and tolerance of the process, and has important significance for improving the yield and electrical performance of the device.

[0056] ​The method of the embodiment of the present application can be applied to the manufacture of semiconductor devices, and is particularly suitable for high-frequency devices with strict requirements on parasitic capacitance.

[0057] In some embodiments, the method is used for manufacturing a silicon germanium device.

[0058] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus the diagrams only show the components related to the present application, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0059] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A self-aligned isolation method, characterized by, At least comprising: Step one, forming a sacrificial layer on a substrate; Step two, forming an isolation wall on the sidewall of the sacrificial layer; Step three, forming a functional layer beside the sidewall of the isolation wall; Step four, removing the isolation wall to form a trench between the sacrificial layer and the functional layer; Step five, filling insulating material in the trench to form a self-aligned isolation structure; Step six, etching the sacrificial layer with a mask to form a cavity, wherein the isolation structure provides lateral protection for the functional layer during etching.

2. The self-aligned isolation process of claim 1 wherein: Before the step one, further comprising: forming a liner layer on the substrate.

3. The self-aligned isolation process of claim 2 wherein: The liner layer comprises an oxide layer.

4. The self-aligned isolation process of claim 1 wherein: In the step one, the sacrificial layer comprises a polysilicon layer.

5. The self-aligned isolation process of claim 1 wherein: In the step two, the isolation wall comprises a nitride layer.

6. The self-aligned isolation process of claim 5 wherein, The nitride layer is a silicon nitride layer.

7. The self-aligned isolation process of claim 1 wherein: In the step three, the functional layer is an epitaxial layer.

8. The self-aligned isolation process of claim 2 wherein: Before the step three, further comprising: removing the exposed liner layer on the substrate.

9. The self-aligned isolation process of claim 7 wherein: The epitaxial layer comprises a silicon layer or a silicon germanium layer.

10. The self-aligned isolation process of claim 1 wherein: In the step four, the isolation wall is removed by a wet etching process.

11. The self-aligned isolation process of claim 1 wherein: In the step five, the insulating material is an oxide.

12. The self-aligned isolation process of claim 11 wherein: The oxide is an oxide formed by a high-density plasma chemical vapor deposition process.

13. The self-aligned isolation process of claim 1 wherein: In the step six, the mask comprises a photoresist layer and a bottom anti-reflective coating layer.

14. The self-aligned isolation process of claim 1 wherein: The method is used for manufacturing a silicon germanium device.

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