Efficient autoregressive inference using statically compiled large language model (LLM)

Abstract

A processor-implemented method for adapting autoregressive inference of a large language model (LLM) to static compilation includes defining a static data structure of maximum size and a variable data mask. The variable data mask indicates an active portion of the data structure of the largest size. A valid data set is determined by applying a variable data mask to a static data structure of maximum size. Computations are performed using only the valid data sets.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Indian Patent Application No. 202341045999, filed on July 8, 2023, entitled “EFFICIENT AUTOREGRESSIVE INFERENCE OF LARGE LANGUAGE MODELS (LLMs) WITH STATIC COMPILATION”, the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0003] The various aspects of this disclosure generally relate to artificial neural networks, and more specifically to efficient autoregressive inference using statically compiled large language models (LLMs). Background Technology

[0004] Artificial neural networks can comprise interconnected groups of artificial neurons (e.g., neuron models). Artificial neural networks can be computing devices or represented as methods to be performed by computing devices. Convolutional neural networks (CNNs) are a type of feedforward artificial neural network. A CNN can comprise an ensemble of neurons, where each neuron has a receptive field and collectively constructs the input space. CNNs, such as deep convolutional neural networks (DCNs), have numerous applications. Specifically, these neural network architectures are used in various technologies such as image recognition, speech recognition, acoustic scene classification, keyword retrieval, autonomous driving, and other classification tasks.

[0005] Large Language Models (LLMs) are gaining popularity due to their usefulness on various natural language processing tasks. LLMs can receive prompts from the user and then generate responses or completions. However, LLMs can be inefficient in generating completions.

[0006] One way to address inefficiency is to use a compiler. Static compilation of neural networks can generate efficient executables. This is partly because the compiler uses fixed-size tensors and static computation. Figure 1 The work begins. However, autoregressive inference of LLMs produces tensors of varying sizes. Compiling LLMs is challenging. Summary of the Invention

[0007] The present disclosure is set forth in the independent claims. Some aspects of the present disclosure are described in the dependent claims.

[0008] In some aspects of this disclosure, a processor-implemented method executed by one or more processors includes defining a maximum-size static data structure and a variable-size data mask. The variable-size data mask indicates the valid portion of the maximum-size static data structure. The processor-implemented method also includes determining the valid dataset by applying the variable-size data mask to the maximum-size static data structure. The processor-implemented method further includes performing computations using only the valid dataset.

[0009] Various aspects of this disclosure relate to an apparatus including components for defining a maximum-size static data structure and a variable-size data mask. The variable-size data mask indicates the valid portion of the maximum-size static data structure. The apparatus also includes components for determining the valid dataset by applying the variable-size data mask to the maximum-size static data structure. The apparatus further includes components for performing computations using only the valid dataset.

[0010] In some aspects of this disclosure, a non-transitory computer-readable medium having program code recorded thereon is disclosed. This program code is executed by a processor and includes program code for defining a maximum-size static data structure and a variable-size data mask. The variable-size data mask indicates the valid portion of the maximum-size static data structure. The program code also includes program code for determining the valid dataset by applying the variable-size data mask to the maximum-size static data structure. The program code also includes program code for performing computations using only the valid dataset.

[0011] Various aspects of this disclosure relate to an apparatus having at least one memory and one or more processors coupled to the at least one memory. The processors are configured to define a maximum-size static data structure and a variable-size data mask. The variable-size data mask indicates the valid portion of the maximum-size static data structure. The processors are also configured to determine the valid dataset by applying the variable-size data mask to the maximum-size static data structure. The processors are further configured to perform computations using only the valid dataset. Attached Figure Description

[0012] The features, substance, and advantages of this disclosure will become more apparent when understood in conjunction with the accompanying drawings, in which the same reference numerals are consistently used for identification.

[0013] Figure 1 Example implementations of neural networks using a system-on-a-chip (SoC) (including a general-purpose processor) according to certain aspects of this disclosure are illustrated.

[0014] Figure 2A , Figure 2B and Figure 2C These are illustrations of neural networks according to various aspects of this disclosure.

[0015] Figure 2D This is a diagram illustrating exemplary deep convolutional networks (DCNs) according to various aspects of this disclosure.

[0016] Figure 3 This is a block diagram illustrating exemplary deep convolutional networks (DCNs) according to various aspects of this disclosure.

[0017] Figure 4 This is a block diagram illustrating exemplary software architectures that enable modularization of artificial intelligence (AI) functions according to various aspects of this disclosure.

[0018] Figure 5 This is a block diagram illustrating examples of autoregressive symbol generation using language models, according to various aspects of this disclosure.

[0019] Figure 6 This is a block diagram illustrating an example architecture of an autoregressive language model (ARLM) configured for static compilation according to various aspects of this disclosure.

[0020] Figure 7 This is a flowchart illustrating a method for adapting autoregressive inference of a large language model (LLM) to static compilation according to various aspects of this disclosure. Detailed Implementation

[0021] The detailed description following, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only configurations in which the described concepts can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0022] Based on the teachings, those skilled in the art will recognize that the scope of this disclosure is intended to cover any aspect of this disclosure, whether implemented independently of or in combination with any other aspect of this disclosure. For example, an apparatus or method may be implemented using any number of the aspects described. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods practiced using other structures, functionalities, or structures and functionalities that complement or differ from the various aspects of this disclosure described. It should be understood that any aspect of this disclosure may be embodied by one or more elements of the claims.

[0023] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” need not be interpreted as superior to or better than other aspects.

[0024] While specific aspects have been described, numerous variations and substitutions of these aspects fall within the scope of this disclosure. Although some benefits and advantages of preferred aspects have been mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or purpose. Rather, aspects of this disclosure are intended to be broadly applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the accompanying drawings and the following description of preferred aspects. The detailed description and drawings are merely illustrative and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0025] Static compilation of neural networks (NNs) typically produces efficient executables because they use fixed-size tensors and static computation. Figure 1 The compiler can pre-allocate and pre-schedule computation-related tasks for efficient inference by leveraging the static properties of computational structures (e.g., tensors and computation graphs).

[0026] However, autoregressive inference on Large Language Models (LLMs) lacks such a static computational structure. The function of an LLM is to generate completions (e.g., responses) for prompts. For example, prompts and completions can have variable lengths. Completions can be generated one symbol at a time by performing the same computational graph a variable number of times using a variable-size data structure. The key variable-size data structure is called a KV cache (KV$), whose size can grow during each iteration of symbol generation. Therefore, performing autoregressive inference on LLMs using static compilation techniques is challenging.

[0027] Therefore, to address these and other challenges, aspects of this disclosure relate to adapting autoregressive inference of large language models (LLMs) to static compilation. According to aspects of this disclosure, a maximum-size data structure can be defined and accompanied by another structure called a mask. The mask can indicate the currently valid portion of the maximum-size data structure.

[0028] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the described techniques can improve processing efficiency and reduce latency in autoregressive inference of LLMs.

[0029] Figure 1An example implementation of a system-on-a-chip (SoC) 100 is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured to adapt autoregressive inference of an LLM to static compilation. Variables (e.g., neural signals and synaptic weights), system parameters associated with the computing device (e.g., a weighted neural network), latency, frequency slot information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with the CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from the program memory associated with the CPU 102 or from memory block 118.

[0030] SOC 100 may also include additional processing blocks tailored for specific functions, such as GPU 104, DSP 106, connectivity block 110 (which may include fifth-generation (5G) connectivity, fourth-generation LTE (4G) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and multimedia processor 112 capable of, for example, detecting and recognizing gestures. In one specific implementation, NPU 108 is implemented within CPU 102, DSP 106, and / or GPU 104. SOC 100 may also include sensor processor 114, image signal processor (ISP) 116, and / or navigation module 120, which may include a global positioning system.

[0031] The SOC 100 may be based on the ARM instruction set. In various aspects of this disclosure, instructions loaded into the general-purpose processor 102 may include code for defining a maximum-size static data structure and a variable-size data mask. The variable-size data mask indicates the valid portion of the maximum-size data structure. The general-purpose processor 102 may also include code for determining the valid dataset by applying the variable-size data mask to the maximum-size static data structure. The general-purpose processor 102 may also include code for performing computations using only the valid dataset.

[0032] Deep learning architectures perform object recognition tasks by learning to represent inputs at progressively higher levels of abstraction in each layer, thereby constructing useful feature representations of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Before deep learning, machine learning methods for object recognition problems often relied heavily on human-designed features, possibly in conjunction with shallow classifiers. Shallow classifiers could be two-class linear classifiers, where a weighted sum of feature vector components is compared to a threshold to predict which class the input belongs to. Human-designed features could be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, this requires training. Furthermore, deep networks can learn to represent and recognize novel types of features that humans might not have considered.

[0033] Deep learning architectures can learn hierarchical structures of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power at specific frequencies. The second layer, taking the output of the first layer as input, can learn to recognize combinations of features, such as simple shapes in visual data or combinations of sounds in auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0034] Deep learning architectures perform particularly well when applied to problems with a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to identify features such as wheels, windshields, and others. These features can then be combined in different ways at higher levels to identify cars, trucks, and airplanes.

[0035] Neural networks can be designed to have multiple connectivity patterns. In feedforward networks, information is passed from lower layers to higher layers, where each neuron in a given layer communicates with neurons in higher layers. As described above, hierarchical representations can be built in successive layers of a feedforward network. Neural networks can also have recurrent or feedback (also known as top-down) connections. In recurrent connections, the output from a neuron in a given layer can be passed to another neuron in the same layer. Recurrent architectures can help identify patterns across more than one block of input data that is sequentially delivered to the neural network. Connections from neurons in a given layer to neurons in lower layers are called feedback (or top-down) connections. Networks with many feedback connections can be helpful when the recognition of higher-level concepts can aid in discerning specific lower-level features of the input.

[0036] The connections between layers in a neural network can be fully connected or locally connected. Figure 2A An example of a fully connected neural network 202 is shown. In the fully connected neural network 202, neurons in the first layer can pass their outputs to each neuron in the second layer, so that each neuron in the second layer will receive inputs from each neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is shown. In the locally connected neural network 204, neurons in the first layer can connect to a finite number of neurons in the second layer. More generally, the locally connected layers of the locally connected neural network 204 can be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strength can have different values ​​(e.g., 210, 212, 214, and 216). The connectivity pattern of locally connected layers can produce spatially different receptive fields in higher layers because higher-layer neurons in a given region can receive inputs that are tuned to the characteristics of a restricted portion of the total input to the network through training.

[0037] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is shown. Convolutional neural network 206 can be configured such that the connection strength associated with the input for each neuron in the second layer is shared (e.g., 208). Convolutional neural networks may be well-suited for problems where the spatial location of the input is meaningful.

[0038] One type of convolutional neural network is the deep convolutional network (DCN). Figure 2D A detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as an in-vehicle camera) is provided. The DCN 200 in this example can be trained to identify traffic signs and the numbers provided on them. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or traffic lights.

[0039] Supervised learning can be used to train the DCN 200. During training, an image (such as image 226 of a speed limit sign) can be presented to the DCN 200, and then forward passes can be computed to produce output 222. The DCN 200 may include a feature extraction part and a classification part. Upon receiving image 226, convolutional layer 232 can apply a convolutional kernel (not shown) to image 226 to generate a first set 218 of feature maps. As an example, the convolutional kernel used for convolutional layer 232 may be a 5x5 kernel that generates 28x28 feature maps. In this example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels are applied to image 226 at convolutional layer 232. Convolutional kernels may also be referred to as filters or convolutional filters.

[0040] The first set of feature maps 218 can be subsampled by a max-pooling layer (not shown) to generate a second set of feature maps 220. The max-pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (e.g., 14x14) is smaller than the size of the first set of feature maps 218 (e.g., 28x28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 can be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0041] exist Figure 2D In the example, the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of image 226, such as "sign", "60", and "100". A softmax function (not shown) can convert the numbers in the second feature vector 228 into probabilities. Thus, the output 222 of DCN 200 can be the probability that image 226 includes one or more features.

[0042] In this example, the probabilities for "sign" and "60" in output 222 are higher than the probabilities for other numbers in output 222 (such as "30", "40", "50", "70", "80", "90", and "100"). Before training, output 222 generated by DCN 200 may be incorrect. Therefore, the error between output 222 and the target output can be calculated. The target output is the ground truth value of image 226 (e.g., "sign" and "60"). The weights of DCN 200 can then be adjusted so that output 222 of DCN 200 is more closely aligned with the target output.

[0043] To adjust the weights, the learning algorithm computes the gradient vector of the weights. The gradient indicates by how much the error will increase or decrease as the weights are adjusted. At the top layers, the gradient corresponds directly to the values ​​of the weights connecting the activated neurons in the penultimate layer to the neurons in the output layer. In lower layers, the gradient depends on the values ​​of the weights and the error gradient computed in the higher layers. The weights can then be adjusted to reduce the error. This method of adjusting weights is called "backpropagation" because it involves "passing backward" through the neural network.

[0044] In practice, the error gradient of the weights can be calculated using a small number of examples to make the calculated gradient approximate the true error gradient. This approximation method is called stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, DCN 200 can present a new picture, and the forward pass of DCN 200 can produce an output that can be considered an inference or prediction of DCN 200.

[0045] Deep Belief Networks (DBNs) are probabilistic models that include multiple layers of hidden nodes. DBNs can be used to extract hierarchical representations of training datasets. DBNs are obtained by stacking layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that learns a probability distribution from a set of inputs. Because RBMs can learn a probability distribution without information about the class each input should be classified into, they are often used for unsupervised learning. Using a hybrid paradigm of supervised and unsupervised learning, the bottom RBM of a DBN can be trained unsupervised and used as a feature extractor, while the top RBM can be trained supervisedly (on the joint distribution of inputs from the previous layer and the target class) and used as a classifier.

[0046] DCN is a network of convolutional networks configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many paradigms and are used to modify the network's weights using gradient descent.

[0047] DCNs can be feedforward networks. Furthermore, as described above, connections from neurons in the first layer of a DCN to a set of neurons in the next higher layer are shared across neurons in the first layer. The feedforward and shared connections of a DCN can be used for fast processing. For example, the computational cost of a DCN may be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0048] The processing at each layer of a convolutional network can be thought of as a spatially invariant template or base projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then a convolutional network trained on that input can be considered three-dimensional, with two spatial dimensions along the image's axes and a third dimension capturing color information. The output of the convolutional connections can be viewed as forming a feature map in the next layer, where each element in the feature map (e.g., 220) receives input from a range of neurons in the previous layer (e.g., feature map 218) and from each of the multiple channels. The values ​​in the feature map can be further processed with nonlinearities (such as correction, max(0,x)). Values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and provides additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied through lateral inhibition between neurons in the feature map.

[0049] Figure 3 This is a block diagram illustrating a DCN 350. A DCN 350 can include multiple layers of different types based on connectivity and weight sharing. For example... Figure 3 As shown, DCN 350 includes convolutional blocks 354A and 354B. Each convolutional block in convolutional blocks 354A and 354B can be configured with a convolutional layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.

[0050] Although only two of the convolutional blocks 354A and 354B are shown, this disclosure is not limited thereto, and any number of convolutional blocks 354A and 354B may be included in the DCN 350 according to design preferences.

[0051] Convolutional layer 356 may include one or more convolutional filters that can be applied to the input data to generate feature maps. Normalization layer 358 can normalize the output of the convolutional filters. For example, normalization layer 358 can provide whitening or lateral suppression. Max pooling layer 360 can provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0052] For example, a parallel filter bank of a DCN can be loaded into a SOC 100 (e.g., Figure 1 The CPU 102 or GPU 104 of the SOC 100 can be used to achieve high performance and low power consumption. In an alternative implementation, a parallel filter bank can be loaded onto the DSP 106 or ISP 116 of the SOC 100. Additionally, the DCN 350 can access other processing blocks that may exist on the SOC 100, such as the sensor processor 114 and navigation module 120, which are dedicated to sensors and navigation, respectively.

[0053] The DCN 350 may also include one or more fully connected layers 362 (FC1 and FC2). The DCN 350 may also include logistic regression (LR) layers 364. Weights (not shown) to be updated are located between each of the layers 356, 358, 360, 362, and 364 of the DCN 350. The output of each layer (e.g., 356, 358, 360, 362, and 364) can be used as input to the next layer in the DCN 350 to learn hierarchical feature representations from the input data 352 (e.g., images, audio, video, sensor data, and / or other input data) supplied at the first convolutional block in convolutional block 354A. The output of the DCN 350 is a classification score 366 of the input data 352. The classification score 366 may be a set of probabilities, where each probability is the probability that the input data includes a feature from the feature set.

[0054] Figure 4 This is a block diagram illustrating an exemplary software architecture 400 that enables modularization of artificial intelligence (AI) functionality. According to various aspects of this disclosure, by using architecture 400, various processing blocks of SOC 420 (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) can be designed to support autoregressive inference of large language models (LLMs) adapted to static compilation for AI applications 402. Architecture 400 can, for example, be included in a computing device such as a smartphone.

[0055] AI application 402 can be configured to invoke functions defined in user space 404, which may, for example, provide the detection and recognition of a scene indicating the current location of the computing device (including architecture 400). For example, AI application 402 may configure microphones and cameras differently depending on whether the recognized scene is an office, lecture hall, restaurant, or outdoor environment such as a lake. AI application 402 may make requests to compiled program code associated with libraries defined in the AI ​​Function Application Programming Interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide inferred responses based on, for example, video and location data.

[0056] The runtime engine 408 (which may be compiled code of the runtime framework) may further be accessible to the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request inferences, for example, at specific time intervals or triggered by events detected by the user interface of the AI ​​application 402. Upon causing the runtime engine 408 to provide an inference response, the runtime engine may then signal to the operating system (OS) space 410 running on the SOC 420, such as the kernel 412. In some examples, the kernel 412 may be a LINUX kernel. The operating system may then enable sequential quantization relaxation to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed via drivers, such as drivers 414, 416, or 418 for the DSP 424, GPU 426, or NPU 428, respectively. In an exemplary example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422, DSP 424 and GPU 426, or on NPU 428.

[0057] Various aspects of this disclosure relate to adapting autoregressive inference of large language models (LLMs) to static compilation.

[0058] Figure 5 This is a block diagram illustrating examples of autoregressive symbol generation using language models, according to various aspects of this disclosure. (Reference) Figure 5 Language model 502 can receive symbols or symbol strings as input. A symbol can be considered a sequence of one or more characters (e.g., the average length of a symbol can be approximately four characters). Therefore, language model 502 can receive character sequences, including but not limited to, words, sentences, paragraphs, or documents. In the example, such as... Figure 5 As shown, language model 502 can receive phrases such as "The achilles" as input. Language model 502 can process the input to generate predictions for individual subsequent symbols, such as the word "tendon".

[0059] Language model 502 can be configured to generate multiple subsequent symbols. That is, language model 502 can be configured to perform autoregressive generation by invoking language model 502 with different inputs. Subsequent symbols can be appended to the input to form the next input. For example, language model 502 can receive a first input and process it to generate a first output symbol. The output symbol can be written to memory to retain the internal state KV$ (e.g., a key variable-size data structure called a KV cache). The internal state can be read from memory and appended to the first input, and provided as input to language model 502. This process can continue to repeat in this manner. Thus, language model 502 can generate multiple symbols. However, the size of the internal state KV$ grows as symbols are generated.

[0060] However, as described, autoregressive inference on large language models (LLMs) does not possess such a static computational structure. The function of an LLM is to generate completions (e.g., responses) for prompts. For example, prompts and completions can have variable lengths. By performing the same computational graph a variable number of times using a variable-size data structure, completions can be generated one symbol at a time. The size of KV$ may grow during each iteration of symbol generation. Therefore, performing autoregressive inference on LLMs using static compilation techniques is challenging.

[0061] Dynamic problems cannot be simply solved by statically defining the largest possible data structure, because the range of possible values ​​for dynamic variables can be very high. This is because doing so could significantly degrade model efficiency by performing computations on invalid data within an excessively large data structure.

[0062] In various ways, a maximum-size data structure can be defined. The maximum-size data structure can have a fixed size. This size can be the maximum context length that the LLM can handle. This maximum context length can be the maximum possible sum of the hint length and the generated length, for which the LLM can be invoked. As an example, and not a limitation, the maximum context length can vary from two thousand to hundreds of thousands of symbols (or more), depending on the LLM.

[0063] In various ways, masks indicating the currently valid portion of a data structure of maximum size can be generated. Masks can be generated based on the variable-size internal state of an LLM. It can be viewed as a high-dimensional tensor of a matrix. The size can be set up to the maximum of the rows equal to the maximum context length (CL). The effective portion of the matrix can be... The line begins, in which Initially equal to the cue length used in the pre-filling phase. During each autoregressive call during the decoding phase, Incrementing can be done using 1. Integers. It can be a compact representation of a mask.

[0064] The computation can perform conditional evaluations on the mask and the maximum-sized data structure. That is, the computation can be performed using only the valid portion of the maximum-sized data structure. For example, conditional evaluations can be specified as follows:

[0065] (1),

[0066] in express Query vector, express Key express Result vector Vectors representing constants and This represents a mask indicating the valid portion of a data structure of maximum size. Operations It can be partially calculated. That is, only with respect to... The element corresponding to the bit set in the table can be calculated, and other elements can be directly assigned from the bits specified in the table. The corresponding constant value. Therefore, a static compiler can use conditional evaluation to skip unnecessary computations on other elements of a maximum-size data structure. In some respects, conditional evaluation can skip the entire data flow that leads to the skipped element / computation. In other respects, conditional evaluation can skip all memory accesses associated with unnecessary computations.

[0067] Figure 6 This is a block diagram illustrating an example architecture 600 configured for statically compiled autoregressive language models (ARLMs) according to various aspects of this disclosure. Figure 6 As shown, the example architecture 600 includes a cyclic orchestrator module 602 and an ARLM 604. The cyclic orchestrator module 602 may be located on a host 606, and the ARLM 604 may operate on a device 608. The host 606 may include, but is not limited to, a terminal device such as a smartphone. The device 608 may include, but is not limited to, an inference accelerometer device. In some aspects, the host 606 and the device 608 may be included in the same or separate devices.

[0068] During the pre-filling phase (e.g., initial call), the loop orchestrator module 602 can provide the input symbol set to the ARLM 604. Input symbol set This can be considered a hint about ARLM 604. ARLM 604 processes input symbol sets. And determine the next symbol. ARLM 604 can provide the loop orchestrator module 602 with an output symbol (or corresponding logit) having KV$ and maximum context length (CL).

[0069] During the decoding phase (e.g., subsequent calls), the loop orchestrator module 602 can append the output symbols for the previous call to the input symbol set. This forms the basis for subsequent hints. CL can be used to define the static data structure of the internal state KV$. Then, the effective data mask (e.g.) ) can be generated to indicate the current valid part of the data structure of the internal state KV$, as specified in Equation 1.

[0070] Subsequent hints can be provided to ARLM 604. The internal state KV$ can be maintained on device 608. Instead of providing the internal state KV$ (whose size increases with each call), the transmission of the internal state KV$ can be suppressed (indicated in strikethrough text 610). In some respects, compilation flags can be set during model compilation to associate the suppressed model input with an earlier output. ARLM 604 can be configured to conditionally compute only the valid portion of the largest-sized data structure using a valid data mask. That is, the internal state can be updated on device 608 with each subsequent call. Furthermore, subsequent output symbols generated by ARLM 604 can be provided to the loop orchestrator module 602. Additional calls can then be made to generate additional output symbols without transmitting the internal state KV$.

[0071] Another challenge posed by LLM deployment involves whether cyclic orchestration (e.g., autoregressive calls in the LLM) is performed by the host 606 or by the device 608 (e.g., an inference accelerator device) itself. Performing cyclic orchestration on the host 606 offers flexibility, where various beam search and random sampling techniques can be easily combined. That is, although beam search and random sampling techniques may involve scalar computations, which may not be ideal candidates for execution in an accelerator device, performing cyclic orchestration on the host 606 allows such techniques to be employed to determine the next one or more input symbols based on the output logit from the LLM.

[0072] However, the computed internal state KV$ (of this variable-sized structure) must be available for the next loop iteration to avoid the costly recompiling of the internal state KV$. This can be achieved by transmitting the variable-sized internal state KV$ back to device 608 (e.g., the inference accelerator) via host 606. Doing so can make the device-host link a bottleneck, as the larger KV$ must be transmitted back and forth via the link, potentially leaving the device idle during transmission.

[0073] Therefore, to avoid transferring variable-sized internal state KV$ between host 606 and device 608, aspects of this disclosure provide partial tensor transfer. Partial tensor transfer allows direct memory access (DMA) / data transfers associated with some inputs and outputs to be optionally suppressed during each call. For example, during the first subsequent symbol generation (in the decoding phase), a fixed-size KV$ can be transferred to device 608. Then, during subsequent calls, the associated DMA can be suppressed. Similarly, in some aspects, the output of KV$ from device 608 to host 606 can be suppressed on all calls. In one example, device 608 can pass a buffer and the size of that buffer (e.g., size zero) to host 606, and only the amount of data indicated by that size can be transferred. On the other hand, if circular orchestration is performed on device 608, the described techniques can still be applied to address the problems of variable-sized data structures and dynamism.

[0074] Figure 7 This is a flowchart illustrating a processor implementation of a method 700 for adapting autoregressive inference of a large language model (LLM) to static compilation, according to various aspects of this disclosure. For example, the processor implementation of method 700 can be executed by one or more processors such as a CPU (e.g., 102, 422), a GPU (e.g., 104, 426), and / or other processing units (e.g., DSP424, NPU 428). Furthermore, a compiler can be used to implement the processor implementation of method 700.

[0075] like Figure 7 As shown, at box 702, the processor defines a maximum-size static data structure and a variable-size data mask. The variable-size data mask indicates the valid portion of the maximum-size static data structure. As described, for example, refer to... Figure 6 The maximum context length (CL) can be used to define the static data structure of the internal state KV$. A valid data mask (e.g., validMask) can then be generated to indicate the currently valid portion of the data structure of the internal state KV$. In some aspects, for example, a variable data mask can be generated based on the symbols generated by the autoregressive LLM.

[0076] At box 704, the processor determines the valid dataset by applying a variable data mask to a static data structure of maximum size. The valid dataset has a variable size. For example, as referenced... Figure 6As described, by applying a valid data mask to the maximum-sized data structure, the current valid portion of the internal state KV$ data structure is as specified in Equation 1. In some aspects, the valid dataset can be generated by the LLM. For example, the valid dataset may include the internal state KV$ associated with the LLM.

[0077] At box 706, the processor uses only the valid dataset to perform computations. As described, for example, refer to Figure 6 ARLM 604 can be configured to conditionally compute only the effective portion of the largest data structure using an effective data mask. For example, computation using only the effective dataset can be used to generate inferences related to cues from a large language model. In various ways, code (e.g., executable code) for performing computations using the effective dataset can be generated prior to runtime. For example, the code can be generated during model compilation time. In some aspects, the code can be specified to perform minimal computations using the effective dataset. That is, the code can be defined to reduce and, in some cases, avoid overcomputation (e.g., performing additional computations to produce the same or similar functionally correct results) using described conditional computation techniques.

[0078] Specific implementation examples are included in the following numbered clauses.

[0079] 1. An apparatus, the apparatus comprising:

[0080] At least one memory; and

[0081] At least one processor, coupled to the at least one memory, is configured to:

[0082] Define a maximum-size static data structure and a variable data mask, wherein the variable data mask indicates the valid portion of the maximum-size static data structure;

[0083] The valid dataset is determined by applying the variable data mask to the maximum-size static data structure; and

[0084] The computation is performed using only the valid dataset.

[0085] 2. The apparatus according to Clause 1, wherein the effective dataset has a variable size.

[0086] 3. The apparatus according to clause 1 or 2, wherein the effective dataset is generated by a large language model.

[0087] 4. The apparatus according to any one of clauses 1 to 3, wherein the valid dataset includes internal states associated with the large language model.

[0088] 5. The apparatus according to any one of clauses 1 to 4, wherein the internal state is preserved on the inference accelerator device.

[0089] 6. The apparatus according to any one of clauses 1 to 5, wherein the at least one processor is further configured to: suppress transmission of at least one of the inputs or outputs during subsequent calls to the large language model.

[0090] 7. The apparatus according to any one of clauses 1 to 6, wherein the compiler associates the internal state with the suppressed input.

[0091] 8. The apparatus according to any one of clauses 1 to 7, wherein the large language model is implemented on an inference accelerator.

[0092] 9. The apparatus according to any one of clauses 1 to 8, wherein the at least one processor is further configured to generate code prior to runtime to perform minimal computation using the effective dataset.

[0093] 10. A processor-implemented method executed by at least one processor, the processor-implemented method comprising:

[0094] Define a maximum-size static data structure and a variable data mask, wherein the variable data mask indicates the valid portion of the maximum-size static data structure;

[0095] The valid dataset is determined by applying the variable data mask to the maximum-size static data structure; and

[0096] The computation is performed using only the valid dataset.

[0097] 11. The processor-implemented method according to Clause 10, wherein the effective dataset has a variable size.

[0098] 12. The processor-implemented method according to Clause 10 or 11, wherein the effective dataset is generated by a large language model.

[0099] 13. The processor-implemented method according to any one of clauses 10 to 12, wherein the effective dataset includes internal states associated with the large language model.

[0100] 14. The processor-implemented method according to any one of clauses 10 to 13, wherein the internal state is preserved on the inference accelerator device.

[0101] 15. The processor-implemented method according to any one of Clauses 10 to 14, the processor-implemented method further comprising: suppressing the transmission of at least one of the inputs or outputs during subsequent calls to the large language model.

[0102] 16. A processor-implemented method according to any one of clauses 10 to 15, wherein the compiler associates the internal state with the suppressed input.

[0103] 17. The processor-implemented method according to any one of Clauses 10 to 16, wherein the large language model is implemented on an inference accelerator.

[0104] 18. The processor-implemented method according to any one of clauses 10 to 17, the processor-implemented method further comprising generating code prior to runtime to perform minimal computation using the effective dataset.

[0105] 19. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising:

[0106] Program code for defining a maximum-size static data structure and a variable data mask, wherein the variable data mask indicates the valid portion of the maximum-size static data structure;

[0107] Program code for determining the valid dataset by applying the variable data mask to the maximum-sized static data structure; and

[0108] Program code for performing computations using only the valid dataset.

[0109] 20. An apparatus comprising:

[0110] A component for defining a maximum-size static data structure and a variable data mask, wherein the variable data mask indicates the valid portion of the maximum-size static data structure;

[0111] Components for determining the valid dataset by applying the variable data mask to the maximum-sized static data structure; and

[0112] A component for performing computations using only the valid dataset.

[0113] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the cases where operations are illustrated in the accompanying drawings, these operations may have corresponding paired components with similar numbering plus functional components.

[0114] As used, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculation, computation, processing, derivation, research, searching (e.g., looking in a table, database, or other data structure), assertion, etc. Additionally, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Furthermore, "determine" can include parsing, selecting, choosing, building, etc.

[0115] As used, the phrase "at least one of the items in the list" refers to any combination of these items, including a single member. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0116] The various exemplary logic blocks, modules, and circuits described in this disclosure can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic component, discrete hardware component, or any combination thereof designed to perform the described functions. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0117] The steps or algorithms of the methods described in this disclosure may be directly embodied in hardware, a software module executed by a processor, or a combination of both. The software module may reside in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction or multiple instructions and may be distributed across several different code segments, across different programs, and across multiple storage media. The storage medium may be coupled to the processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor.

[0118] The disclosed method includes one or more steps or actions for implementing the described method. The steps and / or actions of the method may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims.

[0119] The described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system within the device. This processing system may utilize a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnect buses and bridges. The bus can link various circuits together, including processors, machine-readable media, and bus interfaces. The bus interface can be used to connect network adapters, etc., to the processing system via the bus. The network adapter can be used to implement signal processing functions. In some respects, user interfaces (e.g., keypads, displays, mice, joysticks, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0120] A processor may be responsible for managing the bus and general-purpose processing, including executing software stored on a machine-readable medium. A processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software should be interpreted broadly as instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. By way of example, a machine-readable medium may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, disks, optical disks, hard disks, or any other suitable storage medium, or any combination thereof. A machine-readable medium may be embodied as a computer program product. A computer program product may include packaging material.

[0121] In a hardware implementation, machine-readable media can be part of a processing system separate from the processor. However, as those skilled in the art will readily understand, machine-readable media, or any portion thereof, can be external to the processing system. By way of example, machine-readable media may include transmit lines, carrier waves modulated by data, and / or computer components separate from the device, all accessible to the processor via a bus interface. Alternatively or additionally, machine-readable media, or any portion thereof, may be integrated into the processor, such as in the case of a cache and / or a general-purpose register file. Although the various components discussed may be described as having a specific location, such as local components, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

[0122] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of machine-readable medium, all of which are linked together with other supporting circuitry via an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron and nervous system models. As another alternative, the processing system may be implemented using an application-specific integrated circuit (ASIC) having a processor, bus interface, user interface, supporting circuitry, and at least a portion of machine-readable medium integrated on a single chip, or using one or more field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic components, discrete hardware components, or any other suitable circuitry, or any combination of circuitry capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality of the processing system depends on the specific application and the overall design constraints imposed on the system as a whole.

[0123] Machine-readable media may include multiple software modules. These software modules include instructions that, when executed by a processor, enable the processing system to perform various functions. Software modules may include send and receive modules. Each software module may reside in a single storage device or be distributed across multiple storage devices. For example, when a triggering event occurs, a software module may be loaded from a hard disk drive into RAM. During the execution of a software module, the processor may load some of the instructions into a cache to improve access speed. One or more cache lines may then be loaded into a general-purpose register file for processor execution. When the functionality of a software module is referred to below, it will be understood that such functionality is implemented by the processor when executing the instructions from that software module. Furthermore, it should be understood that aspects of this disclosure result in improvements to the functionality of a processor, computer, machine, or other system implementing such aspects.

[0124] If implemented in software, the functions may be stored as one or more instructions or codes on or transmitted through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. A storage medium can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Additionally, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then such coaxial cable, optical fiber, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. The disks and optical discs used include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. ® Optical discs, where magnetic disks typically reproduce data magnetically, and optical discs reproduce data optically using lasers. Therefore, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Furthermore, in other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0125] Therefore, some aspects may include a computer program product for performing the presented operations. For example, such a computer program product may include a computer-readable medium on which instructions are stored (and / or encoded) that can be executed by one or more processors to perform the described operations. In some aspects, the computer program product may include packaging material.

[0126] Furthermore, it should be understood that modules and / or other suitable components for performing the described methods and techniques may be downloaded and / or otherwise obtained by the user terminal and / or base station where applicable. For example, such devices can be coupled to a server to facilitate the delivery of components for performing the described methods. Alternatively, the various methods described can be provided via storage components (e.g., RAM, ROM, physical storage media such as CDs or floppy disks) so that the user terminal and / or base station can obtain the various methods once the storage component is coupled to or provided to the device. In addition, any other suitable techniques suitable for providing the described methods and techniques to the device may be utilized.

[0127] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An apparatus, the apparatus comprising: At least one memory; and At least one processor, coupled to the at least one memory, is configured to: Define a maximum-size static data structure and a variable data mask, wherein the variable data mask indicates the valid portion of the maximum-size static data structure; The valid dataset is determined by applying the variable data mask to the maximum-sized static data structure; as well as The computation is performed using only the valid dataset.

2. The apparatus of claim 1, wherein the effective dataset has a variable size.

3. The apparatus of claim 1, wherein the effective dataset is generated by a large language model.

4. The apparatus of claim 3, wherein the effective dataset includes internal states associated with the large language model.

5. The apparatus of claim 4, wherein the internal state is preserved on the inference accelerator device.

6. The apparatus of claim 5, wherein the at least one processor is further configured to: suppress transmission of at least one of the inputs or outputs during subsequent calls to the large language model.

7. The apparatus of claim 6, wherein the compiler associates the internal state with the suppressed input.

8. The apparatus of claim 3, wherein the large language model is implemented on an inference accelerator.

9. The apparatus of claim 1, wherein the at least one processor is further configured to generate code prior to runtime to perform minimal computation using the effective dataset.

10. A processor-implemented method executed by at least one processor, the processor-implemented method comprising: Define a maximum-size static data structure and a variable data mask, wherein the variable data mask indicates the valid portion of the maximum-size static data structure; The valid dataset is determined by applying the variable data mask to the maximum-sized static data structure; as well as The computation is performed using only the valid dataset.

11. The processor-implemented method of claim 10, wherein the effective dataset has a variable size.

12. The processor-implemented method of claim 10, wherein the effective dataset is generated by a large language model.

13. The processor-implemented method of claim 12, wherein the effective dataset includes internal states associated with the large language model.

14. The processor-implemented method of claim 13, wherein the internal state is preserved on the inference accelerator device.

15. The processor-implemented method according to claim 14, further comprising: During subsequent calls to the large language model, transmission of at least one of the inputs or outputs is suppressed.

16. The processor implementation of claim 15, wherein the compiler associates the internal state with the suppressed input.

17. The processor-implemented method of claim 12, wherein the large language model is implemented on an inference accelerator.

18. The processor-implemented method of claim 10, further comprising generating code prior to runtime to perform minimal computation using the effective dataset.

19. An apparatus comprising: A component for defining a maximum-size static data structure and a variable data mask, wherein the variable data mask indicates the valid portion of the maximum-size static data structure; A component used to determine the valid dataset by applying the variable data mask to the maximum-sized static data structure; and A component for performing computations using only the valid dataset.

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