Multi-element multi-layer DLC coating as well as preparation method and application thereof

Abstract

The invention discloses a multi-element and multi-layer DLC coating and a preparation method and application thereof, and belongs to the technical field of coatings, the multi-element and multi-layer DLC coating sequentially comprises a CrC-1 layer, a DLC-1 layer, a DLC-2 layer, a CrC-2 layer and a DLC-3 layer from a base body to the surface, the thickness of the multi-element and multi-layer DLC coating is 2.4-10 microns, and the affinity of CrC with the base body and the DLC coating is high, so that the CrC layer is selected as a base coat, and the DLC coating has the advantages that the CrC layer is used as the base coat; and the interface bonding force between the DLC layer and the substrate is improved. In addition, the CrC-2 layer is designed to be a middle layer of the DLC-2 layer and the DLC-3 layer, so that the interlayer interface stress of the DLC is reduced, and the interlayer binding force of the DLC is improved. When the DLC-1 layer and the DLC-2 layer are prepared, incremental bias voltage is adopted, the internal stress of the coating is reduced, the binding force of the multi-element and multi-layer DLC coating is improved, the binding force of the prepared multi-element and multi-layer DLC coating is high, and application under the heavy load abrasion condition is ensured.

Description

Technical Field

[0001] This invention belongs to the field of coating technology, and particularly relates to a multi-element multilayer DLC coating, its preparation method and application. Background Technology

[0002] In industrial applications, diamond-like carbon (DLC) coatings suffer from high internal stress, poor film-substrate adhesion, and a thickness rarely exceeding 1.0 μm, resulting in poor wear resistance and thus a narrow range of industrial applications. To improve adhesion and wear resistance, an intermediate layer is typically constructed between the DLC layer and the substrate to adjust interfacial stress and hardness. Common intermediate layers include: metal layers such as Cr and Ti; nitride layers such as TiN, CrN, and AlCrN; and carbide layers such as TiC and CrC. The thickness of this intermediate-DLC bilayer coating is usually less than 5.0 μm. Further increasing its thickness leads to a sharp decrease in coating adhesion, making it unsuitable for heavy-duty friction and wear conditions.

[0003] Patent CN116837333A discloses a Cr-DLC / Si-DLC multi-element doped diamond-like carbon coating. However, this coating uses Cr as the base layer, and the significant differences in thermal properties (coefficient of thermal expansion, hardness, elastic modulus, etc.) between the metal layer and the DLC coating easily lead to interfacial stress concentration. This interfacial stress concentration is generally considered to cause fatal damage to the coating's adhesion, making the coating prone to peeling. Furthermore, doping DLC ​​with Si or Cr elements can reduce the internal stress of the DLC coating, enabling the preparation of thick DLC coatings. Nevertheless, doping in DLC coatings induces the transformation of SP3 bonds (diamond) to SP2 bonds (graphite) in the coating, resulting in a significant decrease in coating hardness. Therefore, the preparation of thick DLC coatings (thickness greater than 5.0 μm) with high adhesion remains a hot research topic and a challenge in the industry. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a multi-element, multi-layer DLC coating, its preparation method, and its applications. Through multi-layer structure design and interface layer composition optimization, this invention deposits a multi-element, multi-layer DLC coating of a certain thickness on a cemented carbide substrate, further increasing the thickness of the DLC coating and broadening its application range under heavy-duty conditions.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] This invention provides a multi-element multilayer DLC coating, wherein the multi-element multilayer DLC coating consists of, from the substrate to the surface, layers of: CrC-1, DLC-1, DLC-2, CrC-2, and DLC-3.

[0007] The thickness of the multi-element, multi-layer DLC coating is 2.4~10μm;

[0008] The phase structure of both the CrC-1 and CrC-2 layers is chromium carbide phase.

[0009] CrC has a high affinity for both the substrate and the DLC coating; therefore, this invention selects a CrC layer as the underlayer to improve the interfacial adhesion between the DLC layer and the substrate. Furthermore, a CrC-2 layer is designed as an intermediate layer between the DLC-2 and DLC-3 layers to reduce interfacial stress between the DLC layers and improve interlayer adhesion.

[0010] Furthermore, the thickness of the CrC-1 layer is 0.2~1.0 μm;

[0011] The thickness of the DLC-1 layer is 1.0~3.0μm, the thickness of the DLC-2 layer is 0.5~2.5μm, and the thickness of the DLC-1 layer is greater than the thickness of the DLC-2 layer;

[0012] The thickness of the CrC-2 layer is 0.5~2.0 μm;

[0013] The thickness of the DLC-3 layer is 0.2~1.5μm.

[0014] The present invention also provides a method for preparing the above-mentioned multi-element multilayer DLC coating, comprising the following steps:

[0015] The substrate is subjected to ultrasonic degreasing treatment;

[0016] The substrate after ultrasonic degreasing treatment is then subjected to argon ion etching cleaning.

[0017] After argon ion etching and cleaning, a multi-element, multi-layer DLC coating is deposited, in which:

[0018] The deposition process parameters for the CrC-1 layer are as follows: chromium target current is 60~200A, bias voltage is -40~-100V, deposition time is 10~50min, and acetylene flow rate is 20~50sccm.

[0019] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -60~-160V, and deposition time is 30~90min.

[0020] The deposition process parameters for DLC-2 layer are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -80~-200V, and deposition time is 15~75min.

[0021] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 60~200A, bias voltage is -40~-100V, deposition time is 25~100min, and acetylene flow rate is 20~50sccm.

[0022] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -60~-120V, and deposition time is 6~45min.

[0023] Increasing bias voltage was used during the fabrication of DLC-1 and DLC-2 layers, which reduced the internal stress of the coating and improved the adhesion of the multi-element, multi-layer DLC coating. This structural design resulted in a high adhesion of the fabricated multi-element, multi-layer DLC coating, ensuring its application under heavy-load and wear conditions.

[0024] Furthermore, the substrate is a cemented carbide substrate.

[0025] For example, the cemented carbide matrix is ​​WC-6Co.

[0026] For example, during the argon ion etching cleaning, the temperature is 200~550℃ and the vacuum degree is less than 5×10⁻⁶. -3 The cleaning bias voltages were -200V, -400V, -600V, -800V, -500V and -200V respectively, and the cleaning times were 5min, 6min, 10min, 5min, 5min and 3min respectively.

[0027] For example, the deposition process parameters for the CrC-1 layer are: chromium target current of 100A, bias voltage of -60V, deposition time of 30min, and acetylene flow rate of 30sccm.

[0028] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -60V, and deposition time is 60min.

[0029] The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -100V, and deposition time is 50min.

[0030] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 100A, bias voltage is -40V, deposition time is 60min, and acetylene flow rate is 30sccm.

[0031] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -80V, and deposition time is 30min.

[0032] For example, the deposition process parameters for the CrC-1 layer are: chromium target current of 60A, bias voltage of -40V, deposition time of 10min, and acetylene flow rate of 20sccm.

[0033] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -60V, and deposition time is 30min.

[0034] The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -80V, and deposition time is 15min.

[0035] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 60A, bias voltage is -40V, deposition time is 25min, and acetylene flow rate is 20sccm.

[0036] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -60V, and deposition time is 6min.

[0037] For example, the deposition process parameters for the CrC-1 layer are: chromium target current of 200A, bias voltage of -100V, deposition time of 50min, and acetylene flow rate of 50sccm.

[0038] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -160V, and deposition time is 90min.

[0039] The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -200V, and deposition time is 75min.

[0040] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 200A, bias voltage is -100V, deposition time is 100min, and acetylene flow rate is 50sccm.

[0041] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -120V, and deposition time is 45min.

[0042] This invention also provides the application of the above-mentioned multi-element multilayer DLC coating in the preparation of non-ferrous metal machining tools.

[0043] This invention also provides the application of the above-mentioned multi-element multilayer DLC coating in the preparation of solid lubricated friction-reducing components.

[0044] Compared with the prior art, the present invention has the following advantages and technical effects:

[0045] CrC exhibits high affinity with both the substrate and the DLC coating; therefore, this invention selects a CrC layer as the underlayer to improve the interfacial adhesion between the DLC layer and the substrate. Furthermore, a CrC-2 layer is designed as an intermediate layer between DLC-2 and DLC-3 layers to reduce interfacial stress between DLC layers and enhance interlayer adhesion. Increasing bias voltage is used during the fabrication of DLC-1 and DLC-2 layers to reduce internal stress within the coating and improve the adhesion of the multi-element, multi-layer DLC coating. This structural design results in a multi-element, multi-layer DLC coating with high adhesion, ensuring its application under heavy-load wear conditions. Attached Figure Description

[0046] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0047] Figure 1 The image shows the cross-sectional microstructure of the multi-element multilayer DLC coating prepared in Example 1. Detailed Implementation

[0048] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as a limitation of the present invention, but rather as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0049] It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the invention. Furthermore, with respect to numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Every smaller range between any stated value or intermediate value within a stated range, and any other stated value or intermediate value within said range, is also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0050] Unless otherwise stated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods and materials have been described herein, any methods and materials similar or equivalent to those described herein may be used in the implementation or testing of this invention. All references to this specification are incorporated by way of citation to disclose and describe methods and / or materials associated with those references. In the event of any conflict with any incorporated reference, the content of this specification shall prevail.

[0051] Various modifications and variations can be made to the specific embodiments described in this specification without departing from the scope or spirit of the invention, as will be apparent to those skilled in the art. Other embodiments derived from this specification will also be readily apparent to those skilled in the art. This specification and embodiments are merely exemplary.

[0052] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0053] An embodiment of the present invention provides a multi-element multilayer DLC coating, wherein the multi-element multilayer DLC coating consists of, from the substrate to the surface, layers CrC-1, DLC-1, DLC-2, CrC-2, and DLC-3.

[0054] The thickness of the multi-element, multi-layer DLC coating is 2.4~10μm;

[0055] Both the CrC-1 and CrC-2 layers have chromium carbide phase structures.

[0056] In a preferred embodiment of the present invention, the thickness of the CrC-1 layer is 0.2~1.0 μm;

[0057] The thickness of the DLC-1 layer is 1.0~3.0μm, and the thickness of the DLC-2 layer is 0.5~2.5μm, with the thickness of the DLC-1 layer being greater than that of the DLC-2 layer;

[0058] The thickness of the CrC-2 layer is 0.5~2.0 μm;

[0059] The thickness of the DLC-3 layer is 0.2~1.5μm.

[0060] An embodiment of the present invention also provides a method for preparing the above-mentioned multi-element multilayer DLC coating, comprising the following steps:

[0061] The substrate is subjected to ultrasonic degreasing treatment;

[0062] The substrate after ultrasonic degreasing is then cleaned by argon ion etching.

[0063] After argon ion etching and cleaning, a multi-element, multi-layer DLC coating is deposited, in which:

[0064] The deposition process parameters for the CrC-1 layer are as follows: chromium target current is 60~200A, bias voltage is -40~-100V, deposition time is 10~50min, and acetylene flow rate is 20~50sccm.

[0065] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -60~-160V, and deposition time is 30~90min.

[0066] The deposition process parameters for DLC-2 layer are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -80~-200V, and deposition time is 15~75min.

[0067] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 60~200A, bias voltage is -40~-100V, deposition time is 25~100min, and acetylene flow rate is 20~50sccm.

[0068] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -60~-120V, and deposition time is 6~45min.

[0069] In a preferred embodiment of the present invention, the step of ultrasonic degreasing treatment of the cemented carbide substrate is as follows: heating the alkaline liquid to 50~80°C, then immersing the cemented carbide substrate in the alkaline liquid, starting the ultrasonic device, and performing ultrasonic cleaning.

[0070] For example, the alkaline liquid is a sodium hydroxide solution with a concentration of 5-6 wt%.

[0071] In a preferred embodiment of the present invention, the substrate is a cemented carbide substrate.

[0072] For example, the cemented carbide matrix is ​​WC-6Co.

[0073] For example, during argon ion etching cleaning, the temperature is 200~550℃ and the vacuum degree is less than 5×10⁻⁶. -3 The cleaning bias voltages were -200V, -400V, -600V, -800V, -500V and -200V respectively, and the cleaning times were 5min, 6min, 10min, 5min, 5min and 3min respectively.

[0074] For example, the deposition process parameters for the CrC-1 layer are: chromium target current of 100A, bias voltage of -60V, deposition time of 30min, and acetylene flow rate of 30sccm.

[0075] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -60V, and deposition time is 60min.

[0076] The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -100V, and deposition time is 50min.

[0077] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 100A, bias voltage is -40V, deposition time is 60min, and acetylene flow rate is 30sccm.

[0078] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -80V, and deposition time is 30min.

[0079] For example, the deposition process parameters for the CrC-1 layer are: chromium target current of 60A, bias voltage of -40V, deposition time of 10min, and acetylene flow rate of 20sccm.

[0080] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -60V, and deposition time is 30min.

[0081] The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -80V, and deposition time is 15min.

[0082] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 60A, bias voltage is -40V, deposition time is 25min, and acetylene flow rate is 20sccm.

[0083] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -60V, and deposition time is 6min.

[0084] For example, the deposition process parameters for the CrC-1 layer are: chromium target current of 200A, bias voltage of -100V, deposition time of 50min, and acetylene flow rate of 50sccm.

[0085] The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -160V, and deposition time is 90min.

[0086] The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -200V, and deposition time is 75min.

[0087] The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 200A, bias voltage is -100V, deposition time is 100min, and acetylene flow rate is 50sccm.

[0088] The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -120V, and deposition time is 45min.

[0089] Embodiments of the present invention also provide the application of the above-mentioned multi-element multilayer DLC coating in the preparation of non-ferrous metal machining tools.

[0090] Embodiments of the present invention also provide the application of the above-mentioned multi-element multilayer DLC coating in the preparation of solid lubricated friction-reducing components.

[0091] The core of this invention lies in its ingenious multi-layer structure design and optimized deposition process, which systematically solves the key technical bottleneck of traditional DLC coatings, where the internal stress increases sharply during thicknessing, leading to insufficient adhesion and easy peeling from the substrate. The mechanism of its high adhesion and resistance to heavy-duty wear is as follows:

[0092] 1. Interface integration optimization mechanism: The "bridge" role of the CrC transition layer

[0093] DLC coatings (especially diamond-like carbon phases with high sp3 bond content) differ significantly from cemented carbide substrates in chemical bond type, crystal structure, and coefficient of thermal expansion. Direct deposition of these coatings results in weak interfacial adhesion, becoming the weakest link in the entire coating system. The solution and mechanism of this invention are as follows:

[0094] (1) Strong interfacial bonding of the CrC-1 layer (bottom layer):

[0095] Bonding with the substrate: CrC belongs to the ceramic phase, and its thermal properties are between those of cemented carbide and DLC coating. It can regulate the distribution of interfacial stress and hardness and improve interfacial bonding.

[0096] (2) Stress buffering and interlaminar pinning of the CrC-2 layer (intermediate layer):

[0097] Stress segmentation and release: After the relatively thick DLC-1 and DLC-2 layers, a metal carbide (CrC-2) layer is inserted to effectively "segment" the continuously deposited DLC layers. The DLC layers have high internal stress, and continuous deposition will cause stress accumulation. As a metal-ceramic layer with good plasticity, the CrC-2 layer can absorb and release some of the stress transmitted from the DLC layers on both sides, preventing longitudinal crack penetration.

[0098] Suppressing columnar crystal growth: In physical vapor deposition, thick coatings tend to form columnar crystal structures, and the boundaries between these structures are weak bonding zones. Inserting a CrC-2 layer can interrupt the continuous growth of DLC columnar crystals, re-nucleate them, refine the coating microstructure, and improve the coating's density and lateral bonding strength.

[0099] Interlayer bonding reinforcement: Similar to the function of the CrC-1 layer, the CrC-2 layer also forms a strong interface bond with the DLC-2 and DLC-3 layers above and below, avoiding interlayer delamination that may occur between DLC layers due to simple physical stacking.

[0100] 2. Internal stress regulation mechanism: gradient bias and multilayer structure design

[0101] The internal stress (especially compressive stress) of DLC coatings accumulates linearly with increasing thickness. When the stress exceeds the bonding strength between the coating and the substrate, the coating will peel, blister, and detach. This is a key limitation on the thickness and application load of traditional DLC coatings. The solution and mechanism of this invention are as follows:

[0102] (1) Gradient bias design in the process (DLC-1 → DLC-2):

[0103] When depositing DLC ​​layers, the bias voltage is a key parameter for controlling the ion bombardment energy, which directly affects the sp3 / sp2 bond ratio, density, and internal stress of the coating.

[0104] This invention employs an incremental bias strategy: the DLC-1 layer is deposited at a relatively low bias voltage (-60 ~ -160V), forming a base layer with good adhesion and relatively low internal stress. Subsequently, the DLC-2 layer is deposited at a higher bias voltage (-80 ~ -200V). The higher ion energy helps to form a DLC layer with a higher sp3 bond content, greater density, and greater hardness.

[0105] This gradual increase in energy input creates a gradient distribution of internal stress, rather than abrupt changes in stress. Compared to depositing directly from a high bias voltage, this method avoids generating enormous internal stress at the initial interface, where bonding is most critical, thus ensuring that the overall stress level remains within a controllable range while achieving high hardness.

[0106] (2) Multi-layer stress dispersion design in structure:

[0107] The coating, with a total thickness of 2.4–10 μm, is designed as a multi-layer structure consisting of “CrC-1 layer / DLC-1 layer / DLC-2 layer / CrC-2 layer / DLC-3 layer”. The interfaces between each layer (e.g., DLC-1 / DLC-2, DLC-2 / CrC-2) serve as stress reflection surfaces and termination points. When the coating is subjected to external loads or internal stresses, crack propagation at the interfaces is deflected, branched, or absorbed, consuming a significant amount of energy. This “multi-layer sandwich” structure disperses the overall high stress across multiple interfaces and layers, ensuring that the stress experienced by any single interface or layer is far below its critical failure value, thus allowing the coating to achieve a greater total thickness without failure.

[0108] 3. Synergistic effect and performance under heavy wear

[0109] Under heavy-load wear conditions (such as high contact stress, impact, and fatigue), the coating needs to simultaneously possess high adhesion, high toughness, and excellent wear resistance / friction reduction properties. The design of this invention precisely meets these requirements:

[0110] Resistance to macroscopic peeling: Extremely high coating-substrate adhesion (guaranteed by the CrC-1 layer) and interlayer adhesion (guaranteed by the CrC-2 layer and gradient bias) ensure that the coating will not peel off in an integral or large area under heavy load.

[0111] Fatigue resistance and microcrack propagation: The multilayer structure (especially the CrC-2 layer) can effectively prevent the propagation of internal microcracks. When a microcrack develops in a DLC layer due to fatigue, the crack will be passivated or its direction will be changed as it propagates to the CrC layer, preventing it from penetrating the entire coating system, thereby significantly improving the coating's toughness and fatigue life.

[0112] Functional gradient and load-bearing capacity: The mechanical properties of the entire coating system gradually change from the substrate to the surface. The thicker DLC-1 and DLC-2 layers provide strong support and load-bearing capacity, resisting plastic deformation. The surface DLC-3 layer leverages the inherent low coefficient of friction and high wear resistance of DLC to achieve solid lubrication. The intermediate CrC layer acts as a tough interlayer, coordinating deformation.

[0113] Stress redistribution: When external loads are applied to the coating surface, the stress caused by the load can be more evenly distributed over a wider area through the multi-layer structure, rather than being concentrated at a single point, thus avoiding early failure caused by stress concentration.

[0114] In this invention, "high-purity graphite target" refers to a graphite target with a purity of 99.999% (5N) or higher.

[0115] In the field of mechanical engineering, especially for components involving reciprocating or rotary motion, lifespan is usually measured in running distance. The lifespan of an expansion joint (which may refer to an expansion joint, tightening sleeve, or similar mechanical component) is measured in meters (m), representing the total running distance that the component can withstand from the start of use until failure.

[0116] All raw materials used in the embodiments of the present invention were obtained through commercial purchase.

[0117] It should be noted that any aspects not described in detail in this invention are conventional practices in the field and are not the focus of this invention.

[0118] The technical solution of the present invention will be further illustrated by the following embodiments.

[0119] Example 1

[0120] This embodiment provides a multi-element, multi-layer DLC coating, which consists of the following layers from the substrate to the surface: CrC-1 layer, DLC-1 layer, DLC-2 layer, CrC-2 layer, and DLC-3 layer, wherein the substrate is WC-6Co;

[0121] The preparation steps of the above-mentioned multi-element multilayer DLC coating are as follows:

[0122] S1: The cemented carbide substrate undergoes ultrasonic degreasing treatment. The specific process is as follows: a 5wt% sodium hydroxide solution is heated to 60°C, then the cemented carbide substrate is immersed in the sodium hydroxide solution. The ultrasonic device is then activated for ultrasonic cleaning (ultrasonic power density is 0.5 W / cm³). 2 (The cleaning time is 5 minutes).

[0123] S2: Place the cleaned cemented carbide substrate into an arc ion plating furnace, heat the furnace to 350°C, and maintain a vacuum level of less than 5 × 10⁻⁶. -3 Pa, then argon gas is introduced for argon ion etching cleaning. The cleaning bias voltages are -200V, -400V, -600V, -800V, -500V and -200V in sequence, and the cleaning times are 5min, 6min, 10min, 5min, 5min and 3min in sequence.

[0124] S3: After argon ion etching and cleaning, a multi-element, multi-layer DLC coating is deposited. The deposition parameters for the CrC-1 layer are: chromium target current 100A, bias voltage -60V, deposition time 30min, acetylene flow rate 30sccm; the deposition parameters for the DLC-1 layer are: high-purity graphite target current 120A, argon flow rate 160sccm, substrate bias voltage -60V, deposition time 60min; the deposition parameters for the DLC-2 layer are: high-purity... The graphite target current was 120A, the argon flow rate was 160sccm, the substrate bias voltage was -100V, and the deposition time was 50min. The deposition process parameters for the CrC-2 layer were: chromium target current 80A, bias voltage -40V, deposition time 60min, and acetylene flow rate 30sccm. The deposition process parameters for the DLC-3 layer were: high-purity graphite target current 120A, argon flow rate 160sccm, substrate bias voltage -80V, and deposition time 30min.

[0125] The cross-sectional microstructure SEM image of the multi-element, multi-layer DLC coating prepared in this embodiment is shown below. Figure 1 As shown, the cross-sectional structure of the coating is consistent with the design structure of this invention patent, exhibiting multi-layer structure characteristics.

[0126] In this embodiment, the phase structure of the CrC-1 layer is chromium carbide phase, the phase structure of the CrC-2 layer is chromium carbide phase, the thickness of the CrC-1 layer is 1.0 μm, the thickness of the DLC-1 layer is 2.0 μm, the thickness of the DLC-2 layer is 1.4 μm, the thickness of the CrC-2 layer is 1.5 μm, the thickness of the DLC-3 layer is 0.5 μm, and the thickness of the multi-element multilayer DLC coating in this embodiment is 6.4 μm.

[0127] Example 2

[0128] This embodiment provides a multi-element, multi-layer DLC coating, which consists of the following layers from the substrate to the surface: CrC-1 layer, DLC-1 layer, DLC-2 layer, CrC-2 layer, and DLC-3 layer, wherein the substrate material is the same as in Embodiment 1;

[0129] Compared with Example 1, the preparation method of the above-mentioned multi-element multilayer DLC coating is the same in processes S1 and S2. The process parameters of S3 are as follows: CrC-1 layer deposition process parameters are: chromium target current of 60A, bias voltage of -40V, deposition time of 10min, and acetylene flow rate of 20sccm; DLC-1 layer deposition process parameters are: high-purity graphite target current of 60A, argon flow rate of 100sccm, substrate bias voltage of -60V, and deposition time of 30min; DLC-2 layer deposition... The process parameters are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -80V, and deposition time is 15min; the CrC-2 layer deposition process parameters are as follows: chromium target current is 60A, bias voltage is -40V, deposition time is 25min, and acetylene flow rate is 20sccm; the DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -60V, and deposition time is 6min.

[0130] In this embodiment, the phase structure of the CrC-1 layer is chromium carbide phase, the phase structure of the CrC-2 layer is chromium carbide phase, the thickness of the CrC-1 layer is 0.3 μm, the thickness of the DLC-1 layer is 1.0 μm, the thickness of the DLC-2 layer is 0.5 μm, the thickness of the CrC-2 layer is 0.6 μm, the thickness of the DLC-3 layer is 0.3 μm, and the thickness of the multi-element multilayer DLC coating in this embodiment is 2.7 μm.

[0131] Example 3

[0132] This embodiment provides a multi-element, multi-layer DLC coating, which consists of the following layers from the substrate to the surface: CrC-1 layer, DLC-1 layer, DLC-2 layer, CrC-2 layer, and DLC-3 layer, wherein the substrate material is the same as in Embodiment 1;

[0133] Compared with Example 1, the preparation method of the above-mentioned multi-element multilayer DLC coating is the same for processes S1 and S2. The process parameters for S3 are as follows: CrC-1 layer deposition process parameters: chromium target current 200A, bias voltage -100V, deposition time 50min, acetylene flow rate 50sccm; DLC-1 layer deposition process parameters: high-purity graphite target current 180A, argon flow rate 200sccm, substrate bias voltage -160V, deposition time 90min; DLC-2 layer deposition process... The parameters are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -200V, and deposition time is 75min; the CrC-2 layer deposition process parameters are as follows: chromium target current is 200A, bias voltage is -100V, deposition time is 100min, and acetylene flow rate is 50sccm; the DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -120V, and deposition time is 45min.

[0134] In this embodiment, the phase structure of the CrC-1 layer is chromium carbide phase, the phase structure of the CrC-2 layer is chromium carbide phase, the thickness of the CrC-1 layer is 1.0 μm, the thickness of the DLC-1 layer is 2.5 μm, the thickness of the DLC-2 layer is 1.8 μm, the thickness of the CrC-2 layer is 2.0 μm, the thickness of the DLC-3 layer is 1.0 μm, and the thickness of the multi-element multilayer DLC coating in this embodiment is 8.3 μm.

[0135] Comparative Example 1 (Traditional DLC process)

[0136] Compared to Example 1, processes S1 and S2 remain unchanged, while the DLC-2, CrC-2, and DLC-3 layers are removed from the S3 process parameters, and other process parameters remain unchanged. That is, a CrC-1 / DLC-1 coating is prepared.

[0137] Comparative Example 2

[0138] Compared to Example 1, processes S1 and S2 remain unchanged, while the CrC-2 and DLC-3 layers are removed from the process parameters of S3, and other process parameters remain unchanged. That is, a CrC-1 / DLC-1 / DLC-2 coating is prepared.

[0139] Comparative Example 3

[0140] Compared to Example 1, processes S1 and S2 remain unchanged, while the CrC-2 layer is removed from the process parameters of S3, and other process parameters remain the same. That is, a CrC-1 / DLC-1 / DLC-2 / DLC-3 coating is prepared.

[0141] Comparative Example 4

[0142] Compared to Example 1, processes S1 and S2 remain unchanged, except for the CrC-1 deposition step in process S3, while other process parameters remain the same. That is, a DLC-1 / DLC-2 / CrC-2 / DLC-3 coating is prepared.

[0143] Comparative Example 5

[0144] Compared to Example 1, processes S1 and S2 remain unchanged, except that the DLC-1 and DLC-2 deposition steps in process S3 are swapped, while other process parameters remain the same. That is, a CrC-1 / DLC-2 / DLC-1 / CrC-2 / DLC-3 coating is prepared.

[0145] Comparative Example 6 (DLC Thickening Based on Traditional Processes)

[0146] Compared to Example 1, processes S1 and S2 remain unchanged, except for the DLC-2 and CrC-2 deposition steps in step S3, while other process parameters remain the same. That is, a CrC-1 / DLC-1 / DLC-3 coating is prepared.

[0147] Comparative Example 7

[0148] Compared with Example 1, only the substrate bias voltage of DLC-1 and DLC-2 layers in process S3 is modulated to -60V, while other process parameters remain unchanged.

[0149] Comparative Example 8 (compared with Patent CN116837333A)

[0150] According to the technical solution of Example 1 in patent CN116837333A, a Cr-DLC(Cr)-DLC(Si) coating was prepared, wherein DLC(Cr) represents Cr doping in DLC and DLC(Si) represents Si doping in DLC.

[0151] Performance testing: The coating hardness and adhesion of Examples 1-3 and Comparative Examples 1-7 were tested using a nanoindenter and a Rockwell hardness tester; the friction coefficient and wear rate of the coating were tested using a friction and wear test; a cemented carbide expansion head was used to expand a 304 stainless steel pipe with a diameter of 6.5 mm and a wall thickness of 1.0 mm. When the shrinkage of the pipe length with a diameter of 1 m was greater than 1 cm, the expansion head was considered to have failed. The length of the expanded pipe was counted as the service life of the coating expansion head.

[0152] The performance test results of the coatings in Examples 1-3 and Comparative Examples 1-8 are shown in Table 1.

[0153] Table 1. Performance test results of coatings in Examples 1-3 and Comparative Examples 1-8

[0154] Analysis of Table 1 shows that the multi-element, multi-layer DLC coating of Example 1 possesses both high adhesion and hardness, low coefficient of friction, and long service life of the expansion head. Compared to the traditional DLC process (Comparative Example 1), the multi-element, multi-layer DLC coating product prepared by this invention exhibits better service performance. Furthermore, compared to the traditional DLC coating (Comparative Example 1), increasing the coating thickness (Comparative Examples 2, 3, and 6) leads to increases in coating adhesion, coefficient of friction, and wear rate, ultimately resulting in a significant decrease in the service life of the expansion head. Additionally, changing the multi-element, multi-layer coating process (Comparative Example 5) reduces coating adhesion, leading to an increase in the coefficient of friction and a significant decrease in the service life of the expansion head. When the bias voltage in both DLC-1 and DLC-2 is modulated to -60V (Comparative Example 7), the coating adhesion decreases significantly, and slight peeling occurs during friction and wear, resulting in an increase in the coefficient of friction and ultimately a decrease in the service performance of the coated product. When Cr is used as the base coat and Si or Cr is doped in the DLC (Comparative Example 8), Example 1 of the present invention has higher hardness and adhesion, and the coating obtained by the method of the present invention has better wear resistance and service performance.

[0155] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-element, multi-layer DLC coating, characterized in that, The multi-element, multi-layer DLC coating consists of the following layers from the substrate to the surface: CrC-1 layer, DLC-1 layer, DLC-2 layer, CrC-2 layer, and DLC-3 layer. The thickness of the multi-element, multi-layer DLC coating is 2.4~10μm; The phase structure of both the CrC-1 and CrC-2 layers is chromium carbide phase.

2. The multi-element, multi-layer DLC coating according to claim 1, characterized in that, The thickness of the CrC-1 layer is 0.2~1.0 μm; The thickness of the DLC-1 layer is 1.0~3.0μm, the thickness of the DLC-2 layer is 0.5~2.5μm, and the thickness of the DLC-1 layer is greater than the thickness of the DLC-2 layer; The thickness of the CrC-2 layer is 0.5~2.0 μm; The thickness of the DLC-3 layer is 0.2~1.5μm.

3. A method for preparing a multi-element, multi-layer DLC coating according to any one of claims 1 to 2, characterized in that, Includes the following steps: The substrate is subjected to ultrasonic degreasing treatment; The substrate after ultrasonic degreasing treatment is then subjected to argon ion etching cleaning. After argon ion etching and cleaning, a multi-element, multi-layer DLC coating is deposited, in which: The deposition process parameters for the CrC-1 layer are as follows: chromium target current is 60~200A, bias voltage is -40~-100V, deposition time is 10~50min, and acetylene flow rate is 20~50sccm. The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -60~-160V, and deposition time is 30~90min. The deposition process parameters for DLC-2 layer are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -80~-200V, and deposition time is 15~75min. The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 60~200A, bias voltage is -40~-100V, deposition time is 25~100min, and acetylene flow rate is 20~50sccm. The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 60~180A, argon flow rate is 100~200sccm, substrate bias voltage is -60~-120V, and deposition time is 6~45min.

4. The method for preparing a multi-element, multi-layer DLC coating according to claim 3, characterized in that, The substrate is a cemented carbide substrate.

5. The method for preparing a multi-element, multi-layer DLC coating according to claim 3, characterized in that, During the argon ion etching cleaning process, the temperature is 200~550℃ and the vacuum degree is less than 5×10⁻⁶. -3 The cleaning bias voltages were -200V, -400V, -600V, -800V, -500V and -200V respectively, and the cleaning times were 5min, 6min, 10min, 5min, 5min and 3min respectively.

6. The method for preparing a multi-element, multi-layer DLC coating according to claim 3, characterized in that, The deposition process parameters for the CrC-1 layer are as follows: chromium target current is 100A, bias voltage is -60V, deposition time is 30min, and acetylene flow rate is 30sccm. The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -60V, and deposition time is 60min. The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -100V, and deposition time is 50min. The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 100A, bias voltage is -40V, deposition time is 60min, and acetylene flow rate is 30sccm. The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 120A, argon flow rate is 160sccm, substrate bias voltage is -80V, and deposition time is 30min.

7. The method for preparing a multi-element, multi-layer DLC coating according to claim 3, characterized in that, The deposition process parameters for the CrC-1 layer are as follows: chromium target current is 60A, bias voltage is -40V, deposition time is 10min, and acetylene flow rate is 20sccm. The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -60V, and deposition time is 30min. The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -80V, and deposition time is 15min. The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 60A, bias voltage is -40V, deposition time is 25min, and acetylene flow rate is 20sccm. The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 60A, argon flow rate is 100sccm, substrate bias voltage is -60V, and deposition time is 6min.

8. The method for preparing a multi-element, multi-layer DLC coating according to claim 3, characterized in that, The deposition process parameters for the CrC-1 layer are as follows: chromium target current is 200A, bias voltage is -100V, deposition time is 50min, and acetylene flow rate is 50sccm. The deposition process parameters for the DLC-1 layer are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -160V, and deposition time is 90min. The deposition process parameters for the DLC-2 layer are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -200V, and deposition time is 75min. The deposition process parameters for the CrC-2 layer are as follows: chromium target current is 200A, bias voltage is -100V, deposition time is 100min, and acetylene flow rate is 50sccm. The DLC-3 layer deposition process parameters are as follows: high-purity graphite target current is 180A, argon flow rate is 200sccm, substrate bias voltage is -120V, and deposition time is 45min.

9. The application of a multi-element multilayer DLC coating as described in any one of claims 1 to 2 in the preparation of non-ferrous metal machining tools.

10. The application of a multi-element, multi-layer DLC coating as described in any one of claims 1 to 2 in the preparation of solid lubricated friction-reducing components.

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