Low dropout linear regulator with high power-supply rejection ratio and no off-chip capacitance

Abstract

The application discloses a high-power-voltage-suppression-ratio non-external-capacitance low-dropout linear voltage stabilizer, which comprises an error amplifier, a power tube, a Miller compensation capacitor, a PSRR compensation capacitor, a first voltage dividing resistor and a second voltage dividing resistor; the positive input end of the error amplifier is connected with one end of the first voltage dividing resistor and one end of the second voltage dividing resistor; the output end of the error amplifier is connected with one end of the Miller compensation capacitor and the gate of the power tube; the source of the power tube is connected with the other end of the first voltage dividing resistor; the error amplifier is further connected with the PSRR compensation capacitor between the error amplifier and the ground; and the error amplifier is at least one of a one-stage amplifier, a sleeve type common-source common-gate amplifier and a common-source common-gate amplifier. The application adds a PSRR compensation capacitor connected with the ground in the error amplifier, which can effectively compensate the influence of the Miller compensation capacitor and the parasitic capacitance of the power tube, so that the PSRR of the LDO at the intermediate frequency in the GBW bandwidth is improved.

Description

Technical Field

[0001] This invention relates to the field of industrial Internet of Things (IIoT) service technology, specifically to a low dropout linear regulator with high power supply voltage rejection ratio and no external capacitor for industrial IoT services. Background Technology

[0002] With the continuous development of integrated circuit technology, more and more circuits are integrated on a single chip to form a System-on-a-Chip (SoC), especially wireless transceiver chips, where analog RF circuits such as LNA, PLL, ADC / DAC, and digital circuits such as digital baseband are all integrated on a single chip.

[0003] To extend standby time, improve integration, and reduce the complexity of peripheral circuits, modern SoCs generally adopt a DC / DC + LDO power supply architecture, that is, an external DC / DC converter and an internal LDO without external capacitors; or both the DC / DC converter and the LDO are integrated into the SoC.

[0004] Since DC / DC converters are clock-driven, they have significant output ripple at their operating clock frequency. Furthermore, devices such as PLLs, ADCs, and LNAs are highly sensitive to power supply parameters, which places high demands on the PSRR (Power Surge Reduction) of on-chip LDOs.

[0005] However, the PSRR of a standard LDO without external capacitors is poor at the intermediate frequency (IF), and the operating clock frequency of a DC / DC converter is essentially at the IF of the LDO. Therefore, to improve the PSRR of a standard LDO without external capacitors at the IF, the GBW (Gross Power W) of the LDO must be increased. This will significantly increase the power consumption of the LDO, leading to a decrease in its efficiency.

[0006] PSRR: Power Supply Rejection Ratio, abbreviated as PSRR, describes the ability of a circuit to suppress any power supply changes that are transmitted to its output signal. It is usually measured in dB and is used to describe the influence of the power supply on the output signal. Summary of the Invention

[0007] The purpose of this invention is to provide a low dropout linear regulator (LDO) with high power supply voltage rejection ratio (PSRR) and no external capacitor for industrial Internet of Things (IIoT) services. By adding a PSRR compensation capacitor to ground in the error amplifier, the influence of Miller compensation capacitor and power transistor parasitic capacitance can be effectively compensated, thereby improving the PSRR of the LDO at the intermediate frequency within the GBW bandwidth.

[0008] To achieve the above object, the present invention provides the following technical solution: A low-dropout linear regulator without an external capacitor with a high power supply voltage rejection ratio, including an error amplifier, a power transistor, a Miller compensation capacitor, a PSRR compensation capacitor, a first voltage-dividing resistor, and a second voltage-dividing resistor. The positive input terminal of the error amplifier is connected to the common terminal of the first voltage-dividing resistor and the second voltage-dividing resistor, and the other end of the second voltage-dividing resistor is grounded. The output terminal of the error amplifier is connected to one end of the Miller compensation capacitor and the gate of the power transistor. The drain of the power transistor is connected to the other end of the first voltage-dividing resistor and the other end of the Miller compensation capacitor. A PSRR compensation capacitor is also connected between the error amplifier and the ground. The error amplifier is at least one of a single-stage amplifier, a cascode amplifier, and a common-source cascode amplifier.

[0009] Further preferably, when the error amplifier is a single-stage amplifier, the single-stage amplifier includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a constant current source. The gate of the first NMOS transistor is the negative input terminal of the error amplifier, and the gate of the second NMOS transistor is the positive input terminal of the error amplifier. The sources of the first NMOS transistor and the second NMOS transistor are both connected to the input terminal of the constant current source. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and is the output terminal of the error amplifier. The sources of the first PMOS transistor, the second PMOS transistor, and the power transistor are connected to the power supply voltage. The gates of the first PMOS transistor and the second PMOS transistor are connected and are both connected to one end of the PSRR compensation capacitor. The other end of the PSRR compensation capacitor and the output terminal of the constant current source are grounded.

[0010] Further preferably, the error amplifier further includes an impedance capacitor and an impedance resistor; the other end of the Miller compensation capacitor, one end of the impedance capacitor, and one end of the impedance resistor are connected. The other end of the impedance capacitor and the other end of the impedance resistor are both grounded.

[0011] Further preferably, the power supply rejection ratio PSRR formula is:

[0012] When the frequency F < P0, ;

[0013] When P0 < F < GBW, ;

[0014] When F > GBW, ;

[0015] Where, gm1 is the transconductance of the first NMOS transistor, rdsn1 and rdsp1 are the output impedances of the first NMOS transistor and the power transistor, respectively; gm3 is the output transconductance of the power transistor; and Ro3 is the output impedance of the power transistor. It is the feedback coefficient. R1 is the resistance of the first voltage divider resistor, R2 is the resistance of the second voltage divider resistor, P0 is the dominant pole of the low dropout linear regulator (LDO), and GBW is the gain-bandwidth product of the LDO. CL is the capacitance value of the impedance capacitor, RL is the resistance value of the impedance resistor; Ct is the sum of the Miller compensation capacitor and the parasitic capacitance of the power transistor.

[0016] More preferably, a zero-point cancellation resistor is connected between the output terminal of the error amplifier and one end of the Miller compensation capacitor.

[0017] More preferably, when the error amplifier is a sleeve-type cascode amplifier, the sleeve-type cascode amplifier includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the third NMOS transistor is the negative input terminal of the sleeve-type cascode amplifier. The gate of the fourth NMOS transistor is the positive input terminal of the sleeve-type cascode amplifier. The drain of the third NMOS transistor is connected to the source of the fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor, the gate of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, the source of the fourth PMOS transistor is connected to the drain of the sixth PMOS transistor, the source of the fifth PMOS transistor is connected to the drain of the seventh PMOS transistor, and the gate of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor. All of these are connected to one end of the PSRR compensation capacitor, and the other end of the PSRR compensation capacitor is grounded.

[0018] More preferably, when the error amplifier is a common-source common-gate amplifier, the common-source common-gate amplifier includes a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor. The gate of the seventh NMOS transistor is the negative input terminal of the common-source common-gate amplifier, the gate of the eighth NMOS transistor is the positive input terminal of the common-source common-gate amplifier, the source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, the drain of the seventh NMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth NMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, the source of the seventh PMOS transistor is connected to the drain of the ninth PMOS transistor, the source of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor, the gate of the ninth PMOS transistor is connected to the gate of the tenth PMOS transistor, and all are connected to one end of the PSRR compensation capacitor, the other end of the PSRR compensation capacitor is grounded.

[0019] More preferably, when the error amplifier is another common-source cascode amplifier, the other common-source cascode amplifier includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor. The gate of the ninth NMOS transistor is the negative input terminal of the common-source cascode amplifier, the gate of the tenth NMOS transistor is the positive input terminal of the common-source cascode amplifier, the source of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor, and the drain of the ninth NMOS transistor is connected to the source of the eleventh NMOS transistor. The drain of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor, the gate of the eleventh NMOS transistor is connected to the gate of the twelfth NMOS transistor, the drain of the eleventh NMOS transistor is connected to the drain of the eleventh PMOS transistor, and the drain of the twelfth NMOS transistor is connected to the drain of the twelfth PMOS transistor. This connection is also the output terminal of the other common-source common-gate amplifier. The gates of the eleventh PMOS transistor and the twelfth PMOS transistor are connected and both are connected to one end of the PSRR compensation capacitor, the other end of which is grounded.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1. The present invention adds a PSRR compensation capacitor C2 to ground in the error amplifier, which can effectively compensate for the influence of Miller compensation capacitor C1 and the parasitic capacitance of power transistor MP, thereby improving the PSRR of LDO at the intermediate frequency within the GBW bandwidth.

[0022] 2. The technical solution of the present invention has a very wide range of applications and can be used with a first-stage amplifier, a sleeve-type common-source cascode amplifier, and a common-source cascode amplifier.

[0023] 3. The modifications in this invention are relatively minor, but they can achieve significant results and breakthrough progress. They solve the technical problem that in order to improve the PSRR of existing ordinary low dropout linear regulators without external capacitors at the intermediate frequency, the GBW of the LDO must be increased, which will greatly increase the power consumption of the LDO and reduce its efficiency.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the present invention;

[0026] Figure 2 This is a comparison diagram showing the effect of the first embodiment of the present invention compared to a conventional low-dropout linear regulator without external capacitors in the prior art;

[0027] Figure 3 This is a schematic diagram of the high power supply voltage rejection ratio, capacitor-free, low dropout linear regulator of the present invention;

[0028] Figure 4 A schematic diagram of the high power supply voltage rejection ratio, capacitor-free, low dropout linear regulator of the present invention, for application in a first-stage amplifier;

[0029] Figure 5 A schematic diagram of the high power supply voltage rejection ratio, capacitor-free, low dropout linear regulator of the present invention, for application in a sleeve-type cascode amplifier;

[0030] Figure 6 A schematic diagram of the high power supply voltage rejection ratio, capacitor-free, low dropout linear regulator of the present invention, for application in a common-source cascode amplifier;

[0031] Figure 7 A schematic diagram of the high power supply voltage rejection ratio, capacitor-free, low dropout linear regulator of the present invention, for application in another common-source cascode amplifier;

[0032] Wherein, EA is the error amplifier; C1 is the Miller compensation capacitor; C2 is the PSRR compensation capacitor; CL is the impedance capacitor; R1 is the first voltage divider resistor; R2 is the second voltage divider resistor; R3 is the zero-point cancellation resistor; RL is the impedance resistor; MP is the power transistor; MN1 is the first NMOS transistor; MN2 is the second NMOS transistor; MN3 is the third NMOS transistor; MN4 is the fourth NMOS transistor; MN5 is the fifth NMOS transistor; MN6 is the sixth NMOS transistor; MN7 is the seventh NMOS transistor; MN8 is the eighth NMOS transistor; MN9 is the ninth NMOS transistor. NMOS transistor; MN10, tenth NMOS transistor; MN11, eleventh NMOS transistor; MN12, twelfth NMOS transistor; MP1, first PMOS transistor; MP2, second PMOS transistor; MP4, fourth PMOS transistor; MP5, fifth PMOS transistor; MP6, sixth PMOS transistor; MP7, seventh PMOS transistor; MP8, eighth PMOS transistor; MP9, ninth PMOS transistor; MP10, tenth PMOS transistor; MP11, eleventh PMOS transistor; MP12, twelfth PMOS transistor; I, constant current source; Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0035] Example 1

[0036] To address the aforementioned problems, this invention provides a technical solution: a low-dropout linear regulator with high power supply voltage rejection ratio and no external capacitor, such as... Figure 1As shown, the amplifier includes an error amplifier EA, a power transistor MP, a Miller compensation capacitor C1, a PSRR compensation capacitor C2, a first voltage divider resistor R1, and a second voltage divider resistor R2. The positive input terminal of the error amplifier EA is connected to the common terminal of the first voltage divider resistor R1 and the second voltage divider resistor R2. The other end of the second voltage divider resistor R2 is grounded. The output terminal of the error amplifier EA is connected to one end of the Miller compensation capacitor C1 and the gate of the power transistor MP. The drain of the power transistor MP is connected to the other end of the first voltage divider resistor R1 and the other end of the Miller compensation capacitor C1. The error amplifier EA is also connected to ground via a PSRR compensation capacitor C2. The error amplifier EA is at least one of the following: a single-stage amplifier, a sleeve-type cascode amplifier, and a cascode amplifier.

[0037] This invention, by introducing a PSRR compensation capacitor C2 to ground (or virtual ground) in the error amplifier EA, can effectively compensate for the effects of the Miller compensation capacitor C1 and the parasitic capacitance of the power transistor MP, thereby improving the power supply rejection ratio (PSRR) of the low dropout linear regulator (LDO) at the intermediate frequency within the GBW bandwidth. Figure 2 As shown in the comparison diagram of the effects of the conventional capacitorless low-dropout linear regulator and the high power supply voltage rejection ratio capacitorless low-dropout linear regulator of the present invention, when the power consumption of the two are exactly the same, it can be seen that after adopting the technical solution of the present invention, the PSRR of the LDO in the mid-frequency band is improved by more than 30dB.

[0038] The PSRR compensation capacitor C2 can be a simple MOM or MIM capacitor, but in order to achieve a better compensation effect, the PSRR compensation capacitor C2 can be divided into two parts: one part is a fixed MOM or MIM capacitor, and the other part is a variable MOS capacitor.

[0039] Example 2

[0040] The difference between this embodiment and Embodiment 1 is that when the error amplifier EA is a single-stage amplifier, such as Figure 3As shown, the first-stage amplifier includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, and a constant current source I. The gate of the first NMOS transistor MN1 is the negative input terminal of the error amplifier EA, and the gate of the second NMOS transistor MN2 is the positive input terminal of the error amplifier EA. The sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to the input terminal of the constant current source I. The drain of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1. The drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, and it is the output terminal of the error amplifier EA. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the power transistor MP are connected to the power supply voltage. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected and are both connected to one end of the PSRR compensation capacitor C2. The other end of the PSRR compensation capacitor C2 and the output terminal of the constant current source I are grounded.

[0041] The error amplifier EA further includes an impedance capacitor CL and an impedance resistor RL; the other end of the Miller compensation capacitor C1 is connected to one end of the impedance capacitor CL and one end of the impedance resistor RL. The other end of the impedance capacitor CL and the other end of the impedance resistor RL are both grounded.

[0042] The power supply rejection ratio PSRR formula is:

[0043] When the frequency F < P0, ; (1);

[0044] When P0 < F < GBW, ,(2);

[0045] When F > GBW, ,(3);

[0046] Among them, gm1 is the transconductance of the first NMOS transistor, , rdsn1 and rdsp1 are the output impedances of the first NMOS transistor and the power transistor respectively, gm3 is the output transconductance of the power transistor, Ro3 is the output impedance of the power transistor, is the feedback coefficient, , R1 is the resistance of the first voltage-dividing resistor, R2 is the resistance of the second voltage-dividing resistor, P0 is the main pole of the low dropout regulator LDO, GBW is the gain-bandwidth product of the low dropout regulator LDO, , CL is the capacitance value of the impedance capacitor, RL is the resistance value of the impedance resistor; Ct is the sum of the Miller compensation capacitor and the parasitic capacitance of the power transistor. It can be seen from formula (2) that when a suitable PSRR compensation capacitor C2 is selected, the PSRR of the LDO can be significantly improved.

[0047] For a typical low-dropout linear regulator without external capacitors, to improve its PSRR at the intermediate frequency, the GBW of the LDO must be increased. This will greatly increase the power consumption of the LDO, resulting in a decrease in the efficiency of the LDO.

[0048] Based on this, the present invention adds a PSRR compensation capacitor C2 to ground in the error amplifier. As can be seen from the above formula, by adding the PSRR compensation capacitor C2, the influence of Miller compensation capacitor C1 and the parasitic capacitance of power transistor MP can be effectively compensated, thereby improving the PSRR of LDO at the intermediate frequency within the GBW bandwidth.

[0049] Where Ct is the sum of Miller compensation capacitor C1 and the parasitic capacitance of power transistor MP.

[0050] Example 3

[0051] The difference between this embodiment and Embodiment 2 is that: Figure 4 As shown, a zero-point cancellation resistor R3 is connected between the output of the error amplifier EA and one end of the Miller compensation capacitor C1. This design can improve the GBW of the LDO in some cases.

[0052] Example 4

[0053] The difference between this embodiment and Embodiment 1 is that when the error amplifier EA is a sleeve-type common-source cascode amplifier, such as Figure 5As shown, the sleeve-type cascode amplifier includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP7. The source of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4. The gate of the third NMOS transistor MN3 is the negative input terminal of the sleeve-type cascode amplifier, and the gate of the fourth NMOS transistor MN4 is the positive input terminal of the sleeve-type cascode amplifier. The drain of the third NMOS transistor MN3 is connected to the source of the fifth NMOS transistor MN5, and the drain of the fourth NMOS transistor MN4 is connected to the sixth NMOS transistor MP7. The source of the OS transistor MN6, the gate of the fifth NMOS transistor MN5 is connected to the gate of the sixth NMOS transistor MN6, the drain of the fifth NMOS transistor MN5 is connected to the drain of the fourth PMOS transistor MP4, the drain of the sixth NMOS transistor MN6 is connected to the drain of the fifth PMOS transistor MP5, the gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5, the source of the fourth PMOS transistor MP4 is connected to the drain of the sixth PMOS transistor MP6, the source of the fifth PMOS transistor MP5 is connected to the drain of the seventh PMOS transistor MP7, and the gate of the sixth PMOS transistor MP6 is connected to the gate of the seventh PMOS transistor MP7. All of these are connected to one end of the PSRR compensation capacitor C2, and the other end of the PSRR compensation capacitor C2 is grounded.

[0054] Example 5

[0055] The difference between this embodiment and Embodiment 1 is that when the error amplifier EA is a common-source cascode amplifier, such as Figure 6 As shown, the common-source cascode amplifier includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a tenth PMOS transistor MP10. The gate of the seventh NMOS transistor MN7 is the negative input terminal of the common-source cascode amplifier, and the gate of the eighth NMOS transistor MN8 is the positive input terminal of the common-source cascode amplifier. The source of the seventh NMOS transistor MN7 is connected to the source of the eighth NMOS transistor MN8, and the drain of the seventh NMOS transistor MN7 is connected to the seventh PMOS transistor MP10. The drain of MP7 is connected to the drain of the eighth NMOS transistor MN8, the gate of the seventh PMOS transistor MP7 is connected to the gate of the eighth PMOS transistor MP8, the source of the seventh PMOS transistor MP7 is connected to the drain of the ninth PMOS transistor MP9, the source of the eighth PMOS transistor MP8 is connected to the drain of the tenth PMOS transistor MP10, the gate of the ninth PMOS transistor MP9 is connected to the gate of the tenth PMOS transistor MP10, and all of them are connected to one end of the PSRR compensation capacitor C2, and the other end of the PSRR compensation capacitor C2 is grounded.

[0056] Example 6

[0057] The difference between this embodiment and Embodiment 1 is that when the error amplifier EA is another common-source cascode amplifier, such as... Figure 7 As shown, another common-source cascode amplifier includes a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, an eleventh PMOS transistor MP11, and a twelfth PMOS transistor MP12. The gate of the ninth NMOS transistor MN9 is the negative input terminal of the common-source cascode amplifier, and the gate of the tenth NMOS transistor MN10 is the positive input terminal of the common-source cascode amplifier. The source of the ninth NMOS transistor MN9 is connected to the source of the tenth NMOS transistor MN10, and the drain of the ninth NMOS transistor MN9 is connected to the source of the eleventh NMOS transistor MN11. The drain of S-channel transistor MN10 is connected to the source of the twelfth NMOS transistor MN12. The gate of the eleventh NMOS transistor MN11 is connected to the gate of the twelfth NMOS transistor MN12. The drain of the eleventh NMOS transistor MN11 is connected to the drain of the eleventh PMOS transistor MP11. The drain of the twelfth NMOS transistor MN12 is connected to the drain of the twelfth PMOS transistor MP12, and is also the output terminal of another common-source common-gate amplifier. The gate of the eleventh PMOS transistor MP11 is connected to the gate of the twelfth PMOS transistor MP12, and both are connected to one end of the PSRR compensation capacitor C2. The other end of the PSRR compensation capacitor C2 is grounded.

[0058] In summary, embodiments 4-6 of the present invention can also effectively compensate for the effects of Miller compensation capacitor C1 and the parasitic capacitance of the power transistor MP by adding PSRR compensation capacitor C2, thereby improving the PSRR of the LDO at the intermediate frequency within the GBW bandwidth.

[0059] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0060] Although embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A low-dropout linear regulator with high power supply voltage rejection ratio and no external capacitor, characterized in that, The system includes an error amplifier (EA), a power transistor (MP), a Miller compensation capacitor (C1), a PSRR compensation capacitor (C2), a first voltage divider resistor (R1), and a second voltage divider resistor (R2). The positive input terminal of the error amplifier (EA) is connected to the common terminal of the first voltage divider resistor (R1) and the second voltage divider resistor (R2). The other end of the second voltage divider resistor (R2) is grounded. The output terminal of the error amplifier (EA) is connected to one end of the Miller compensation capacitor (C1) and the gate of the power transistor (MP). The drain of the power transistor (MP) is connected to the other end of the first voltage divider resistor (R1) and the other end of the Miller compensation capacitor (C1). The error amplifier (EA) is also connected to ground. The error amplifier (EA) is at least one of the following: a single-stage amplifier, a sleeve-type cascode amplifier, and a cascode amplifier. When the error amplifier (EA) is a single-stage amplifier, the single-stage amplifier includes a first NMOS transistor (MN1), a second NMOS transistor (MN2), a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a constant current source (I). The gate of the first NMOS transistor (MN1) is the negative input terminal of the error amplifier (EA), and the gate of the second NMOS transistor (MN2) is the positive input terminal of the error amplifier (EA). The sources of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are both connected to the input terminal of the constant current source (I). The drain of N1 is connected to the drain of the first PMOS transistor (MP1), the drain of the second NMOS transistor (MN2) is connected to the drain of the second PMOS transistor (MP2), and is the output terminal of the error amplifier (EA). The sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2), and the power transistor (MP) are connected to the power supply voltage. The gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are connected and are both connected to one end of the PSRR compensation capacitor (C2). The other end of the PSRR compensation capacitor (C2) and the output terminal of the constant current source (I) are grounded. When the error amplifier (EA) is a sleeve-type common-source common-gate amplifier, the sleeve-type common-source common-gate amplifier includes a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), and a seventh PMOS transistor (MP7). The source of the third NMOS transistor (MN3) is connected to the source of the fourth NMOS transistor (MN4). The gate of the third NMOS transistor (MN3) is the negative input terminal of the sleeve-type common-source common-gate amplifier, and the gate of the fourth NMOS transistor (MN4) is the positive input terminal of the sleeve-type common-source common-gate amplifier. The drain of the third NMOS transistor (MN3) is connected to the source of the fifth NMOS transistor (MN5), and the drain of the fourth NMOS transistor (MN4) is connected to the source of the fifth NMOS transistor (MN5). The source of the sixth NMOS transistor (MN6) is connected to the source of the fifth NMOS transistor (MN5), the gate of the fifth NMOS transistor (MN5) is connected to the gate of the sixth NMOS transistor (MN6), the drain of the fifth NMOS transistor (MN5) is connected to the drain of the fourth PMOS transistor (MP4), the drain of the sixth NMOS transistor (MN6) is connected to the drain of the fifth PMOS transistor (MP5), the gate of the fourth PMOS transistor (MP4) is connected to the gate of the fifth PMOS transistor (MP5), the source of the fourth PMOS transistor (MP4) is connected to the drain of the sixth PMOS transistor (MP6), the source of the fifth PMOS transistor (MP5) is connected to the drain of the seventh PMOS transistor (MP7), and the gate of the sixth PMOS transistor (MP6) is connected to the gate of the seventh PMOS transistor (MP7). All of these are connected to one end of the PSRR compensation capacitor (C2), and the other end of the PSRR compensation capacitor (C2) is grounded. When the error amplifier (EA) is a common-source cascode amplifier, the common-source cascode amplifier includes a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a seventh PMOS transistor (MP7), an eighth PMOS transistor (MP8), a ninth PMOS transistor (MP9), and a tenth PMOS transistor (MP10). The gate of the seventh NMOS transistor (MN7) is the negative input terminal of the common-source cascode amplifier, and the gate of the eighth NMOS transistor (MN8) is the positive input terminal of the common-source cascode amplifier. The source of the seventh NMOS transistor (MN7) is connected to the source of the eighth NMOS transistor (MN8), and the drain of the seventh NMOS transistor (MN7) is connected to the... The drain of the seventh PMOS transistor (MP7) is connected to the drain of the eighth NMOS transistor (MN8). The gate of the seventh PMOS transistor (MP7) is connected to the gate of the eighth PMOS transistor (MP8). The source of the seventh PMOS transistor (MP7) is connected to the drain of the ninth PMOS transistor (MP9). The source of the eighth PMOS transistor (MP8) is connected to the drain of the tenth PMOS transistor (MP10). The gate of the ninth PMOS transistor (MP9) is connected to the gate of the tenth PMOS transistor (MP10), and both are connected to one end of the PSRR compensation capacitor (C2). The other end of the PSRR compensation capacitor (C2) is grounded. When the error amplifier (EA) is another common-source cascode amplifier, the other common-source cascode amplifier includes a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), an eleventh NMOS transistor (MN11), a twelfth NMOS transistor (MN12), an eleventh PMOS transistor (MP11), and a twelfth PMOS transistor (MP12). The gate of the ninth NMOS transistor (MN9) is the negative input terminal of the common-source cascode amplifier, the gate of the tenth NMOS transistor (MN10) is the positive input terminal of the common-source cascode amplifier, the source of the ninth NMOS transistor (MN9) is connected to the source of the tenth NMOS transistor (MN10), and the drain of the ninth NMOS transistor (MN9) is connected to the source of the eleventh NMOS transistor (MN11). The drain of the tenth NMOS transistor (MN10) is connected to the source of the twelfth NMOS transistor (MN12), the gate of the eleventh NMOS transistor (MN11) is connected to the gate of the twelfth NMOS transistor (MN12), the drain of the eleventh NMOS transistor (MN11) is connected to the drain of the eleventh PMOS transistor (MP11), the drain of the twelfth NMOS transistor (MN12) is connected to the drain of the twelfth PMOS transistor (MP12), and is the output terminal of the other common-source common-gate amplifier. The gate of the eleventh PMOS transistor (MP11) and the gate of the twelfth PMOS transistor (MP12) are connected and both are connected to one end of the PSRR compensation capacitor (C2), and the other end of the PSRR compensation capacitor (C2) is grounded.

2. The high power supply voltage rejection ratio capacitorless low dropout linear regulator according to claim 1, characterized in that: When the error amplifier (EA) is a single-stage amplifier, the error amplifier (EA) also includes an impedance capacitor (CL) and an impedance resistor (RL); the other end of the Miller compensation capacitor (C1) is connected to one end of the impedance capacitor (CL) and one end of the impedance resistor (RL), and the other end of the impedance capacitor (CL) and the other end of the impedance resistor (RL) are both grounded.

3. The high power supply voltage rejection ratio capacitorless low dropout linear regulator according to claim 2, characterized in that: The formula for Power Supply Rejection Ratio (PSRR) is: When the frequency F < P0, ; When P0 < F < GBW, ; When F > GBW ; Where gm1 is the transconductance of the first NMOS transistor. rdsn1 and rdsp1 are the output impedances of the first NMOS transistor and the power transistor, respectively; gm3 is the output transconductance of the power transistor; and Ro3 is the output impedance of the power transistor. It is the feedback coefficient. R1 is the resistance of the first voltage divider resistor, R2 is the resistance of the second voltage divider resistor, P0 is the dominant pole of the low dropout linear regulator (LDO), and GBW is the gain-bandwidth product of the LDO. CL is the capacitance value of the impedance capacitor, RL is the resistance value of the impedance resistor; Ct is the sum of the Miller compensation capacitor and the power transistor parasitic capacitance; C2 is the PSRR compensation capacitor, and s is the Laplace operator.

4. The high power supply voltage rejection ratio capacitorless low dropout linear regulator according to claim 1, characterized in that: When the error amplifier (EA) is a single-stage amplifier, a zero-point cancellation resistor (R3) is connected between the output terminal of the error amplifier (EA) and one end of the Miller compensation capacitor (C1).

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