Multi-thread processor pipeline architecture system, scheduling method and equipment

Abstract

The invention relates to the technical field of processor design, discloses a multi-thread processor pipeline architecture system, a scheduling method and equipment, and designs an instruction prefetching scheduling algorithm based on mixed priorities, and the algorithm realizes load balancing of thread instruction queues through a static level decision mechanism and a dynamic level decision mechanism. The static level preferentially processes an empty queue thread to avoid starvation, and the dynamic level dynamically adjusts instruction fetching priority according to each queue depth, thread validity and a branch risk state to ensure that an instruction stream is continuously and stably supplied to a subsequent stage; a coupled polling emission scheduling algorithm is provided, so that high complexity of full-permutation search is avoided, and structural conflicts and data conflicts are effectively reduced; a special hardware architecture is designed around the algorithm, a multi-program counter and an instruction queue are integrated at the front end, a double-transmitting channel, a multifunctional unit and a thread private register file are configured at the rear end, and the performance of the single-core CPU is improved by optimizing the hardware architecture.

Description

Technical Field

[0001] This application relates to the field of processor design technology, such as a multi-threaded processor pipeline architecture system, scheduling method, and device. Background Technology

[0002] In modern computing systems, instruction-level parallelism and thread-level parallelism are key approaches to improving processor performance. However, traditional single-threaded processors are limited by data dependencies, control dependencies, and structural dependencies in the code, making it difficult to fully exploit the parallel potential of the pipeline. Especially when encountering cache access latency, branch prediction errors, or overlapping execution units, pipeline stalls are inevitable, leading to idle computing resources. To overcome this limitation, hardware multithreading technology has been widely introduced. By sharing processor resources such as arithmetic units and memory interfaces among multiple threads, the independence between threads hides the latency of single-threaded execution, thereby improving overall throughput.

[0003] Existing hardware multithreaded architectures mainly include three scheduling strategies: fine-grained multithreading (FGMT), coarse-grained multithreading (CGMT), and synchronous multithreading (SMT). FGMT uses a polling method to switch threads every cycle. Although it can effectively hide short-term latency, it cannot fully utilize the potential of a multi-issue architecture. When there are dependencies between instructions within a thread, the dual-issue or multi-issue capability is wasted. CGMT only switches threads when long-latency events occur (such as cache misses), reducing the overhead of thread switching, but it cannot respond to short-term pause events, and its scheduling granularity is relatively coarse, resulting in insufficient flexibility in resource allocation. SMT allows instructions from different threads to be issued within the same cycle, theoretically maximizing the utilization of hardware resources. However, traditional SMT implementations rely on complex dynamic scheduling logic and out-of-order execution mechanisms, resulting in significant hardware overhead. Especially in scenarios with a large number of threads, the decision complexity of the scheduler increases exponentially, making it difficult to apply in area- and power-sensitive embedded scenarios.

[0004] In summary, existing technical solutions suffer from low multi-threaded processor scheduling efficiency and high hardware overhead.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] The multi-threaded processor pipeline architecture system, scheduling method, and device provided in this disclosure can solve the problems of low scheduling efficiency and high hardware overhead of multi-threaded processors in existing technical solutions.

[0008] This disclosure provides a multi-threaded processor pipeline architecture system, which may include a front-end module and a back-end module; The front-end module includes multiple program counters, instruction prefetching units, multiple thread instruction queues, and a launch scheduling module. The backend module includes a decoding module, a data transmission module, multiple execution units, and a write-back module; The instruction prefetching unit uses a hybrid priority instruction prefetching scheduling algorithm to dynamically select the prefetching thread; The launch scheduling module uses a coupled polling launch scheduling algorithm to select launchable command pairs; The architecture supports the parallel execution of multiple hardware threads and employs a dual-launch mechanism.

[0009] This disclosure provides a multi-threaded processor instruction scheduling method, applied to the above-described architecture system, the method comprising: A hybrid priority instruction prefetching scheduling algorithm is adopted to dynamically select prefetching threads and fill them into the corresponding thread instruction queues; A coupled polling-based launch scheduling algorithm is used to select conflict-free instruction pairs from multiple threads for launch; The selected instruction pair is executed in parallel under the dual-issue mechanism, and the execution result is written back to the register or memory.

[0010] This disclosure provides an electronic device that includes at least one processor; and memory that is communicatively connected to at least one processor; The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the multi-threaded processor instruction scheduling method described above.

[0011] This disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the above-described multi-threaded processor instruction scheduling method.

[0012] The multi-threaded processor pipeline architecture system, scheduling method, and device provided in this disclosure can achieve the following technical effects: This disclosure addresses the problems of low scheduling efficiency and high hardware overhead in existing multi-threaded processor technologies by proposing a multi-threaded processor pipeline architecture and its instruction scheduling method. The core solution includes the following aspects: First, a hybrid priority-based instruction prefetch scheduling algorithm is designed. This algorithm achieves load balancing of thread instruction queues through a two-level decision mechanism of static and dynamic levels. The static level prioritizes threads with empty queues to avoid starvation, while the dynamic level dynamically adjusts the instruction fetch priority based on the depth of each queue, thread validity, and branch risk status, thereby ensuring a continuous and stable supply of instructions to subsequent stages. Second, this invention proposes a coupled polling issue scheduling algorithm based on a multi-issue mechanism. By grouping hardware threads into coupled pairs (such as two-to-two coupling of threads in a dual-issue architecture), a polling method is used within each group to select instruction pairs without data dependencies for issuance. This avoids the high complexity of full permutation search and effectively reduces structural and data conflicts. Finally, this invention designs a dedicated hardware architecture around the above algorithm, employing a front-end that integrates multiple program counters and instruction queues, and a back-end configured with dual issue channels, multi-functional units, and thread-private register files. By optimizing the hardware architecture, the performance of a single-core CPU is improved.

[0013] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0014] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a multi-threaded processor pipeline architecture system provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the overall architecture of a multi-threaded processor pipeline architecture and its instruction scheduling method provided in this embodiment of the disclosure; Figure 3 This is a schematic diagram illustrating a specific implementation of a hybrid priority instruction prefetching and scheduling algorithm provided in this embodiment of the disclosure; Figure 4 This is a schematic diagram of a coupled polling launch scheduling algorithm provided in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating a multi-threaded processor instruction scheduling method provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a multi-threaded processor instruction scheduling device provided in an embodiment of this disclosure. Detailed Implementation

[0015] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0016] The terms "first," "second," etc., used in the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0017] Unless otherwise stated, the term "multiple" means two or more.

[0018] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0019] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0020] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0021] To address the aforementioned issues, this disclosure provides a multi-threaded processor pipeline architecture system, scheduling method, device, and storage medium.

[0022] The following description, in conjunction with the accompanying drawings, illustrates the multi-threaded processor pipeline architecture system, scheduling method, device, and storage medium provided in the embodiments of this disclosure.

[0023] Figure 1 This is a schematic diagram of a multi-threaded processor pipeline architecture system provided in an embodiment of this disclosure.

[0024] Combination Figure 1 As shown, a multi-threaded processor pipeline architecture system may include: Front-end module 101 and back-end module 102; The aforementioned front-end module 101 includes multiple program counters, instruction prefetching units, multiple thread instruction queues, and a launch scheduling module. The backend module includes a decoding module, a data transmission module, multiple execution units, and a write-back module; The instruction prefetching unit uses a hybrid priority instruction prefetching scheduling algorithm to dynamically select the prefetching thread; The launch scheduling module uses a coupled polling launch scheduling algorithm to select launchable command pairs; The architecture supports the parallel execution of multiple hardware threads and employs a dual-launch mechanism.

[0025] In some embodiments, the instruction prefetching scheduling algorithm described above includes static priority determination and dynamic priority calculation; Static priority determination is used to prioritize threads whose instruction prefetch queue is empty; Dynamic priority calculation is based on a weighted score of queue depth, thread validity, and branch risk status.

[0026] In some embodiments, the parameters used in the above dynamic priority calculation include the inverse of the queue depth, the thread validity flag, and the branch risk coefficient. Each parameter is combined with a configured weight coefficient to generate a priority score.

[0027] In some embodiments, the above-described coupled polling launch scheduling algorithm groups multiple hardware threads into pairs, with each pair serving as a scheduling unit. Within the group, a polling method is used to select instruction pairs without data dependencies for launch.

[0028] In some embodiments, when the instruction of one thread in the coupling pair is blocked, the instruction of the other thread is issued first. If both threads are blocked, the unblocked threads are recombined to form a new coupling pair and continue firing.

[0029] In some embodiments, the execution unit includes an integer calculation unit, a floating-point calculation unit, a special function calculation unit, and a storage loading unit; each hardware thread has a private register file.

[0030] In some embodiments, the pipeline described above is an eight-stage pipeline structure, including instruction prefetching, instruction filling, issue scheduling, decoding, data issuance, execution, memory access, and write-back stages.

[0031] Figure 2 This is a schematic diagram of the overall architecture of a multi-threaded processor pipeline architecture and its instruction scheduling method provided in this disclosure. Figure 3 This is a schematic diagram illustrating a specific implementation of a hybrid priority instruction prefetching scheduling algorithm provided in this embodiment. Figure 4 This is a schematic diagram of a coupled polling launch scheduling algorithm provided in an embodiment of this disclosure, combined with... Figures 2 to 4 ,right Figure 1 The multi-threaded processor pipeline architecture system will be further described.

[0032] This disclosure addresses the problems of low scheduling efficiency and high hardware overhead in existing multi-threaded processor technologies by proposing a multi-threaded processor pipeline architecture and its instruction scheduling method. This invention achieves technical breakthroughs through the following three aspects: (I) Multi-threaded processor pipeline architecture In this invention, an eight-stage pipeline architecture is adopted, specifically designed for multi-threaded parallel execution. The overall architecture can be divided into two main parts: the front-end and the back-end. It supports parallel processing of multiple hardware threads (e.g., four threads) and improves instruction throughput through a dual-issue mechanism. The specific architecture is as follows: Figure 2 As shown: The front-end is responsible for instruction prefetching and issue scheduling, and includes the following execution components and stages: First, there are multiple program counters, each hardware thread has an independent program counter to record the current instruction address. The subsequent instruction fetching stage fetches instructions from the corresponding address in the L1 instruction cache based on the program counter value. Figure 2 In this example, there are 4 hardware threads, but in actual projects, the configuration can be freely adjusted. Next is the instruction prefetching unit, which has a built-in instruction prefetching algorithm. It dynamically selects the thread to prefetch in the current cycle using a hybrid priority scheduling algorithm (see below). Each cycle completes the prefetching operation of one instruction and stores the obtained instruction in the corresponding thread instruction queue. The instruction cache is a shared instruction storage space for all threads, providing low-latency instruction access for all threads. Following this is the thread instruction queue for the instruction filling stage, corresponding to the number of hardware threads. Each thread has an independent instruction queue (with configurable depth, such as 8 entries) used to temporarily store prefetched instructions, preventing pipeline stalls. Then comes the issue scheduling module. This module is responsible for checking data dependencies (such as RAW, WAR, WAW conflicts) and structural dependencies (such as functional unit conflicts) between instructions. Simultaneously, based on the effective relationships between threads, it uses a coupled polling algorithm (see below) to select issueable instruction pairs (dual issue) to ensure that conflict-free instructions enter the execution phase.

[0033] The backend is responsible for the decoding, issuing, execution, and write-back of instructions, and includes the following components and stages: First, the decoding module. To adapt to the dual-issue execution process, two independent decoding modules are used to complete the decoding, responsible for decoding instructions from binary format into micro-operations and identifying instruction types (such as arithmetic, store, and branch). Next is the data issuing stage. Each hardware thread has a thread-private register file to avoid data pollution between multiple threads. The issuing module reads data from the corresponding register file in parallel according to the selected thread ID and arbitrates before sending it to the corresponding execution unit. In the execution unit, there are four main types of calculation units: integer, floating-point, special function, and data storage loading units. Different calculation units require different time periods to complete the calculations, which are also important input weights for the subsequent coupled polling issue scheduling algorithm. Finally, the data write-back stage is responsible for writing the execution results back to registers or memory and updating the thread state. The integer, floating-point, and special function calculation units interact with the registers of each thread, and the data storage loading unit interacts with the data cache.

[0034] (II) Specific Implementation of the Hybrid Priority Instruction Prefetch Scheduling Algorithm In this invention, to improve instruction prefetching efficiency, a hybrid priority instruction prefetching scheduling algorithm is employed to achieve dynamic load balancing of the thread instruction queues through a multi-level decision-making mechanism. Its core idea is to ensure basic fairness through static priority while combining it with dynamic priority to achieve real-time performance optimization. The algorithm comprehensively evaluates the instruction queue status of the four hardware threads each clock cycle and dynamically adjusts the prefetching priority based on factors such as queue depth, thread validity, and branch risk status.

[0035] In the static priority hierarchy, the algorithm first checks for the existence of threads with empty queues. If a thread's instruction queue is empty, a prefetch operation is immediately triggered to ensure no thread falls into a starvation state. This mechanism is implemented through a hardware state machine. When the queue depth counter shows zero, the arbitrator skips the dynamic calculation process and prioritizes serving that thread. If there are no threads with empty queues, the dynamic priority calculation phase begins. This phase uses a weighted scoring model, considering three key parameters: the inverse of the queue depth (to prevent queue exhaustion), a thread validity flag (to distinguish between active and dormant threads), and a branch risk coefficient (to compensate for threads with high misprediction rates). These parameters are combined using configurable weight coefficients to generate a priority score for each thread, with the thread having the highest score gaining prefetch privileges.

[0036] The hardware implementation of this algorithm requires the collaborative work of multiple dedicated components, including a queue depth monitor, a thread status register, a priority calculation unit, and an arbitrator. The queue depth monitor uses a counter structure to track the fill status of each thread's instruction queue in real time; the thread status register stores status information from the branch prediction unit and the thread management unit; the priority calculation unit, composed of adders, multipliers, and comparators, can complete the score calculation for all threads within a single cycle; and the arbitrator generates the final thread selection signal based on the score results. The entire calculation process is implemented in a pipelined manner, ensuring that an effective prefetch decision is generated in each clock cycle.

[0037] The algorithm execution flow comprises five consecutive phases: state detection, static judgment, dynamic computation, arbitration execution, and state update. In the state detection phase, the hardware collects real-time data from all threads; the static judgment phase identifies emergency situations involving empty queues; the dynamic computation phase completes the scoring model calculation; the arbitration phase selects the target thread; and finally, the state registers of the relevant threads are updated. Furthermore, the algorithm integrates multiple exception handling mechanisms, including priority compensation for threads with mispredicted branches, priority downgrading for threads with cache misses, and intelligent ignoring of sleeping threads. These optimization strategies significantly improve the system's response speed and energy efficiency.

[0038] (III) Specific Implementation of Coupled Polling Launch Scheduling Algorithm In this invention, the coupled polling launch scheduling algorithm achieves efficient instruction scheduling through an innovative thread grouping mechanism and dynamic polling strategy. The algorithm first groups multiple hardware threads into pairs, for example, pairing thread 0 with thread 1 and thread 2 with thread 3 in a four-thread architecture. Each pair acts as an independent scheduling unit. This grouping design reduces the complexity of scheduling decisions from exponential to linear, making the hardware implementation more efficient. At the beginning of each launch cycle, the scheduler evaluates the activity status of each pair and prioritizes the pair containing more ready instructions for processing, ensuring full utilization of execution resources. Furthermore, the pairwise grouping of threads aligns with the backend execution module in a dual-launch architecture; for a four-launch module, the corresponding grouping granularity is four.

[0039] During the selection of coupled thread pairs, polling arbitration is used first. Taking coupled pair 0 = {thread 0, thread 1} and coupled pair 1 = {thread 2, thread 3} as an example, the corresponding instructions of coupled pair 0 and coupled pair 1 are polled and emitted in each cycle. When an instruction in a coupled pair becomes blocked (e.g., branch prediction failure, instruction requiring too long to load from memory, execution unit conflict, etc.), the instructions of the thread in the other coupled pair are continuously emitted. Furthermore, when both coupled pairs have stalled instructions, the coupled pairs are reassembled according to the stalled threads, and the threads that have not stalled are formed into new coupled pairs and emitted again.

[0040] The advantages of this invention are as follows: Addressing the problems of low scheduling efficiency and high hardware overhead in existing multi-threaded processor technologies, this invention proposes a multi-threaded processor pipeline architecture and its instruction scheduling method. The core solution includes the following aspects: First, a hybrid priority-based instruction prefetch scheduling algorithm is designed. This algorithm achieves load balancing of the thread instruction queue through a two-level decision mechanism of static and dynamic levels. The static level prioritizes threads with empty queues to avoid starvation, while the dynamic level dynamically adjusts the instruction fetch priority based on the depth of each queue, thread validity, and branch risk status, thereby ensuring a continuous and stable supply of instructions to subsequent stages. Second, this invention proposes a coupled polling-based issue scheduling algorithm based on a multi-issue mechanism. By grouping hardware threads into coupled pairs (e.g., two-way coupling of threads in a dual-issue architecture), a polling method is used within each group to select instruction pairs without data dependencies for issuance. This avoids the high complexity of full permutation search and effectively reduces structural and data conflicts. Finally, this invention designs a dedicated hardware architecture around the above algorithm, employing a front-end integrating multiple program counters and instruction queues, and a back-end configured with dual-issue channels, multi-functional units, and thread-private register files. Optimizing the hardware architecture improves the performance of a single-core CPU.

[0041] and Figure 1 Corresponding to the structural diagram of the multi-threaded processor pipelined architecture system, this disclosure also provides a multi-threaded processor instruction scheduling method applied to the aforementioned multi-threaded processor pipelined architecture system, such as... Figure 5 As shown, a multi-threaded processor instruction scheduling method may include: S501 employs a hybrid priority instruction prefetching scheduling algorithm to dynamically select prefetching threads and fill them into the corresponding thread instruction queues. S502 employs a coupled polling-based launch scheduling algorithm to select conflict-free instruction pairs from multiple threads for launch. The S503 executes selected instruction pairs in parallel under a dual-issue mechanism and writes the execution results back to registers or memory.

[0042] In some embodiments, the above instruction prefetching scheduling algorithm may include: Check the depth of the instruction queue for each thread. If there is an empty queue for a thread, prefetch the instructions of that thread first. Otherwise, a prefetch thread is selected based on the inverse of the queue depth, thread validity, and branch risk status to calculate the dynamic priority.

[0043] Combination Figure 6As shown in the illustration, this disclosure also provides a multi-threaded processor instruction scheduling device 600, including a processor 604 and a memory 601. Optionally, the system may further include a communication interface 602 and a bus 603. The processor 604, communication interface 602, and memory 601 can communicate with each other via the bus 603. The communication interface 602 can be used for information transmission. The processor 604 can call logical instructions in the memory 601 to execute the multi-threaded processor instruction scheduling method of the above embodiments.

[0044] Furthermore, the logic instructions in the aforementioned memory 601 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0045] The memory 601, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 604 executes functional applications and data processing by running the program instructions / modules stored in the memory 601, thereby implementing the multi-threaded processor instruction scheduling method in the above embodiments.

[0046] The memory 601 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 601 may include high-speed random access memory and may also include non-volatile memory.

[0047] This disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured as a multi-threaded processor instruction scheduling method.

[0048] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0049] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0050] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes the element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0051] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0052] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0053] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0054] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0055] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0056] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0057] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0058] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0059] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0060] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0061] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A multi-threaded processor pipeline architecture system, characterized by, The architecture system comprises a front-end module and a back-end module; The front-end module comprises a plurality of program counters, an instruction prefetch unit, a plurality of thread instruction queues and a dispatch module; The back-end module comprises a decoding module, a data dispatch module, a plurality of execution units and a write-back module; The instruction prefetch unit dynamically selects a thread for prefetching by using a hybrid priority instruction prefetch scheduling algorithm; The dispatch module selects a dispatchable instruction pair by using a coupled polling dispatch algorithm; The architecture supports parallel execution of a plurality of hardware threads and uses a dual dispatch mechanism.

2. The architectural system of claim 1, wherein, The instruction prefetch scheduling algorithm comprises static priority judgment and dynamic priority calculation; The static priority judgment is used to preferentially prefetch a thread with an empty instruction queue; The dynamic priority calculation is based on weighted scoring of queue depth, thread validity and branch risk state.

3. The architectural system of claim 2, wherein, The parameters used in the dynamic priority calculation include queue depth reciprocal, thread validity flag and branch risk coefficient, and each parameter is combined by a configured weight coefficient to generate a priority score.

4. The architectural system of claim 1, wherein, The coupled polling dispatch algorithm groups the plurality of hardware threads into coupled pairs, each coupled pair being a dispatch unit, and selects an instruction pair without data dependency in the group for dispatch by polling.

5. The architectural system of claim 4, wherein, When the instructions of a thread in a coupled pair are blocked, the instructions of the other thread are preferentially dispatched; If both threads are blocked, the unblocked thread is recombined to form a new coupled pair for continued dispatch.

6. The architectural system of claim 1, wherein, The execution unit comprises an integer calculation unit, a floating point calculation unit, a special function calculation unit and a memory load unit; each hardware thread has a private register file.

7. The architectural system of claim 1, wherein, The pipeline is an eight-stage pipeline structure comprising instruction prefetching, instruction padding, dispatch, decoding, data dispatch, execution, memory access and write-back stages.

8. A method for instruction scheduling of a multi-threaded processor, applied to the architecture system of any one of claims 1-7, characterized in that, The method comprises: using a hybrid priority instruction prefetch scheduling algorithm to dynamically select a thread for prefetching and padding to a corresponding thread instruction queue; using a coupled polling dispatch algorithm to select an instruction pair without conflict from a plurality of threads for dispatch; parallel execution of the selected instruction pair under a dual dispatch mechanism and write-back of the execution result to a register or memory.

9. The method of claim 8, wherein, The instruction prefetch scheduling algorithm comprises: detecting the depth of each thread instruction queue, and if there is an empty queue thread, preferentially prefetching the instructions of the thread; otherwise, calculating a dynamic priority based on queue depth reciprocal, thread validity and branch risk state to select a thread for prefetching.

10. An electronic device, comprising: comprises: at least one processor; and a memory in communication connection with the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of claim 8 or 9.

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