Active inductor assembly for power data systems and related methods

Abstract

The invention relates to an active inductor assembly for a power data system and a related method. An active inductor assembly for a data on power (DoP) system includes a first active inductor and a second active inductor. The first active inductor includes a first pass element and a first control circuit. The first control circuit is configured to control the first pass element such that (i) the first pass element simulates the first inductor in response to a change in voltage across the first pass element, and (ii) the first pass unit adjusts a voltage drop across the first pass element during steady-state operation. The second active inductor includes a second pass element and a second control circuit. The second control circuit is configured to control the second pass element such that (i) the second pass element simulates the second inductor in response to a change in voltage across the second pass element, and (ii) the second pass element adjusts a voltage drop across the second pass element during steady-state operation.

Description

BACKGROUND

[0001] A data over power (DoP) system transmits power and data signals over a common electrical conductor. For example, a DoP system is used to transmit data signals between a central unit and a remote unit, and to power the remote unit from the central unit. BRIEF DESCRIPTION OF DRAWINGS

[0002] Figure 1 is a schematic diagram of a conventional active inductor.

[0003] Figure 2 is a schematic diagram of a data over power (DoP) system including two active inductor assemblies according to an embodiment.

[0004] Figure 3 includes two diagrams of one example of operation of a first station of a DoP system Figure 2

[0005] Figure 4 includes two diagrams of one example of operation of a second station of a DoP system Figure 2

[0006] Figure 5 is a schematic diagram of one embodiment of a first active inductor of a first station of a DoP system Figure 2

[0007] Figure 6 is a schematic diagram of one embodiment of a first active inductor of a second station of a DoP system Figure 2

[0008] Figure 7 is a schematic diagram of one embodiment of a second active inductor of a first station of a DoP system Figure 2

[0009] Figure 8 is a schematic diagram of one embodiment of a second active inductor of a second station of a DoP system Figure 2

[0010] Figure 9 is a schematic diagram of another embodiment of a first active inductor of a first station of a DoP system Figure 2

[0011] Figure 10 is a schematic diagram of another embodiment of a first active inductor of a second station of a DoP system Figure 2

[0012] Figure 11 is a schematic diagram of another embodiment of a second active inductor of a first station of a DoP system Figure 2 ​​​​​​​​​

[0013] Figure 12 yes Figure 2 A schematic diagram of another embodiment of the second active inductor of the second station of the DoP system.

[0014] Figure 13 yes Figure 2 A schematic diagram of an alternative embodiment of the first station of the DoP system also includes a diode.

[0015] Figure 14 It includes additional stations. Figure 2 A schematic diagram of an alternative embodiment of the DoP system.

[0016] Figure 15 It further includes protection circuitry. Figure 13 A schematic diagram of an alternative embodiment of the station.

[0017] Figure 16 yes Figure 2 A schematic diagram of an alternative embodiment of the second station of the DoP system also includes a bridge rectifier. Detailed Implementation

[0018] Power-on-data (DoP) systems typically require one or more magnetic devices, such as transformers or inductors, to isolate the data signal from the power supply and electrical load circuits. A large inductance value is usually desirable for these magnetic devices to help ensure the integrity of the data signal.

[0019] Magnetic devices are typically relatively large, heavy, and expensive. Electronic circuits, on the other hand, are generally relatively small, lightweight, and inexpensive. Therefore, it is desirable to replace the magnetic devices in a DoP system with electronic circuits configured as analog inductors. Such circuits can be called "active inductors." Figure 1 This is a schematic diagram of an active inductor 100, an example of a conventional active inductor. The active inductor 100 includes an enhancement-mode N-channel metal-oxide-semiconductor field-effect transistor (NMOS FET) 102, a resistor 104, and a capacitor 106. The NMOS FET 102 includes a drain (D), a source (S), a gate (G), and a parasitic body diode 108. The resistor 104 is electrically coupled between the drain (D) and the gate (G) of the NMOS FET 102. The capacitor 106 is electrically coupled between the gate (G) and the source (S) of the NMOS FET 102. The active inductor 100 has an inductance L as specified in EQN 1 below, where R is the resistance of the resistor 104, C is the capacitance of the capacitor 106, and g... m It is the transconductance of NMOS FET 102.

[0020]

[0021] While the active inductor 100 can be smaller, lighter, and cheaper than magnetic devices, its use in DoP systems can present significant drawbacks. For example, using the active inductor 100 in a DoP system can lead to undesirable variations in the electrical bus voltage, such as due to temperature variations in the NMOS FET 102, variations in the current amplitude flowing through the active inductor 100, and manufacturing variations of the active inductor 100 components. Furthermore, the active inductor 100 requires resistor 104 to have a large resistance value and capacitor 106 to have a large capacitance value in order to achieve a large inductance value, which can make the active inductor 100 highly sensitive to leakage current flowing to the gate G of the NMOS FET 102. Additionally, the presence of the parasitic body diode 108 can undesirably limit the amplitude of data signals when used in a DoP system.

[0022] This document discloses an active inductor assembly and related methods for DoP systems, which at least partially overcome the aforementioned drawbacks. The new active inductor assembly advantageously regulates the steady-state voltage drop, as well as the analog inductor. Therefore, the new active inductor assembly can reliably accommodate data signals with large positive and negative amplitudes, thereby promoting reliable data signal transmission and flexibility in data transceiver design. Furthermore, the new active inductor assembly improves energy efficiency by precisely controlling the steady-state voltage drop, thereby eliminating the need for a large voltage drop and providing a margin for possible voltage drop variations. In addition, certain embodiments are configured to limit the current charging the energy storage capacitor of the active inductor assembly, thereby promoting a large inductance value during large-signal transient operating events (e.g., during data transmission) while maintaining precise regulation of the steady-state voltage drop.

[0023] Figure 2 This is a schematic diagram of a DoP system 200, an example of a DoP system including embodiments of the novel active inductor assembly disclosed herein. The DoP system 200 includes station 202, station 204, and an electrical bus 206 electrically coupling station 204 to station 202. The DoP system 200 is configured to transmit data signals between station 202 and station 204 via the electrical bus 206. In some embodiments, the DoP system 200 is configured for bidirectional data signal transmission, i.e., from station 202 to station 204 and from station 204 to station 202. In some other embodiments, the DoP system 200 is configured to support only unidirectional data signal transmission, i.e., from station 202 to station 204 or from station 204 to station 202. The DoP system 200 is also configured such that station 202 supplies power to station 204 via the electrical bus 206.

[0024] In some embodiments, station 202 is a central unit and station 204 is a remote unit. Applications of the DoP system 200 include, but are not limited to, automotive applications and building or other home applications. For example, in some embodiments, station 202 is part of an automotive control module, and station 204 is part of an automotive sensor or user interface. As another example, in a particular embodiment, station 202 is part of a central heating, ventilation, and air conditioning (HVAC) system, and station 204 is part of a remote HVAC system. As another example, in some embodiments, station 202 is part of a central communication, security, or building automation system, and station 204 is part of a remote communication, security, or building automation device. However, it should be understood that the DoP system 200 is not limited to the above-described examples. For example, station 202 may alternatively be a remote unit, and station 204 may alternatively be a central unit. As another example, stations 202 and 204 may be physically located in a common location such that neither station 202 nor station 204 is central or remote relative to the other.

[0025] Electrical bus 206 includes a first electrical conductor 208 and a second electrical conductor 210. In some embodiments, the first electrical conductor 208 and the second electrical conductor 210 are wires of a twisted-pair cable. In some other embodiments, the first electrical conductor 208 and the second electrical conductor 210 are conductors of a coaxial cable. In certain other embodiments, the first electrical conductor 208 and the second electrical conductor 210 are printed circuit board (PCB) traces and / or PCB electrical planes. Furthermore, the first electrical conductor 208 and the second electrical conductor 210 may be implemented in other ways without departing from the scope of this document. The length of electrical bus 206 may vary depending on the application of DoP system 200. For example, if stations 202 and 204 are supported by a common PCB, electrical bus 206 may be relatively short; if stations 2020 and 204 are located in different rooms of a building, electrical bus 206 may be relatively long.

[0026] Station 202 includes a positive power rail 212, a negative power rail 214, a first port 216, a second port 218, an active inductor assembly 220, a power supply 222, a transceiver 224, a first data coupling capacitor 226, and a second data coupling capacitor 228. The first port 216 electrically couples station 202 to a first conductor 208, and the second port 218 electrically couples station 202 to a second conductor 210. In some embodiments, the first port 216 and the second port 218 are discrete components, such as electrical terminals or contacts, while in some other embodiments, each of the first port 216 and the second port 218 is a respective electrical node.

[0027] Transceiver 224 is configured to generate and / or receive differential data signal V T For example, in some embodiments where the DoP system 200 is configured for bidirectional signal transmission, transceiver 224 is configured to generate and receive differential data signals V. T Another example is that in some embodiments where the DoP system 200 is configured to support only unidirectional data signal transmission, the transceiver 224 is configured to generate only differential data signals V. T Or only receive differential information V T The first data coupling capacitor 226 is configured to electrically couple the differential data signal V between the transceiver 224 and the first port 216. T The first component, and the second data coupling capacitor 228 is configured to convert the differential data signal V T The second component is electrically coupled between transceiver 224 and second port 218.

[0028] Power supply 222 is electrically coupled between the positive power supply rail 212 and the negative power supply rail 214. Power supply 222 electrically biases the positive power supply rail 212 to voltage V. in_p And power supply 222 is biased to negative power rail 214 to voltage V. in_n As described below, power supply 222 supplies power to one or more loads of station 204. Active inductor assembly 220 includes a first active inductor 230 and a second active inductor 232. The first active inductor 230 includes a path element 234 and control circuitry 236. Path element 234 is electrically coupled between (i) the positive power rail 212 and (ii) the first port 216 (and the first electrical conductor 208), and control circuitry 236 is electrically coupled to each of the positive power rail 212, the first port 216, and path element 234. See below for reference. Figure 13 In some alternative embodiments, the path element 234 and the control circuit 236 are electrically coupled to the first port 216 via a current control circuit (e.g., one or more diodes or electronic circuitry simulating one or more diodes).

[0029] The path element 234 includes, for example, one or more transistors, such as field-effect transistors or bipolar junction transistors, configured to operate as a variable resistor under the control of the control circuit 236. Specifically, the control circuit 236 is configured to control the path element 234 such that the voltage drop V across the path element 234 is... drop_1 It conforms to EQN.2 below, where I1 is the current flowing through the path element 234, V reg_1Here, t is a predetermined value, t is time, and L1 is the inductance exhibited by the active inductor 230. Therefore, the control circuit 236 is configured to control the path element 234 such that (i) during the steady-state operation of the first active inductor 230, the path element 234 will apply voltage V... drop_1 Adjust to the predetermined value V reg_1 (ii) The pass element 234 responds to the voltage V across the pass element 234. drop_1 The change in voltage is used to simulate an inductor with inductance L1. In this patent, the steady-state operation of an active inductor means that the voltage V across the path element of the active inductor changes. drop The amplitude is constant, for example, when the DoP system 200 does not transmit differential data signal V through electrical bus 206. T For example, the steady-state operation of the active inductor 230 is characterized by voltage V. drop1 The amplitude is constant. As described below, V is selected based on the expected amplitude of the data signal on electrical bus 206. reg_1 A particular embodiment of the active inductor 230 is configured such that the inductance L1 presented by the active inductor 230 is boosted during large-signal transient events in the DoP system 200, such as when the DoP system 200 transmits differential data signal V via electrical bus 206. T Therefore, in these embodiments, when the DoP system 200 transmits the differential data signal V via the electrical bus 206... T When the value of inductor L1 is greater than that of the DoP system 100, differential data signal V is not transmitted through electrical bus 206. T The value of inductance L1 at that time.

[0030]

[0031] The second active inductor 232 includes a pass element 238 and a control circuit 240. The pass element 238 is electrically coupled between (i) a negative power rail 214 and (ii) a second port 218 (and a second electrical conductor 210), and the control circuit 240 is electrically coupled to each of the negative power rail 214, the second port 218, and the pass element 238. The pass element 238 includes, for example, one or more transistors, such as field-effect transistors or bipolar junction transistors, configured to operate as a variable resistor under the control of the control circuit 240. Specifically, the control circuit 240 is configured to control the pass element 238 such that the voltage drop V across the pass element 238... drop_2 It conforms to EQN.3 below, where I2 is the current flowing through the path element 238, and the voltage V... reg_2Here, t is a predetermined value, t is time, and L2 is the inductance exhibited by the active inductor 232. Therefore, the control circuit 240 is configured to control the path element 238 such that (i) during the steady-state operation of the second active inductor 232, the path element 238 will apply voltage V drop_2 Adjust to the predetermined value V reg_2 And (ii) the path element 238 responds to voltage V drop_2 The variation of the path element 238 simulates an inductor with inductance L2. In some embodiments of the active inductor assembly 220, each of the control circuits 236 and 240 is configured to cause the voltage V... reg_1 and voltage V reg_2 These are all common predetermined values ​​selected based on the expected amplitude of the data signal on electrical bus 206. A specific embodiment of the active inductor 232 is configured such that the inductance L2 presented by the active inductor 232 is boosted during large-signal transient events in the DoP system 200, such as when the DoP system 100 transmits a differential data signal V via electrical bus 206. T Therefore, in these embodiments, when the DoP system 200 transmits the differential data signal V via the electrical bus 206... T When the value of inductor L2 is greater than that of the DoP system 100, differential data signal V is not transmitted through electrical bus 206. T The value of inductance L2 at that time.

[0032]

[0033] Figure 3 Figures 300 and 302 together illustrate an example of the operation of station 202. However, it should be understood that station 202 is not limited to the following. Figure 3 The example is operated on. Figures 300 and 302 are voltage versus time graphs, and Figures 300 and 302 share a common time base. Figure 300 includes a representation of the voltage V on the positive power rail 212. in_p The curve and the voltage V on the first conductor 208 b_1 The curve. Figure 302 includes the voltage V across the second conductor 210. b_2 The curve. Voltage V b_1 nominal value V nom_1 equals V in_p -V reg_1 And voltage V b_2 nominal value V nom_2 equals V in_n +V reg_2 .exist Figure 3 In the example, V reg_1 and V reg_2 Each of them has a common amplitude.

[0034] Differential data signal V T In time period T a During this period, a positive assertion is made, characterized in that (i) the voltage V on the first conductor 208 is... b_1 The magnitude of the increase is VT / 2, and (ii) the voltage V on the second conductor 210 is increased. b_2 The magnitude of the decrease V T / 2. During time period T b During this period, the differential data signal V is asserted in a negative manner. T The feature is that (i) the voltage V on the first conductor 208 is... b_1 The magnitude of the decrease V T / 2, and (ii) the voltage V on the second conductor 210 b_2 The increase in amplitude V T / 2. It should be noted that the voltage V reg_1 The amplitude is greater than the differential data signal V on the first conductor 208 T Peak amplitude V T / 2 Big V mar_1 The margin is sufficient to ensure the differential data signal V on the first conductor 208. T There is sufficient margin. Similarly, the voltage V reg_2 The amplitude is greater than the differential data signal V on the second conductor 210. T Peak amplitude V T / 2 Big V mar_2 The margin is sufficient to ensure the differential data signal V on the second conductor 210. T There is sufficient margin. However, the circuit elements 234 and 238 respectively adjust the voltage V. drop_1 and voltage V drop_2 The fact that the steady-state value makes each margin V mar_1 and margin V mar_2 Both are small, while still ensuring signal integrity on electrical bus 206. Small margin V mar_1 and margin V mar_2 These factors help to minimize power consumption in path element 234 and path element 238, respectively, thereby improving the energy efficiency of the DoP system 200.

[0035] Refer again Figure 2Station 204 includes a positive power rail 242, a negative power rail 244, a first port 246, a second port 248, an active inductor assembly 250, a load 252, a transceiver 254, a first data coupling capacitor 256, and a second data coupling capacitor 258. The first port 246 electrically couples station 204 to a first conductor 208, and the second port 248 electrically couples station 204 to a second conductor 210. In some embodiments, the first port 246 and the second port 248 are discrete components, such as electrical terminals or contacts, while in some other embodiments, each of the first port 246 and the second port 248 is a respective electrical node.

[0036] Transceiver 254 is configured to generate and / or receive differential data signal V T In some embodiments where the DoP system 200 is configured for bidirectional signal transmission, the transceiver 254 is set to generate and receive differential data signals V. T As another example, in some embodiments where the DoP system 200 is configured to support only unidirectional data signal transmission, the transceiver 254 is set to generate only differential data signals V. T Or only receive differential data signal V T The first data coupling capacitor 256 is configured to electrically couple the differential data signal V between the transceiver 254 and the first port 246. T The first component, and the second data coupling capacitor 258 are configured to electrically couple the differential data signal V between the transceiver 254 and the second port 248. T The second component.

[0037] A load 252 is electrically coupled between the positive power rail 242 and the negative power rail 244. In some embodiments, the load 252 includes a capacitor (not shown) and power-consuming circuitry. The power supply 222 of station 202 electrically biases the positive power rail 242 to voltage V via the active inductor 230 of the active inductor assembly 250, the first electrical conductor 208, and the first active inductor 260 (discussed below). out_p Furthermore, the power supply 222 of station 202 electrically biases the negative power rail 244 to voltage V via the active inductor 232 of the active inductor assembly 250, the second conductor 210, and the second active inductor 262 (discussed below). out_n Therefore, load 252 is powered by power supply 222 of station 202.

[0038] The active inductor assembly 250 includes a first active inductor 260 and a second active inductor 262. The first active inductor 260 includes a pass element 264 and a control circuit 266. The pass element 264 is electrically coupled between a first port 246 and a positive power rail 242, and the control circuit 266 is electrically coupled to each of the first port 246, the positive power rail 241, and the pass element 264. See below for reference. Figure 16 In some alternative embodiments, the path element 264 and the control circuit 266 are electrically coupled to the first port 246 via a bridge rectifier.

[0039] The path element 264 includes, for example, one or more transistors, such as field-effect transistors or bipolar junction transistors, configured to operate as a variable resistor under the control of the control circuit 266. Specifically, the control circuit 266 is configured to control the path element 264 such that the voltage drop V across the path element 264 is... drop_3 It conforms to EQN.4 below, where I3 is the current flowing through the path element 264, and the voltage V is... reg_3 Here, t is a predetermined value, t is time, and L3 is the inductance exhibited by the active inductor 260. Therefore, the control circuit 266 is configured to control the path element 264 such that (i) during the steady-state operation of the active inductor 260, the path element 264 will apply voltage V... drop_3 Adjust to the predetermined value V reg_3 (ii) The pass element 264 responds to the voltage V across the pass element 264. drop_3 The change in V simulates an inductor with inductance L3. As described below, V is selected based on the expected amplitude of the data signal on electrical bus 206. reg_3 A particular embodiment of the active inductor 260 is configured such that the inductance L3 presented by the active inductor 260 is boosted during large-signal transient events in the DoP system 200, such as when the DoP system 100 transmits differential data signal V via electrical bus 206. T Therefore, in these embodiments, when the DoP system 200 transmits the differential data signal V via the electrical bus 206... T When the value of inductor L3 is greater than that of the DoP system, differential data signal V is not transmitted through electrical bus 206. T The value of inductance L3 at that time.

[0040]

[0041] The second active inductor 262 includes a pass element 268 and a control circuit 270. The pass element 268 is electrically coupled between the second port 248 and the negative power rail 244, and the control circuit 270 is electrically coupled to each of the second port 248, the negative power rail 244, and the pass element 268. See below for reference.Figure 16 In some alternative embodiments, the path element 268 and the control circuit 270 are electrically coupled to the second port 248 via a bridge rectifier.

[0042] The path element 268 includes, for example, one or more transistors, such as field-effect transistors or bipolar junction transistors, configured to operate as a variable resistor under the control of the control circuit 270. Specifically, the control circuit 270 is configured to control the path element 268 such that the voltage drop V across the path element 268 is... drop_4 It conforms to EQN.5 below, where I4 is the current flowing through the path element 268, and the voltage V is... reg_4 Here, t is a predetermined steady-state value, t is time, and L4 is the inductance exhibited by the active inductor 262. Therefore, the control circuit 270 is configured to control the path element 268 such that (i) during the steady-state operation of the second active inductor 262, the path element 268 will transfer voltage V... drop_4 Adjust to the predetermined value V reg_4 (ii) The pass element 268 responds to the voltage V across the pass element 268. drop_4 The change in voltage V simulates an inductor with inductance L4. In some embodiments of the active inductor assembly 250, control circuitry 266 and 270 are configured to cause voltage V to change. reg_3 and voltage V reg_4 Each of these values ​​is a common predetermined value selected based on the expected amplitude of the data signal on electrical bus 206. A specific embodiment of the active inductor 262 is configured such that the inductance L4 presented by the active inductor 262 is boosted during large-signal transient events in the DoP system 200, such as when the DoP system 100 transmits the differential data signal V via electrical bus 206. T Therefore, in these embodiments, when the DoP system 200 transmits the differential data signal V via the electrical bus 206... T When the value of inductor L4 is greater than that of the DoP system, differential data signal V is not transmitted through electrical bus 216. T The value of inductance L4 at that time.

[0043]

[0044] Figure 4 Figures 400 and 402 together illustrate an example of the operation of station 204. However, it should be understood that station 204 is not limited to the following. Figure 4 The example is operated on. Figures 400 and 402 are voltage versus time graphs, and Figures 400 and 402 share a common time base. Figure 400 includes a representation of the voltage V on the positive power rail 242. out_p The curve and the voltage V on the first conductor 208 b_1The curve. Figure 402 includes the voltage V on the negative power rail 244. out_n The curve and the voltage V on the second conductor 210 b_2 The curve. Voltage V b_1 nominal value V nom_1 equals V out_p +V reg_3 And voltage V b_2 nominal value V nom_2 equals V out_n -V reg_4 .exist Figure 4 In the example, V reg_3 and V reg_4 Each of them has a common amplitude, and in Figure 3 and Figure 4 In the example, V reg_1 =V reg_2 =V reg_3 =V reg_4 .

[0045] Figure 4 Including the above regarding Figure 3 The time period T under discussion a and T b Voltage V reg_3 The amplitude is greater than the differential data signal V on the first conductor 208. t Peak amplitude V of the pulse T / 2 Big V mar_3 The margin is sufficient to ensure the differential data signal V on the first conductor 208. t There is sufficient margin. Similarly, the voltage V ref_4 The amplitude is greater than the data signal V on the second conductor 210. T Peak amplitude V of the pulse T / 2 Big V mar_4 The margin is sufficient to ensure the differential data signal V on the second conductor 210. T There is sufficient clear space. (This is in accordance with the above regarding...) Figure 3 In a similar manner, path element 264 and path element 268 respectively adjust voltage V drop_3 and voltage V drop_4 The fact that the steady-state value makes the margin V mar_3 and margin V mar_4 Smaller, while still ensuring signal integrity on electrical bus 206. Margin V mar_3 and margin V mar_4 The smaller values ​​of help to minimize the power consumption in path element 264 and path element 268, thereby improving the energy efficiency of DoP system 200.

[0046] The following reference Figures 5-12The discussion focuses on exemplary embodiments of the active inductors disclosed herein. However, it should be understood that the active inductors disclosed herein may be embodied in other ways without departing from the scope of this document.

[0047] Figure 5 This is a schematic diagram of an active inductor 500, where the active inductor 500 is... Figure 2 One possible embodiment of the active inductor 230. The active inductor 500 includes an NMOS FET 502 and a control circuit 504, wherein the NMOS FET 502 is an embodiment of the pass element 234 and the control circuit 504 is an embodiment of the control circuit 236. The NMOS FET 502 includes a drain D, a source S, a gate G, and a parasitic body diode 506. The drain D of the NMOS FET 502 is electrically coupled to a positive power rail 212, and the source S of the NMOS FET 502 is electrically coupled to a first port 216 and a first electrical conductor 208. The control circuit 504 includes a storage capacitor 508, a transconductance amplifier 510, a resistor 512, a resistor 514, and a reference voltage source 516. The storage capacitor 508 is electrically coupled between the gate G and the source S of the NMOS FET 502. Resistors 512 and 514 are series-coupled between the drain (D) and source (S) of the NMOS FET 502. Reference voltage source 516 references the source (S) of the NMOS FET 502, and reference voltage source 518 generates a reference voltage V. ref_5 The transconductance amplifier 510 is configured to generate a voltage V corresponding to the input voltage V of the transconductance amplifier 510. in_5 Proportional output current It c_5 The input voltage V in_5 Equal to voltage V in_5 and reference voltage V ref_5 The difference between them. Voltage V mid_5 It is the voltage at the midpoint of the voltage divider between resistors 512 and 514, therefore the voltage V mid_5 With voltage V drop_1 Related. Transconductance amplifier 510 via its output current It c_5 Drive each of the gate G of the NMOS FET 502 and the energy storage capacitor 508 to control the NMOS FET 502.

[0048] According to EQN.6 below, during the steady-state operation of the first active inductor 500, the NMOS FET 502, under the control of the control circuit 504, will change the voltage V drop_1 The amplitude is adjusted to the predetermined value V. reg_1 , where R 512 It is the resistance of resistor 512, and R 514It is the resistance of resistor 514. Therefore, in the design process of active inductor 500, the resistance can be changed by altering R. 512 R 514 and V ref_5 One or more of them are used to adjust the voltage V reg_1 The amplitude. Furthermore, the control circuit 504 controls the NMOS FET 502, causing the active inductor 500 to respond to the voltage V across the NMOS FET 502. drop_1 The effective inductance L1 is exhibited due to the change in g. The inductance L1 presented by the active inductor 500 is given in EQN.7 below, where g m_ota5 It is the transconductance of the 510 transconductance amplifier, g m_FET5 It is the transconductance of the NMOS FET 502, C 508 It is the capacitance of the energy storage capacitor 508, and K5 is equal to R. 514 / (R 512 +R 514 The scaling factor. g m_ota5 The product of K5 and g can be considered as the gain of the transconductance amplifier 510, while g m_FET5 This can be considered as the gain of the NMOS FET 502.

[0049]

[0050] As can be clearly seen from EQN.7 below, the gain of the transconductance amplifier 510 and the NMOS FET 502 are inversely proportional to each other. Therefore, a smaller gain for the transconductance amplifier 510 is desirable to achieve a large inductance in the active inductor 500, because a large inductance in the active inductor in the DoP system 200 helps maintain a constant current flowing through the active inductor. This compensates for variations in the current flowing through the active inductor by minimizing the current demand through the coupling capacitor, thereby promoting the integrity of data communication signals on the electrical bus 206. On the other hand, a larger gain for the transconductance amplifier 510 is desirable to reduce the sensitivity of the active inductor 500 to leakage current flowing to the gate G of the NMOS FET 502, thereby achieving a voltage V reg_1 Strict adjustment. The applicant found that the conflict between these two objectives can be overcome by: (i) adjusting the gain (K5 and g) of the transconductance amplifier 510. m_ota5 (ii) set the product of (i) and (ii) set the output current It to a relatively high value. c_5 The amplitude is limited to a predetermined saturation value I. sat_5 Set the gain of transconductance amplifier 510 to a relatively...

[0051] A higher value helps improve immunity to leakage current flowing into the gate G of the NMOS FET 502 and to the voltage V during steady-state operation of the first active inductor 500. drop_1 The amplitude is precisely adjusted accordingly. Furthermore, the current It is... c_5 The amplitude is limited to the saturation value I. sat_5 Limitation during large-signal transient events (e.g., during the transmission of differential data signal V via electrical bus 206) T During this period, the rate of voltage change across the energy storage capacitor 508 increases the effective inductance of the first active inductor 500 during large-signal transients.

[0052] For example, consider one embodiment of an active inductor 500, wherein (i) the capacitance of the energy storage capacitor 508 is 100 nanofarads, and the gain (g) of the NMOS FET 502 is... m_FET5 The gain (K5 and g) of the transconductance amplifier 510 is 5 amps per volt. m_ota5 The product of ( ) is 6 microamps per volt, and the predetermined saturation value I sat_5 The current is 4 microamps. In this embodiment, the inductance L1 is equal to 3.33 millihenries (mH) as determined by EQN.7, but during a large-signal transient event in the form of a 2.5-volt pulse applied to the first port 216, the inductance L1 is boosted to 12.5 mH.

[0053] Therefore, a particular embodiment of the transconductance amplifier 510 is configured to define the saturation current value I according to EQN.8 below. sat_5 For example, in some embodiments, the saturation current value I sat_5 Less than V T / 2、g m_ota5 50% of the product of K5. As another example, in a specific embodiment, the saturation current value I... sat_5 Less than V T / 2、g m_ota5 10% of the product of K5. As another example, in some embodiments, the saturation current value I... sat_5 Less than V T / 2、g m_ota5 1% of the product of K and K.

[0054]

[0055] The active inductor 260 of station 204 can be implemented in a manner similar to that of active inductor 500. For example, Figure 6This is a schematic diagram of an active inductor 600, which is a possible embodiment of the active inductor 260 of station 204. The active inductor 600 includes an NMOS FET 602 and a control circuit 604, respectively, similar to an NMOS FET 502 and a control circuit 504. The NMOS FET 602 is an embodiment of the pass element 264, and the control circuit 604 is an embodiment of the control circuit 266. The NMOS FET 602 includes a drain (D), a source (S), a gate (G), and a parasitic body diode 606. The drain (D) of the NMOS FET 602 is electrically coupled to a first port 246 and a first electrical conductor 208, and the source (S) of the NMOS FET 602 is electrically coupled to a positive power rail 212. Control circuit 604 includes energy storage capacitor 608, transconductance amplifier 610, resistor 612, resistor 614, and reference voltage source 616, which are respectively analogous to energy storage capacitor 508, transconductance amplifier 510, resistor 512, resistor 514, and reference voltage source 516. Therefore, active inductor 600 operates in a manner similar to active inductor 500. For example, active inductor 600 operates in a manner similar to active inductor 500 to deliver voltage V during steady-state operation of active inductor 600. drop_3 The amplitude is adjusted to the predetermined value V. reg_3 Furthermore, the active inductor 600 operates in a manner similar to the active inductor 500, presenting an inductance of L3 in response to the dynamic current flowing through the NMOS FET 602. Additionally, some embodiments of the active inductor 600 are configured to convert the output current I generated by the transconductance amplifier 610 into an inductance of L3. tc_6 The amplitude is limited to a predetermined saturation value I. sat_6 To enable the transmission of differential data signal V via electrical bus 206 during large-signal transient events. T During this period, the effective inductance exhibited by the active inductor 600 is improved.

[0056] Figure 7 This is a schematic diagram of an active inductor 700, where the active inductor 700 is... Figure 2One possible embodiment of the active inductor 232. The active inductor 700 includes an NMOS FET 702 and control circuitry 704, wherein the NMOS FET 702 is an embodiment of the pass element 238, and the control circuitry 704 is an embodiment of the control circuitry 240. The NMOS FET 702 includes a drain (D), a source (S), a gate (G), and a parasitic body diode 706. The drain (D) of the NMOS FET 702 is electrically coupled to a second port 218 and a second electrical conductor 210, and the source (S) of the NMOS FET 702 is electrically coupled to a negative power rail 214. The control circuitry 704 includes a storage capacitor 708, a transconductance amplifier 710, resistors 712 and 714, and a reference voltage source 716. The storage capacitor 708 is electrically coupled between the gate (G) and source (S) of the NMOS FET 702. Resistors 712 and 714 are series-coupled between the drain (D) and source (S) of the NMOS FET 702. Reference voltage source 716 references the source (S) of the NMOS FET 702, and reference voltage source 714 generates a reference voltage V. ref_7 The transconductance amplifier 710 is configured to generate a voltage V corresponding to the input voltage V of the transconductance amplifier 710. in_7 Proportional output current It c_7 The input voltage V in_7 Equal to voltage V mid_7 and reference voltage V ref_7 The difference between them. Voltage V mid_7 It is the voltage at the midpoint of the voltage divider between resistors 712 and 714, therefore the voltage V is... mid_7 With voltage V drop_2 Related. Transconductance amplifier 710 via its output current It c_7 Drive each of the gate G of the NMOS FET 702 and the energy storage capacitor 708 to control the NMOS FET 702.

[0057] According to EQN.9 below, during the steady-state operation of the active inductor 700, the NMOS FET 702, under the control of the control circuit 704, will change the voltage V drop_2 The amplitude is adjusted to the predetermined value V. reg_2 , where R 712 It is the resistance of resistor 712 and R 714 It is the resistance of resistor 714. Therefore, in the design process of active inductor 700, the resistance can be changed by altering R. 712 R 714 and V ref_7 One or more of them are used to adjust the voltage V reg_2The amplitude. Furthermore, the control circuit 704 controls the NMOS FET 702, causing the active inductor 700 to respond to the voltage V across the NMOS FET 702. drop_2 The effective inductance of L2 is exhibited by the change in g. The inductance L2 presented by the active inductor 700 is given in EQN.10 below, where g m_ota7 It is the transconductance of the transconductance amplifier 710, g m_FET7 It is the transconductance of the NMOSFET 702, C 708 It is the capacitance of energy storage capacitor 708, and K7 is equal to R. 714 / (R 712 +R 714 The scaling factor of ). Furthermore, in a particular embodiment of the active inductor 700, the control circuit 704 is configured such that (i) the gain (K7 and g) of the transconductance amplifier 710 is increased. m_ota7 The product of (i) and (ii) the output current It is set to a relatively high value. c_7 The amplitude is limited to a predetermined saturation current value I. sat_7 For reasons similar to those discussed above regarding the active inductor 500, the saturation current value I... sat_7 It is defined according to EQN.11 below. For example, in some embodiments, the saturation current value I... sat_7 Less than V T / 2、g m_ota7 50% of the product of K7. As another example, in a specific embodiment, the saturation current value I... sat_7 Less than V T / 2、g m_ota7 10% of the product of K7. As another example, in some embodiments, the saturation current value I... sat_7 Less than V T / 2、g m_ota7 1% of the product of K7 and K7.

[0058]

[0059] The active inductor 262 of station 204 can be implemented in a manner similar to that of active inductor 700. For example, Figure 8This is a schematic diagram of an active inductor 800, which is a possible embodiment of the active inductor 262 at station 204. The active inductor 800 includes an NMOS FET 802 and a control circuit 804, which are similar to NMOS FET 702 and control circuit 704, respectively. NMOS FET 802 is an embodiment of the pass element 268, and control circuit 804 is an embodiment of control circuit 270. The drain (D) of NMOS FET 802 is electrically coupled to the negative power rail 244, and the source (S) of NMOS FET 802 is electrically coupled to the second port 248 and the second conductor 210. Control circuit 804 includes a storage capacitor 808, a transconductance amplifier 810, resistors 812 and 814, and a reference voltage source 816, which are similar to the storage capacitor 708, transconductance amplifier 710, resistors 712 and 714, and reference voltage source 716, respectively. Therefore, the active inductor 800 operates in a manner similar to that of the active inductor 700. For example, the active inductor 800 operates in a manner similar to that of the active inductor 700 to deliver voltage V during the steady-state operation of the active inductor 800. drop_4 The amplitude is adjusted to the predetermined value V. reg_4 Furthermore, the active inductor 800 operates in a manner similar to that of the active inductor 700, in response to the voltage V across the NMOS FET 802. drop_4 The inductance of L4 is altered by the change in current. Furthermore, some embodiments of the active inductor 800 are configured to convert the output current I generated by the transconductance amplifier 810. tc_8 The amplitude is limited to a predetermined saturation value I. sat_8 To enable the transmission of differential data signal V via electrical bus 206 during large-signal transient events. T During this period, the effective inductance exhibited by the active inductor 800 is improved.

[0060] Figure 9 This is a schematic diagram of an active inductor 900, where the active inductor 900 is... Figure 2Another possible embodiment of the active inductor 230. The active inductor 900 includes an enhancement-mode P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) 902 and control circuitry 904, wherein the PMOSFET 902 is an embodiment of the pass element 234, and the control circuitry 904 is an embodiment of the control circuitry 236. The PMOSFET 902 includes a drain (D), a source (S), a gate (G), and a parasitic body diode 906. The source (S) of the PMOSFET 902 is electrically coupled to a positive power rail 212, and the drain (D) of the PMOSFET 902 is electrically coupled to a first port 216 and a first electrical conductor 208. The control circuitry 904 includes a storage capacitor 908, a transconductance amplifier 910, resistors 912 and 914, and a reference voltage source 916. The storage capacitor 908 is electrically coupled between the gate (G) and source (S) of the PMOSFET 902. Reference voltage source 916 references the source S of PMOS FET 902, and reference voltage source 914 generates a reference voltage V. ref_9 Resistors 912 and 914 are series-coupled between the source (S) and drain (D) of the PMOS FET 902. Transconductance amplifier 910 is configured to generate an input voltage V0. in_9 Proportional output current It c_9 The input voltage V in_9 Equal to reference voltage V ref_9 and voltage V mid_9 The difference between them. Voltage V mid_9 It is the voltage at the midpoint of the voltage divider between resistors 912 and 914, therefore the voltage V is... mid_9 With voltage V drop_1 Related. Transconductance amplifier 910 via its output current It c_9 Each of the gate G of the PMOS FET 902 and the energy storage capacitor 908 is driven to control the PMOS FET 902.

[0061] According to EQN.12 below, during the steady-state operation of the active inductor 900, the PMOS FET 902, under the control of the control circuit 904, will change the voltage V drop_1 The amplitude is adjusted to the predetermined value V. reg_1 , where R 912 It is the resistance of resistor 912, and R 914 It is the resistance of resistor 914. Therefore, in the design process of active inductor 900, the resistance can be changed by altering R. 912 R 914 and V ref_9 One or more of them are used to adjust the voltage V reg_1The amplitude. Furthermore, the control circuit 904 controls the PMOS FET 902, causing the active inductor 900 to respond to the V across the PMOS FET 902. drop_1 The effective inductance of L1 is determined by the voltage change across its terminals. The inductance L1 presented by the active inductor 900 is given in EQN.13 below, where g m_ota9 It is the transconductance of the transconductance amplifier 910, g m_FET9 It is the transconductance of the PMOS FET 902, C 908 It is the capacitance of energy storage capacitor 908, and K9 is equal to R. 912 / (R 912 +R 914 The scaling factor of ). Furthermore, in a particular embodiment of the active inductor 900, the control circuit 904 is configured such that (i) the gain (K9 and g) of the transconductance amplifier 910 is increased. m_ota9 The product of (i) and (ii) the output current It is set to a relatively high value. c_9 The amplitude is limited to a predetermined saturation current value I. sat_9 For reasons similar to those discussed above regarding the active inductor 500, the saturation current value I... sat_9 It is defined according to EQN.14 below. For example, in some embodiments, the saturation current value I... sat_9 Less than V T / 2、g m_ota9 50% of the product of K9. As another example, in a specific embodiment, the saturation current value I... sat_9 Less than V T / 2、g m_ota9 10% of the product of K9. As another example, in some embodiments, the saturation current value I... sat_9 Less than V T / 2、g m_ota9 1% of the product of K9 and K9.

[0062]

[0063] The active inductor 260 of station 204 can be implemented in a manner similar to that of active inductor 900. For example, Figure 10This is a schematic diagram of an active inductor 1000, which is another possible embodiment of the active inductor 260 of station 204. The active inductor 1000 includes a PMOS FET 1002 and a control circuit 1004, which are respectively similar to a PMOS FET 902 and a control circuit 904. The PMOS FET 1002 includes a drain (D), a source (S), a gate (G), and a parasitic body diode 1006. The source (S) of the PMOS FET 1002 is electrically coupled to a first port 246 and a first electrical conductor 208, and the drain (D) of the PMOS FET 1002 is electrically coupled to a positive power rail 242. The control circuit 1004 includes a storage capacitor 1008, a transconductance amplifier 1010, resistors 1012 and 1014, and a reference voltage source 1016, which are respectively similar to the storage capacitor 908, the transconductance amplifier 910, the resistors 912 and 914, and the reference voltage source 916. Therefore, the active inductor 1000 operates in a manner similar to that of the active inductor 900. For example, the active inductor 1000 operates in a manner similar to that of the active inductor 900 to deliver voltage V during the steady-state operation of the active inductor 1000. drop_3 The amplitude is adjusted to the predetermined steady-state value V. reg_3 Furthermore, the active inductor 1000 operates in a manner similar to the active inductor 900, presenting an inductance of L3 in response to the dynamic current flowing through the PMOS FET 1002. Additionally, some embodiments of the active inductor 1000 are configured to convert the output current I generated by the transconductance amplifier 1010 into an inductance of L3. tc_10 The amplitude is limited to a predetermined saturation value I. sat_10 To enable the transmission of differential data signal V via electrical bus 206 during large-signal transient events. T During this period, the effective inductance exhibited by the active inductor 1000 is improved.

[0064] Figure 11 This is a schematic diagram of an active inductor 1100, where the active inductor 1100 is... Figure 2Another possible embodiment of the active inductor 232. The active inductor 1100 includes a PMOS FET 1102 and control circuitry 1104, wherein the PMOS FET 1102 is an embodiment of the pass element 238, and the control circuitry 1104 is an embodiment of the control circuitry 240. The PMOS FET 1102 includes a drain (D), a source (S), a gate (G), and a parasitic diode 1106. The drain (D) of the PMOS FET 1102 is electrically coupled to a negative power rail 214, and the source (S) of the PMOS FET 1102 is electrically coupled to a second port 218 and a second conductor 210. The control circuitry 1104 includes a storage capacitor 1108, a transconductance amplifier 1110, resistors 1112 and 1114, and a reference voltage source 1116. The storage capacitor 1108 is electrically coupled between the gate (G) and source (S) of the PMOS FET 1102. Resistors 1112 and 1114 are series-coupled between the source (S) and drain (D) of the PMOS FET 1102. Reference voltage source 1116 is referenced to the source (S) of the PMOS FET 1102, and generates a reference voltage V. ref_11 The transconductance amplifier 1110 is configured to generate a voltage V corresponding to the input voltage V of the transconductance amplifier 1110. in_11 Proportional output current It c_11 The input voltage V in_11 Equal to voltage V mid_11 and reference voltage V ref_11 The difference between them. Voltage V mid_11 It is the voltage at the midpoint of the voltage divider between resistors 1112 and 1114, therefore the voltage V is... mid_11 With voltage V drop_2 Related. Transconductance amplifier 1110 via the output current It of transconductance amplifier 1110 c_11 Drive each of the gate G of the PMOS FET 1102 and the energy storage capacitor 1108 to control the PMOS FET 1102.

[0065] According to EQN.15 below, during the steady-state operation of the active inductor 1100, the PMOS FET 1102, under the control of the control circuit 1104, directs the voltage V... drop_2 The amplitude is adjusted to the predetermined value V. reg_2 , where R 1112 It is the resistance of resistor 1112 and R 1114 It is the resistance of resistor 1114. Therefore, in the design process of active inductor 1100, the resistance can be changed by altering R. 1112 R 1114 and V ref_11 One or more of them are used to adjust the voltage V reg_2The amplitude. Furthermore, the control circuit 1104 controls the PMOS FET 1102, causing the active inductor 1100 to respond to the voltage V across the PMOS FET 1102. drop_2 The effective inductance of L2 is exhibited by the change in g. The inductance L2 presented by the active inductor 1100 is given in EQN.16 below, where g m_ota11 It is the transconductance of the transconductance amplifier 1110, g m_FET11 It is the transconductance of the PMOS FET 1102, C 1108 It is the capacitance of energy storage capacitor 1108, and K 11 It is equal to R 1112 / (R 1112 +R 1114 The scaling factor of ). Furthermore, in a particular embodiment of the active inductor 1100, the control circuit 1104 is configured such that (i) the gain (K) of the transconductance amplifier 1110 is increased. 11 and g m_ota11 The product of (i) and (ii) the output current It is set to a relatively high value. c_11 The amplitude is limited to a predetermined saturation current value I. sat_11 For reasons similar to those discussed above regarding the active inductor 500, the saturation current value I... sat_11 It is defined according to EQN.17 below. For example, in some embodiments, the saturation current value I... sat_11 Less than V T / 2、g m_ota11 and K 11 50% of the product. As another example, in a specific embodiment, the saturation current value I... sat_11 Less than V T / 2、g m_ota11 and K 11 10% of the product. As another example, in some embodiments, the saturation current value I... sat_11 Less than V T / 2、g m_ota11 and K 11 1% of the product.

[0066]

[0067] The active inductor 262 of station 204 can be implemented in a manner similar to that of active inductor 1100. For example, Figure 12This is a schematic diagram of an active inductor 1200, which is another possible embodiment of the active inductor 262 at station 204. The active inductor 1200 includes a PMOS FET 1202 and a control circuit 1204, which are similar to PMOS FET 1102 and control circuit 1104, respectively. PMOS FET 1202 is an embodiment of the pass element 268, and control circuit 1204 is an embodiment of control circuit 270. PMOS FET 1202 includes a drain (D), a source (S), a gate (G), and a parasitic body diode 1206. The drain (D) of PMOS FET 1202 is electrically coupled to a second port 248 and a second conductor 210, and the source (S) of PMOS FET 1202 is electrically coupled to a negative power rail 244. The control circuit 1204 includes an energy storage capacitor 1208, a transconductance amplifier 1210, resistors 1212 and 1214, and a reference voltage source 1216, which are respectively similar to the energy storage capacitor 1108, the transconductance amplifier 1110, the resistors 1112 and 1114, and the reference voltage source 1116. Therefore, the active inductor 1200 operates in a manner similar to that of the active inductor 1100. For example, the active inductor 1200 operates in a manner similar to that of the active inductor 1100 to deliver voltage V during the steady-state operation of the active inductor 1200. drop_4 The amplitude is adjusted to the predetermined value V. reg_4 Furthermore, the active inductor 1200 operates in a manner similar to that of the active inductor 1100 in response to the voltage V across the PMOS FET 1202. drop_4 The inductance of L4 is altered by the change in current. Furthermore, some embodiments of the active inductor 1200 are configured to convert the output current I generated by the transconductance amplifier 1210. tc_12 The amplitude is limited to a predetermined saturation value I. sat_12 To enable the transmission of differential data signal V via electrical bus 206 during large-signal transient events. T During this period, the effective inductance exhibited by the active inductor 1200 is improved.

[0068] Refer again Figure 2 Two or more of the path elements 234, 238, 264, and 268 can be implemented using transistors of different types. For example, in some embodiments, path element 234 is implemented using a PMOSFET, as described above. Figure 9 As mentioned above, the path element 238 is implemented by an NMOS FET, as described above. Figure 7 As another example, in some embodiments, the path element 234 is implemented by an NMOS FET, as described above. Figure 5 As mentioned above, the path element 238 is implemented by a PMOS FET, as described above. Figure 11As stated above.

[0069] DoP system 200 can be modified to include one or more additional stations, such as one or more additional instances of station 202 and / or one or more additional instances of station 204. Furthermore, station 202 can be modified to include features that facilitate the electrical coupling of multiple instances of station 202 to electrical bus 206. For example, Figure 13 This is a schematic diagram of station 1300, an alternative embodiment of station 202, which also includes a current control device (CCD) 1302 electrically coupling a path element 234 and control circuitry 236 to a first port 216. The current control device 1302 is configured to limit current flowing through it in a single direction, i.e., from the path element 234 to the first port 216. In some embodiments, the current control device 1302 includes a diode or active electronic circuitry configured to simulate a diode. For example, the current control device 1302 is used to enable multiple instances of station 1300 to be electrically coupled in parallel to electrical bus 206.

[0070] Figure 14 This is a schematic diagram of DoP system 200, which is an alternative to a DoP system comprising two instances of station 1300 replacing station 202 and two instances of station 204. In this document, specific instances of a project (e.g., station 1300(1)) may be referred to by numbers in parentheses, while numbers without parentheses refer to any such project (e.g., station 1300). Stations 1300(1) and 1300(2) are electrically coupled in parallel to electrical bus 206, and stations 204(1) and 204(2) are electrically coupled to electrical bus 206. For clarity, Figure 14 Details of station 1300 and station 204 are not shown. Regardless of which station 1300 has the highest voltage at its respective first port 216 and second port 218, it will supply power to the corresponding load of station 204 via electrical bus 206. Stations 1300(1) and 1300(2) share electrical bus 206 for transmitting and / or receiving corresponding data signals, for example using time-division multiplexing and / or frequency-division multiplexing techniques. Similarly, stations 204(1) and 204(2) share electrical bus 206 for transmitting and / or receiving corresponding data signals, for example using time-division multiplexing and / or frequency-division multiplexing techniques.

[0071] In some applications, it is possible for two or more instances of station 1300 to be electrically coupled in parallel to electrical bus 206 with conflicting polarities, such that a first port 216 of one instance of station 1300 is connected to a second port 218 in another instance of station 1300. For example, a user may inadvertently connect two or more stations in parallel with conflicting polarities, or may not specify the polarities of the first conductor 208 and the second conductor 210. Such polarity conflict can damage one or more instances of station 1300 and / or electrical bus 206. Therefore, some alternative embodiments of station 1300 also include protection circuitry configured to shut down the station in the event of a polarity conflict with another station instance. For example, Figure 15 This is a diagram of station 1500, and this station is station 1300. Figure 13 Another embodiment of the circuit also includes a protection circuit 1502. The protection circuit 1502 is configured to monitor the voltage V between the first port 216 and the second port 218. port Furthermore, the protection circuit 1502 is configured to respond to voltage V port An abnormal value is detected, for example, due to another station being connected to station 1500 with conflicting polarity, signal sd is issued to shut down power supply 222. Voltage V port Outliers include, for example, voltages V with amplitudes below a threshold. port Value and / or voltage V port The value is negative. The protection circuit 1502 may be replaced or supplemented by a current protection circuit (not shown) and / or a thermal protection circuit (not shown), wherein (i) the current protection circuit is configured to assert signal sd in response to an overcurrent condition, such as due to another station being connected to station 1500 with conflicting polarities, and (i) the thermal protection circuit is configured to assert information sd in response to an overheat condition, such as due to another station being connected to station 1500 with conflicting polarities.

[0072] Refer again Figure 2 Station 202 is electrically coupled to electrical bus 206, causing the voltage V on the first electrical conductor 208 to... b_1 Greater than the voltage V across the second conductor 210 b_2 However, in some alternative embodiments of the DoP system 200, there is a voltage V across the first electrical conductor. b_1 It may be less than the voltage V across the second conductor 210. b_2 The possibility exists, for example, if the connection between station 202 and electrical bus 206 is swapped. Therefore, some alternative embodiments of station 204 also include a rectifier circuit to enable station 204 to operate independently of the voltage polarity between the first conductor 208 and the second conductor 210.

[0073] For example, Figure 16This is a schematic diagram of station 1600, an alternative embodiment of station 204, which also includes a bridge rectifier 1602. The bridge rectifier 1602 includes a first diode 1604, a second diode 1606, a third diode 1608, and a fourth diode 1610. The first diode 1604 is electrically coupled between a first port 246 and a pass element 264, allowing current to flow from the first port 246 to the pass element 264. The second diode 1606 is electrically coupled between the pass element 268 and the first port 246, allowing current to flow from the pass element 268 to the first port 246. The third diode 1608 is electrically coupled between the second port 248 and the pass element 264, allowing current to flow from the second port 248 to the pass element 264. The fourth diode 1610 is electrically coupled between the pass element 268 and the second port 248, enabling current to flow from the pass element 268 to the second port 248. Therefore, the path element 264 and the control circuit 266 are electrically coupled to each of the first port 246 and the second port 248 via the bridge rectifier 1602, and the path element 268 and the control circuit 270 are electrically coupled to each of the second ports 246 and 248 via the bridge rectifier 1602. Thus, the bridge rectifier 1602 enables the station 1600 to operate regardless of the voltage polarity between the first conductor 208 and the second conductor 210.

[0074] Refer again Figure 2 The DoP system 100 can be further modified as long as the DoP system 200 includes embodiments of the novel active inductor assembly disclosed herein. For example, transceiver 224 and transceiver 254 can be modified to transmit and / or receive single-ended data signals instead of differential data signals. As another example, station 202 and / or station 204 can be modified to include one or more additional elements, such as providing additional functionality to station 202 and / or station 204.

[0075] Feature combinations

[0076] Without departing from the scope of this article, the above features can be combined in various ways. The following examples illustrate some possible combinations.

[0077] (A1) An active inductor assembly for a power-on-data (DoP) system, comprising a first active inductor and a second active inductor. The first active inductor includes: (1) a first path element configured to be electrically coupled between a positive power rail of the DoP system and a first electrical conductor of the DoP system; and (2) a first control circuit configured to control the first path element such that (i) the first path element simulates a first inductor in response to a voltage change across the first path element; and (ii) during steady-state operation of the first active inductor, the first path element regulates the voltage drop across the first path element to a first predetermined value. The second active inductor includes: (1) a second path element configured to be electrically coupled between the negative power rail of the DoP system and a second electrical conductor of the DoP system; and (2) a second control circuit configured to control the second path element such that (i) the second path element simulates a second inductor in response to a voltage change across the second path element; and (ii) during steady-state operation of the second active inductor, the second path element regulates the voltage drop across the second path unit to a second predetermined value.

[0078] (A2) In the active inductor assembly denoted as (A1), (1) the first pass element may include a first transistor, and (2) the second pass element may include a second transistor.

[0079] (A3) In the active inductor assembly denoted as (A1), (1) the first path element may include a first enhancement field-effect transistor (first FET); (2) the first control circuit may be configured to control the first path element at least partially by driving the gate of the first FET; (3) the second path element may include a second enhancement field-effect transistor (second FET); and (4) the second control circuit may be configured to control the second path element at least partially by driving the gate of the second FET.

[0080] (A4) In the active inductor assembly denoted as (A3), (1) the first control circuitry may include: (a) a first energy storage capacitor electrically coupled to the gate of the first FET, and (b) a first transconductance amplifier configured to drive (i) the gate of the first FET and (ii) each of the first energy storage capacitors via the output current of the first transconductance amplifier; and (2) the second control circuitry may include: (a) a second energy storage capacitor electrically coupled to the gate of the second FET, and (b) a second transconductance amplifier configured to drive (i) the gate of the second FET and (ii) each of the second energy storage capacitors via the output current of the second transconductance amplifier circuitry.

[0081] (A5) In the active inductor assembly denoted as (A4), (1) the first transconductance amplifier is configured such that the amplitude of the output current of the first transconductance amplifier is limited to a first predetermined saturation current value, such that the effective inductance of the first active inductor is greater than the effective inductance when the DoP system is transmitting a data signal; and (2) the second transconductance amplifier is configured such that the amplitude of the output current of the second transconductance amplifier is limited to a second predetermined saturation current value, such that the effective inductance of the second active inductor is greater than the effective inductance when the DoP system is transmitting a data signal.

[0082] (A6) In any of the active inductor assemblies denoted as (A4) and (A5), (1) the first transconductance amplifier may be configured to generate an output current of the first transconductance amplifier in response to the difference between (i) a first reference voltage value and (ii) a voltage related to the voltage drop across the first path element; and (2) the second transconductance amplifier may be configured to generate an output current of the second transconductance amplifier in response to the difference between (i) a second reference voltage value and (ii) a voltage related to the voltage drop across the second path element.

[0083] (B1) A station for a power-to-data (DoP) system, comprising: (1) a positive power rail; (2) a negative power rail; (3) a first port configured to electrically couple the station to a first electrical conductor of the DoP system; (4) a second port configured to electrically couple the station to a second electrical conductor of the DoP system; (5) a first active inductor; and (6) a second active inductor. The first active inductor comprises: (1) a first path element electrically coupled between the positive power rail and the first port; and (2) a first control circuit configured to control the first path element such that: (i) the first path element simulates a first inductor in response to a voltage change across the first path element; and (ii) during steady-state operation of the first active inductor, the first path element regulates the voltage drop across the first path element to a first predetermined value. The second active inductor includes: (1) a second path element electrically coupled between the negative power rail and the second port; and (2) a second control circuit configured to control the second path element such that (i) the second path element simulates a second inductor in response to a voltage change across the second path element; and (ii) during steady-state operation of the second active inductor, the second path element regulates the voltage drop across the second path unit to a second predetermined value.

[0084] (B2) The station denoted as (B1) may also include a power source electrically coupled between the positive power rail and the negative power rail.

[0085] (B3) can also include a load electrically coupled between the positive and negative power rails, either of which is represented by (B1) or (B2).

[0086] (B4) Any of the stations denoted as (B1) to (B3) may further include: (1) a transceiver; (2) a first data coupling capacitor configured to electrically couple a first component of a data signal between the transceiver and the first port; and (3) a second data coupling capacitor configured to electrically couple a second component of a data signal between the transceiver and the second port.

[0087] (B5) In any of the stations denoted as (B1) to (B4), (1) the first access element may include a first enhancement field-effect transistor (first FET); (2) the first control circuit may be configured to control the first access element at least partially by driving the gate of the first FET; (3) the second access element may include a second enhancement field-effect transistor (second FET); and (4) the second control circuit may be configured to control the second access element at least partially by driving the gate of the second FET.

[0088] (B6) In the station denoted as (B5), (1) the first control circuit may include: (a) a first energy storage capacitor electrically coupled to the gate of the first FET, and (b) a first transconductance amplifier configured to drive (i) the gate of the first FET and (ii) each of the first energy storage capacitors via the output current of the first transconductance amplifier; and (2) the second control circuit may include: (a) a second energy storage capacitor electrically coupled to the gate of the second FET, and (b) a second transconductance amplifier configured to drive (i) the gate of the second FET and (ii) each of the second energy storage capacitors via the output current of the second transconductance amplifier circuit.

[0089] (B7) In the station denoted as (B6), (1) the first transconductance amplifier is configured such that the amplitude of the output current of the first transconductance amplifier is limited to a first saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the first active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal; and (2) the second transconductance amplifier is configured such that the amplitude of the output current of the second transconductance amplifier is limited to a second saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the second active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal.

[0090] (B8) In any of the stations denoted as (B6) to (B7), (1) the first transconductance amplifier may be configured to generate an output current of the first transconductance amplifier in response to the difference between (i) a first reference voltage value and (ii) a voltage related to the voltage drop across the first path element; and (2) the second transconductance amplifier may be configured to generate an output current of the second transconductance amplifier in response to the difference between (i) a second reference voltage value and (ii) a voltage related to the voltage drop across the second path element.

[0091] (B9) In any of the stations denoted as (B1) to (B8), the first path element may be electrically coupled to the first port via a current control device configured to limit the current passing through it to a single direction.

[0092] (B10) Any of the stations represented by (B1) to (B9) may further include a bridge rectifier, wherein: (1) the first path element is electrically coupled to each of the first port and the second port via the bridge rectifier; and (2) the second path element is electrically coupled to each of the first port and the second port via the bridge rectifier.

[0093] (C1) A method for an inductor in a station of an electronic analog power-on-data (DoP) system, the method comprising: (1) controlling a first transistor of a first active inductor to (i) regulate a voltage drop across the first transistor to a first predetermined value during steady-state operation of the first active inductor, and (ii) simulating an inductor in response to a change in voltage across the first transistor, the first transistor being electrically coupled between a positive power rail of the station and a first electrical conductor of the DoP system; and (2) controlling a second transistor of a second active inductor to (i) regulate a voltage drop across the second transistor to a second predetermined value during steady-state operation of the second active inductor, and (ii) simulating an inductor in response to a change in voltage across the second transistor, the second transistor being electrically coupled between a negative power rail of the station and a second electrical conductor of the DoP system.

[0094] (C2) In the method denoted as (C1), (1) the first transistor may include a first field-effect transistor (first FET); (2) the second transistor may include a second field-effect transistor (second FET); (3) controlling the first transistor may include driving (i) the gate of the first FET and (ii) each of the first energy storage capacitors via the output current of the first transconductance amplifier; and (4) controlling the second transistor may include driving (i) the gate of the second FET and (ii) each of the second energy storage capacitors via the output current of the second transconductance amplifier.

[0095] (C3) The method represented by (C2) may further include: (1) limiting the amplitude of the output current of the first transconductance amplifier to a first predetermined saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the first active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal; and (2) limiting the amplitude of the output current of the second transconductance amplifier to a second predetermined saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the second active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal.

[0096] (C4) In any of the methods represented as (C1) to (C3), (1) the first transistor can be electrically coupled to a first electrical conductor of the DoP system via one or more first diodes; and (2) the second transistor can be electrically coupled to a second electrical conductor of the DoP system via one or more second diodes.

[0097] Modifications to the methods, apparatus, and systems described herein may be made without departing from the scope of this document. Therefore, it should be noted that the descriptions and figures above are to be interpreted illustratively and not restrictively. The following claims are intended to cover the general and specific features described herein, as well as all statements relating to the scope of the methods and systems, which, in linguistic terms, may be said to fall between the two.

Claims

1. An active inductor assembly for a power-to-data (DoP) system, the active inductor assembly comprising: A first active inductor, comprising: The first path element is configured to be electrically coupled between the positive power rail of the DoP system and the first electrical conductor of the DoP system. A first control circuit is configured to control the first path element such that: The first path element responds to voltage changes across its terminals to simulate a first inductor, and During the steady-state operation of the first active inductor, the first path element regulates the voltage drop across the first path element to a first predetermined value; and The second active inductor includes: The second path element is configured to be electrically coupled between the negative power rail of the DoP system and the second electrical conductor of the DoP system. The second control circuit is configured to control the second path element such that: The second path element responds to voltage changes across the second path element to simulate a second inductor, and During steady-state operation of the second active inductor, the second path element regulates the voltage drop across the second path unit to a second predetermined value.

2. The active inductor assembly according to claim 1, wherein: The first path element includes a first transistor; and The second path element includes a second transistor.

3. The active inductor assembly according to claim 1, wherein: The first path element includes a first enhancement-mode field-effect transistor (first FET); The first control circuit is configured to control the first path element at least in part by driving the gate of the first FET; The second path element includes a second enhancement-mode field-effect transistor (second FET); and The second control circuit is configured to control the second path element at least in part by driving the gate of the second FET.

4. The active inductor assembly according to claim 3, wherein: The first control circuit includes: The first energy storage capacitor is electrically coupled to the gate of the first FET, and A first transconductance amplifier is configured to drive (i) the gate of the first FET and (ii) each of the first energy storage capacitors via the output current of the first transconductance amplifier; and The second control circuit includes: The second energy storage capacitor is electrically coupled to the gate of the second FET, and The second transconductance amplifier is configured to drive (i) the gate of the second FET and (ii) each of the second energy storage capacitor via the output current of the second transconductance amplifier circuit.

5. The active inductor assembly according to claim 4, wherein: The first transconductance amplifier is configured such that the amplitude of the output current of the first transconductance amplifier is limited to a first predetermined saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the first active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal; and The second transconductance amplifier is configured such that the amplitude of the output current of the second transconductance amplifier is limited to a second predetermined saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the second active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal.

6. The active inductor assembly according to claim 4, wherein: The first transconductance amplifier is configured to generate an output current in response to the difference between (i) a first reference voltage value and (ii) a voltage related to the voltage drop across the first path element; and The second transconductance amplifier is configured to generate an output current in response to (i) a second reference voltage value and (ii) the difference between a voltage related to the voltage drop across the second path element.

7. A station for a power-on-data (DoP) system, the station comprising: Positive power rail; Negative power rail; The first port is configured to couple the station power to the first electrical conductor of the DoP system; The second port is configured as a second electrical conductor to couple the station power to the DoP system; A first active inductor, comprising: The first path element is electrically coupled between the positive power rail and the first port, and A first control circuit is configured to control the first path element such that: The first path element responds to voltage changes across its terminals to simulate a first inductor, and During the steady-state operation of the first active inductor, the first path element regulates the voltage drop across the first path element to a first predetermined value; and The second active inductor includes: The second path element is electrically coupled between the negative power rail and the second port. The second control circuit is configured to control the second path element such that: The second path element responds to voltage changes across the second path element to simulate a second inductor, and During steady-state operation of the second active inductor, the second path element regulates the voltage drop across the second path unit to a second predetermined value.

8. The station according to claim 7 further includes a power source electrically coupled between the positive power rail and the negative power rail.

9. The station according to claim 7 further includes a load electrically coupled between the positive power rail and the negative power rail.

10. The station according to claim 7, further comprising: transceiver; A first data coupling capacitor is configured to electrically couple a first component of a data signal between the transceiver and the first port; and The second data coupling capacitor is configured to electrically couple a second component of the data signal between the transceiver and the second port.

11. The station according to claim 7, wherein: The first path element includes a first enhancement-mode field-effect transistor (first FET); The first control circuit is configured to control the first path element at least in part by driving the gate of the first FET; The second path element includes a second enhancement-mode field-effect transistor (second FET); and The second control circuit is configured to control the second path element at least in part by driving the gate of the second FET.

12. The station according to claim 11, wherein: The first control circuit includes: The first energy storage capacitor is electrically coupled to the gate of the first FET, and A first transconductance amplifier is configured to drive (i) the gate of the first FET and (ii) each of the first energy storage capacitors via the output current of the first transconductance amplifier; and The second control circuit includes: The second energy storage capacitor is electrically coupled to the gate of the second FET, and The second transconductance amplifier is configured to drive (i) the gate of the second FET and (ii) each of the second energy storage capacitor via the output current of the second transconductance amplifier circuit.

13. The station according to claim 12, wherein: The first transconductance amplifier is configured such that the amplitude of its output current is limited to a first saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the first active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal; and The second transconductance amplifier is configured such that the amplitude of the output current of the second transconductance amplifier is limited to a second saturation current value, such that when the DoP system is transmitting a data signal, the effective inductance of the second active inductor is greater than the effective inductance when the DoP system is not transmitting a data signal.

14. The station according to claim 12, wherein: The first transconductance amplifier is configured to generate an output current in response to the difference between (i) a first reference voltage value and (ii) a voltage related to the voltage drop across the first path element; and The second transconductance amplifier is configured to generate an output current in response to (i) a second reference voltage value and (ii) the difference between a voltage related to the voltage drop across the second path element.

15. The station of claim 7, wherein the first path element is electrically coupled to the first port via a current control device configured to restrict the current passing through it to a single direction.

16. The station according to claim 7, further comprising a bridge rectifier, wherein: The first path element is electrically coupled to each of the first port and the second port via the bridge rectifier; and The second path element is electrically coupled to each of the first port and the second port via the bridge rectifier.

17. A method for using an inductor in a station of an electronic analog power-to-data (DoP) system, the method comprising: A first transistor of a first active inductor is controlled to (i) adjust the voltage drop across the first transistor to a first predetermined value during steady-state operation of the first active inductor, and (ii) simulate an inductor in response to changes in the voltage across the first transistor, the first transistor being electrically coupled between the positive power rail of the station and a first electrical conductor of the DoP system. and A second transistor controlling a second active inductor to (i) regulate the voltage drop across the second transistor to a second predetermined value during steady-state operation of the second active inductor, and (ii) simulate an inductor in response to voltage changes on the second transistor, the second transistor being electrically coupled between the negative power rail of the station and a second electrical conductor of the DoP system.

18. The method of claim 17, wherein: The first transistor includes a first field-effect transistor (first FET); The second transistor includes a second field-effect transistor (second FET); Controlling the first transistor includes driving (i) the gate of the first FET and (ii) each of the first energy storage capacitors via the output current of the first transconductance amplifier; and Controlling the second transistor includes driving (i) the gate of the second FET and (ii) each of the second energy storage capacitor via the output current of the second transconductance amplifier.

19. The method of claim 18, further comprising: The amplitude of the output current of the first transconductance amplifier is limited to a first predetermined saturation current value, such that when the DoP system is transmitting data signals, the effective inductance of the first active inductor is greater than the effective inductance when the DoP system is not transmitting data signals; and The amplitude of the output current of the second transconductance amplifier is limited to a second predetermined saturation current value, such that when the DoP system is transmitting data signals, the effective inductance of the second active inductor is greater than the effective inductance when the DoP system is not transmitting data signals.

20. The method of claim 17, wherein: The first transistor is electrically coupled to a first electrical conductor of the DoP system via one or more first diodes; and The second transistor is electrically coupled to a second electrical conductor of the DoP system via one or more second diodes.

Images