PTP high-precision safe time synchronization method and device based on link layer

Abstract

The invention relates to the technical field of high-precision security time synchronization, and particularly discloses a PTP high-precision security time synchronization method and device based on a link layer, and the method comprises the following steps: a time synchronization service application issues configuration information to an FPGA; the FPGA obtains an external time reference from the time reference module and generates a local time reference; the FPGA analyzes the PTP data packet on a link layer, and performs compliance verification on the PTP data packet based on the configuration information; for the PTP data packet passing the compliance verification, the FPGA directly receives and transmits the PTP data packet on a link layer; recording a high-precision timestamp based on a local time reference when the data packet arrives at or is sent out of a network port; the FPGA calculates transmission delay and time difference by using the first timestamp, the second timestamp, the third timestamp and the fourth timestamp; and the FPGA transmits the calculated transmission delay and time difference to a back-end application through direct memory access. According to the invention, a high-precision, high-controllability, safe and reliable time synchronization effect can be realized.

Description

Technical Field

[0001] This invention relates to the field of high-precision and secure time synchronization technology, specifically to a PTP high-precision and secure time synchronization method and apparatus based on the link layer. Background Technology

[0002] Traditional PTP (Precision Time Protocol, IEEE 1588) time synchronization schemes typically rely on the operating system kernel software layer or PHY chip to process timestamps, which has the following core problems: 1. Limited accuracy: Software implementation is affected by factors such as CPU clock speed, interrupt latency, and task scheduling, and the accuracy can only reach the millisecond level (ms). 2. Network jitter interference: In multi-hop networks such as power systems and telecommunications networks, sudden traffic or differences in switch performance can cause transmission delay fluctuations, and the accuracy of traditional PTP may be reduced to the level of hundreds of nanoseconds to microseconds; 3. Insufficient compliance verification: The IP address, port, and protocol fields of data packets are not strictly verified, which poses a risk of being attacked by unauthorized devices that forge time sources; 4. Uncontrollable intermediate layer processing: Data packets need to be processed through the UDP / TCP transport layer and the PTP service application layer, introducing unpredictable delays. Summary of the Invention

[0003] The purpose of this invention is to provide a PTP high-precision and secure time synchronization method and apparatus based on the link layer, thereby solving the above-mentioned technical problems.

[0004] The objective of this invention can be achieved through the following technical solutions: The PTP high-precision secure time synchronization method based on the link layer includes the following steps: The time synchronization service application sends configuration information to the FPGA, which includes IP address range, port number and protocol compliance rules; The FPGA obtains an external time base from the time base module and generates a local time base. The FPGA parses PTP packets at the link layer and performs compliance verification on the PTP packets based on the configuration information. The compliance verification includes verification based on the IP address range, port number, and protocol compliance rules. For PTP data packets that pass the compliance verification, the FPGA directly sends and receives the PTP data packets at the link layer, and records a high-precision timestamp based on the local time reference when the data packet arrives at or is sent from the network interface. The high-precision timestamp includes a first timestamp when the master clock sends a Sync message, a second timestamp when the slave clock receives a Sync message, a third timestamp when the slave clock sends a Delay_Req message, and a fourth timestamp when the master clock receives a Delay_Req message. The FPGA uses the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to calculate the transmission delay and time difference; The FPGA transmits the calculated transmission delay and time difference to the backend application via direct memory access.

[0005] As a further aspect of the present invention, the configuration information also includes time reference module parameters, which are used to configure the priority and calibration period of the external time reference.

[0006] As a further aspect of the present invention: the time reference module includes at least one of a Beidou satellite receiver, a GPS receiver, and an atomic clock, and the FPGA interfaces with the time reference module through a hardware clock synchronization interface.

[0007] As a further aspect of the present invention: the compliance verification includes verifying whether the IP address of the PTP data packet is within the range of the IP address, verifying whether the port number of the PTP data packet is consistent with the port number, and verifying whether the protocol field of the PTP data packet conforms to the protocol compliance rules, the protocol compliance rules including the version number, message type and domain number of the PTP data packet.

[0008] As a further aspect of the present invention: the recording of high-precision timestamps is performed by a clock-driven counter inside the FPGA, the clock-driven counter being tamed by the local time base.

[0009] As a further aspect of the present invention: calculating the transmission delay includes: calculating the difference A between the fourth timestamp and the first timestamp, subtracting the difference between the third timestamp and the second timestamp from the difference A to obtain the difference B, and B / 2 being the transmission delay; The calculation of the time difference includes: calculating the difference C between the second timestamp and the first timestamp, adding the difference C to the difference between the fourth timestamp and the third timestamp to obtain the target value D, and then D / 2 is the time difference.

[0010] As a further aspect of the present invention, the FPGA is also used to perform hardware-level encryption and authentication of PTP data packets.

[0011] As a further aspect of the present invention: the time reference module supports multiple external time reference inputs, and the FPGA adaptively selects the optimal external time reference based on signal strength and stability parameters.

[0012] PTP high-precision and secure time synchronization device based on the link layer includes: The distribution module: The time synchronization service application distributes configuration information to the FPGA, including IP address range, port number, and protocol compliance rules; The FPGA obtains an external time base from the time base module and generates a local time base. Verification module: The FPGA parses PTP packets at the link layer and performs compliance verification on the PTP packets based on the configuration information. The compliance verification includes verification based on the IP address range, port number, and protocol compliance rules. Recording module: For PTP data packets that pass the compliance verification, the FPGA directly sends and receives the PTP data packets at the link layer, and records a high-precision timestamp based on the local time reference when the data packet arrives at or is sent from the network interface. The high-precision timestamp includes a first timestamp when the master clock sends a Sync message, a second timestamp when the slave clock receives a Sync message, a third timestamp when the slave clock sends a Delay_Req message, and a fourth timestamp when the master clock receives a Delay_Req message. Synthesis Module: The FPGA uses the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to calculate the transmission delay and time difference; The FPGA transmits the calculated transmission delay and time difference to the backend application via direct memory access.

[0013] The beneficial effects of this invention compared to the prior art are as follows: This invention achieves controllable and stable latency during time synchronization by directly parsing and processing PTP data packets at the link layer, significantly improving time synchronization accuracy. By recording and calculating multiple timestamps within the FPGA, it enables precise calculation of the time difference and transmission delay between master and slave clocks, ensuring accurate time synchronization. Compliance verification of the IP address, port number, and protocol fields of the data packets ensures data legality and security during time synchronization. Configuring external time base parameters and generating a local time base enables effective calibration and adaptive synchronization of the system to external time sources, guaranteeing the stability and reliability of the time synchronization system. Hardware-level encryption and authentication of PTP data packets within the FPGA enhances the security of synchronous communication. Direct memory access transmits calculation results to the backend application, achieving efficient data processing and optimized utilization of system resources. In summary, this invention achieves high-precision, highly controllable, and secure time synchronization. Attached Figure Description

[0014] The invention will now be further described with reference to the accompanying drawings.

[0015] Figure 1 This is a flowchart illustrating the PTP high-precision and secure time synchronization method based on the link layer of this invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Please see Figure 1 As shown, this invention is a PTP high-precision and secure time synchronization method based on the link layer, comprising the following steps: The time synchronization service application sends configuration information to the FPGA, which includes IP address range, port number and protocol compliance rules; Specifically, after loading the configuration interface during system initialization, the time synchronization service application generates a configuration information file based on parameters set by the management terminal or upper-layer application. This file contains IP address ranges to limit the scope of legal communication, port numbers to identify PTP protocol communication ports, and protocol compliance rules to constrain message structure. The configuration information is encapsulated into data frames via the Ethernet bus in the form of control messages and sent to the FPGA module through the driver layer calling the underlying communication interface. The FPGA parses and caches the configuration information at the receiving port and writes the content to its internal register set for subsequent message verification and time synchronization logic execution. The IP address range field limits the address ranges of the master and slave clock devices participating in time synchronization; the port number field indicates the communication channel between event messages and ordinary messages; and the protocol compliance rule field defines protocol standard elements such as the version number, message type, and domain number of the PTP data packet, enabling the FPGA to match and determine the legality of received data packets at the link layer.

[0018] In a preferred embodiment of the present invention, the configuration information further includes time reference module parameters, which are used to configure the priority and calibration period of the external time reference.

[0019] Specifically, the configuration information also includes time reference module parameters. These parameters are used to configure the priority and calibration period of the external time reference on the FPGA side. The time reference module parameters are set by the time synchronization service application according to the system deployment requirements, including the type identifier of the external time source and its priority order identifier under multi-source conditions. After these parameters are sent to the FPGA, the FPGA determines the acquisition order of the external time reference signal in its internal control logic based on these settings, and performs time synchronization updates according to the set calibration period, thereby ensuring that the local time reference generated by the FPGA is always consistent with the external time reference.

[0020] For example, the BeiDou satellite signal is set as the primary time reference, the GPS signal as the secondary reference source, and the atomic clock signal as the backup reference. When the time synchronization service application generates configuration information, it writes this priority relationship and the calibration cycle parameters of each reference source into the configuration data packet and sends it to the FPGA via the Ethernet interface. After receiving the parameters, the FPGA stores the identifiers and corresponding priorities of different external time references in its internal configuration register. During operation, it selects the currently used external time reference according to the set priority. When the primary time source signal is detected to be unavailable, it automatically switches to the next-level time reference to maintain the continuity of time synchronization. At the same time, based on the received calibration cycle parameters, the FPGA sends calibration requests to the external time reference module or performs synchronization correction operations at predetermined time intervals to ensure that the local time reference remains consistent with the external reference.

[0021] The FPGA obtains an external time base from the time base module and generates a local time base. In another preferred embodiment of the present invention, the time reference module includes at least one of a BeiDou satellite receiver, a GPS receiver, and an atomic clock, and the FPGA interfaces with the time reference module through a hardware clock synchronization interface.

[0022] It should be noted that the FPGA receives a standard time signal provided externally through a hardware synchronization interface established with the time reference module, and uses this signal as a reference to generate its own local time reference. The time reference module can include devices such as a BeiDou satellite receiver, a GPS receiver, or an atomic clock. These devices output standardized time reference signals to the FPGA, such as pulse-per-second signals and time message signals. The FPGA has a dedicated clock synchronization circuit and counting module. Upon receiving the external time signal, it compares and adjusts the signal with the clock frequency of the internal oscillator through a phase-locked loop and frequency calibration logic, ensuring that the internal counter is strictly consistent with the external time. After synchronization processing, the counting result generated internally by the FPGA constitutes the local time reference.

[0023] Optionally, the time reference module simultaneously inputs reference signals from multiple external time sources into the FPGA. For example, each signal carries a 1PPS pulse and time data. The FPGA internally contains a signal evaluation logic unit that continuously monitors the signal strength and stability parameters of each external signal. Signal strength reflects signal reception quality, such as the signal-to-noise ratio or lock status of satellite signals; stability parameters reflect the temporal continuity of the signal, such as the magnitude of pulse period jitter, time drift trend, or loss of pulses. Based on these real-time acquired characteristic data, the FPGA compares them with preset evaluation criteria, scoring or ranking each time source within the logic judgment module. One feasible evaluation criterion is to perform a weighted summation of the signal strength and stability parameters, selecting the optimal external time reference based on the summation score.

[0024] It is important to note that during time synchronization, while the FPGA is parsing and sending / receiving PTP data packets, its internal security processing unit performs hardware-level encryption and authentication of the packet content. This security processing unit performs encryption operations on the PTP data packets at the link layer and generates a message signature to ensure the integrity and tamper-proof nature of the message during transmission. When the FPGA receives a PTP data packet, it calls the encryption verification logic to read the signature information carried in the message and matches it with the locally stored encryption key or certificate. If the verification result matches, the message is deemed to have a legitimate source and that the data has not been tampered with, thus allowing it to proceed to the subsequent time synchronization calculation process. If the verification fails, the FPGA immediately discards the message and records the abnormal state to prevent unauthorized devices from forging the master clock signal or tampering with synchronization information. This mechanism ensures dual security protection at the data layer and identity layer during the PTP time synchronization process, making the synchronization communication between the master and slave clocks reliable and attack-resistant in the network environment.

[0025] The FPGA parses PTP packets at the link layer and performs compliance verification on the PTP packets based on the configuration information. The compliance verification includes verification based on the IP address range, port number, and protocol compliance rules. In another preferred embodiment of the present invention, the compliance verification includes verifying whether the IP address of the PTP data packet is within the range of the IP address, verifying whether the port number of the PTP data packet is consistent with the port number, and verifying whether the protocol field of the PTP data packet conforms to the protocol compliance rules, wherein the protocol compliance rules include the version number, message type and domain number of the PTP data packet.

[0026] Specifically, after receiving network data frames at the link layer, the FPGA uses its internal hardware parsing unit to parse the data frame header and payload layer by layer, identifying data packets that conform to the PTP protocol characteristics. During the parsing process, the FPGA extracts the destination address, source address, protocol type, and key fields related to the PTP protocol from the data frame, and performs compliance verification based on the stored configuration information. This verification process is automatically executed by the hardware logic. The FPGA has a dedicated verification module that compares the received PTP data packets item by item: First, the logic judgment unit extracts the source IP address from the data packet and compares it with the IP address range defined in the configuration information. When the address is detected to be within the allowed range, the data packet is marked as a legitimate communication object; otherwise, it is discarded. Then, the port number field in the data packet is read and matched with the port number set in the configuration information to confirm whether the data packet belongs to the PTP communication channel. If the port number does not meet the set value, the data packet is marked as non-compliant and will not proceed to the subsequent time synchronization process. After completing address and port verification, the protocol verification logic reads and analyzes the protocol fields of the PTP data packet. Based on the protocol compliance rules stored in the configuration information, it determines whether the packet's version number, message type, and domain number meet the predetermined standards. The version number field is used to distinguish the PTP protocol version, the message type is used to identify the role of the data packet in the PTP interaction, and the domain number is used to verify whether the data packet belongs to the current synchronization domain. The FPGA compares the parsing results with the stored rules through logic judgment circuits. When all fields meet the compliance requirements, the data packet is recognized as a trusted message and enters the link layer timestamp processing process. If any field does not meet the requirements in the configuration information, the FPGA immediately terminates further processing of the message, directly discards the data, and triggers a status flag update for upper-layer recording and anomaly response.

[0027] For PTP data packets that pass the compliance verification, the FPGA directly sends and receives the PTP data packets at the link layer, and records a high-precision timestamp based on the local time reference when the data packet arrives at or is sent from the network interface. The high-precision timestamp includes a first timestamp when the master clock sends a Sync message, a second timestamp when the slave clock receives a Sync message, a third timestamp when the slave clock sends a Delay_Req message, and a fourth timestamp when the master clock receives a Delay_Req message. In another preferred embodiment of the present invention, the recording of high-precision timestamps is performed by a clock-driven counter inside the FPGA, the clock-driven counter being disciplined by the local time base.

[0028] Specifically, after passing compliance verification, PTP data packets are directly sent and received by the link layer transceiver control module upon entering the FPGA. The data packets no longer pass through upper-layer transmission protocols or the operating system kernel; instead, forwarding and time recording are completed within the hardware logic. When the master clock node sends a Sync message through the FPGA, the FPGA's transmission control logic triggers a time sampling command the instant the message enters the physical layer transmission channel from the transmission buffer. The internal counting module records the local time value at that moment, generating the first timestamp. This timestamp is written to the timestamp register and associated with the corresponding message identifier for subsequent calculation of the master-slave time difference.

[0029] When a Sync message is received from the master clock from the clock node, the receiving logic triggers a sampling command the instant it detects the message header and confirms the protocol type, records the time when the data packet arrives at the receiving end network interface, and generates a second timestamp.

[0030] The FPGA internally uses a message identification unit to determine the message type and associates the time information with the corresponding synchronization sequence number. When sending a Delay_Req message from the clock, the sending logic completes a time sampling operation before the message is output to the physical layer, recording a third timestamp to describe the actual time when the request was initiated from the clock.

[0031] When the master clock receives a Delay_Req message from the slave clock, it captures the time when the message arrives at the network interface through the receiving logic and records the fourth timestamp, forming a complete time record chain for the master-slave communication process.

[0032] All timestamp generation is accomplished by a clock-driven counter within the FPGA. This counter continuously operates under the control of the local time base, and phase-locked loop (PLL) calibration and frequency discipline mechanisms ensure that the internal count is synchronized with the external time base, thereby guaranteeing the continuity and consistency of timestamp records. Time sampling operations are implemented in the hardware logic using interrupt triggering, avoiding interference from software delays and ensuring accurate and reliable binding of time records and data packet events. The generated timestamps are temporarily stored in registers and then enter an internal buffer, awaiting reading by subsequent delay and offset calculation modules to provide basic time information for time synchronization calculations.

[0033] Understandably, when time synchronization occurs in a network, the master clock sends a Sync message to the slave clock, and the slave clock then sends a Delay_Req message to the master clock. To calculate the actual time difference and link delay between the master and slave clocks, four points in time are needed: the moment the master clock sends the Sync message, the moment the slave clock receives the Sync message, the moment the slave clock sends the Delay_Req message, and the moment the master clock receives the Delay_Req message. These four moments correspond to the physical instants at which data packets are sent from and arrive at the network interface.

[0034] The FPGA uses the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to calculate the transmission delay and time difference; In another preferred embodiment of the present invention, the calculation of transmission delay includes: calculating the difference A between the fourth timestamp and the first timestamp, subtracting the difference between the third timestamp and the second timestamp from the difference A to obtain the difference B, and B / 2 being the transmission delay; The calculation of the time difference includes: calculating the difference C between the second timestamp and the first timestamp, adding the difference C to the difference between the fourth timestamp and the third timestamp to obtain the target value D, and then D / 2 is the time difference.

[0035] The FPGA transmits the calculated transmission delay and time difference to the backend application via direct memory access.

[0036] Specifically, after the calculation is complete, the FPGA writes the result to the Direct Memory Access Control Unit (DMI) via its internal bus control module. This unit can efficiently transfer data to the memory area of ​​the backend application without consuming processor resources. Upon receiving the delay and time difference data, the backend application adjusts the local time of the slave clock based on the deviation information to ensure consistency between the slave and master clocks. The key to the entire time synchronization process lies in the FPGA's recording of timestamps and the calculation of delays and time differences. When these calculation results are transmitted to the backend and used to correct the slave clock time, the time synchronization process is complete. In this way, the system achieves a complete closed loop from physical layer time capture to logical layer time calibration, ensuring that the master and slave clocks remain synchronized under the same time base.

[0037] PTP high-precision and secure time synchronization device based on the link layer includes: The distribution module: The time synchronization service application distributes configuration information to the FPGA, including IP address range, port number, and protocol compliance rules; The FPGA obtains an external time base from the time base module and generates a local time base. Verification module: The FPGA parses PTP packets at the link layer and performs compliance verification on the PTP packets based on the configuration information. The compliance verification includes verification based on the IP address range, port number, and protocol compliance rules. Recording module: For PTP data packets that pass the compliance verification, the FPGA directly sends and receives the PTP data packets at the link layer, and records a high-precision timestamp based on the local time reference when the data packet arrives at or is sent from the network interface. The high-precision timestamp includes a first timestamp when the master clock sends a Sync message, a second timestamp when the slave clock receives a Sync message, a third timestamp when the slave clock sends a Delay_Req message, and a fourth timestamp when the master clock receives a Delay_Req message. Synthesis Module: The FPGA uses the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to calculate the transmission delay and time difference; The FPGA transmits the calculated transmission delay and time difference to the backend application via direct memory access.

[0038] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A PTP high-precision secure time synchronization method based on the link layer, characterized in that, Includes the following steps: The time synchronization service application sends configuration information to the FPGA, which includes IP address range, port number and protocol compliance rules; The FPGA obtains an external time base from the time base module and generates a local time base. The FPGA parses PTP packets at the link layer and performs compliance verification on the PTP packets based on the configuration information. The compliance verification includes verification based on the IP address range, port number, and protocol compliance rules. For PTP data packets that pass the compliance verification, the FPGA directly sends and receives the PTP data packets at the link layer, and records a high-precision timestamp based on the local time reference when the data packet arrives at or is sent from the network interface. The high-precision timestamp includes a first timestamp when the master clock sends a Sync message, a second timestamp when the slave clock receives a Sync message, a third timestamp when the slave clock sends a Delay_Req message, and a fourth timestamp when the master clock receives a Delay_Req message. The FPGA uses the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to calculate the transmission delay and time difference; The FPGA transmits the calculated transmission delay and time difference to the backend application via direct memory access.

2. The PTP high-precision secure time synchronization method based on the link layer according to claim 1, characterized in that, The configuration information also includes time reference module parameters, which are used to configure the priority and calibration period of the external time reference.

3. The PTP high-precision secure time synchronization method based on the link layer according to claim 1, characterized in that, The time reference module includes at least one of a BeiDou satellite receiver, a GPS receiver, and an atomic clock, and the FPGA interfaces with the time reference module through a hardware clock synchronization interface.

4. The PTP high-precision secure time synchronization method based on the link layer according to claim 1, characterized in that, The compliance verification includes verifying whether the IP address of the PTP packet is within the range of the IP address, verifying whether the port number of the PTP packet is consistent with the port number, and verifying whether the protocol fields of the PTP packet conform to the protocol compliance rules. The protocol compliance rules include the version number, message type, and domain number of the PTP packet.

5. The PTP high-precision secure time synchronization method based on the link layer according to claim 1, characterized in that, The recording of high-precision timestamps is performed by a clock-driven counter inside the FPGA, which is tamed by the local time base.

6. The PTP high-precision secure time synchronization method based on the link layer according to claim 1, characterized in that, The calculation of transmission delay includes: calculating the difference A between the fourth timestamp and the first timestamp, subtracting the difference between the third timestamp and the second timestamp from the difference A to obtain the difference B, and B / 2 is the transmission delay; The calculation of the time difference includes: calculating the difference C between the second timestamp and the first timestamp, adding the difference C to the difference between the fourth timestamp and the third timestamp to obtain the target value D, and then D / 2 is the time difference.

7. The PTP high-precision secure time synchronization method based on the link layer according to claim 1, characterized in that, It also includes hardware-level encryption and authentication of PTP data packets by the FPGA.

8. The PTP high-precision secure time synchronization method based on the link layer according to claim 1, characterized in that, The time reference module supports multiple external time reference inputs, and the FPGA adaptively selects the optimal external time reference based on signal strength and stability parameters.

9. A PTP high-precision and secure time synchronization device based on the link layer, characterized in that, include: The distribution module: The time synchronization service application distributes configuration information to the FPGA, including IP address range, port number, and protocol compliance rules; The FPGA obtains an external time base from the time base module and generates a local time base. Verification module: The FPGA parses PTP packets at the link layer and performs compliance verification on the PTP packets based on the configuration information. The compliance verification includes verification based on the IP address range, port number, and protocol compliance rules. Recording module: For PTP data packets that pass the compliance verification, the FPGA directly sends and receives the PTP data packets at the link layer, and records a high-precision timestamp based on the local time reference when the data packet arrives at or is sent from the network interface. The high-precision timestamp includes a first timestamp when the master clock sends a Sync message, a second timestamp when the slave clock receives a Sync message, a third timestamp when the slave clock sends a Delay_Req message, and a fourth timestamp when the master clock receives a Delay_Req message. Synthesis Module: The FPGA uses the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to calculate the transmission delay and time difference; The FPGA transmits the calculated transmission delay and time difference to the backend application via direct memory access.

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