C code and verilog code generation method and device
By using GCKontrol modeling software to build models and perform floating-point simulation and scaling, the problems of long FPGA project cycles and high design thresholds have been solved. It has also enabled the automatic generation of C and Verilog code, adapted to hardware timing, and reduced the design difficulty and cost for engineers.
Patent Information
- Application Number
- CN202511672057.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-02-10
AI Technical Summary
In existing technologies, FPGA projects have long cycles and high design thresholds for engineers, and there is a lack of software integration solutions that can automatically generate C code and Verilog code that meet hardware design rules.
The model was built using GCKontrol modeling software, floating-point simulation and scaling were performed, Verilog code modules were encapsulated, a fixed-point model was generated, and C code and Verilog code were generated simultaneously from the calibrated model.
It achieves automatic generation of C and Verilog code based on hardware compatibility, shortens the development cycle, reduces labor costs, adapts to hardware timing and computing power, and avoids functional failure.
Smart Images
Figure CN121501263A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of software development technology, and in particular to a method and apparatus for generating C code and Verilog code. Background Technology
[0002] With the rapid development of technology, FPGA applications are becoming increasingly widespread. Short project cycles and fast paces have become the norm. However, the development and simulation of Verilog code takes up a long development cycle and has a high design threshold for engineers. In order to shorten project cycles and reduce labor costs, the business demand for automatic generation of Verilog code is increasing. In addition, with the widespread use of SOPC chips, the high integration of ARM+FPGA hardware has matured. However, the high integration of software that can simultaneously and automatically generate Verilog code and C code that meet hardware design rules is still lacking.
[0003] In conclusion, how to automatically generate C code and Verilog code is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] In view of this, this application provides a method and apparatus for generating C code and Verilog code, which aims to automatically generate C code and Verilog code.
[0005] Firstly, this application provides a method for generating C code and Verilog code, including:
[0006] The model was built using GCKontrol modeling software;
[0007] Perform floating-point simulation on the model to obtain the floating-point simulation results;
[0008] The module used for automatically generating Verilog code in the model is encapsulated into a subsystem;
[0009] The model is calibrated based on the floating-point simulation results to obtain a fixed-point model.
[0010] The fixed-point model is simulated to obtain the simulation results of the fixed-point model;
[0011] If the simulation of the fixed-point model meets expectations, then C code and Verilog code are automatically generated using the fixed-point model.
[0012] Optionally, the subsystem encapsulation of the module in the model used for automatically generating Verilog code includes:
[0013] Determine the portion of the model used to generate the C code, and the portion of the model used to generate the Verilog code;
[0014] The part of the model used to generate the Verilog code is encapsulated into a subsystem.
[0015] Optionally, if the simulation of the fixed-point model meets expectations, then automatically generating C code and Verilog code using the fixed-point model includes:
[0016] If the simulation results of the model meet expectations, the C code is automatically generated using the part of the fixed-point model used to generate the C code, and the Verilog code is automatically generated using the subsystem.
[0017] Optionally, if the simulation of the fixed-point model meets expectations, after automatically generating C code and Verilog code using the fixed-point model, the method further includes:
[0018] Compile the C code and the Verilog code respectively;
[0019] The compiled C code and compiled Verilog code were then downloaded and debugged to obtain the debugging results.
[0020] If the debugging results are consistent with the simulation results of the model, then the C code is determined to be the target C code, and the Verilog code is determined to be the target Verilog code.
[0021] Optionally, compiling the C code and the Verilog code respectively includes:
[0022] The C code is compiled using IAR software to obtain the corresponding binary file.
[0023] The Verilog code was compiled using Vivado software to obtain the corresponding binary file.
[0024] Optionally, the step of debugging the compiled C code and the compiled Verilog code on the board to obtain the debugging results includes:
[0025] Deploy the binary file corresponding to the C code to the PS side of the chip;
[0026] Deploy the binary file corresponding to the Verilog code to the PL terminal of the chip;
[0027] Using the Xilinx emulator and the ARM emulator, the binary files corresponding to the C code and the Verilog code are debugged to obtain the debugging results.
[0028] Secondly, this application provides a C code and Verilog code generation apparatus, comprising:
[0029] The module is used to build models using GCKontrol modeling software.
[0030] The first simulation module is used to perform floating-point simulation on the model and obtain the floating-point simulation results;
[0031] An encapsulation module is used to encapsulate the module in the model that is used to automatically generate Verilog code into a subsystem.
[0032] The calibration module is used to calibrate the model based on the floating-point simulation results to obtain a fixed-point model;
[0033] The second simulation module is used to simulate the fixed-point model and obtain the simulation results of the fixed-point model;
[0034] The generation module is used to automatically generate C code and Verilog code using the fixed-point model if the simulation of the fixed-point model meets expectations.
[0035] Optionally, the encapsulation module includes:
[0036] A submodule is defined to determine the portion of the model used to generate the C code and the portion of the model used to generate the Verilog code.
[0037] The encapsulation submodule is used to encapsulate the part of the model used to generate the Verilog code into a subsystem.
[0038] Optionally, the generation module includes:
[0039] A generation submodule is used to automatically generate the C code using the part of the fixed-point model used to generate C code if the simulation results of the model meet expectations, and to automatically generate the Verilog code using the subsystem.
[0040] Optionally, the device further includes:
[0041] A compilation module is used to compile the C code and the Verilog code respectively;
[0042] The debugging module is used to debug the compiled C code and compiled Verilog code off-board and obtain the debugging results;
[0043] The determination module is used to determine that if the debugging result is consistent with the simulation result of the model, then the C code is determined to be the target C code and the Verilog code is determined to be the target Verilog code.
[0044] Optionally, the compilation module includes:
[0045] The first compilation submodule is used to compile the C code using IAR software to obtain the binary file corresponding to the C code;
[0046] The second compilation submodule is used to compile the Verilog code using Vivado software to obtain the binary file corresponding to the Verilog code.
[0047] Optionally, the debugging module includes:
[0048] The first deployment submodule is used to deploy the binary file corresponding to the C code to the PS end of the chip;
[0049] The second deployment submodule is used to deploy the binary file corresponding to the Verilog code to the PL terminal of the chip;
[0050] The debugging submodule is used to debug the binary files corresponding to the C code and the Verilog code using the Xilinx emulator and the ARM emulator, and obtain the debugging results.
[0051] This application provides a method for generating C code and Verilog code. When executing the method, firstly, a model is built using GCKontrol modeling software; secondly, floating-point simulation is performed on the model; thirdly, the modules in the model that require automatic Verilog code generation are encapsulated into subsystems; then, the modules within the subsystems requiring automatic Verilog code generation are calibrated based on the floating-point simulation results; next, the calibrated model is simulated to obtain the simulation results of the fixed-point model; finally, if the simulation results of the model meet expectations, C code and Verilog code are generated simultaneously using the calibrated model. In this way, the calibration processing based on floating-point results can adapt the model parameters to hardware timing and computing power, avoiding functional failures due to hardware incompatibility after code generation, and generating C code and Verilog code using the calibrated model, thereby achieving simultaneous automatic generation of C code and Verilog code. Attached Figure Description
[0052] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0053] Figure 1 A flowchart illustrating a method for generating C code and Verilog code as provided in this application embodiment;
[0054] Figure 2 A PID velocity model built using GCKontrol modeling software is provided for an embodiment of this application;
[0055] Figure 3 This is a schematic diagram illustrating the calibration of a PID speed model using floating-point simulation results, provided in an embodiment of this application.
[0056] Figure 4 This is a schematic diagram of the subsystem encapsulation provided in an embodiment of this application;
[0057] Figure 5 This is a schematic diagram of a C code and Verilog code generation device provided in an embodiment of this application. Detailed Implementation
[0058] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. This application provides a method and apparatus for generating C code and Verilog code, applicable to the field of software development technology. The above are merely examples and do not limit the application areas of the methods and apparatus provided in this application.
[0059] With the rapid development of technology, FPGA applications are becoming increasingly widespread. Short project cycles and fast paces have become the norm. However, the development and simulation of Verilog code takes up a long development cycle and has a high design threshold for engineers. In order to shorten project cycles and reduce labor costs, the business demand for automatic generation of Verilog code is increasing. In addition, with the widespread use of SOPC chips, the high integration of ARM+FPGA hardware has matured. However, the high integration of software that can simultaneously and automatically generate Verilog code and C code that meet hardware design rules is still lacking.
[0060] The inventors, through research, proposed the technical solution of this application. First, a model is built using GCKontrol modeling software. Second, floating-point simulation is performed on the model. Third, the modules in the model that require automatic Verilog code generation are encapsulated into subsystems. Then, based on the floating-point simulation results, the modules within the subsystems requiring automatic Verilog code generation are calibrated. Next, the calibrated model is simulated to obtain the simulation results of the fixed-point model. Finally, if the simulation results meet expectations, C code and Verilog code are generated simultaneously using the calibrated model. This calibration process based on floating-point results adapts the model parameters to hardware timing and computational capabilities, avoiding functional failures due to hardware incompatibility after code generation. Furthermore, by using the calibrated model to generate C code and Verilog code, the simultaneous automatic generation of both C code and Verilog code is achieved.
[0061] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application. It should be noted that, for ease of description, only the parts related to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of the present application can be combined with each other.
[0062] See Figure 1 , Figure 1 A flowchart of a C code and Verilog code generation method provided for embodiments of this application includes:
[0063] S101: Build the model using GCKontrol modeling software.
[0064] First, the basic model is built using GCKontrol modeling software. This model will serve as the core logic carrier for the subsequent automatic generation of C and Verilog code. To clearly illustrate the implementation process of the overall solution, this embodiment uses the construction of a PID speed control model as an example for specific explanation. Figure 2 As shown, Figure 2 This application provides a PID velocity model built using GCKontrol modeling software. Through GCKontrol's visual modeling capabilities, complex control algorithm logic can be transformed into a modular graphical model, providing an intuitive and standardized framework for subsequent simulation verification and code generation.
[0065] S102: Perform floating-point simulation on the model to obtain the floating-point simulation results.
[0066] After building the PID speed model, floating-point simulation is required. During floating-point simulation, the model uses floating-point numbers as the unit of operation to fully reproduce the theoretical logic and data processing results, including details such as signal transmission between modules, parameter calculations, and output value changes. This step yields floating-point simulation results of the PID speed model under different input conditions. These results will serve as important references for subsequent model optimization and parameter adjustment, verifying the correctness of the model's core logic.
[0067] S103: Subsystem encapsulation of the module in the model used for automatically generating Verilog code.
[0068] First, the functional division of the different parts of the model needs to be clarified: one part will be used to generate C code, which will eventually be deployed and run on the ARM side (PS side) of the board; the other part will be used to generate Verilog code, which will be deployed and run on the FPGA side (PL side) of the board, such as... Figure 4 As shown, Figure 4 The diagram illustrates the subsystem encapsulation provided in this application embodiment. Specifically, the module that needs to generate Verilog code is encapsulated into an independent subsystem using GCKontrol software, and the subsystem is renamed "pl" to clearly define the generation scope of the two types of code.
[0069] S104: Based on the floating-point simulation results, the model is calibrated to obtain a fixed-point model.
[0070] like Figure 3 As shown, Figure 3 This diagram illustrates the calibration of a PID speed model using floating-point simulation results, as provided in this embodiment. The core of the calibration operation is to combine the numerical range presented by the floating-point simulation (such as the maximum and minimum values of parameters like speed and acceleration) with precision requirements to set key parameters in the model using fixed-point settings. For example, by configuring precision parameters like fixdt(1,32,4), the rules for allocating the sign bit, integer bits, and decimal places of the numerical values are clearly defined. This process effectively solves the problem of traditional automatically generated code "containing only combinational logic and lacking timing constraints," ensuring that the subsequently generated Verilog code can adapt to the timing requirements of the hardware, providing a fundamental guarantee for direct code deployment and execution.
[0071] S105: Simulate the fixed-point model to obtain the simulation results of the fixed-point model.
[0072] After model calibration is completed, simulation verification of the calibrated model is required again. This simulation yields the overall operating results of the calibrated model, which verifies whether the calibration operation caused any deviations in the model logic and ensures that the model can maintain functional correctness after hardware adaptation and adjustment.
[0073] S106: If the simulation of the fixed-point model meets expectations, then the fixed-point model will be used to automatically generate C code and Verilog code.
[0074] Click the "Code Generation" tab in GCCortrol, configure parameters such as project alias, compiler (GCC), HDL object (specify "pl" subsystem), etc., and trigger the simultaneous generation of C code and Verilog code.
[0075] After generating C code and Verilog code, the C code and Verilog code need to be compiled separately. The specific method is as follows: use the IAR software to compile the C code to obtain the corresponding binary file, and use the Vivado software to compile the Verilog code to obtain the corresponding binary file.
[0076] Next, the compiled C code and Verilog code are deployed to the chip's PS (Power Switch) and PL (Power Probe) terminals for debugging. Using Xilinx and ARM simulators, the binary files for both C and Verilog codes are debugged to obtain the results. If the debugging results match the simulation results of the model, the C code is determined to be the target C code, and the Verilog code is determined to be the target Verilog code.
[0077] In this embodiment, firstly, a model is built using GCKontrol modeling software. Secondly, floating-point simulation is performed on the model. Thirdly, the modules in the model that require automatic Verilog code generation are encapsulated into subsystems. Then, based on the floating-point simulation results, the modules within the subsystems requiring automatic Verilog code generation are calibrated. Next, the calibrated model is simulated to obtain the simulation results of the fixed-point model. Finally, if the simulation results of the model meet expectations, C code and Verilog code are generated simultaneously using the calibrated model. This calibration process based on floating-point results adapts the model parameters to hardware timing and computational capabilities, avoiding functional failures due to hardware incompatibility after code generation. Furthermore, by using the calibrated model to generate C code and Verilog code, simultaneous automatic generation of both C code and Verilog code is achieved.
[0078] The above provides some specific implementations of the C code and Verilog code methods in the embodiments of this application. Based on this, this application also provides a corresponding device. The device provided in the embodiments of this application will be described below from the perspective of functional modularity.
[0079] See Figure 5 , Figure 5 This application provides a schematic diagram of the structure of a C code and Verilog code generation apparatus 500, which includes:
[0080] Module 510 is used to build models using GCKontrol modeling software.
[0081] The first simulation module 520 is used to perform floating-point simulation on the model and obtain the floating-point simulation results.
[0082] The encapsulation module 530 is used to encapsulate the module in the model that is used to automatically generate Verilog code into a subsystem.
[0083] The calibration module 540 is used to calibrate the model based on the floating-point simulation results to obtain a fixed-point model;
[0084] The second simulation module 550 is used to simulate the fixed-point model and obtain the simulation results of the fixed-point model.
[0085] The generation module 560 is used to automatically generate C code and Verilog code using the fixed-point model if the simulation of the fixed-point model meets expectations.
[0086] Optionally, the packaging module 530 includes:
[0087] A submodule is defined to determine the portion of the model used to generate the C code and the portion of the model used to generate the Verilog code.
[0088] The encapsulation submodule is used to encapsulate the part of the model used to generate the Verilog code into a subsystem.
[0089] Optionally, the generation module 560 includes:
[0090] A generation submodule is used to automatically generate the C code using the part of the fixed-point model used to generate C code if the simulation results of the model meet expectations, and to automatically generate the Verilog code using the subsystem.
[0091] Optionally, the device 500 further includes:
[0092] A compilation module is used to compile the C code and the Verilog code respectively;
[0093] The debugging module is used to debug the compiled C code and compiled Verilog code off-board and obtain the debugging results;
[0094] The determination module is used to determine that if the debugging result is consistent with the simulation result of the model, then the C code is determined to be the target C code and the Verilog code is determined to be the target Verilog code.
[0095] Optionally, the compilation module includes:
[0096] The first compilation submodule is used to compile the C code using IAR software to obtain the binary file corresponding to the C code;
[0097] The second compilation submodule is used to compile the Verilog code using Vivado software to obtain the binary file corresponding to the Verilog code.
[0098] Optionally, the debugging module includes:
[0099] The first deployment submodule is used to deploy the binary file corresponding to the C code to the PS end of the chip;
[0100] The second deployment submodule is used to deploy the binary file corresponding to the Verilog code to the PL terminal of the chip;
[0101] The debugging submodule is used to debug the binary files corresponding to the C code and the Verilog code using the Xilinx emulator and the ARM emulator, and obtain the debugging results.
[0102] This application also provides corresponding devices and computer storage media for implementing the solutions provided in this application.
[0103] The device includes a memory and a processor. The memory stores instructions or code, and the processor executes the instructions or code to cause the device to perform the method described in any embodiment of this application.
[0104] The computer storage medium stores code, and when the code is run, the device running the code implements the method described in any embodiment of this application.
[0105] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.
[0106] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0107] It should also be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the device and apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The apparatus embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. The components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0108] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for generating C code and Verilog code, characterized in that, include: The model was built using GCKontrol modeling software; Perform floating-point simulation on the model to obtain the floating-point simulation results; The module used for automatically generating Verilog code in the model is encapsulated into a subsystem; The model is calibrated based on the floating-point simulation results to obtain a fixed-point model. The fixed-point model is simulated to obtain the simulation results of the fixed-point model; If the simulation of the fixed-point model meets expectations, then C code and Verilog code are automatically generated using the fixed-point model.
2. The method according to claim 1, characterized in that, The subsystem encapsulation of the module in the model used for automatically generating Verilog code includes: Determine the portion of the model used to generate the C code, and the portion of the model used to generate the Verilog code; The part of the model used to generate the Verilog code is encapsulated into a subsystem.
3. The method according to claim 2, characterized in that, If the simulation of the fixed-point model meets expectations, then C code and Verilog code are automatically generated using the fixed-point model, including: If the simulation results of the model meet expectations, the C code is automatically generated using the part of the fixed-point model used to generate the C code, and the Verilog code is automatically generated using the subsystem.
4. The method according to claim 1, characterized in that, If the simulation of the fixed-point model meets expectations, then after automatically generating C code and Verilog code using the fixed-point model, the method further includes: Compile the C code and the Verilog code respectively; The compiled C code and compiled Verilog code were then downloaded and debugged to obtain the debugging results. If the debugging results are consistent with the simulation results of the model, then the C code is determined to be the target C code, and the Verilog code is determined to be the target Verilog code.
5. The method according to claim 4, characterized in that, The process of compiling the C code and the Verilog code respectively includes: The C code is compiled using IAR software to obtain the corresponding binary file. The Verilog code was compiled using Vivado software to obtain the corresponding binary file.
6. The method according to claim 5, characterized in that, The process of debugging the compiled C code and compiled Verilog code on the board and obtaining the debugging results includes: Deploy the binary file corresponding to the C code to the PS side of the chip; Deploy the binary file corresponding to the Verilog code to the PL terminal of the chip; Using the Xilinx emulator and the ARM emulator, the binary files corresponding to the C code and the Verilog code are debugged to obtain the debugging results.
7. A C code and Verilog code generation apparatus, characterized in that, include: The module is used to build models using GCKontrol modeling software. The first simulation module is used to perform floating-point simulation on the model and obtain the floating-point simulation results; An encapsulation module is used to encapsulate the module in the model that is used to automatically generate Verilog code into a subsystem. The calibration module is used to calibrate the model based on the floating-point simulation results to obtain a fixed-point model; The second simulation module is used to simulate the fixed-point model and obtain the simulation results of the fixed-point model; The generation module is used to automatically generate C code and Verilog code using the fixed-point model if the simulation of the fixed-point model meets expectations.
8. The apparatus according to claim 7, characterized in that, The packaging module includes: A submodule is defined to determine the portion of the model used to generate the C code and the portion of the model used to generate the Verilog code. The encapsulation submodule is used to encapsulate the part of the model used to generate the Verilog code into a subsystem.
9. The apparatus according to claim 8, characterized in that, The generation module includes: A generation submodule is used to automatically generate the C code using the part of the fixed-point model used to generate C code if the simulation results of the model meet expectations, and to automatically generate the Verilog code using the subsystem.
10. The apparatus according to claim 7, characterized in that, The device further includes: A compilation module is used to compile the C code and the Verilog code respectively; The debugging module is used to debug the compiled C code and compiled Verilog code off-board and obtain the debugging results; The determination module is used to determine that if the debugging result is consistent with the simulation result of the model, then the C code is determined to be the target C code and the Verilog code is determined to be the target Verilog code.