Radar chip cascade starting method, radar chip and terminal equipment

Abstract

The invention discloses a radar chip cascade starting method, a radar chip and terminal equipment. The radar chip cascade starting method comprises the steps that after a first chip receives a starting command, a bootstrap program is acquired from an external Flash for starting; the first chip carries out handshake with a second chip based on the serdes technology by using a first serdes configuration parameter, the second chip is a chip connected with the first chip, and a bootstrap program is transmitted to the second chip by using the first serdes configuration parameter based on the serdes technology so that the second chip can be started.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radar sensing, and in particular to a radar chip cascading starting method, a radar chip and a terminal device. BACKGROUND

[0002] Compared with traditional millimeter wave radars, the advantage of 4D imaging radars is high resolution, that is, higher resolution of targets in the distance dimension and the angle dimension. Multi-chip cascading is a solution, each chip has its own multi-transmitting and multi-receiving radar antenna, so that more multi-transmitting and multi-receiving antennas are provided after cascading, thereby improving the resolution. SUMMARY

[0003] Embodiments of the present application provide a radar chip cascading starting method, a radar chip and a terminal device, which ensure high-speed transmission of data between cascaded radar chips.

[0004] In one aspect, the present application provides a radar chip cascading starting method, which is applicable to a first chip, and the method comprises:

[0005] After receiving a starting command, the first chip obtains a boot program from an external Flash for starting.

[0006] The first chip uses first serdes configuration parameters to handshake with a second chip based on serdes technology, the second chip is a chip connected to the first chip, and the first serdes configuration parameters are used to transmit the boot program to the second chip based on serdes technology, so that the second chip starts.

[0007] In another aspect, the present application provides a radar chip cascading starting method, which is applicable to a second chip, and the method comprises:

[0008] The second chip uses first serdes configuration parameters to handshake with a first chip based on serdes technology, and obtains a boot program from the first chip based on serdes technology using the first serdes configuration parameters, and starts based on the boot program; when the second chip has a subordinate chip, the second chip uses second serdes configuration parameters to transmit a boot program to the subordinate chip based on serdes technology, so that the subordinate chip starts.

[0009] In another aspect, the present application provides a radar chip, which comprises:

[0010] A first processing unit is configured to obtain a boot program from an external Flash for starting after receiving a starting command; and

[0011] The first connection unit is configured to handshake with a second chip using a first serdes configuration parameter based on a serdes technology, the second chip being a chip connected to the chip, and transmit a boot program to the second chip using the first serdes configuration parameter based on the serdes technology for starting up the second chip.

[0012] In another aspect, the embodiment of the present disclosure further provides a radar chip, comprising:

[0013] The second connection unit is configured to handshake with a first chip using a first serdes configuration parameter based on a serdes technology, and acquire a boot program from the first chip using the first serdes configuration parameter based on the serdes technology, and when there is a subordinate chip, transmit a boot program to the subordinate chip using a second serdes configuration parameter based on the serdes technology for starting up the subordinate chip.

[0014] The second processing unit is configured to start up based on the boot program acquired from the first chip.

[0015] In another aspect, the embodiment of the present disclosure further provides a terminal device, comprising:

[0016] A device body; and

[0017] The radar chip as described above is arranged on the device body.

[0018] The embodiment of the present disclosure establishes a link of a high-speed interface between chips by using pre-debugged parameters, and can realize high-speed transmission whether it is handshake or data transmission, and no longer needs to use a low-speed channel for configuration and rate negotiation, so that multi-chip starting is faster.

[0019] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. Other advantages of the present application can be realized and obtained by means of the schemes described in the specification and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used to explain the technical scheme of the present application together with the embodiments of the present application, and do not constitute a limitation to the technical scheme of the present application.

[0021] Figure 1 A flow chart of a radar chip cascading start-up method provided by the embodiment of the present disclosure;

[0022] Figure 2 A flow chart of another radar chip cascading start-up method provided by the embodiment of the present disclosure;

[0023] Figure 3 This is a schematic diagram of two radar chips cascaded according to an embodiment of this disclosure;

[0024] Figure 4 This is a schematic diagram illustrating a connection method between a master chip and a slave chip according to an embodiment of this disclosure;

[0025] Figure 5 This is a topology diagram of two cascaded chips according to an embodiment of this disclosure;

[0026] Figure 6 This is a diagram of a multi-chip cascaded topology according to an embodiment of this disclosure;

[0027] Figure 7 This is a topology diagram of multiple chips connected in series in a ring according to an embodiment of this disclosure;

[0028] Figure 8 This is a topology diagram of multiple chips connected in parallel according to an embodiment of this disclosure;

[0029] Figure 9 This is an embodiment of the present disclosure. Figure 6 The diagram shows a data flow pattern in the topology shown.

[0030] Figure 10 This is a flowchart illustrating the process of obtaining startup data from the chip via the main chip;

[0031] Figure 11 This is a flowchart of data transmission for cascaded radar chips.

[0032] Figure 12 This is a flowchart of the main chip startup process provided in an embodiment of the present disclosure;

[0033] Figure 13 This is a flowchart illustrating the chip boot process provided in an embodiment of the present disclosure. Detailed Implementation

[0034] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0035] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0036] When multiple radar chips are cascaded, each chip is interconnected via a high-speed differential signal interface, using a common high-speed clock to achieve high-speed transmission of radar data between chips. To ensure high-speed data transmission between cascaded radar chips, this disclosure proposes a radar chip cascading startup method suitable for the first chip, such as... Figure 1 As shown, it includes:

[0037] Step 10: After receiving the boot command, the first chip obtains the boot program from the external Flash and starts the boot process;

[0038] Step 11: The first chip uses the first SERDES configuration parameters to handshake with the second chip based on SERDES technology. The second chip is a chip connected to the first chip. The first chip uses the first SERDES configuration parameters to transmit the boot program to the second chip based on SERDES technology for the second chip to start.

[0039] SERDES (Serializer / Deserializer) technology is a technique used in digital communication to convert parallel data into serial data (and vice versa). SERDES configuration parameters include, but are not limited to, one or more of the following: data rate, encoding method, clock management parameters, power management parameters, signal integrity parameters, interface type parameters, and bit error rate.

[0040] The first SERDES configuration parameters can be pre-configured and stored on the first chip, for example, they can be pre-stored in the first non-volatile storage medium of the first chip. By using the pre-tuned parameters to establish a high-speed interface link between chips, high-speed transmission can be achieved for both handshaking and data transmission, eliminating the need for low-speed channels for configuration and rate negotiation, thus enabling faster startup of multiple chips.

[0041] For example, the first chip is a master chip, and the second chip is a slave chip.

[0042] In an exemplary embodiment, before the first chip receives the startup command, the method further includes: the first chip determining itself as the master chip based on the level of the Strap pin. By selecting the master / slave relationship based on the level of an external pin, any chip can be designated as either a master or slave chip, providing good scalability.

[0043] In an exemplary embodiment, before transmitting the bootloader to the second chip using pre-stored first SERDES configuration parameters based on SERDES technology, the method further includes: the first chip signing the bootloader data using a private key, and encrypting the bootloader data using an encryption key. The encryption algorithm includes, but is not limited to, any of the following: RSA (asymmetric encryption algorithm), ECC (elliptic curve cryptography), AES (Advanced Encryption Standard), etc. These steps enable high-security data transmission and prevent data leakage.

[0044] In an exemplary embodiment, after the first chip obtains the boot program from external Flash and starts booting, the method further includes, if the first chip decrypts and verifies the application's signature is correct, starting the application. Decryption and signature verification ensure the correctness of the application.

[0045] In an exemplary embodiment, the method further includes the first chip sending a Flash boot command to the second chip, and, upon receiving a Flash boot failure message from the second chip, transmitting a boot program to the second chip using the first SERDES configuration parameters based on SERDES technology. This embodiment provides a way to enable the first chip, when acting as the master chip, to send a Flash boot command to the second chip. This allows compatibility with slave chips connected to Flash, enabling these slave chips to boot from their connected Flash. If a slave chip is not connected to Flash, the master chip can actively transmit the boot program by reporting a Flash boot failure message.

[0046] This embodiment presents a multi-chip cascaded boot method applicable to radar master chips, providing excellent scalability for radar slave chips. Any chip can be designated as either a master or slave chip, with control of the master and slave chips determined by the level of the Strap pin. The master chip connects to the corresponding Flash memory to store the bootloader, application program, etc. Slave chips can choose to connect or not connect to Flash. If not connected, data can be output from the master chip to the slave chip. If there are multiple levels, data can be output from either the slave chip or the master chip to the next level slave chip. Furthermore, slave chips can communicate with the master chip to adapt to boot strategies based on whether the slave chip has Flash memory, providing greater flexibility to the board-level solution. Additionally, by employing a secure domain hardware design architecture, the key is not leaked, and data between chips is transmitted in encrypted form, making cascaded booting more secure. High-speed interfaces between chips are established using locally debugged parameters, enabling faster booting of multiple chips.

[0047] This disclosure also provides an embodiment that can achieve... Figure 1 The radar chip of the method shown includes:

[0048] The first processing unit is used to obtain a boot program from external Flash and start the computer after receiving a boot command; and

[0049] The first connection unit is used to handshake with the second chip based on the SERDes technology using the first SERDes configuration parameters, the second chip being a chip connected to this chip, and to transmit the boot program to the second chip based on the SERDes technology using the first SERDes configuration parameters for the second chip to start.

[0050] The chip described in this embodiment establishes a high-speed interface link between chips using pre-tuned parameters. Whether for handshaking or data transmission, high-speed transmission can be achieved, eliminating the need for low-speed channels for configuration and rate negotiation, thus enabling faster startup of multiple chips. The chip in this example is the main chip.

[0051] In an exemplary embodiment, the chip further includes a first non-volatile storage medium for storing the first SERDES configuration parameters. An eFuse (electronically programmable fuse) is a programmable memory technology used in integrated circuits. It consists of a series of tiny resistors or wires that can be burned off by current or a laser, changing their state from conductive to non-conductive. Once the fuse is broken, it cannot be reconnected, thus the data or settings are permanent. By burning off specific eFuses during manufacturing, this information can be written to and locked into the chip, preventing unauthorized users or malicious attackers from modifying or copying the data.

[0052] In an exemplary embodiment, the first processing unit is further configured to determine that the chip is the master chip based on the level of the Strap pin of the chip. In other embodiments, the radar chip further includes a ROM, wherein the ROM contains boot code that determines that the chip is the master chip based on the level of the Strap pin of the chip. Determining the master / slave chip via ROM eliminates the need for processing unit intervention, making it faster and saving processing unit resources. By selecting the master / slave chip based on the level of an external pin, any chip can be designated as either a master or slave chip, providing good scalability.

[0053] In an exemplary embodiment, the radar chip further includes a first security unit, configured to sign boot program data sent to a lower-level chip using a private key, encrypt the boot program data using an encryption key, and decrypt and verify the signature of boot program data received from Flash. This enables high-security data transmission and prevents data leakage.

[0054] In an exemplary embodiment, the first processing unit is further configured to send a Flash boot command to the second chip, and, upon receiving a Flash boot failure message from the second chip, to transmit a boot program to the second chip using the first SERDES configuration parameters based on SERDES technology. This chip, acting as the master chip, has the capability to send a Flash boot command to the second chip, thereby enabling compatibility with slave chips connected to Flash, allowing these slave chips to boot from their connected Flash. If a slave chip is not connected to Flash, the master chip can actively transmit the boot program by sending a Flash boot failure message.

[0055] In an exemplary embodiment, the first processing unit is a first security processing unit, and the chip further includes at least one first application processing unit, used to launch the application when the security unit decrypts and verifies the application signature correctly. By distinguishing between the security processing unit and the application processing unit, the startup process can only be completed by the security processing unit, and the data and operations of cascaded startup are controlled by the security processing unit and cannot be obtained by the application, thereby improving the security of cascaded startup.

[0056] This disclosure also provides a radar chip cascade startup method suitable for a second chip, such as... Figure 2 As shown, it includes:

[0057] Step 21: The second chip uses the first SERDE configuration parameters to handshake with the first chip based on SERDE technology, and uses the first SERDE configuration parameters to obtain the boot program from the first chip based on SERDE technology;

[0058] Step 22: Startup is achieved based on the bootloader. When there is a lower-level chip in the second chip, the bootloader is transmitted to the lower-level chip using the second SERDES configuration parameters based on SERDES technology, so that the lower-level chip can start.

[0059] The first and second SERDE configuration parameters can be pre-configured and stored on the second chip, for example, they can be pre-stored in the second non-volatile storage medium of the second chip. By establishing a high-speed interface link between chips using the pre-tuned parameters, high-speed transmission can be achieved for both handshaking and data transmission, eliminating the need for low-speed channels for configuration and rate negotiation, thus enabling faster startup of multiple chips.

[0060] When the differences between chips are small, the configuration parameters of the first SERDS and the second SERDS can be the same.

[0061] For example, the first chip is a master chip, and the second chip is a slave chip.

[0062] In an exemplary embodiment, before handshaking with the first chip, the method further includes: the second chip determining whether it is a slave chip based on the level of the Strap pin. By selecting master or slave based on the level of an external pin, any chip can be designated as either a master or slave chip, providing good scalability.

[0063] In an exemplary embodiment, after receiving data from the first chip, the second chip determines whether the data is a boot program or a command to boot from Flash. If the data is a boot program, the second chip starts the boot process based on the boot program. If the data is a command to boot from Flash, the second chip executes the program to boot from Flash. If the boot process from Flash fails, the second chip reports the failure to the first chip and waits for the first chip to send the boot program.

[0064] In an exemplary embodiment, after the second chip obtains the bootloader from the first chip, the method further includes:

[0065] The received bootloader is subjected to one or more of the following checks: Magic Number correctness, address check, length check, hash check, and security check. If the check is successful, the bootloader is run; if the check fails, a check failure message is sent back to the first chip.

[0066] This embodiment presents a multi-chip cascaded boot method applicable to radar slave chips, providing them with excellent scalability. Any chip can be designated as a master or slave chip, controlled by the level of the Strap pin. Slave chips can optionally connect to or not connect to Flash memory. If Flash is not connected, data can be output from the master chip to the slave chip. If there are multiple levels, data can be output from either the slave or master chip to the next level slave chip. Slave chips can communicate with the master chip to adapt to boot strategies based on whether they have Flash memory, offering greater flexibility to board-level solutions. Furthermore, by employing a secure domain hardware design architecture, the key is not leaked, and data between chips is transmitted in encrypted form, making cascaded boot more secure. High-speed inter-chip interfaces are established using locally debugged parameters, enabling faster booting of multiple chips.

[0067] This disclosure also provides an embodiment that can achieve... Figure 2 The radar chip of the method shown includes:

[0068] The second connection unit is used to handshake with the first chip using the first SERDE configuration parameters based on SERDE technology, and to obtain the boot program from the first chip using the first SERDE configuration parameters based on SERDE technology. When there is a downstream chip, it uses the second SERDE configuration parameters based on SERDE technology to transmit the boot program to the downstream chip for the downstream chip to boot.

[0069] The second processing unit starts up based on the boot program obtained from the first chip.

[0070] The chip described in this embodiment establishes a high-speed interface link between chips using pre-tuned parameters. Whether for handshaking or data transmission, high-speed transmission can be achieved, eliminating the need for low-speed channels for configuration and rate negotiation, thus enabling faster startup of multiple chips. The chip in question is, for example, a slave chip.

[0071] In an exemplary embodiment, the chip further includes a second non-volatile storage medium for storing the first SERDES configuration parameters and the second SERDES configuration parameters. As previously mentioned, storing the configuration parameters in eFuse prevents unauthorized users or malicious attackers from modifying or copying the data.

[0072] In an exemplary embodiment, the second processing unit is further configured to determine whether the chip is a slave chip based on the level of the Strap pin of the chip. In other embodiments, the radar chip further includes a ROM containing boot code, which can determine whether the chip is a slave chip based on the level of the Strap pin of the chip. By selecting the master or slave chip based on the level of an external pin, any chip can be designated as a master chip or a slave chip, providing good scalability.

[0073] In an exemplary embodiment, the second connection unit uses the first SERDES configuration parameters to obtain data from the first chip based on SERDES technology; the second processing unit determines whether the data is a bootloader or a command to boot from Flash. If the data is a bootloader, booting is performed based on the bootloader; if the data is a command to boot from Flash, the program to boot from Flash is executed. If booting from Flash fails, a failure report is sent to the first chip, and the chip waits for the first chip to send the bootloader. This chip can obtain a bootloader from Flash or obtain a bootloader from the first chip (i.e., the main chip), providing flexible booting options.

[0074] In an exemplary embodiment, the second processing unit is further configured to perform one or more of the following checks on the received bootloader: correctness of the magic number, address check, length check, hash check, and security check. If the check is successful, the bootloader is run; if the check fails, a check failure message is sent back to the first chip. Through the above checks, the correctness of the data can be guaranteed.

[0075] In an exemplary embodiment, a second security unit is further included, configured to sign the boot program data sent to the lower-level chip using a private key, encrypt the boot program data using an encryption key, and decrypt and verify the signature on the received boot program data. This enables data transmission with a high level of security, preventing data leakage.

[0076] In an exemplary embodiment, the second processing unit is a second security processing unit, and the chip further includes at least one second application processing unit, used to launch the application when the second security unit decrypts and verifies the signature correctly. By distinguishing between the security processing unit and the application processing unit, the startup process can only be completed by the security processing unit, and the data and operations of cascaded startup are controlled by the security processing unit and cannot be obtained by the application, thereby improving the security of cascaded startup.

[0077] Using the embodiments of this disclosure Figure 1 or Figure 2 The radar chip cascade startup method and radar chip described in any embodiment have the following advantages:

[0078] The relevant parameters and configurations for the high-speed interface are stored in the on-chip non-volatile storage medium (eFUSE, Antifuse, etc.). The parameters can be adjusted according to the calibration scheme, and can be programmed in a certain way or compressed to reduce the size before the chip leaves the factory. The master chip does not need to use a low-speed bus to transmit configuration parameters, which reduces the interconnection between chips and saves the startup time of the master and slave chips.

[0079] The chip's hardware architecture isolates the security domain from the application domain. Cascaded data and computations reside in the security domain, inaccessible to applications. Furthermore, debugging within the security domain can only be performed through a dedicated, authorized security interface. Additionally, the hardware supports various asymmetric algorithms, including AES encryption / decryption, and ensures the security of the key, which is designed to be unreadable by the CPU.

[0080] When the master chip starts up, it can attempt to instruct the slave chip to boot from Flash. If the boot attempt fails, the slave chip then boots from its own secure memory (sent by the master chip). Therefore, in the design of cascaded boards, whether the slave chip has Flash memory offers more flexibility. The master chip sends boot commands or boot data to the slave chip. If the slave chip successfully boots up, its parent chip can be completely released, and the slave chip then becomes the parent chip of the next slave chip, acting as the "master chip." This process continues, reducing the complexity of the transmission design.

[0081] Taking the cascading of two radar chips as an example, one composition is as follows: Figure 3 As shown:

[0082] The cascaded chip described in this embodiment includes: a processing unit, a storage unit, a security unit, and a connectivity unit, wherein:

[0083] The processing unit, such as a CPU, may include a secure CPU and an application CPU. The secure CPU is used to complete the chip's boot process, including the ROM stage and the bootloader stage. The ROM stage boots the bootloader, and the bootloader stage boots the user's application and the application CPU. There may be multiple application CPUs, which are used to execute relevant operations of the application. After the chip powers on, the secure CPU first boots from the ROM and verifies the payload data, which includes the bootloader. If the verification is successful, the bootloader is run. The bootloader is used to start the application and the application CPU. When the current chip is connected to a next-level slave chip, the bootloader is also used to start the next-level slave chip, whose bootloader comes from the slave chip's master chip.

[0084] Storage units include, but are not limited to: ROM (Read Only Memory), SRAM (Static Random Access Memory), and eFUSE (electronic Fuse), among which:

[0085] The ROM contains the chip's boot code. In this example, for the master chip, the boot code in the ROM is used to read the payload from the Flash to enable the master chip to boot. The payload includes the bootloader. For the slave chip, the boot code in the ROM is used to receive the payload transmitted by the master chip through a high-speed interface to enable the slave chip to boot. At this time, the payload is equivalent to the boot data of the next level. The code and data that the master and slave chips boot from the ROM can only be accessed by a secure CPU.

[0086] SRAM includes secure SRAM for secure CPU access and ordinary SRAM for application CPU access. Secure SRAM is used to store the received bootloader and some sensitive data, while ordinary SRAM is used to store user apps and user data.

[0087] eFUSE is a non-volatile storage medium that can only be programmed once. In this example, the eFUSE is used to store PLL (Phase-Locked Loop) related parameters. The PLLs involved include, but are not limited to: Reference PLL, System PLL, and serdes PLL (serializer / deserializer phase-locked loop). The parameters involved in these PLLs include, but are not limited to, configuration parameters of the frequency sweep strategy, frequency division coefficient, frequency locking judgment parameters, time delay parameters, LDO (low dropout linear regulator) parameters, etc. The eFUSE is also used to store calibration configuration parameters of the C2C (Chip to Chip) high-speed interface. The high-speed interface between chips requires the use of serdes. The purpose of serdes configuration parameters is to enable the chips to perform handshake negotiation and ultimately establish a stable transmission path. For example, by adjusting parameters such as pre-emphasis, the receiving chip can obtain a high-quality eye diagram. These parameters can be generated in real time or preset after manual debugging. In this example, the preset SERDES configuration parameters involve multiple aspects such as data rate, signal integrity, clock management, and power management, including but not limited to one or more of the following: Data rate: Characterizes the speed at which SERDES transmits data, usually in Gbps (gigabits per second), such as 10Gbps, 25Gbps, 40Gbps, etc.; Encoding method: Used to ensure correct data transmission and provide a clock recovery mechanism, such as 8B / 10B, 64B / 66B, etc.; Clock management parameters: Used to ensure data synchronization and signal integrity. Integrity parameters include: clock frequency, clock jitter parameters, and clock data recovery (CDR) parameters; power management parameters, used to reduce device power consumption and heat, such as supply voltage, current, and power consumption control; signal integrity parameters, used to ensure signal quality and stability during transmission, such as signal rise time, signal attenuation, and crosstalk; interface type parameters, used to determine how the SERDES unit connects to external devices, such as SFP (Small Form Factor Pluggable Module), QSFP (Quad Form Factor Pluggable Module), and CFP (Cross Form Factor Pluggable Module) interface types; and bit error rate (BER), used to measure the accuracy of data transmission. When configuring SERDES, appropriate parameters can be selected based on the specific application scenario and requirements. For example, in high-speed data center applications, higher data rates and lower BER may be considered; while in embedded systems, power consumption and size may be more important. Different chips have different configuration parameters; by reducing chip differences through measures such as wiring, the configuration parameters of different chips can be kept consistent, thus facilitating chip replacement.

[0088] The security unit is used to encrypt and decrypt data, including one or more encryption algorithm engines, including but not limited to one or more of the following: RSA (asymmetric encryption algorithm), ECC (elliptic curve cryptography), AES (Advanced Encryption Standard) and other algorithm engines, used to decrypt or verify signatures of data transmitted between C2C.

[0089] The connection unit is used to realize communication connections with other modules, such as C2C (Chip to Chip) mode. The connection unit includes a master connection unit (M_C2C) set on the master chip and a slave connection unit (S_C2C) set on the slave chip. M_C2C is the master module, used to connect with the slave module S_C2C. S_C2C is the slave module. The connection unit includes a parallel-to-serial conversion (SERDES) module, which can connect to the chip pins through a set of low-voltage differential signals (including the data transmission differential signal tx and differential signal rx). The parallel-to-serial conversion module includes a serializer and a deserializer, which can convert parallel data into serial data for transmission and serial data into parallel data for reception, thereby realizing high-speed transmission.

[0090] A connection method between a master chip and a slave chip, such as Figure 4 As shown, the master chip's boot process is controlled by chip pins (e.g., Strappin). Strappin connects a chip or device's pin to a specific power supply or signal to configure its function or behavior. Combinations of pulling the pin high or low can select different functional modes; for example, Strappin allows flexible control over whether the chip is in master or slave mode. The Strappin pin signal can be obtained by a secure CPU or read from code embedded in the ROM. The boot code determines whether the chip is a master or slave chip based on the Strappin pin's level to achieve fast boot. To boot, the master chip connects to Flash (non-volatile memory) via an external bus. Flash stores program data such as the bootloader and application. When the slave chip is not connected to Flash, after the master chip boots from Flash, it can send boot data to the slave chip via a connection unit. The slave chip can also actively obtain boot data from the master chip. If the slave chip is connected to Flash, the master chip can decide whether the slave chip boots from Flash or not. Data transmission between the master and slave chips requires encryption and decryption via a secure unit.

[0091] To achieve high-speed transmission and reduce handshake time between chips, embodiments of this disclosure pre-calibrate the configuration parameters of the high-speed interface and store the calibrated configuration parameters in a non-volatile storage medium (e.g., eFUSE) in the storage unit. This allows the master and slave chips to directly use the calibrated configuration parameters for high-speed data transmission. The configuration parameters include, but are not limited to, one or more of the following: data rate, encoding method, clock management parameters, power management parameters, signal integrity parameters, interface type parameters, and bit error rate.

[0092] The cascading of master and slave chips can be achieved by connecting at least two chips to each other via a high-speed interface. This connection can be serial or parallel, and in a serial connection, they can be linked in a ring. The number of chips can be determined based on the specific application scenario. When determining the topology for multiple chips, the wiring arrangement needs to be considered, and appropriate wiring lengths must be determined to ensure signal quality. Figure 5 This is a topology diagram of two cascaded chips. Figure 6 This is a schematic diagram of multiple chips connected in series. Figure 7 This is a schematic diagram of multiple chips connected in series to form a ring. Figure 8 This diagram illustrates a multi-chip parallel connection. The topology shown is merely an example and should not be construed as limiting the scope of this application. In practical applications, various modifications can be made as needed. For different topologies, the data distribution role and transmission direction can be implemented in different ways. Figure 6 Taking the serial connection shown as an example, the main chip can be as follows: Figure 6 As shown, startup data is transmitted to slave chip 1. After slave chip 1 starts up, it becomes the master chip of slave chip 2 and transmits startup data to slave chip 2, and so on. It can be seen that, according to the direction of data transmission, Figure 6 The illustrated scheme involves the master chip actively sending data to the slave chips. Alternatively, as shown in Figure 9, slave chip 2 can actively acquire data from the master chip. After slave chip 2 starts up, it acts as the master chip for slave chip 3, and slave chip 3 can actively acquire data from slave chip 2, and so on. From the perspective of data distribution roles, both schemes involve multiple senders. The data needed by the next-level chip depends only on the previous-level chip. Thus, once the master chip has started slave chip 1, the startup of subsequent chips is independent of the master chip. However, these two schemes can be combined. For example, the master chip can actively send data to slave chip 1, and slave chip 2 can actively acquire data from slave chip 1. This disclosure does not limit this. The data transmission direction can be selected according to the actual scenario. In the exemplary embodiment, according to the data transmission role, the master chip can send data to all slave chips upon startup. The master chip then distributes the data to slave chip 1, slave chip 2, etc. In this case, there is only one data distributor. The advantage of this scheme is that the sending logic is simple, centralized, and easy to maintain.

[0093] For chip cascading, the slave chip can be booted by the master chip issuing a boot command from the Flash memory, or by the strappin. In scenarios where the slave chip has no external Flash memory and the master chip issues the boot command, the process for the slave chip to obtain boot data from the master chip is as follows: Figure 10 As shown, it includes the following steps:

[0094] Step 1.1: The master chip sends a command to boot from Flash to slave chip 1;

[0095] Specifically, the security CPU of the main chip sends a command to the security CPU of the slave chip to boot from Flash.

[0096] Step 1.2: Determine from chip 1 whether the boot from Flash was successful. If so, notify the main chip that the boot was successful and proceed with the normal process. If it fails, notify the main chip that the boot failed and proceed with step 3.

[0097] According to the general process, chip 1 first attempts to initialize the Flash driver and read the payload from the Flash to start. At this time, the chip is not connected to the Flash, so the Flash startup fails. The chip's security CPU determines that the Flash startup has failed and then reports the startup failure to the main chip.

[0098] Step 1.3: After receiving feedback from slave chip 1, the master chip determines if the startup fails and initiates the data transmission process, sending the data required for startup to slave chip 1 through signature and encryption.

[0099] The encrypted data includes at least the data required for startup, such as the bootloader, and the signature can be used to verify the authenticity and integrity of the encrypted data from chip 1.

[0100] Step 1.4: After receiving data from chip 1, the data is verified. Chip 1 determines whether the verification is successful. If it is successful, the main chip is notified that the data reception was successful and the normal startup process is executed according to the received data. If it fails, the main chip is notified that the data reception failed and step 1.5 is executed.

[0101] Step 1.5: After receiving feedback from slave chip 1, the master chip determines if data reception has failed and restarts the data transmission process, then sends the required data to the slave chip again.

[0102] Once chip 1 has successfully booted up, it can act as the master chip for chip 2 and repeat the above process. Figure 10 The process shown is such that chip 1 is the master chip in the above process, and chip 2 is the slave chip 1 in the above process. This continues until all slave chips have finished starting up.

[0103] Figure 11 The data transmission flowchart for cascaded chips includes the following steps:

[0104] Step 2.1: The master chip sends the data packet header and data to the slave chip;

[0105] Step 2.2: Obtain data and data packet header from the chip, and determine whether the Magic number is correct. If correct, proceed to step 2.3; otherwise, proceed to step 2.7.

[0106] The master and slave chips interact by reading and writing data packet headers at fixed addresses. The master chip writes a magic number (a pre-defined magic number) at the beginning of the data packet or at a specific position. The slave chip clears the magic number upon receiving the packet and returns a success message. One possible format for the data packet header is: address + length + 32-byte hash value + success flag + magic number. The magic number can be used to identify or characterize file type or format, data structure, or protocol; the magic number can be a predefined fixed value.

[0107] Step 2.3: Check the address and length of the data packet from the chip to determine if the address and length are correct. If correct, proceed to step 2.4; otherwise, proceed to step 2.7.

[0108] Step 2.4: Perform a hash check on the chip to verify the integrity of the data. If correct, proceed to step 2.5; otherwise, proceed to step 2.7.

[0109] Step 2.5: Perform a security check on the chip to verify whether the data has been tampered with. If correct, proceed to step 2.6; otherwise, proceed to step 2.7.

[0110] Step 2.6: Read the bootloader from the data and run it;

[0111] Step 2.7: Clear the Magic number and send a verification failure message to the main chip;

[0112] Step 2.8: After receiving feedback from the slave chip, the master chip reads and checks the feedback data packet. If the Magicnumber is cleared and the verification is successful, the process ends; otherwise, it returns to step 2.1 and resends the data packet header and data to the slave chip.

[0113] The magic number check, address and length check, hash verification, and security check in the above process are all used to ensure the correctness of the transmitted data. In other embodiments, the above checks may be performed only in certain parts.

[0114] The following describes the boot process of the master chip and slave chip using a cascaded two-chip boot process as an example.

[0115] The master chip's boot process includes a ROM stage and a bootloader stage, while the slave chip only has a ROM stage. The ROM stage involves actions fixed within the chip, which can only be modified by re-faking the chip. In this example, the master chip's initialization parameters and boot data are sourced from Flash storage. The master chip completes the initialization of the master connection unit (i.e., the aforementioned M_C2C) and data transfer with the slave chip during the bootloader stage, which offers better robustness compared to completing it in the ROM stage.

[0116] The main chip boot process is as follows Figure 12 As shown, it includes:

[0117] Step 3.1: After the main chip is powered on, the boot code embedded in the ROM is executed;

[0118] Step 3.2: Receive the Strappin signal, which indicates that the current chip is in master chip mode;

[0119] The master / slave mode of the chip is determined by the strappin signal. The chip designated as the master needs to be connected to the Flash storage medium.

[0120] Step 3.3, Initialize the system phase-locked loop (PLL);

[0121] Phase-locked loops (PLLs) are used to provide the clock signal and to synchronize the time of various modules within the radar chip. Before enabling chip cascading, the necessary PLLs must be initialized and locked, including but not limited to: the system PLLs used by the CPU and bus, and the PLLs used by the SERDES high-speed data transmission interface.

[0122] Step 3.4: Flash driver initialization, reading the bootloader from Flash;

[0123] Then it enters the bootloader stage;

[0124] Step 3.5, Bootloader startup phase;

[0125] Step 3.6, Initialize the connection unit;

[0126] The connection unit initialization includes SERDES PLL initialization and M_C2C initialization. SERDES PLL provides the clock signal for SERDES, serving as the high-speed clock for inter-chip data communication. M_C2C initialization includes the initialization of both analog and digital SERDES. The analog SERDES is used for high-speed analog signal transmission between chips, while the digital SERDES correctly converts analog signals into digital signals and parses them into the correct encoding.

[0127] The C2C configuration parameters are obtained in advance through a calibration procedure, and the configured parameters are then written into the eFUSE using ATE (automatic test equipment) or other methods.

[0128] Step 3.7: Handshake with the slave chip and determine whether it is successful. If successful, proceed to the next step. If unsuccessful, return to this step to continue the handshake.

[0129] The master chip uses pre-calibrated C2C parameters to handshake with the slave chip. A successful handshake is required for data transmission to proceed with cascading startup. The master and slave chips only need to perform a single handshake. Specifically, the master and slave chip connection units are pre-calibrated, including but not limited to serdes pll parameter calibration and M_C2C master connection unit initial parameter calibration. The calibrated parameters are stored in eFUSE. The handshake between the master and slave chips can directly use the configuration parameters in eFUSE, enabling high-speed data transmission during the handshake process and allowing for rapid completion.

[0130] Step 3.8: Read the bootloader from Flash and send it to the slave chip via the connection unit;

[0131] Key pairs are pre-generated according to user instructions, including a private key and a public key, as well as an encryption key and a decryption key. The private key is used by the main chip to sign the bootloader data, and the public key is used by the slave chip to verify the signature. The encryption key is used by the main chip to encrypt the bootloader data; the encryption key depends on the encryption algorithm used. When using AES, the encryption key is an AES key. The signed and encrypted bootloader data is stored in Flash memory for the main chip to read. The decryption key is used by the slave chip to decrypt the data. Since the slave chip needs both the public and decryption keys, they are encrypted and stored in the slave chip's non-volatile memory (such as an eFUSE) after generation. For example, the public key can be hashed or encrypted using other methods and then stored in the eFUSE. Similarly, the decryption key is also stored in the eFUSE. A read-write lock can be applied to the decryption key via hardware, meaning the CPU cannot read the decryption key from the eFUSE; the decryption key can only be accessed directly by the security unit. For example, if the encryption algorithm uses AES, the decryption key is an AES key and can only be accessed directly by the AES decryption engine. Depending on the security level, data can be encrypted with a single AES (or other symmetric encryption algorithms) or signed with a single signature (or other asymmetric algorithms).

[0132] Step 3.9: After the main chip decrypts and verifies the signature of the application, the application is started, and the process ends.

[0133] The order of steps 3.9 and 3.8 above is not limited.

[0134] From the chip boot process, such as Figure 13 As shown, it includes:

[0135] Step 4.1: After the chip is powered on, the boot code embedded in the ROM is executed;

[0136] Step 4.2: Receive the Strappin signal, which indicates that the current chip is in slave mode;

[0137] Step 4.3, Initialize the system phase-locked loop (PLL);

[0138] Step 4.4, Initialize the connection unit;

[0139] The connection unit initialization includes SERDES PLL initialization and S_C2C initialization. SERDES PLL provides the clock signal for SERDES, serving as the high-speed clock for inter-chip data communication. S_C2C initialization includes the initialization of both analog and digital SERDES. The analog SERDES is used for high-speed analog signal transmission between chips, while the digital SERDES correctly converts analog signals into digital signals and parses them into the correct encoding.

[0140] The C2C configuration parameters are obtained in advance through a calibration procedure, and the configured parameters are then written into the eFUSE using ATE (automatic test equipment) or other methods.

[0141] Step 4.5, Bootloader startup phase;

[0142] Step 4.6: Handshake with the main chip and determine if it is successful. If successful, proceed to the next step; otherwise, return to this step to continue the handshake.

[0143] The slave chip uses pre-calibrated C2C parameters to handshake with the master chip. Successful handshake is required for data transmission to proceed with cascading startup. Specifically, the slave chip's connection unit and the master chip's connection unit undergo pre-calibration of parameters, including but not limited to serdes pll parameter calibration and S_C2C master connection unit initial parameter calibration. The calibrated parameters are stored in eFUSE. The handshake between the slave chip and the master chip can directly utilize the configuration parameters in eFUSE, enabling high-speed data transmission during the handshake process and allowing for rapid completion.

[0144] Step 4.7: Determine whether the data received from the main chip is startup data or a command. If it is startup data, proceed to step 4.8; if it is a command, proceed to step 4.12.

[0145] Step 4.8: After receiving the data transmitted at high speed via the C2C bus from the chip, perform one or more checks on the data, such as hash verification to ensure data integrity, or execute other checks. Figure 11 The process shown;

[0146] Step 4.9: The security element (e.g., the AES engine) obtains the public key and decryption key from eFUSE;

[0147] Step 4.10: Decrypt the received data using AES from the chip, then verify the signature using the public key. Only data that passes the signature verification is considered legitimate, and then proceed to step 4.11.

[0148] If a decryption or signature verification error occurs, the process will exit directly, notifying the main chip of the data error. Upon receiving the failure feedback, the main chip needs to retransmit the data. The detailed interaction process is as follows: Figure 10 As shown.

[0149] Step 4.11, run the bootloader;

[0150] Step 4.12: Receive the command to boot from Flash. If Flash initialization fails, notify the main chip and return to step 4.7 to continue waiting for the command. If Flash initialization is successful, start the bootloader.

[0151] The radar chip described in this embodiment can be a millimeter-wave radar chip.

[0152] The electromagnetic waves in this disclosure may include radio waves and light waves. Radio waves include shortwave, medium wave, long wave and microwave, etc. Microwaves include centimeter waves (i.e. electromagnetic waves of 3 GHz to 30 GHz, such as electromagnetic waves of 3.1 GHz to 10.6 GHz, electromagnetic waves in the 24 GHz band, etc.) and millimeter waves (i.e. electromagnetic waves of 30 GHz to 300 GHz, such as electromagnetic waves in the 60 GHz band, electromagnetic waves in the 77 GHz band (such as electromagnetic waves in the 77 GHz to 81 GHz band, etc.)). Light waves may include ultraviolet light, visible light, infrared light and laser, etc., wherein the electromagnetic wave frequency band of laser is (3.846 to 7.895)*10^5 GHz, that is, laser is included in part of the frequency band of ultraviolet light and visible light.

[0153] This disclosure also provides an integrated circuit, which may include: a signal transmitting module configured to transmit electromagnetic waves for target detection; a signal receiving module configured to receive echoes formed by reflection and / or scattering of the electromagnetic waves; and a processing module configured to perform signal and data processing on the echoes to achieve target detection. The target detection may include, for example, at least one of the following operations on a target in a region of interest: determination, localization, and / or identification.

[0154] In an exemplary embodiment, the integrated circuit may be a millimeter-wave radar chip (or die).

[0155] Optionally, the integrated circuit may be an AiP (Antenna-In-Package) chip structure, an AoP (Antenna-On-Package) chip structure, or an AoC (Antenna-On-Chip) chip structure.

[0156] According to other embodiments of this disclosure, an electromagnetic wave sensor (such as a radar sensor) is also proposed. This electromagnetic wave sensor may include an antenna and an integrated circuit as described above. The integrated circuit is electrically connected to the antenna and is used to transmit and receive electromagnetic wave signals. For example, the electromagnetic wave sensor may include: a carrier, an integrated circuit as described in any of the above embodiments, and an antenna, etc. The integrated circuit may be disposed on the carrier; the antenna may be disposed on the carrier, or integrated with the integrated circuit as a single device disposed on the carrier (i.e., the antenna may be an antenna disposed in an AiP, AoP, or AoC structure); wherein the integrated circuit is connected to the antenna (i.e., the sensing chip or integrated circuit does not integrate an antenna, such as a conventional SoC), and is used to transmit and receive electromagnetic wave signals. The carrier may be a printed circuit board (PCB), and the corresponding transmission line may be a PCB trace.

[0157] This disclosure provides a terminal device, which may include: a device body; and an electromagnetic wave sensor as described above disposed on the device body; wherein the electromagnetic wave sensor is used for target detection and / or communication to provide reference information for the operation of the device body.

[0158] This disclosure also provides an electronic device (which can be understood as a terminal device), which can be manifested in the form of a general computing device. The components of the electronic device may include, but are not limited to: at least one processing unit, at least one storage unit, a bus connecting different system components (including the storage unit and the processing unit), a display unit, etc. The storage unit stores program code, which can be executed by the processing unit to cause the processing unit to perform the methods described in this specification according to the various exemplary embodiments of this disclosure. The storage unit may include a readable medium in the form of volatile storage units, such as random access memory (RAM) and / or cache memory units, and may further include read-only memory (ROM).

[0159] The storage unit may also include a program / utility having a set (at least one) of program modules, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0160] A bus can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus that uses any of the various bus structures.

[0161] The electronic device can also communicate with one or more external devices (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other computing devices (e.g., routers, modems, etc.). This communication can be performed via input / output (I / O) interfaces. Furthermore, the electronic device can communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter. The network adapter can communicate with other modules of the electronic device via a bus. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0162] For example, the electronic device in this embodiment may further include: a device body; and an electromagnetic wave sensor disposed on the device body as described in any of the above embodiments; wherein the electromagnetic wave sensor can be used to realize functions such as target detection and / or wireless communication.

[0163] Based on the above embodiments, in one optional embodiment of this disclosure, the electromagnetic wave sensor can be disposed outside the device body or inside the device body. In other optional embodiments of this disclosure, the electromagnetic wave sensor can be partially disposed inside the device body and partially disposed outside the device body. This disclosure does not limit the scope of the embodiments and may be determined as appropriate.

[0164] In an optional embodiment, the aforementioned device body can be a component or product applied in fields such as smart cities, smart homes, transportation, smart homes, consumer electronics, security monitoring, industrial automation, in-cabin detection (such as smart cockpits), medical devices, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments for detecting vital signs parameters and various devices equipped with such instruments, such as in-cabin vital sign detection in automobiles, indoor personnel monitoring, smart medical devices, and consumer electronic devices.

[0165] This disclosure also provides a non-transitory computer-readable storage medium storing computer-readable instructions that, when executed by a processor, cause the processor to perform the feeder unequal length compensation method described above.

[0166] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. The technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the methods described above according to the embodiments of this disclosure.

[0167] Software products may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example,, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0168] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0169] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing devices can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0170] The aforementioned computer-readable medium carries one or more programs, which, when executed by a device, cause the computer-readable medium to perform the aforementioned functions.

[0171] Those skilled in the art will understand that the above modules can be distributed in the device as described in the embodiments, or they can be modified accordingly and placed in one or more devices that are unique to this embodiment. The modules in the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0172] According to embodiments of this disclosure, a computer program is proposed, including a computer program or instructions, which, when executed by a processor, can perform the methods described above. In an optional embodiment, the integrated circuit described above can be a millimeter-wave radar chip. The types of digital functional modules in the integrated circuit can be determined according to actual needs. For example, in a millimeter-wave radar chip, the data processing module can be used for operations such as range Vidopler transformation, velocity Vidopler transformation, constant false alarm rate detection, direction of arrival detection, point cloud processing, etc., to acquire information such as the target's range, angle, velocity, height, micro-Doppler motion characteristics, shape, size, surface roughness, and dielectric properties.

[0173] It should be noted that electromagnetic wave sensors can achieve functions such as target detection and / or communication by transmitting and receiving electromagnetic wave signals, so as to provide the device body with target detection information and / or communication information, thereby assisting or even controlling the operation of the device body.

[0174] For example, when the aforementioned equipment is applied to an advanced driver assistance system (ADAS), wireless devices (such as millimeter-wave radar) used as vehicle sensors can assist the ADAS system in realizing application scenarios such as adaptive cruise control, automatic braking assist (AEB), blind spot detection warning (BSD), lane change assist warning (LCA), rear cross traffic alert (RCTA), parking assist, rear vehicle warning, collision avoidance, pedestrian detection, and cabin liveness detection (CPD).

[0175] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0176] The above-described embodiments merely illustrate preferred embodiments of the present invention and the technical principles employed. While the descriptions are detailed, they should not be construed as limiting the scope of the invention. Various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the inventive concept, and the scope of protection of this patent is determined by the appended claims.

[0177] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A radar chip cascade startup method, characterized in that, Applicable to a first chip, the method includes: After receiving the boot command, the first chip obtains the boot program from the external Flash and starts the boot process; The first chip uses the first SERDE configuration parameters to handshake with the second chip based on SERDE technology. The second chip is a chip connected to the first chip. The first chip uses the first SERDE configuration parameters to transmit the boot program to the second chip based on SERDE technology for the second chip to start.

2. The method according to claim 1, characterized in that, Before the first chip receives the start command, the method further includes: the first chip determining itself as the main chip based on the level of the Strap pin.

3. The method according to claim 1, characterized in that, Before transmitting the bootloader to the second chip using the first SERDES configuration parameters based on SERDES technology, the method further includes: The first chip uses a private key to sign the bootstrap data and uses an encryption key to encrypt the bootstrap data.

4. The method according to claim 1, characterized in that, After the first chip obtains the boot program from external Flash and starts booting, the method further includes starting the application when the first chip decrypts and verifies that the application is correct.

5. The method according to claim 1, characterized in that, The method further includes the first chip sending a Flash boot command to the second chip, and after receiving a Flash boot failure message from the second chip, transmitting a boot program to the second chip using the first serdes configuration parameters based on serdes technology.

6. The method according to claim 1, characterized in that, The first serdes configuration parameters are pre-stored in the first non-volatile storage medium of the first chip.

7. A radar chip cascade startup method, characterized in that, Applicable to a second chip, the method includes: The second chip uses the first SERDE configuration parameters to handshake with the first chip based on SERDE technology, and uses the first SERDE configuration parameters to obtain the boot program from the first chip based on SERDE technology, and implements boot based on the boot program; when there is a lower-level chip, the second chip uses the second SERDE configuration parameters to transmit the boot program to the lower-level chip based on SERDE technology, so that the lower-level chip can boot.

8. The method according to claim 7, characterized in that, Before shaking hands with the first chip, the method further includes: the second chip determining that it is a slave chip based on the level of the Strap pin.

9. The method according to claim 7, characterized in that, The second chip uses the first SERDES configuration parameters to obtain the bootloader from the first chip based on SERDES technology, including: After receiving data from the first chip, the second chip determines whether the data is a boot program or a command to boot from Flash. If the data is a boot program, the second chip starts the boot process based on the boot program. If the data is a command to boot from Flash, the second chip executes the program to boot from Flash. If booting from Flash fails, the second chip reports the failure to the first chip and waits for the first chip to send the boot program.

10. The method according to claim 7, characterized in that, After the second chip obtains the boot program from the first chip, the method further includes: The received bootloader is checked for one or more of the following: the correctness of the Magic Number, address check, length check, hash check, and security check. If the verification is successful, the boot program is run; if the verification fails, a verification failure message is sent back to the first chip.

11. The method according to claim 7, characterized in that, The first SERDE configuration parameters are pre-stored in the second non-volatile storage medium of the second chip.

12. A radar chip, characterized in that, include: The first processing unit is used to obtain the boot program from the external Flash and start the computer after receiving the boot command; as well as The first connection unit is used to handshake with the second chip based on the SERDes technology using the first SERDes configuration parameters, the second chip being a chip connected to this chip, and to transmit the boot program to the second chip based on the SERDes technology using the first SERDes configuration parameters for the second chip to start.

13. The radar chip according to claim 12, characterized in that, It also includes a first non-volatile storage medium for storing the first serdes configuration parameters.

14. The radar chip according to claim 12, characterized in that, It also includes a ROM containing boot code, which determines the chip as the main chip based on the level of the Strap pin of the chip.

15. The radar chip according to claim 12, characterized in that, It also includes a first security unit for signing bootloader data using a private key, encrypting the bootloader data using an encryption key, and decrypting and verifying the received bootloader data.

16. The radar chip according to claim 12, characterized in that, The first processing unit is also configured to send a Flash boot command to the second chip, and, upon receiving a Flash boot failure message from the second chip, transmit the boot program to the second chip using the first serdes configuration parameters based on serdes technology.

17. The radar chip according to claim 12, characterized in that, The first processing unit is a first security processing unit, and the chip further includes at least one first application processing unit for launching the application when the application is decrypted and the signature is verified correctly.

18. A radar chip, characterized in that, include: The second connection unit is used to handshake with the first chip using the first serdes configuration parameters based on serdes technology, and to obtain the boot program from the first chip using the first serdes configuration parameters based on serdes technology. When there is a lower-level chip in this chip, the second serdes configuration parameters are used to transmit the boot program to the lower-level chip based on serdes technology so that the lower-level chip can start. as well as The second processing unit starts up based on the boot program obtained from the first chip.

19. The radar chip according to claim 18, characterized in that, It also includes a second non-volatile storage medium for storing the first serdes configuration parameters and the second serdes configuration parameters.

20. The radar chip according to claim 18, characterized in that, It also includes a ROM containing boot code, which determines whether the chip is a slave chip based on the level of the Strap pin of the chip.

21. The radar chip according to claim 18, characterized in that, The second connection unit uses the first SERDE configuration parameters to obtain data from the first chip based on SERDE technology; The second processing unit determines whether the data is a boot program or a command to boot from Flash. If the data is a boot program, the boot process is implemented based on the boot program. If the data is a command to boot from Flash, the program to boot from Flash is executed. If booting from Flash fails, the unit reports the failure to the first chip and waits for the first chip to send the boot program.

22. The radar chip according to claim 18, characterized in that, The second processing unit is also used to perform one or more of the following checks on the received bootloader: the correctness of the magic number, address check, length check, hash check, and security check. If the check is successful, the bootloader is run; if the check fails, a check failure message is sent back to the first chip.

23. A terminal device, characterized in that, include: Equipment body; as well as The radar chip as described in any one of claims 12-17 or 18-22 is disposed on the device body.

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