Control protection method and control protection system for memory access in many-core system

Abstract

The invention relates to the technical field of memory access protection, and discloses a control protection method and a control protection system for memory access in a many-core system, and the many-core system comprises a host node and a plurality of slave nodes which are interconnected through a network-on-chip; the control protection system is integrated in each slave node and comprises an access restriction register group, an access evaluation unit and an error feedback unit; the access evaluation unit is configured to respond to a received memory access request of a second slave node, determine that the second slave node has access authority and a memory range requested to be accessed by the second slave node is included in a permitted subdivision storage range of the second slave node, and generate an access hit signal; the error feedback unit is configured to trigger access permission when the analysis indicates that the access moments corresponding to the at least two access hit signals are different, or the access moments are the same but the requested memory access ranges are different; therefore, each memory access behavior can be monitored, the memory is protected, and the reliability of the system-on-chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory access protection, for example to a control protection method and system for memory access in a many-core system. BACKGROUND

[0002] With the wide application of multi-core processors and complex system on chip (SoC), memory access security has become a key issue of system reliability. The traditional memory protection unit (MPU) is usually based on a single processor core or bus matrix implementation, such as the MPU integrated in the ARM Cortex-M series, but it can only protect the access initiated by the core, and cannot monitor the illegal access behavior of other master devices (such as DMA, Ethernet controller, etc.) in the system, and there are problems of task interference and data consistency. In recent years, some researchers have proposed a system-level MPU design based on bus matrix. However, this method is still limited to bus matrix architecture and is difficult to extend to more complex network on chip (NoC) interconnection structure.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] To have a basic understanding of some aspects of the disclosed embodiments, a brief overview is given below. The summary is not an overall description of the application, nor is it intended to identify key / important elements or delineate the scope of the embodiments, but to serve as a prelude to the detailed description below.

[0005] The embodiments of the present disclosure provide a method and system for controlling and protecting memory access in a many-core system, which can dynamically monitor the access behavior of different types of nodes in the many-core system to exclude illegal access behavior without access permission, can timely feedback when multiple access tasks interfere, and can solve the problem of interference between multiple nodes of parallel tasks and the resulting data consistency.

[0006] In some embodiments, a control protection system for memory access in a many-core system, the many-core system comprising one master node and a plurality of slave nodes interconnected through an on-chip network; the control protection system integrated in each slave node and comprising: a set of access restriction registers configured to be programmed by the master node to define a set of sub-storage ranges and corresponding access permissions for memory regions of the first slave node; an access evaluation unit communicatively connected to the set of access restriction registers; and an error feedback unit communicatively connected to the access evaluation unit. The access evaluation unit is configured to: in response to receiving a memory access request from a second slave node other than the first slave node in the on-chip network, compare access request information of the access request with the set of sub-storage ranges and access permissions set in the set of access restriction registers, and generate an access hit signal and send to the error feedback unit when it is determined that the second slave node has access permission and the memory range it requests to access is contained in the sub-storage range it is permitted to access. The error feedback unit is configured to: monitor the number of access hit signals received within a first time interval; when at least two access hit signals are received within the first time interval, analyze the at least two access hit signals; and when the analysis indicates that the access time corresponding to the at least two access hit signals is different, or the access time is the same but the requested memory access range is different, trigger the access permission to permit the second slave node to perform memory access.

[0007] In some embodiments, a method for controlling and protecting memory access in a many-core system is provided. The method is applied to a many-core system including host nodes and slave nodes interconnected via an on-chip network. Each slave node is equipped with a control and protection system including an access restriction register set, an access evaluation unit, and an error feedback unit. The method includes the following steps: The host node configures the access restriction register set of each first slave node to define the subdivided storage range and corresponding access permissions of the memory region of each first slave node. When the access evaluation unit of a first slave node receives an access request from a second slave node other than the first slave node in the on-chip network, it compares the access request information of the access request with the settings in the access restriction register set. If it determines that the second slave node has the access permission and the memory range it requests to access is included within its permitted subdivided storage range, it generates an access hit signal and sends it to the error feedback unit. The error feedback unit of the first slave node monitors the number of access hit signals received within a first time interval; when at least two access hit signals are received within the first time interval, the at least two access hit signals are analyzed; and when the analysis shows that the access times corresponding to the at least two access hit signals are different, or the access times are the same but the requested memory access ranges are different, an access permission is triggered to allow the second slave node to perform memory access.

[0008] The memory access control and protection method and system provided in this disclosure for a many-core system involve the host node first programming the access restriction register groups of each slave node to pre-divide the memory regions of each slave node and configure corresponding access permissions. This allows for real-time monitoring of illegal access behavior of each slave node during subsequent on-chip system operation. When a second slave node accesses a first slave node during on-chip system operation, the access evaluation unit of the first slave node first checks the access permissions and memory access range to exclude illegal access behavior of the slave node. The error feedback unit evaluates multiple accesses and feeds back the access behaviors of multiple conflicting slave nodes to the host node, enabling the host node to promptly identify and resolve conflicts. Since multiple conflicting slave nodes fail to access successfully, data consistency issues can be prevented under inter-task interference. Therefore, during the operation of the on-chip system, various memory access behaviors can be monitored, memory can be protected, and the reliability of the on-chip system can be increased.

[0009] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This diagram illustrates the structure of a memory access control and protection system in a many-core system according to an embodiment of the present disclosure. Figure 2 A flowchart illustrating the process of controlling and protecting memory access in a many-core system according to an embodiment of the present disclosure is shown. Figure 3 A flowchart illustrating a method for controlling and protecting memory access in a many-core system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0011] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures, steps, and apparatus may be simplified to simplify the illustrations.

[0012] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The term "multiple" means two or more. In embodiments of this disclosure, the character " / " indicates an "or" relationship between the preceding and following objects. For example, A / B means: A or B. The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0014] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0015] Those skilled in the art will understand that in the methods described in this application and other parts thereof, for example, in the methods of various embodiments, examples, or claims, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The detailed execution order of each step should be determined by its function and possible internal logic. Unless otherwise specified, all steps of this application may be performed sequentially or randomly, preferably sequentially. For example, if the method includes steps A and B, it means that the method may include steps A and B performed sequentially, or it may include steps B and A performed sequentially. For example, if the method may also include step C, it means that step C can be added to the method in any order. For example, the method may include steps A, B, and C, or it may include steps A, C, and B, or it may include steps C, A, and B, etc.

[0016] In this application, open-ended technical features or solutions described using terms such as "containing," "including," or "comprising" do not exclude additional members beyond those listed unless otherwise specified. They can be considered as providing both closed-ended features or solutions comprised of the listed members and open-ended features or solutions that include additional members beyond the listed members. For example, if A includes a1, a2, and a3, it may also include other members or exclude additional members unless otherwise specified. This can be considered as providing both the feature or solution that "A consists of a1, a2, and a3" and the feature or solution that "A includes not only a1, a2, and a3, but also other members."

[0017] The "range" disclosed in this application can be defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of the specific range. Ranges defined in this way can include or exclude endpoints. Any endpoint can be independently included or excluded, and they can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 2000–10000 rpm and 3000–10000 rpm are listed for a specific parameter, it is also expected that ranges of 2000–10000 rpm and 3000–10000 rpm are also included. Furthermore, if minimum range values ​​1 and 2 are listed, and if maximum range values ​​3, 4, and 5 are also listed, then the following ranges are all expected: 1–3, 1–4, 1–5, 2–3, 2–4, and 2–5. In this application, unless otherwise stated, the numerical range "a~b" represents a shortened representation of any combination of real numbers between a and b, where a and b are both real numbers. For example, the numerical range "0~5" means that all real numbers between "0~5" have been listed in this document, and "0~5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is expressed as an integer ≥2, it is equivalent to listing the parameter as, for example, integers 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc. For instance, when a parameter is expressed as an integer selected from "2~10", it is equivalent to listing integers 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0018] In this application, unless otherwise specified, A (e.g., B) means that B is a non-limiting example of A, and it is understood that A is not limited to B.

[0019] This disclosure provides a system for memory access control protection in a many-core system. Figure 1 A structural diagram of a memory access control protection system in a many-core system according to an embodiment of this disclosure is shown. Figure 1 As shown, the many-core system 100 includes a master node 101 and multiple slave nodes 102 interconnected via an on-chip network. The control and protection system 1021 is integrated into each slave node 102 and includes: an access restriction register group 1021-1, which is configured to be programmed by the master node 101 to define the subdivided storage range and corresponding access permissions of the memory region 1022 of the first slave node; an access evaluation unit 1021-2, which is communicatively connected to the access restriction register group 1021-1; and an error feedback unit 1021-3, which is communicatively connected to the access evaluation unit 1021-2.

[0020] The many-core system 100 based on on-chip networking has multiple types of cores, including master nodes 101 and slave nodes 102. The master node 101 can be a command initiating node and can communicate with each slave node 102. The slave nodes 102 can include computing nodes, storage nodes, etc.

[0021] Each slave node 102 includes a memory area 1022, and each slave node 102 is equipped with a control and protection system 1021 so that the master node 101 can perform access control and protection on the memory area 1022 of each slave node 102.

[0022] The master node 101 configures each slave node 102 by programming the access restriction register group 1021-1 of each slave node 102's entry point, so as to achieve overall division and protection of the memory area 1022 of each slave node 102.

[0023] The access evaluation unit 1021-2 is configured to: in response to receiving a memory access request from a second slave node other than the first slave node in the on-chip network, compare the access request information of the access request with the subdivided storage range and access permissions set in the access restriction register group 1021-1, and when it is determined that the second slave node has access permissions and the memory range it requests to access is included in its permitted subdivided storage range, generate an access hit signal and send it to the error feedback unit 1021-3.

[0024] Optionally, the access hit signal includes at least one or a combination of the following information: the node identification information of the second slave node, the access time information of the memory access request, and the requested memory access range information. The access time information may be the time when the second slave node issued the access request.

[0025] The access evaluation unit 1021-2 can communicate with the access restriction register group 1021-1 to obtain the various subdivided storage ranges and access permissions of the memory region 1022, thus understanding the protected range and access permissions.

[0026] By comparing the access request information with each subdivided storage range, it can be determined whether the second slave node has the necessary access permissions. It can also be determined whether the address range accessed by the second slave node falls within the subdivided storage range it is authorized to access. For example, in memory region 1022, the address range accessed by the second slave node is within the address range of the second access area. Once confirmed, an access hit is triggered. By comparing access permissions and access address ranges, illegal access attempts from other slave nodes 102 in the on-chip system can be prevented, thus protecting memory access.

[0027] The error feedback unit 1021-3 is configured to: monitor the number of access hit signals received within a first time interval; analyze the at least two access hit signals when at least two access hit signals are received within the first time interval; and, when the analysis indicates that the access times corresponding to the at least two access hit signals are different, or that the access times are the same but the requested memory access ranges are different, trigger an access permission to allow the second slave node to perform memory access.

[0028] Two access requests made at the same time can trigger access hit signals within a first time interval after access evaluation. The first time interval can be preset and can be set to a short period to detect multiple access requests made at the same time and reduce waiting time. If at least two second slave nodes have different access times or the same access times but different memory access ranges, it indicates that the access behaviors of different access nodes do not conflict.

[0029] If the access evaluation unit 1021-2 evaluates an access hit, it sends a feedback hit signal to the error feedback unit 1021-3. The error feedback unit 1021-3 can analyze the received access hit signal based on timing. If at least two access hit signals are received within the first time interval, an access conflict may occur. Further analysis is then performed. If the access times of the at least two second slave nodes are different, it indicates that no conflict has occurred. If at least two access hit signals are found at the same time, the memory access range of the at least two access hit signals received at the same time is checked. If the memory access ranges of the access requests from the at least two second slave nodes received at the same time are different, it indicates that no access conflict has occurred and no data consistency problem will occur. Only then will these at least two second slave nodes be allowed to access memory.

[0030] Optionally, the access evaluation unit 1021-2 is also configured to directly trigger access permission upon receiving an access hit signal within the first time interval. Since adjacent access hit signals are spaced far apart, the probability of a conflict is low. Directly triggering access permission allows the second slave node to directly access memory, reducing latency.

[0031] By further analyzing multiple access hit signals through the error feedback unit 1021-3, the interference of access tasks of multiple slave nodes 102 of the on-chip system can be identified, ensuring that memory access is carried out without inter-task interference, thus protecting the memory.

[0032] This application designs a control and protection system 1021 for each slave node 102, and configures the memory protection plan for each slave node 102 independently through the master node 101. During actual memory access, the control and protection system 1021 checks the access of the second slave node according to the configured memory protection plan, eliminates illegal access behavior, and can also avoid accessing memory under inter-task interference, thereby avoiding data consistency problems. This forms a dynamic and effective memory protection mechanism during the operation of the on-chip system, increasing the reliability of the on-chip system.

[0033] In some embodiments, the host node 101 is configured to perform configuration by sending control packets to the access restriction register group 1021-1 of each slave node 102, the control packets containing memory address information for defining protected areas and corresponding access permissions.

[0034] The memory regions 1022 of each slave node 102 may be different, and the control packets received by each slave node 102 may also be different. The master node 101 defines the memory address range and access rules that need to be protected for the memory regions 1022 of each slave node 102 by sending the protection scope and access permissions of the specific memory regions 1022 to each slave node 102 respectively.

[0035] Optionally, the access restriction register group 1021-1 of each slave node 102 can be configured with a programmable interface. This allows system software (such as an operating system or security monitoring program) to flexibly and dynamically set protection policies for different memory regions 1022 through the control package, achieving fine-grained and dynamic control over the memory access behavior of multiple slave nodes 102. The control package can also dynamically enable or disable specific regions through the access restriction register group 1021-1 to dynamically adjust the protection functions of specific regions.

[0036] In some embodiments, the subdivided storage range of the memory region 1022 includes one or a combination of the following types: private node access area: an area that grants access rights to one or more designated second slave nodes; private access area: an area that grants access rights only to the local slave node 102 itself; shared access area: an area that grants access rights to both the local slave node 102 and one or more second slave nodes.

[0037] The control package includes the protection scope of memory region 1022, which can be the start and end addresses of the protected area. By dividing the region according to the protected and shared areas, various subdivided storage areas of memory region 1022 can be obtained. For example, memory region 1022 can be divided into a first private node access area, a second private node access area, and a private and shared access area. The first private node access area is mounted on the second slave node of the on-chip system, and the third slave node has access rights; the second private node access area is mounted on the fourth slave node of the on-chip system, and the fifth slave node has access rights; the private access area is accessible to the local node; the shared access area is the area that can be accessed by all slave nodes 102 and the local node. The third, fourth, and fifth slave nodes are any one of the slave nodes 102 in the many-core system. The second and third slave nodes can be the same or different, and the fourth and fifth slave nodes can be the same or different. The local node is different from the slave node 102. By distinguishing the protected areas, the private areas can be effectively protected.

[0038] In some embodiments, the process by which the access evaluation unit 1021-2 performs comparison and triggers an access hit signal includes: Based on the node identifier and memory access range contained in the access request information, the access permissions stored in the access restriction register group 1021-1 are compared; After determining that the second slave node has access rights, the requested memory access range is further compared with the subdivided storage range permitted by the node; The access hit signal is triggered only if the requested memory access range is contained within the permitted subdivision of storage.

[0039] Figure 2 A process diagram illustrating the control and protection of memory access in a many-core system according to an embodiment of this disclosure is shown. Figure 2 As shown, the first slave node can obtain the various sub-storage ranges and access permissions of memory region 1022 through access restriction register group 1201-1, or the access restriction register group 1201-1 can send the various sub-storage ranges and access permissions to access evaluation unit 1021-2.

[0040] Upon receiving an access request 201, trigger the process. Figure 2Step 202, access permission comparison. Access evaluation unit 1021-2, by analyzing access request 201, can obtain the node identifier and memory access range of the second slave node. The node identifier can be the ID value of the second slave node; each slave node 102 has a different ID value, thus distinguishing different slave nodes 102. The memory access range can be the address range of memory access. By comparing the node identifier and the access permission, access evaluation unit 1021-2 can determine whether the second slave node is within the range of slave nodes 102 with access permissions.

[0041] After determining that the second slave node has access permissions, proceed to step 203, memory access range verification. Verify whether the memory range accessed by the second slave node is within the sub-storage range it has access to. For example, if the first slave node contains multiple sub-storage ranges, and the second slave node has access permissions to one of these sub-storage ranges, then verify whether the second slave node's memory access range is contained within that sub-storage range. If it is determined to be contained within that sub-storage range, an access hit signal is triggered. After an access hit, proceed to step 204, access conflict determination. If step 204 determines that there is no conflict, the second slave node can proceed to step 206 to access memory.

[0042] The receipt of an access hit signal indicates that the access permissions and access area are both compliant, and the access behavior of the second slave node is a legitimate access behavior. Therefore, the evaluation process of the access evaluation unit 1021-2 of this application can dynamically monitor the access behavior of different types of slave nodes 102 in the on-chip system, achieving fine-grained access control over the memory area 1022 and improving the security of the on-chip system's memory function.

[0043] In some embodiments, the error feedback unit 1021-3 is further configured to: send an error report to the host node 101 when at least two access hit signals are received within the first time interval, and analysis indicates that the access times corresponding to these signals are the same and the memory access ranges are also the same. This situation indicates that two or more second slave nodes access the same memory simultaneously, causing an access conflict, which may lead to data consistency problems. In this case, if... Figure 2 As shown, the error feedback unit 1021-3 of the first slave node enters step 205 and sends an error report. Since the access attempts by the conflicting second slave nodes fail, the master node 101 handles the access conflict event, resolving the data consistency issue in memory region 1022 during the access task conflict.

[0044] In some embodiments, the access evaluation unit 1021-2 is further configured to: trigger an operation-disallowed signal when it is determined that the second slave node does not have access rights; The error feedback unit 1021-3 is also configured to send an error report to the host node 101 when it receives the operation not allowed signal.

[0045] During the evaluation process, the access evaluation unit 1021-2 can first determine whether the second slave node has the necessary permissions. If it does, a permission signal is triggered, and then the access scope can be checked. For example... Figure 2 As shown, if step 202 determines that the user lacks the necessary permissions, the process proceeds directly to step 205, where an error report is sent. This allows for timely detection of unauthorized access, eliminating the need for access scope checks, reducing circuit power consumption, and improving system performance.

[0046] In some embodiments, the access evaluation unit 1021-2 is further configured to: trigger an access miss signal when it is determined that the memory access range of the second slave node exceeds or is different from its permitted subdivided storage range; The error feedback unit 1021-3 is also configured to send an error report to the host node 101 when it receives the access miss signal.

[0047] Even if the second slave node has access permissions, but the desired address range includes not only the sub-storage range it has access to but also other sub-storage ranges it does not have access to, or the address range it wants to access is different from the sub-storage range it has access to, this will still be classified as unauthorized access. Figure 2 As shown, after step 203 determines that the access was not successful, the error feedback unit 1021-3 will proceed to step 205 and send an error report. This can eliminate illegal access behavior with an unreasonable access range.

[0048] like Figure 2 As shown, step 205 is triggered in cases of insufficient permissions, access miss, and access conflict. Memory access is only permitted when all three conditions are met, and the three checks can be performed sequentially, which can reduce system power consumption and improve system performance.

[0049] In some embodiments, the error report sent by the error feedback unit 1021-3 to the host node 101 includes one or a combination of the following information: node identification information of the second slave node that initiated the access request, node identification information of the first slave node that received the request, and access request information that triggered the error.

[0050] Error feedback unit 1021-3 collects error information and reports it to host node 101 so that host node 101 can know the error situation and take corrective measures, such as sending a re-access message to the second slave node.

[0051] This disclosure also provides a method for memory access control and protection in a many-core system. The method is applied to a many-core system comprising host nodes and slave nodes interconnected via an on-chip network, wherein each slave node is equipped with a control and protection system including an access restriction register set, an access evaluation unit, and an error feedback unit. Figure 3 A flowchart illustrating a method for controlling and protecting memory access in a many-core system according to an embodiment of this disclosure is provided. Figure 3 As shown, the method includes the following steps.

[0052] In step 301, the host node configures the access restriction register group of each first slave node to define the subdivided storage range of the memory region of each first slave node and the corresponding access permissions.

[0053] In step 302, when the access evaluation unit of the first slave node receives an access request from a second slave node other than the first slave node in the on-chip network, it compares the access request information of the access request with the settings in the access restriction register group; when it determines that the second slave node has access rights and the memory range it requests to access is included in its permitted subdivided storage range, it generates an access hit signal and sends it to the error feedback unit.

[0054] In step 303, the error feedback unit of the first slave node monitors the number of access hit signals received within the first time interval; when at least two access hit signals are received within the first time interval, the at least two access hit signals are analyzed; and when the analysis shows that the access times corresponding to the at least two access hit signals are different, or the access times are the same but the requested memory access ranges are different, an access permission is triggered to allow the second slave node to perform memory access.

[0055] The control and protection system of this application checks the access of the second slave node according to the configured memory protection plan, eliminates illegal access behavior, and can also avoid accessing memory under inter-task interference, thereby avoiding data consistency problems. This forms a dynamic and effective memory protection mechanism during the operation of the on-chip system, increasing the reliability of the on-chip system.

[0056] In some embodiments, when the error feedback unit receives at least two access hit signals within the first time interval, and analysis indicates that the access times corresponding to these signals are the same and the memory access ranges are also the same, it sends an error report to the host node.

[0057] In some embodiments, the access evaluation unit triggers an operation-disallowed signal when it determines that the second slave node does not have access rights. The error feedback unit sends an error report to the host node when it receives the operation not allowed signal.

[0058] In some embodiments, the access evaluation unit triggers an access miss signal when it determines that the memory access range of the second slave node exceeds or differs from its permitted subdivided storage range. The error feedback unit is further configured to send an error report to the host node when it receives the access miss signal.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A memory access control and protection system in a many-core system, characterized in that, The many-core system includes a master node and multiple slave nodes interconnected via an on-chip network; The control and protection system is integrated into each slave node and includes: An access restriction register set, which is configured to be programmed by the host node to define the subdivided storage ranges and corresponding access permissions of the memory region belonging to the first slave node; Access evaluation unit, whose communication is connected to the access restriction register set; and An error feedback unit, which is communicatively connected to the access evaluation unit; The access evaluation unit is configured to: in response to receiving a memory access request from a second slave node other than the first slave node in the on-chip network, compare the access request information of the access request with the subdivided storage range and access permissions set in the access restriction register group, and when it is determined that the second slave node has access permissions and the memory range it requests to access is included in its permitted subdivided storage range, generate an access hit signal and send it to the error feedback unit. The error feedback unit is configured to: monitor the number of access hit signals received within a first time interval; analyze the at least two access hit signals when at least two access hit signals are received within the first time interval; and trigger an access permission to allow the second slave node to perform memory access when the analysis indicates that the at least two access hit signals correspond to different access times, or the access times are the same but the requested memory access ranges are different.

2. The control and protection system according to claim 1, characterized in that, The host node is configured to perform the configuration by sending control packets to the access restriction register groups of each slave node. The control packets contain memory address information for defining the protected area and the corresponding access permissions.

3. The control and protection system according to claim 1, characterized in that, The process by which the access evaluation unit performs comparison and triggers an access hit signal includes: The node identifier and memory access range contained in the access request information are compared with the access permissions stored in the access restriction register group; After determining that the second slave node has access rights, the requested memory access range is further compared with the subdivided storage range permitted by the node; The access hit signal is triggered only if the requested memory access range is contained within the permitted subdivision of storage.

4. The control and protection system according to claim 1, characterized in that, The error feedback unit is also configured to: When at least two access hit signals are received within the first time interval, and analysis shows that the access times corresponding to these signals are the same and the memory access ranges are also the same, an error report is sent to the host node.

5. The control and protection system according to claim 3, characterized in that, The access evaluation unit is also configured to: When it is determined that the second slave node does not have access rights, an operation-disallowed signal is triggered; The error feedback unit is also configured to: Upon receiving the operation-disallowed signal, an error report is sent to the host node.

6. The control and protection system according to claim 3, characterized in that, The access evaluation unit is also configured to: When it is determined that the memory access range of the second slave node exceeds or differs from its permitted subdivided storage range, an access miss signal is triggered; The error feedback unit is also configured to: Upon receiving the access failure signal, an error report is sent to the host node.

7. The control and protection system according to claim 1, characterized in that, The subdivided storage range of the memory region includes one or a combination of the following types: Private Node Access Zone: The area that grants access permissions to one or more specified second slave nodes; Private access zone: A zone that is granted access permissions only to the local slave node itself; Shared access zone: The zone that grants access permissions to the local slave node and one or more second slave nodes.

8. The control and protection system according to any one of claims 4, 5, or 6, characterized in that, The error report sent by the error feedback unit to the host node includes one or a combination of the following information: node information of the second slave node that initiated the access request, node information of the first slave node that received the request, and access request information that triggered the error.

9. A memory access control and protection method for many-core systems, characterized in that, The method is applied to a many-core system including a master node and slave nodes interconnected via an on-chip network, wherein each slave node is equipped with a control and protection system including an access restriction register set, an access evaluation unit, and an error feedback unit; the method includes: The host node configures the access restriction register group of each first slave node to define the subdivided storage range of the memory region of each first slave node and the corresponding access permissions; When the access evaluation unit of the first slave node receives an access request from a second slave node other than the first slave node in the on-chip network, it compares the access request information of the access request with the settings in the access restriction register group; when it determines that the second slave node has access rights and the memory range it requests to access is included in its permitted subdivided storage range, it generates an access hit signal and sends it to the error feedback unit. The error feedback unit of the first slave node monitors the number of access hit signals received within a first time interval; when at least two access hit signals are received within the first time interval, the at least two access hit signals are analyzed; when the analysis shows that the access times corresponding to the at least two access hit signals are different, or the access times are the same but the requested memory access ranges are different, an access permission is triggered to allow the second slave node to perform memory access.

10. The control and protection method according to claim 9, characterized in that, The method further includes: When the error feedback unit receives at least two access hit signals within the first time interval, and analysis shows that the access times corresponding to these signals are the same and the memory access ranges are also the same, it sends an error report to the host node.

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