Load balance graph convolutional neural network accelerator architecture based on FPGA

Abstract

The invention discloses a load balance graph convolutional neural network accelerator architecture based on an FPGA (Field Programmable Gate Array). The architecture is established on the basis of a node renumbering algorithm, focuses on optimization of load balancing, data sharing, data storage and the like, supports various dynamic scheduling of load balancing, and realizes collaborative optimization of calculation efficiency and energy efficiency ratio. According to the architecture, an aggregation process and a combination process are separated, and special hardware modules are respectively designed, so that the calculation efficiency is effectively improved. Besides, the architecture also supports dynamic scheduling and resource allocation, can adaptively adjust the use of hardware resources according to different GCN tasks, further improves the utilization rate of the hardware resources, reduces the consumption of the hardware resources and the data processing delay, and has strong practicability.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence hardware accelerators, and more particularly to an FPGA-based load-balanced graph convolutional neural network accelerator architecture. Background Technology

[0002] In the real world, much data naturally exhibits graph structure characteristics. For example, user relationships in social networks, road connections in transportation networks, and protein interactions in biological networks can all be represented using graph structures. Graph structure data can not only describe relationships between entities but also reveal hidden patterns and laws in complex systems. Therefore, how to effectively analyze and mine the information contained in graph structure data has become an important topic of common concern in academia and industry. To overcome the limitations of traditional deep learning frameworks in processing graph structure data, Graph Neural Networks (GNNs) emerged. Graph Neural Networks are a class of deep learning models specifically designed for processing graph structure data, capable of directly transmitting information and extracting features on the graph structure. Graph Convolutional Neural Networks (GCNs) are the pioneering work of graph neural networks, establishing the basic architecture and computational paradigm of graph neural networks. By introducing graph convolution operations, GCNs extended the ideas of convolutional neural networks to graph structure data, laying the foundation for subsequent graph neural network research. As research deepens, more and more variants of graph neural networks have been proposed, such as graph attention networks (GAT), graph autoencoders (GAE), and graph generative networks (GraphGAN). These models have achieved significant results in fields such as social network analysis, recommender systems, chemical molecule modeling, and intelligent transportation. Graph neural networks have demonstrated broad application prospects in practical production activities. For example, in chemical molecule structure analysis, graph neural networks are used to predict protein properties and infer molecular structures, providing important support for new drug development and materials design; in the field of human-computer interaction, graph neural networks promote the development of intelligent interactive systems by modeling and recognizing human movements; in the field of intelligent transportation, graph neural networks can effectively predict traffic flow and road conditions, providing a scientific basis for urban traffic management.

[0003] However, compared to traditional neural networks, graph neural networks exhibit significant irregularities in their computational patterns, leading to substantial challenges in memory access and scheduling. Large-scale graph networks often employ distributed multi-machine computation, with the number of nodes frequently reaching billions or even tens of billions. The transmission of data across geographically dispersed locations results in enormous time and bandwidth consumption. As the scale of graph neural network models and the depth of network layers continue to increase, their computational complexity and resource consumption also increase significantly. Processing large-scale graph data requires higher computing power and storage bandwidth, leading to longer network inference times and increased power consumption. These problems severely restrict the deployment and widespread adoption of graph neural networks in practical applications.

[0004] Currently, mainstream graph neural network (Graph Neural Network) computing platforms primarily rely on Graphics Processing Units (GPUs). GPUs, with their powerful parallel computing capabilities and abundant computing units, can effectively accelerate the computation process of various neural networks. However, for large-scale graph neural networks, the irregular data characteristics (such as sparsity and dynamism) limit the computational efficiency of GPUs. Furthermore, GPU-based computing platforms suffer from high power consumption and large size, making them unsuitable for edge computing and mobile device applications. In contrast, Application-Specific Integrated Circuits (ASICs), as hardware designs optimized for specific algorithms, are better suited to the computational characteristics of graph neural networks. By adapting the hardware structure to the algorithm structure, ASICs can achieve optimization goals such as high speed, low power consumption, and small area. In recent years, researchers have proposed various ASIC accelerator designs for graph neural networks, such as HyGCN and GraphACT. These accelerators significantly improve the computational efficiency of graph neural networks by optimizing data flow, reducing memory access overhead, and increasing computational parallelism.

[0005] The existing HyGCN graph convolutional network accelerator is the first to propose a design concept that separates the aggregation and combination processes, and designs dedicated hardware modules for each of these two stages. This accelerator architecture effectively improves computational efficiency and provides an important reference for subsequent graph neural network accelerator designs. However, existing accelerator designs still face many challenges, such as how to further optimize data locality, how to achieve load balancing, and how to reduce hardware resource overhead. Summary of the Invention

[0006] The technical problem this invention aims to solve is to address the shortcomings of existing GCN accelerators, such as unbalanced loads on various engines and long waiting times for computing units due to uneven graph data. This invention provides an FPGA-based load-balanced graph neural network architecture suitable for collaborative computing in the aggregation and combination phases. This architecture improves the overall operating efficiency of the accelerator through a delay-triggered load balancing strategy.

[0007] The technical solution adopted by this invention to solve its technical problem is: constructing an FPGA-based load balancing graph convolutional neural network accelerator architecture, focusing on optimizing load balancing, data sharing, and data storage, and supporting various dynamic scheduling aspects of load balancing. This is achieved by separating the aggregation and combination processes, and designing dedicated hardware modules for each. The accelerator architecture includes: The aggregation stage engine collects feature information from neighboring nodes and stores the output in a two-level buffer. The two-level buffer reads data from the data into the combination stage engine via four pointers, and then the aggregation result is processed by a neural network layer. AggroPE, the aggregation stage engine, reads data from feature memory, performs irregular multiply-accumulate operations related to node degree through the Unified Media Access Control (MAC) module, and stores node features in the cache for reuse. The Combination Stage Engine (CombPE) reads data from the weighted memory and performs relatively regular multiplication and accumulation operations through multiple MAC modules. Because the aggregation stage takes an unpredictable amount of time, it relies on MAC modules to ensure flexible and efficient operation, and writes the results to memory or the next accelerator. The load-balanced two-level buffer AggroToComb receives the output of the aggregation stage in parallel through a handshake protocol, calculates the storage volume in real time and releases the load balancing signal, and supports four-pointer block reading and fully parallel output.

[0008] Preferably, the aggregation stage engine includes: The feature reading module is used to read node feature data from the feature memory; A unified MAC module, connected to the feature reading module, is used to perform multiplication and accumulation operations on the read node feature data; The data caching module, connected to the feature reading module and the unified MAC module respectively, is used to store node feature data loaded from the feature memory for reuse in subsequent requests; The handshake protocol interface module is used to transmit data via the handshake protocol. The configuration register is used to store the input working mode configuration information when the engine start signal pe start goes high during the aggregation phase, and to release the configuration until the clear signal arrives or the calculation is completed. The state machine control module is connected to the unified MAC module and the configuration register, respectively, and is used to control the state transition of the workflow according to the configuration file.

[0009] Preferably, the combined stage engine includes: The weight reading module is used to read weight data from the weight memory; Multiple MAC modules are connected to the weight reading module and are used to perform multiplication and accumulation operations on the read weight data and the input feature data; The result output module is connected to the plurality of MAC modules and is used to write the result of the multiplication-accumulation operation into memory or the next stage accelerator. The state machine control module is connected to the multiple MAC modules and the result output module respectively, and is used to control the module to work according to the fixed state transition path of "module start → module calculation → module output". The data pathway module is used to realize the transmission and flow of data within the module.

[0010] Preferably, the load balancing two-level buffer includes: The adder group module and the block buffer receive the output of the aggregation stage engine. The block buffer is responsible for storing the output. The adder group module outputs the result to the dual-pointer cluster module. These two modules jointly output to the read block module, which determines the result to be output to the combination stage engine. The pointer controller and the toggle signal controller are responsible for controlling the relevant signals of the two-level buffers. The adder group module is used to receive the output of the aggregation stage engine, determine the corresponding pointer, and establish a path from the result to the dual pointer cluster; The dual-pointer cluster module, connected to the addition group module, is used to point to the corresponding block in the block buffer according to the stored information; The block buffer is used to store the results output by the aggregation stage engine, which are then pointed to by the dual-pointer cluster module and read out subsequently. The read block module is connected to the block buffer and the four-pointer block read module, and is used to output the data in the block buffer according to the reading requirements; The pointer controller is connected to the dual-pointer cluster module and the block buffer, and is used to control the pointing of the dual-pointer cluster and the read / write logic of the block buffer; The flip signal controller is used to coordinate signal inversion control during buffer read and write processes.

[0011] Preferably, the adder module processes the done signal output by AggrPE sequentially through adders to generate a result vector to locate the pointers in the pointer cluster.

[0012] Preferably, the dual-pointer cluster module adopts a pointer cluster working mode to address the irregularities in writing during the aggregation stage. The pointer cluster records information such as column number, starting row number, and number of pointers. Each pointer cluster points to a column in the buffer and is stored with the column number.

[0013] Preferably, the read block module uses four pointers to determine the read block and output it to the read block. The four pointers are responsible for column indication, row indication and other functions respectively. CombPE and AggrPE in the scheduling phase select the corresponding block to read according to their own storage information. The read process follows the four pointer working rules, writes the four blocks pointed to by the four pointers into four blocks, and then locks the corresponding block through the column pointer recorded by each PE and the PE type.

[0014] Preferably, the control module includes a flip signal control module and a pointer control module. The flip signal control module generates a flip signal based on the buffer filling status and triggers the flip to start the combination phase operation after AggrPE completes its current work. The pointer control module updates the four pointers according to the rules.

[0015] Preferably, the load balancing two-level buffer segmentation strategy segments the buffer to adapt to the calculation of PE.

[0016] Preferably, the two-level load balancing strategy is scheduled based on the buffer fill level and adopts a delayed triggering strategy.

[0017] The FPGA-based load-balanced graph convolutional neural network accelerator architecture of this invention has the following advantages: By scheduling the aggregation and combination phase operations of AggroPE, load balancing between the two stages of computation is achieved. The scheduling flip signal is given based on the buffer fill status, and a delayed triggering method is used for flip scheduling. To achieve regularized writing in the aggregation phase, this invention innovatively proposes a writing strategy using adder groups and a dual-pointer cluster. For reading in the combination phase, this invention effectively reduces the bandwidth requirement for reading through a four-pointer design, achieving an efficient reading strategy. These strategies can effectively handle graph neural network computations, achieving efficient graph neural network acceleration through certain scheduling and maximum resource and time reuse. Attached Figure Description

[0018] Figure 1 Graph Convolutional Neural Network Accelerator Architecture Figure 2 AggrPE internal structure and data flow Figure 3 CombPE internal structure and data flow Figure 4 Internal structure diagram of AggrToCombBuffer Detailed Implementation The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] This invention designs a load-balanced graph convolutional neural network accelerator architecture based on FPGA, such as... Figure 1 As shown, it mainly includes three core modules: an aggregation stage engine, a combination stage engine, and a two-level load balancing buffer. Through the scheduling of aggregation and combination stage operations, it achieves load balancing between the two levels of operations, accelerating the computation process of the aggregation and combination stages in the graph convolutional neural network.

[0020] 1) Aggregation Phase Engine Design and Data Flow Control The internal structure and data flow of AggrPE are as follows: Figure 2As shown, it needs to simultaneously accommodate the computational methods of both the aggregation and combination phases. Specifically, data is transmitted via a handshake protocol, ensuring module compatibility and future scalability. The working mode is configured by inputting when the pe_start signal goes high and stored in a register until the clear signal arrives or the AggroPE calculation is completed, at which point the configuration register is released. The module's workflow is controlled by a state machine, implementing different state transition routes based on different configuration files. This allows for separate control of the aggregation and combination phases, ensuring computational flexibility and effectively reducing the waiting time of the computational units.

[0021] 2) Engine design and data flow control in the assembly stage CombPE's internal structure and data flow are as follows: Figure 3 As shown, the implementation of CombPE is relatively simple. Based on the AggrPE module, it omits the register configuration process. The module only has one state transition path: module start, module computation, and module output. The number of times the module computation is repeated is determined by Out_Feature_Width. Due to the deterministic nature of the neural network structure, this configuration is completed when the module is generated.

[0022] 3) Load balancing two-level buffer design and data flow control The internal structure and data flow of AggrToCombBuffer are as follows: Figure 4 As shown, its design is relatively complex, consisting of several parts including an addition group, a pointer cluster, a buffer, a read block, a flip control, and a pointer control. The module receives the output of AggrPE and uses the addition group to determine the corresponding pointer to realize the path from the signal to the pointer cluster. The pointer cluster points to the corresponding block in the buffer according to the stored information and completes the write operation accordingly.

[0023] The module reads blocks determined by four pointers and outputs data from the four blocks to the read block. This is based on the regularity of the combination phase operations. The data in the four blocks is all the required data. The CombPE and AggrPE modules in the scheduling phase select the corresponding blocks to read based on their own storage information. The Flip control module provides corresponding flip signals based on the fill status of the buffer. When all AggrPE modules have completed their current work, the flip signal is executed, and the combination phase operations begin. The Pointer control module updates the four read pointers according to the rules.

[0024] To address the irregularities of writes during the aggregation phase, the dual-pointer cluster module introduces a pointer cluster working mode, enabling regular writes without the need for routing strategies for irregular inputs. Building upon this, to prevent waiting during cross-column writes, this paper innovatively introduces a dual-pointer cluster working mode. Each pointer cluster records the column's corresponding number (colID), starting row number (start_row), and pointer count (pointer_num). Each pointer cluster points to a column in the buffer and is stored using column numbers. The starting row number corresponds to the number of the first row yet to be written, and the pointer count corresponds to the maximum number of blocks allowed to be written to that column, which is also the upper limit for AggrPE writes. The sum of the pointer counts in both pointer clusters is a constant value equal to In_parallel. This dual-pointer cluster design effectively avoids waiting during cross-column writes.

[0025] In normal cases, the dual-pointer cluster follows these update rules: The pointer cluster retrieves the maximum value of the corresponding addition group, adds it to the original value of start_row, and stores it back in start_row; other registers remain unchanged.

[0026] If a new write pointer exceeds the boundary of a column after a write operation is completed, the excess portion is subtracted and these pointers are assigned to another pointer family. If the other pointer family also exceeds the boundary, the overflow pointer count is added to the remaining pointer count (pointer_remain). When a column is finished being written, the pointer finds the column number of the first column of the last write operation, increments it by one, and declares it as the new column number.

[0027] The read block module is determined by four pointers and outputs the data from the four blocks to the read block. This is based on the regularity of the combination phase operations. The data in the four blocks is all the required data. The CombPE and AggrPE modules in the scheduling phase select the corresponding blocks to read based on their own storage information. The Flip control module provides corresponding flip signals based on the fill status of the buffer. When all AggrPE modules have completed their current work, the flip signal is executed, and the combination phase operations begin. The Pointer control module updates the four read pointers according to the rules.

[0028] In the read design of AggrToCombBuffer, this paper innovatively adopts a four-pointer cluster read strategy while maximizing the utilization of the regularity of the combination phase read. This strategy minimizes the bandwidth requirements of buffer reads while ensuring that the CombPE read is not hindered, and represents the greatest common denominator of the combination phase read logic.

[0029] Given that each node performs a large number of computation rounds during the combination phase, in most cases, the nodes computed by CombPE and the scheduled AggrPE will be limited to different rounds of a single node, with a very low probability of participating in the computation of two nodes. Furthermore, considering that the computation method during the combination phase is fixed, this allows us to use fewer pointers to handle these highly synchronous operations.

[0030] Considering the potential cross-node computations, and taking into account both the general operation of CombPE and the scheduling of AggrPE, a two-row, two-column, four-pointer design is adopted in the read operation design. For clarity, these four pointers are named COL_pointer0, COL_pointer1, comb_Pointer, and a2c_Pointer.

[0031] (1) COL_pointer0: Column pointer, indicating the column in AggrToCombBuffer. Due to the cross-node computation, two column pointers are required here.

[0032] (2) COL_pointer1: Column pointer, indicating a column adjacent to COL_pointer0. The order of the columns pointed to by the two pointers is uncertain, and the order of the two pointers is indicated by a register pointer_first.

[0033] (3) comb_Pointer: row pointer. Since all CombPEs work synchronously, all CombPEs point to the same row, so it is possible to use only one pointer to indicate the blocks required for all CombPEs to be computed.

[0034] (4) a2c_Pointer: Row pointer, where a2c is an abbreviation for aggregate to combination, instructing the scheduled AggrPE to complete the combination phase. As mentioned above, the scheduling of AggrPE is synchronous, so single-pointer row control can also be achieved. However, the synchronization between CombPE and AggrPE requires a relatively long waiting time (the upper limit of the waiting time is the time consumed by Out_Feature_Width multiplication and accumulation operations), which is unacceptable. Therefore, a four-pointer strategy is adopted instead of a three-pointer strategy.

[0035] In the initial stage of the four-pointer read operation, COL_pointer0 is set to 0, COL_pointer1 is set to 1, comb_pointer and a2c_pointer are set to 0, and pointer_first is set to 1. When pointer_first is 1, it indicates that COL_pointer1 precedes COL_pointer0; when pointer_first is 0, it indicates that COL_pointer0 precedes COL_pointer1. The remainder (remaining padding units in AggroToCombBuffer) is 0, at which point read operations cannot be performed, and the system waits for write operations to proceed.

[0036] The write rules in the aggregation phase follow the pointer-to-pointer strategy proposed in the previous section. Based on the scheduling strategy in the previous section, AggrPE in the aggregation phase only needs to make requests and writes. The immediate write request can simplify the design of the judgment logic in the handshake and empty / full detection.

[0037] The read process during the combination phase follows the four-pointer rule, writing the four blocks pointed to by the four pointers into four separate blocks. The corresponding blocks are then locked using the column pointers recorded in each PE and the PE type. This method avoids consuming excessive routing resources in the AggrToCombBuffer. During the combination phase, the CombPE and AggrPE select blocks based on pointers stored in internal registers. COL_pointer0_count and COL_pointer1_count record the number of computation rounds for the column pointed to by the corresponding COL_pointer. This record is updated when the row pointer starts working from 0, including comb_Pointer and a2c_Pointer. The update count corresponds to the number of computation units in the corresponding CombPE working with the corresponding column data and the AggrPE in scheduling mode. When the corresponding COL_pointer_count equals Out_Feature_Width - 1, the calculation for that row is about to end. At this point, it checks if the column pointer is in a scheduled state. If it is, it waits for both comb_Pointer and a2c_Pointer to finish before updating the column pointer. If it is not in a scheduled state, it only needs to wait for comb_Pointer to finish before updating the column pointer. When updating the column pointer, the next pointer is incremented by 2, and the pointer_first register is inverted.

[0038] As a load balancer, AgggrToCombBuffer exhibits significant differences in time and computation content between the two phases. Specifically, for processing a single PE, the aggregation phase requires `node_degree` calculations, processing `MAC_NUM` (number of MACs in the PE) / `In_Feature_Width` (input feature length) nodes per cycle. In the combination phase, the weight matrix size is `In_Feature_Width * Out_Feature_Width` (output feature length). For a single node, this requires `In_Feature_Width` calculations, processing `MAC_NUM` / `Out_Feature_Width` nodes per cycle.

[0039] To accommodate the aforementioned partitioning strategy and ensure the buffer partitioning matches the PE (Process Execution), the buffer is divided into a grid, with each PE's computation filling a portion of it. The size of each grid column should be the minimum partition size required for the aggregation phase. The minimum number of grid cells (i.e., the number of buffer rows) required for the aggregation phase. The definition is as follows.

[0040]

[0041] There is no minimum partition for the combination phase. Calculation can only be performed after all aggregation phase calculations for a node at the current level have been completed. The number of calculations required is Out_Feature_Width / Out_Parallel (CombPE parallelism). There is no explicit requirement for the number of buffer columns, but considering the subsequent use of a dual-pointer cluster design, the number of buffer columns BUFFER_COL should not be less than 2.

[0042] The two-level buffer load balancing strategy schedules based on buffer fill levels. However, considering the potential for excessively frequent flips and significant performance degradation from using only a single critical flip point, this invention employs a delay-triggered load balancing strategy: setting a threshold based on the buffer fill level. At this point, AggrPE is moved to the combinational phase for calculation, reaching the lower bound of the fill. AggroPE is then redirected back to the aggregation phase. To ensure the effectiveness of the above strategy, the upper and lower bounds are filled. , At least the following conditions must be met: (1) The last time it cannot be filled:

[0043] (2) Data cannot be retrieved empty:

[0044] (3) The buffer depth is greater than two columns, and the number of columns is an integer:

[0045] in, It is a positive integer, and Greater than or equal to 2.

[0046] From the formula above, we can derive the upper and lower limits of the fill as follows:

[0047]

[0048] in, To round down, This is for rounding up.

[0049] Because of the scheduling strategy, write operations will not overflow in AggrToCombBuffer. AggrPE uses a two-pointer cluster write strategy to point to the corresponding block and simply shift downwards. However, the CombPE pointer is not easy to determine, and the combination phase requires accessing the entire column, so the number of rounds needs to be calculated. Each node needs to complete In_Feature_Width multiplication and accumulation operations and calculate Out_Feature_Width rounds in each round.

Claims

1. A load-balanced graph convolutional neural network accelerator architecture based on FPGA, used for computational acceleration in the aggregation and combination stages of graph convolutional neural networks, characterized in that, The accelerator architecture includes: The aggregation stage engine collects feature information from neighboring nodes and stores the output in a two-level buffer. The two-level buffer reads data from the data into the combination stage engine via four pointers, and then the aggregation result is processed by a neural network layer. AggroPE, the aggregation stage engine, reads data from feature memory, performs irregular multiply-accumulate operations related to node degree through the Unified Media Access Control (MAC) module, and stores node features in the cache for reuse. The Combination Stage Engine (CombPE) reads data from the weighted memory and performs relatively regular multiplication and accumulation operations through multiple MAC modules. Because the aggregation stage takes an unpredictable amount of time, it relies on MAC modules to ensure flexible and efficient operation, and writes the results to memory or the next accelerator. The load-balanced two-level buffer AggroToComb receives the output of the aggregation stage in parallel through a handshake protocol, calculates the storage volume in real time and releases the load balancing signal, and supports four-pointer block reading and fully parallel output.

2. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 1, characterized in that, The aggregation stage engine includes: The feature reading module is used to read node feature data from the feature memory; A unified MAC module, connected to the feature reading module, is used to perform multiplication and accumulation operations on the read node feature data; The data caching module, connected to the feature reading module and the unified MAC module respectively, is used to store node feature data loaded from the feature memory for reuse in subsequent requests; The handshake protocol interface module is used to transmit data via the handshake protocol. The configuration register is used to store the input working mode configuration information when the engine start signal pe start goes high during the aggregation phase, and to release the configuration until the clear signal arrives or the calculation is completed. The state machine control module is connected to the unified MAC module and the configuration register, respectively, and is used to control the state transition of the workflow according to the configuration file.

3. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 1, characterized in that, The combined stage engine includes: The weight reading module is used to read weight data from the weight memory; Multiple MAC modules are connected to the weight reading module and are used to perform multiplication and accumulation operations on the read weight data and the input feature data; The result output module is connected to the plurality of MAC modules and is used to write the result of the multiplication-accumulation operation into memory or the next stage accelerator. The state machine control module is connected to the multiple MAC modules and the result output module respectively, and is used to control the module to work according to the fixed state transition path of "module start → module calculation → module output". The data pathway module is used to realize the transmission and flow of data within the module.

4. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 1, characterized in that, The load balancing two-level buffer includes: The adder group module and the block buffer receive the output of the aggregation stage engine. The block buffer is responsible for storing the output. The adder group module outputs the result to the dual-pointer cluster module. These two modules jointly output to the read block module, which determines the result to be output to the combination stage engine. The pointer controller and the toggle signal controller are responsible for controlling the relevant signals of the two-level buffers. The adder group module is used to receive the output of the aggregation stage engine, determine the corresponding pointer, and establish a path from the result to the dual pointer cluster; The dual-pointer cluster module, connected to the addition group module, is used to point to the corresponding block in the block buffer according to the stored information; The block buffer is used to store the results output by the aggregation stage engine, which are then pointed to by the dual-pointer cluster module and read out subsequently. The read block module is connected to the block buffer and the four-pointer block read module, and is used to output the data in the block buffer according to the reading requirements; The pointer controller is connected to the dual-pointer cluster module and the block buffer, and is used to control the pointing of the dual-pointer cluster and the read / write logic of the block buffer; The flip signal controller is used to coordinate signal inversion control during buffer read and write processes.

5. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 4, characterized in that, The adder module processes the done signal output by AggrPE sequentially through adders to generate a result vector to locate pointers in the pointer cluster.

6. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 4, characterized in that, To address the irregularities in writing during the aggregation phase, the dual-pointer cluster module employs a pointer cluster working mode. The pointer cluster records information such as column number, starting row number, and number of pointers. Each pointer cluster points to a column in the buffer and is stored with the column number.

7. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 4, characterized in that, The read block module uses four pointers to determine the read block and output it to the read block. The four pointers are responsible for column indication, row indication and other functions respectively. CombPE and AggrPE in the scheduling phase select the corresponding block to read according to their own storage information. The read process follows the four pointer working rules, writes the four blocks pointed to by the four pointers into four blocks, and then locks the corresponding block through the column pointer recorded by each PE and the PE type.

8. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 4, characterized in that, The control module includes a flip control module and a pointer control module. The flip control module generates a flip signal based on the buffer fill status and triggers the flip to start the combination phase operation after AggrPE completes its current work. The pointer control module updates the four pointers according to the rules.

9. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 4, characterized in that, The load balancing two-level buffer segmentation strategy divides the buffer into blocks to adapt to the calculation of PE.

10. The FPGA-based load-balanced graph convolutional neural network accelerator architecture according to claim 4, characterized in that, The two-level load balancing strategy is based on the buffer fill level and uses a delayed triggering strategy.

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