Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises two gate drive circuits which are oppositely arranged, each gate drive circuit comprises a plurality of cascaded shift register units, and each row of sub-pixels respectively receive gate drive signals outputted by the two gate drive circuits; the gate drive circuit comprises a multi-output shift register unit for outputting a plurality of gate drive signals, wherein the plurality of gate drive signals comprise a first to-be-compensated gate drive signal with the lowest potential; the at least one row sub-pixel is connected with a first to-be-compensated gate driving signal, and the gate driving signal is output by the shift register unit connected with the other gate driving circuit at the same time, and the potential of the gate driving signal is higher than that of the first to-be-compensated gate driving signal. According to the embodiment of the invention, the gate driving signals with different potentials are loaded on one row of sub-pixels, so that potential compensation is carried out on the sub-pixel row loaded with the first to-be-compensated gate driving signal, and the display effect is effectively improved.

Description

[0001] This application is a divisional application of Chinese patent application No. 202310327189.4, filed on March 29, 2023, entitled "A display panel, display device and driving method". Technical Field

[0002] This invention relates to the field of display technology, and in particular to a display panel and a display device. Background Technology

[0003] In the field of display technology, pixel arrays, such as those in liquid crystal displays or organic light-emitting diode displays, typically include multiple rows of gate lines and multiple columns of interlaced data lines. Driving the gate lines can be achieved through gate driving circuits, and in particular, through dual-sided gate driving circuits positioned on both sides of the pixel array to simultaneously drive each row of sub-pixels.

[0004] As the demand for resolution increases, the arrangement of sub-pixels on the display substrate becomes denser and denser. However, the display time of a frame remains unchanged, resulting in a relatively reduced charging time for each row of pixels and an insufficient charging rate for each sub-pixel. Therefore, a multi-pulse driving method is used through the gate driving circuit to pre-charge multiple rows of pixels simultaneously.

[0005] However, in actual use, there is uneven display, especially in the middle row of pixels where the brightness is significantly darker. Summary of the Invention

[0006] To solve at least one of the above problems, the first embodiment of the present invention provides a display panel including a display area and a non-display area. The display area includes multiple rows of sub-pixels, and the non-display area includes two gate driving circuits disposed opposite to each other. Each gate driving circuit includes multiple cascaded shift register units, and each row of sub-pixels receives gate driving signals output from the two gate driving circuits respectively. At least one of the two gate drive circuits arranged opposite each other includes at least one multi-output shift register unit, the multi-output shift register unit outputs multiple gate drive signals, the multiple gate drive signals including the first gate drive signal to be compensated with the lowest potential; At least one row sub-pixel is connected to the first gate drive signal to be compensated, and simultaneously connected to the gate drive signal output by the shift register unit of another gate drive circuit, which has a potential higher than the first gate drive signal to be compensated.

[0007] For example, in some embodiments of the display panel provided in this application, the two gate driving circuits arranged opposite each other are a first gate driving circuit and a second gate driving circuit. The first gate driving circuit includes multiple cascaded first shift register units, and the second gate driving circuit includes multiple cascaded second shift register units. The first shift register units and the second shift register units are multi-output shift register units with the same structure. At least one gate drive signal output by the first stage second shift register unit of the second gate drive circuit is used as a pseudo signal, and at least one gate drive signal is connected to the display area. The gate drive signals output by other stages of the second shift register unit are connected to the display area in sequence, so that the row sub-pixel connected to the first gate drive signal to be compensated output by the first gate drive circuit is connected to the gate drive signal other than the first gate drive signal to be compensated output by the second gate drive circuit.

[0008] For example, in the display panel provided in some embodiments of this application, the multi-output shift register unit is a p-output shift register unit. The first gate drive signal output by the first shift register unit includes pm+1, pm+2, up to pm+p, wherein the first gate drive signal pm+p is the first gate drive signal to be compensated; the second gate drive signal output by the second shift register unit includes pn+1, pn+2, up to pn+p, wherein the second gate drive signal pn+p is the first gate drive signal to be compensated. The number of pseudo signals output by the first stage second shift register unit of the second gate drive circuit is greater than or equal to 1 and less than or equal to p-1; Where p, m, and n are all integers greater than or equal to 1.

[0009] For example, in the display panel provided in some embodiments of this application, the multi-output shift register unit is a four-output shift register unit, wherein the first gate drive signal pm+1 output by the first shift register unit is the second gate drive signal to be compensated with the second lowest potential, and the second gate drive signal pn+1 output by the second shift register unit is the second gate drive signal to be compensated. The number of pseudo signals output by the first stage second shift register unit of the second gate drive circuit is 2.

[0010] For example, in some embodiments of the display panel provided in this application, the two gate driving circuits arranged opposite each other are a third gate driving circuit and a fourth gate driving circuit. The third gate drive circuit includes at least one multi-output shift register unit, and the fourth gate drive circuit includes multiple single-output shift register units. The row sub-pixel is connected to the first gate drive signal to be compensated output by the third gate drive circuit, and is also connected to the gate drive signal output by the single output shift register unit of the fourth gate drive circuit.

[0011] For example, in the display panel provided in some embodiments of this application, the third gate driving circuit includes multiple cascaded third shift register unit groups, the fourth gate driving circuit includes multiple cascaded fourth shift register unit groups, the third shift register unit group includes a multi-output shift register unit and a single-output shift register unit, and the structure of the fourth shift register unit group is the same as that of the first shift register unit group. The first gate drive signal output by the multi-output shift register unit of the first stage fourth shift register unit group of the fourth gate drive circuit is used as a pseudo signal. Other gate drive signals output by the fourth gate drive circuit are sequentially connected to the display area so that the row sub-pixel connected to the first gate drive signal to be compensated output by the third gate drive circuit is simultaneously connected to the gate drive signal output by the single-output shift register unit of the fourth gate drive circuit.

[0012] For example, in some embodiments of this application, the display panel includes a compensation area connected to the first-stage shift register unit of the gate driving circuit, and a non-compensation area connected to the last-stage shift register unit of the gate driving circuit, wherein... In the compensation region, the row sub-pixel connected to the first gate drive signal to be compensated has a potential output by the shift register unit of another gate drive circuit that is higher than the gate drive signal of the first gate drive signal to be compensated.

[0013] For example, in some embodiments of the display panel provided in this application, the two gate driving circuits arranged opposite each other are a fifth gate driving circuit and a sixth gate driving circuit. The fifth gate drive circuit includes multiple cascaded fifth shift register units, and the sixth gate drive circuit includes multiple cascaded sixth shift register units. The fifth shift register units and the sixth shift register units are multi-output shift register units with the same structure. In the compensation region, at least one gate drive signal output by the first stage sixth shift register unit of the sixth gate drive circuit is used as a pseudo signal, and at least one gate drive signal is connected to the display area. The gate drive signals output by other stages of the sixth shift register unit are connected to the display area in sequence, so that the row sub-pixel connected to the first gate drive signal to be compensated output by the fifth gate drive circuit is connected to the gate drive signal other than the first gate drive signal to be compensated output by the sixth gate drive circuit. At least one gate drive signal of the last stage fifth shift register unit of the fifth gate drive circuit near the non-compensation region is a pseudo signal, and the number of pseudo signals output by the last stage fifth shift register is the same as the number of pseudo signals output by the first stage sixth shift register unit. In the non-compensated region, each row of sub-pixels is connected to the gate drive signal output by the fifth gate drive circuit and the gate drive signal output by the sixth gate drive circuit, respectively. The gate drive signal output by the fifth gate drive circuit is the same as the gate drive signal output by the sixth gate drive circuit.

[0014] For example, in the display panel provided in some embodiments of this application, the multi-output shift register unit of the gate driving circuit includes an input sub-circuit, a node control sub-circuit, and an output sub-circuit, wherein... The input sub-circuit is configured to output a first input signal to a first node in response to a first input signal; The node control sub-circuit is configured to write a level to the second node that is opposite to the level at the first node; The output sub-circuit is configured to output the input first clock signal to the cascaded signal terminal under the control of the level at the first node, and to output multiple second clock signals to multiple output signal terminals corresponding to the second clock signals under the control of the level at the first node, and is configured to output the input inactive level signal to the cascaded signal terminal and the multiple output signal terminals under the control of the level at the second node.

[0015] For example, in some embodiments of the display panel provided in this application, the input sub-circuit includes a first transistor and a second transistor, wherein The gate and first stage of the first transistor are connected to the first input signal, and the second stage of the first transistor is connected to the first stage of the second transistor. The gate of the second transistor is connected to the first input signal, and the second stage of the second transistor is connected to the first node; The node control sub-circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein... The gate and first stage of the third transistor are connected to a first power supply signal, and the second stage of the third transistor is connected to the first stage of the fourth transistor. The gate of the fourth transistor is connected to the first node, and the second stage of the fourth transistor is connected to a second power supply signal. The gate of the fifth transistor is connected to the first stage of the fourth transistor, the first stage of the fifth transistor is connected to the first node, and the second stage of the fifth transistor is connected to the first stage of the sixth transistor. The gate of the sixth transistor is connected to the first stage of the fourth transistor, and the second stage of the sixth transistor is connected to the second power supply signal; The output sub-circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor, wherein... The gates of the seventh to eleventh transistors are connected to the first node, and the second stage of the seventh to eleventh transistors is connected to the second node. The first stage of the seventh transistor is connected to a first clock signal, the first stage of the first capacitor is connected to the gate of the seventh transistor, and the second stage of the first capacitor is connected to the second terminal of the seventh transistor. The first stage of the eighth transistor is connected to the first sub-signal of the second clock; the first stage of the second capacitor is connected to the gate of the eighth transistor; and the second stage of the second capacitor is connected to the second terminal of the eighth transistor. The first stage of the ninth transistor is connected to the second sub-signal of the second clock; the first stage of the third capacitor is connected to the gate of the ninth transistor; and the second stage of the third capacitor is connected to the second terminal of the ninth transistor. The first stage of the tenth transistor is connected to the second clock third sub-signal; the first stage of the fourth capacitor is connected to the gate of the tenth transistor; and the second stage of the fourth capacitor is connected to the second terminal of the tenth transistor. The first stage of the eleventh transistor is connected to the fourth sub-signal of the second clock, the first stage of the fifth capacitor is connected to the gate of the eleventh transistor, and the second stage of the fifth capacitor is connected to the second terminal of the eleventh transistor.

[0016] For example, in the display panel provided in some embodiments of this application, the input sub-circuit includes a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, and a thirty-fourth transistor, wherein... The gates of the thirty-first transistor and the thirty-second transistor are connected to the first input signal. The first stage of the thirty-first transistor is connected to the eleventh power supply signal, and the second stage of the thirty-first transistor is connected to the first stage of the thirty-second transistor. The second stage of the thirty-second transistor is connected to the first node; The gate and first stage of the thirty-third transistor are connected to the twelfth power supply signal, and the second stage of the thirty-third transistor is connected to the first stage of the thirty-fourth transistor. The gate of the thirty-fourth transistor is connected to the twelfth power supply signal, and the second stage of the thirty-fourth transistor is connected to the first stage of the thirty-second transistor; The node control sub-circuit includes transistors 35, 36, 37, 38, 39, 40, and 41, wherein... The gate of the thirty-fifth transistor is connected to the second stage of the fortieth transistor, the first stage of the thirty-fifth transistor is connected to the thirteenth power supply signal, and the second stage of the thirty-fifth transistor is connected to the first stage of the thirty-sixth transistor. The gate of the thirty-sixth transistor is connected to the first node, and the second stage of the thirty-sixth transistor is connected to the fourteenth power supply signal. The gate of the thirty-seventh transistor is connected to the first stage of the thirty-sixth transistor, the first stage of the thirty-seventh transistor is connected to the first node, and the second stage of the thirty-seventh transistor is connected to the first stage of the thirty-eighth transistor. The gate of the thirty-eighth transistor is connected to the first stage of the thirty-sixth transistor, and the second stage of the thirty-eighth transistor is connected to the fourteenth power supply signal. The gate and first stage of the thirty-ninth transistor are connected to the thirteenth power supply signal, and the second stage of the thirty-ninth transistor is connected to the first stage of the fortieth transistor. The gate of the 40th transistor is connected to the 13th power supply signal, and the second stage of the 40th transistor is connected to the first stage of the 41st transistor. The gate of the forty-first transistor is connected to the first node, and the second stage of the forty-first transistor is connected to the fourteenth power supply signal; The output sub-circuit includes transistors forty-second, forty-third, forty-fourth, forty-fifth, and forty-sixth, capacitors eleventh, twelfth, thirteenth, fourteenth, and fifteenth, wherein... The gates of transistors 42 to 46 are connected to the first node, and the second stage of transistors 42 to 46 is connected to the second node. The first stage of the forty-second transistor is connected to the first clock signal, the first stage of the eleventh capacitor is connected to the gate of the forty-second transistor, and the second stage of the eleventh capacitor is connected to the second terminal of the forty-second transistor. The first stage of the forty-third transistor is connected to the first sub-signal of the second clock; the first stage of the twelfth capacitor is connected to the gate of the forty-third transistor; and the second stage of the twelfth capacitor is connected to the second terminal of the forty-third transistor. The first stage of the forty-fourth transistor is connected to the second sub-signal of the second clock; the first stage of the thirteenth capacitor is connected to the gate of the forty-fourth transistor; and the second stage of the thirteenth capacitor is connected to the second terminal of the forty-fourth transistor. The first stage of the forty-fifth transistor is connected to the second clock third sub-signal; the first stage of the fourteenth capacitor is connected to the gate of the forty-fifth transistor; and the second stage of the fourteenth capacitor is connected to the second terminal of the forty-fifth transistor. The first stage of the forty-sixth transistor is connected to the fourth sub-signal of the second clock, the first stage of the fifteenth capacitor is connected to the gate of the forty-sixth transistor, and the second stage of the fifteenth capacitor is connected to the second terminal of the forty-sixth transistor. The first clock signal and the second clock third sub-signal are synchronized during the display process.

[0017] For example, in the display panel provided in some embodiments of this application, the input sub-circuit includes a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, and a thirty-fourth transistor, wherein... The gates of the thirty-first transistor and the thirty-second transistor are connected to the first input signal. The first stage of the thirty-first transistor is connected to the eleventh power supply signal, and the second stage of the thirty-first transistor is connected to the first stage of the thirty-second transistor. The second stage of the thirty-second transistor is connected to the first node; The gate and first stage of the thirty-third transistor are connected to the twelfth power supply signal, and the second stage of the thirty-third transistor is connected to the first stage of the thirty-fourth transistor. The gate of the thirty-fourth transistor is connected to the twelfth power supply signal, and the second stage of the thirty-fourth transistor is connected to the first stage of the thirty-second transistor; The node control sub-circuit includes transistors 35, 36, 37, 38, 39, 40, and 41, wherein... The gate of the thirty-fifth transistor is connected to the second stage of the fortieth transistor, the first stage of the thirty-fifth transistor is connected to the thirteenth power supply signal, and the second stage of the thirty-fifth transistor is connected to the first stage of the thirty-sixth transistor. The gate of the thirty-sixth transistor is connected to the first node, and the second stage of the thirty-sixth transistor is connected to the fourteenth power supply signal. The gate of the thirty-seventh transistor is connected to the first stage of the thirty-sixth transistor, the first stage of the thirty-seventh transistor is connected to the first node, and the second stage of the thirty-seventh transistor is connected to the first stage of the thirty-eighth transistor. The gate of the thirty-eighth transistor is connected to the first stage of the thirty-sixth transistor, and the second stage of the thirty-eighth transistor is connected to the fourteenth power supply signal. The gate and first stage of the thirty-ninth transistor are connected to the thirteenth power supply signal, and the second stage of the thirty-ninth transistor is connected to the first stage of the fortieth transistor. The gate of the 40th transistor is connected to the 13th power supply signal, and the second stage of the 40th transistor is connected to the first stage of the 41st transistor. The gate of the forty-first transistor is connected to the first node, and the second stage of the forty-first transistor is connected to the fourteenth power supply signal; The output sub-circuit includes transistors forty-second, forty-third, forty-fourth, forty-fifth, and forty-sixth, capacitors eleventh, twelfth, thirteenth, fourteenth, and fifteenth, wherein... The gates of transistors 42 to 46 are connected to the first node, and the second stage of transistors 42 to 46 is connected to the second node. The first stage of the forty-second transistor is connected to the first clock signal, the first stage of the eleventh capacitor is connected to the gate of the forty-second transistor, and the second stage of the eleventh capacitor is connected to the second terminal of the forty-second transistor. The first stage of the forty-third transistor is connected to the first sub-signal of the second clock; the first stage of the twelfth capacitor is connected to the gate of the forty-third transistor; and the second stage of the twelfth capacitor is connected to the second terminal of the forty-third transistor. The first stage of the forty-fourth transistor is connected to the second sub-signal of the second clock; the first stage of the thirteenth capacitor is connected to the gate of the forty-fourth transistor; and the second stage of the thirteenth capacitor is connected to the second terminal of the forty-fourth transistor. The first stage of the forty-fifth transistor is connected to the second clock third sub-signal; the first stage of the fourteenth capacitor is connected to the gate of the forty-fifth transistor; and the second stage of the fourteenth capacitor is connected to the second terminal of the forty-fifth transistor. The first stage of the forty-sixth transistor is connected to the fourth sub-signal of the second clock, the first stage of the fifteenth capacitor is connected to the gate of the forty-sixth transistor, and the second stage of the fifteenth capacitor is connected to the second terminal of the forty-sixth transistor. The first clock signal and the second clock fourth sub-signal are synchronized during the display process.

[0018] A second embodiment of the present invention provides a display device, including a display panel as described in the first embodiment.

[0019] A third embodiment of the present invention provides a driving method for a display panel as described in the first embodiment, comprising: The multi-output shift register unit outputs multiple gate drive signals according to the input signal. The multiple gate drive signals include the first gate drive signal to be compensated with the lowest potential. The multi-output shift register unit is included in at least one of two gate drive circuits arranged opposite to each other. At least one row sub-pixel is connected to the first gate drive signal to be compensated, and simultaneously connected to the gate drive signal output by the shift register unit of another gate drive circuit, which has a potential higher than the first gate drive signal to be compensated.

[0020] For example, in some embodiments of the driving method provided in this application, the multi-output shift register unit is configured to output a cascaded signal in response to an input first clock signal, and to output a plurality of output signals corresponding to the second clock signals in response to an input plurality of second clock signals; The multi-output shift register unit outputs multiple gate drive signals according to the input signal, further including: the first clock signal and the second clock signal corresponding to the first gate drive signal to be compensated are synchronized during the display process.

[0021] The beneficial effects of this invention are as follows: This invention addresses existing problems by providing a display panel, display device, and driving method. It achieves potential compensation for the sub-pixel row with the lowest-potential first gate driving signal by loading gate driving signals of different potentials onto a row of sub-pixels. Specifically, the dual-sided gate driving circuits are staggered, so that the sub-pixel row with the lowest-potential first gate driving signal is simultaneously loaded with another gate driving signal that is not the lowest-potential. This staggered dual-sided gate driving circuitry achieves potential compensation, overcoming the problems in existing technologies, effectively improving display performance, and has broad application prospects. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the dual-gate driving circuit of the display panel described in the related art is shown; Figure 2 A circuit diagram of a dual-gate driving circuit for a display panel as described in the related art is shown. Figure 3 A timing diagram of the dual-gate driving circuit of the display panel described in the related art is shown; Figure 4 A schematic diagram of the dual-gate driving circuit of a display panel according to an embodiment of the present invention is shown; Figure 5 A schematic diagram of the dual-gate driving circuit of the display panel according to another embodiment of the present invention is shown; Figure 6 A schematic diagram of the dual-gate driving circuit of the display panel according to another embodiment of the present invention is shown; Figure 7 A schematic diagram of the dual-gate driving circuit of the display panel according to another embodiment of the present invention is shown; Figure 8 This diagram illustrates the falling edge delay of the gate drive signal of a display panel according to an embodiment of the present invention. Figure 9 A schematic diagram of the dual-gate driving circuit of the display panel according to another embodiment of the present invention is shown; Figure 10 A circuit diagram illustrating a dual-gate driving circuit for a display panel according to another embodiment of the present invention is shown. Figure 11 A circuit diagram of a dual-gate driving circuit for a display panel according to another embodiment of the present invention is shown. Detailed Implementation

[0024] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0025] like Figure 1 The diagram illustrates a dual-sided gate drive circuit driving a row of sub-pixels in related technologies. Both the left and right gate drive circuits include multi-stage shift register units, each with four output drive circuits. This means one shift register unit outputs four gate drive signals, simultaneously providing gate drive signals to four rows of sub-pixels. As shown, the left and right gate drive circuits are symmetrically arranged, and the first row of sub-pixels is simultaneously connected to the gate drive signal G output by the shift register unit GOA_L1 of the left gate drive circuit. <1> _L, and the gate drive signal G output by the shift register unit GOA_R1 of the right-side gate drive circuit. <1> _R, which is the gate drive signal G received by the first row of sub-pixels. <1> For G <1> _L and G <1> _R; Similarly, the gate drive signal G received by the second row of sub-pixels <2> For G <2> _L and G <2> _R, the gate drive signal G received by the third row of sub-pixels <3> For G <3> _L and G <3> _R, the gate drive signal G received by the fourth row of sub-pixels <4> For G <4> _L and G <4> _R, the gate drive signal G received by the fifth row sub-pixel <5> For G <5> _L and G <5> _R, the gate drive signal G received by the sixth row sub-pixel <6> For G <6> _L and G <6> _R.

[0026] like Figure 2 As shown, Figure 1 The circuit diagram of the shift register unit of the dual-gate drive circuit shown is as follows: Figure 3 As shown, Figure 11 The timing diagram of the dual-gate drive circuit shown is for one frame of image, where CR <n-2>CR is the output signal of the previous shift register unit, CLKD3 is the first clock signal, and CR...<N+2> The CR signal of this stage shift register unit is output according to the first clock signal.<N+6> The CR signal output by the next stage shift register unit, Q <n>QB is the pull-up node, QB is the pull-down node, and CLKE is the second clock signal. The corresponding gate drive signal is output based on CLKE. Specifically: CLKE1 is the first sub-signal of the second clock, and the shift register unit outputs the first gate drive signal G based on CLKE1.<N+1> CLKE2 is the second sub-signal of the second clock, and the shift register unit outputs the second gate drive signal G according to CLKE2.<N+2> CLKE3 is the second clock signal and the third sub-signal. The shift register unit outputs the third gate drive signal G based on CLKE3.<N+3> CLKE4 is the fourth sub-signal of the second clock. The shift register unit outputs the fourth gate drive signal G according to CLKE4.<N+4> .

[0027] Combination Figure 3 STU is the CR signal output from the previous shift register unit, TRST is the reset signal; CLKD3 is the first clock signal of the first shift register unit, CLKE1-CLKE4 are the second clock signals of the same shift register unit; CLKD7 is the first clock signal of the second shift register unit, CLKE5-CLKE8 are the second clock signals of the same shift register unit, Q7 is the Q-point potential of Q<5-8>; CLKD11 is the first clock signal of the third shift register unit.

[0028] Taking a single frame of image as an example, the working process of sub-pixels in rows 5 to 8 will be explained. Specifically, during the display of a single frame of image, when the first clock signal CLKD3 of the first shift register unit is high, the Q point of Q<5-8> is written with a high voltage and remains high; when the first clock signal CLKD7 of the second shift register unit is high and CLKE5-8 is high, the outputs CR7 and G<5-8> are sequentially high; when the first clock signal CLKD11 of the third shift register unit is high, G<5-8> is low; the gate drive circuit sequentially completes the display of all rows during the display period through the cascaded shift register units and enters the blanking period.

[0029] As shown in the figure, the potential change at point Q of the second shift register unit exhibits a "tower-like" pattern. Specifically, when the first clock signal CLKD7 is high and CLKE5-8 are sequentially high, the response to the effective output G of CLKE5... <5> During the active output phase of CLKE5, the Q7 potential transitions from the "tower-like" sub-potential to the highest potential. Similarly, this is in response to the active output G of CLKE6. <6> During the active output phase of CLKE6, the Q7 potential is at its highest "tower-like" potential. Similarly, in response to the active output G of CLKE7... <7> During the active output phase of CLKE7, the Q7 potential is at its highest "tower-like" potential. Similarly, in response to the active output G of CLKE8... <8> During the active phase of the CLKE8 output, the Q7 potential drops from its highest "tower-like" potential to the second highest potential. Due to overlap between gate drive signals, only the falling edge is considered. <8> The Q7 potential corresponding to the falling edge of row G<5-7> is lower than the Q7 potential corresponding to the falling edge of row G<5-7>, therefore G <8> The gate drive signal output from the row is the lowest potential; that is, among the four gate drive signals output from the second shift register unit, the fourth gate drive signal has the lowest potential, which is lower than the potentials of the other three gate drive signals. Because... Figure 1 The output of the dual-side gate drive circuit of the display panel shown is symmetrical. Therefore, the 8th row of sub-pixels has an abnormal brightness problem when displayed. That is, the data cannot be completely written due to the deterioration of the falling edge at the center of the display panel where the load is the largest.

[0030] In response to the above situation, the inventors, after extensive research and experimentation, proposed a display panel, such as... Figure 4-6 As shown, the display panel includes a display area and a non-display area. The display area includes multiple rows of sub-pixels, and the non-display area includes two gate driving circuits arranged opposite each other. Each gate driving circuit includes multiple cascaded shift register units, and each row of sub-pixels receives gate driving signals output from the two gate driving circuits respectively. At least one of the two gate drive circuits arranged opposite each other includes at least one multi-output shift register unit, the multi-output shift register unit outputs multiple gate drive signals, the multiple gate drive signals including the first gate drive signal to be compensated with the lowest potential; At least one row sub-pixel is connected to the first gate drive signal to be compensated, and simultaneously connected to the gate drive signal output by the shift register unit of another gate drive circuit, which has a potential higher than the first gate drive signal to be compensated.

[0031] In this embodiment, the display panel employs a dual-gate driving circuit, including a multi-stage shift register unit, including a multi-output shift register unit, such as... Figure 4-6 Each shift register unit is a 4-output shift register unit, meaning that one shift register unit simultaneously provides gate drive signals to four rows of sub-pixels. Each row of sub-pixels receives gate drive signals from both sides, meaning that each row of sub-pixels is driven by gate drive signals from both sides.

[0032] The multi-output shift register unit in this embodiment adopts the following... Figure 2 As shown in the circuit, the four gate drive signals output by the multi-output shift register unit have different potentials. Based on the previous analysis, using the falling edge as a reference, the fourth gate drive signal output by the four-output shift register unit has the lowest potential. The potentials of the other gate drive signals, from the first to the third, are all higher than the fourth gate drive signal. Therefore, the fourth gate drive signal is the first gate drive signal to be compensated. Based on this, to compensate the sub-pixel row receiving the lowest potential first gate drive signal from the shift register unit of the left gate drive circuit, this sub-pixel row is configured to receive a higher potential gate drive signal from the shift register unit of the right gate drive circuit. This achieves compensation for the lowest potential first gate drive signal, thereby raising the potential of the gate drive signal received by this sub-pixel row. In other words, this embodiment addresses the problem of different levels of gate drive signals output by the multi-output shift register unit having different potentials. Utilizing the characteristic that each row of sub-pixels receives bilateral gate drive signals, the bilateral gate drive circuits are staggered. That is, for the lowest potential gate drive signal output by the multi-output shift register unit, a gate drive signal with a higher potential is used for compensation.

[0033] In other words, this embodiment achieves potential compensation for the sub-pixel row with the lowest loaded gate drive signal by loading gate drive signals of different potentials onto a row of sub-pixels. That is, the bilateral gate drive circuits are staggered, so that the sub-pixel row with the lowest loaded gate drive signal is simultaneously loaded with a non-lowest loaded gate drive signal on the other side. Thus, potential compensation is achieved through the staggered bilateral gate drive circuits, thereby overcoming the problems existing in the prior art, effectively improving the display effect, and having broad application prospects.

[0034] It should be noted that, Figure 4-6 Any shift register unit in this application is only used to illustrate the specific implementation of this application. This application does not specifically limit the position of the gate drive circuit. Those skilled in the art should configure the position of the gate drive circuit appropriately according to the actual application requirements. The basic design principle is that each row of sub-pixels receives two gate drive signals and compensates each other through the two gate drive signals. This will not be elaborated here.

[0035] In a specific embodiment, such as Figure 4 As shown, the display panel includes a first gate driving circuit and a second gate driving circuit arranged opposite to each other. The first gate driving circuit includes multiple cascaded first shift register units GOA_L1, GOA_L2, ..., GOA_L(n), GOA_L(n+1) with the same structure, i.e., four-output shift register units. The fourth gate driving signal output by each first shift register unit has the lowest potential and is the first gate driving signal to be compensated. The second gate driving circuit includes multiple cascaded second shift register units GOA_R1, GOA_R2, ..., GOA_R(n), GOA_R(n+1) with the same structure. The second shift register units and the first shift register units are four-output shift register units with the same structure, meaning the fourth gate driving signal output by the second shift register unit has the lowest potential.

[0036] The gate drive signals output from each stage of the shift register unit of the first gate drive circuit are sequentially connected to the display area; the first gate drive signal G output from the first stage second shift register unit GOA_R1 of the second gate drive circuit is... <1> _R acts as a pseudo-signal; the signal at potential GR1 is not connected to the display area, for example, it is in a floating state, i.e., as shown in the figure as Dummy-GR1; the other second gate drive signal G <2> _R, the third gate drive signal G <3> _R, the fourth gate drive signal G <4> _R is connected to the display area, and the gate drive signals output from other stages of the second shift register unit are sequentially connected to the display area. For example... Figure 4 As shown, the gate drive signals output by the first gate drive circuit and the gate drive signals output by the second gate drive circuit are staggered. The gate drive signal output by the first shift register unit connected to the left side of each row of sub-pixels is different from the gate drive signal output by the second shift register unit connected to the right side, which has the same structure as the first shift register unit. For example, the left side of the first row of sub-pixels receives G... <1> _L signal and right side receive G <2> The _R signal, i.e., the potential of the gate drive signal received by the first row of sub-pixels, is GL1 and GR2; similarly, the potential of the gate drive signal received by the second row of sub-pixels is GL2 and GR3, the potential of the gate drive signal received by the third row of sub-pixels is GL3 and GR4, and the potential of the gate drive signal received by the fourth row of sub-pixels is GL4 and GR1, all of which meet the brightness requirements of each row of sub-pixels on the display panel. That is, the first gate drive signal to be compensated output by each first shift register unit of the first gate drive circuit is compensated by the first gate drive signal output by each second shift register unit of the second gate drive circuit, i.e., the non-first gate drive signal to be compensated, thereby raising the potential of the gate drive signal received by the fourth row of sub-pixels and the (n+4)th row of sub-pixels, solving the display abnormality problem caused by the different potentials of the gate drive signals received by sub-pixels in different rows in related technologies, and effectively improving the display effect.

[0037] It is worth noting that, such as Figure 4 As shown, since each of the first shift register units of the first gate driving circuit is sequentially connected to the display area, the first gate driving signal output by the first stage second shift register unit of the second gate driving circuit is used as a pseudo signal, and other gate driving signals are sequentially connected to the display area. Therefore, the fourth gate driving signal output by the last stage first shift register unit of the first gate driving circuit is not connected to the display area and is also used as a pseudo signal, namely Dummy-GL4.

[0038] Similarly, in another specific example, such as Figure 5 As shown, the display panel includes a first gate driving circuit and a second gate driving circuit disposed on both sides of the display area. The first shift register units of the first gate driving circuit and the second shift register units of the second gate driving circuit have the same structure, both being four-output shift register units. Among them, the fourth gate driving signal output by each first shift register unit has the lowest potential and is the first gate driving signal to be compensated.

[0039] The gate drive signals output from each stage of the shift register unit of the first gate drive circuit are sequentially connected to the display area; the first gate drive signal G output from the first stage second shift register unit GOA_R1 of the second gate drive circuit is... <1> _R, the second gate drive signal G <2> _R and the third gate drive signal G <3> _R, as a pseudo-signal, is not connected to the display area; for example, it is in a floating state, i.e., Dummy-GR1, Dummy-GR2, and Dummy-GR3 as shown in the figure; the fourth gate drive signal G <4> _R is connected to the display area, and the gate drive signals output by the other second shift register units are connected to the display area in sequence.

[0040] like Figure 5 As shown, the gate drive signals output by the first gate drive circuit and the gate drive signals output by the second gate drive circuit are staggered. The gate drive signal output by the first shift register unit connected to the left side of each row of sub-pixels is different from the gate drive signal output by the second shift register unit connected to the right side, which has the same structure as the first shift register unit. For example, the left side of the first row of sub-pixels receives G... <1> _L signal and right side receive G <4> The _R signal, i.e., the potential of the gate drive signal received by the first row of sub-pixels, is GL1 and GR4; similarly, the potential of the gate drive signal received by the second row of sub-pixels is GL2 and GR1, the potential of the gate drive signal received by the third row of sub-pixels is GL3 and GR2, and the potential of the gate drive signal received by the fourth row of sub-pixels is GL4 and GR3, all of which meet the brightness requirements of each row of sub-pixels on the display panel. That is, the first gate drive signal to be compensated output by each first shift register unit of the first gate drive circuit is compensated by the third gate drive signal output by each second shift register unit of the second gate drive circuit, i.e., the non-first gate drive signal to be compensated, thereby raising the potential of the gate drive signal received by the fourth row of sub-pixels and the (n+4)th row of sub-pixels, solving the display abnormality problem caused by the different potentials of the gate drive signals received by sub-pixels in different rows in related technologies, and effectively improving the display effect.

[0041] It is worth noting that, such as Figure 5 As shown, since each of the first shift register units of the first gate driving circuit is sequentially connected to the display area, the first, second, and third gate driving signals output by the first stage second shift register unit of the second gate driving circuit are used as pseudo signals, and the fourth gate driving signal and the gate driving signals output by the other stages of the second shift register unit are sequentially connected to the display area. Therefore, the second, third, and fourth gate driving signals output by the last stage first shift register unit of the first gate driving circuit are not connected to the display area and are also used as pseudo signals, namely Dummy-GL2, Dummy-GL3, and Dummy-GL4.

[0042] As can be seen from the above embodiments, the multi-output shift register unit of the display panel is a p-output shift register unit. The first gate drive signal output by the first shift register unit includes pm+1, pm+2, up to pm+p, wherein the first gate drive signal pm+p is the first gate drive signal to be compensated; the second gate drive signal output by the second shift register unit includes pn+1, pn+2, up to pn+p, wherein the second gate drive signal pn+p is the first gate drive signal to be compensated; the number of pseudo signals output by the first stage second shift register unit of the second gate drive circuit is greater than or equal to 1 and less than or equal to p-1; wherein p, m, and n are all integers greater than or equal to 1.

[0043] This application does not specifically limit the structure of the multi-output shift register unit of the display panel. Those skilled in the art should select an appropriate number of output shift register units according to actual application requirements, with the basic principle being to use the non-lowest potential gate drive signal connected on one side to compensate the lowest potential gate drive signal connected on the other side. This will not be elaborated further here.

[0044] like Figure 3 As shown, the potential of the first gate drive signal of the four-output shift register unit is slightly lower than the potentials of the second and third gate drive signals. That is, the first gate drive signal of the four-output shift register is the second gate drive signal to be compensated. Considering further improving the display effect of the display panel, in an optional embodiment, as shown... Figure 6 As shown, the display panel includes a first gate driving circuit and a second gate driving circuit arranged opposite to each other. The first gate driving circuit and the second gate driving circuit have the same structure. Both the first shift register unit and the second shift register unit are four-output shift register units. Among them, the fourth gate driving signal output by each first shift register unit has the lowest potential and is the first gate driving signal to be compensated; the first gate driving signal output by each first shift register unit has the second lowest potential and is the second gate driving signal to be compensated.

[0045] The gate drive signals output from each stage of the shift register unit of the first gate drive circuit are sequentially connected to the display area; the first gate drive signal G output from the first stage second shift register unit GOA_R1 of the second gate drive circuit is... <1> _R and the second gate drive signal G <2> _R, as a pseudo-signal, is not connected to the display area; for example, it is in a floating state, i.e., Dummy-GR1 and Dummy-GR2 as shown in the figure; the other third gate drive signal G <3> _R and the fourth gate drive signal G <4> _R is connected to the display area, and the gate drive signals output by the other second shift register units are connected to the display area in sequence.

[0046] like Figure 6 As shown, the gate drive signals output by the first gate drive circuit and the gate drive signals output by the second gate drive circuit are staggered to compensate the first and second gate drive signals to be compensated, respectively. For example, the left side of the first row of sub-pixels receives G... <1> _L signal and right side receive G <3> The _R signal, i.e., the gate drive signal potentials received by the first row of sub-pixels, are GL1 and GR3, with the higher potential GR3 compensating for the lower potential GL1. Similarly, the gate drive signal potentials received by the second row of sub-pixels are GL2 and GR4, the third row of sub-pixels are GL3 and GR1, and the fourth row of sub-pixels are GL4 and GR2, with the higher potential GR2 compensating for the lower potential GL4. This satisfies the brightness requirements of each row of sub-pixels on the display panel. This raises the potentials of the gate drive signals received by the fourth row of sub-pixels and the (n+4)th row of sub-pixels, further raising the potentials of the gate drive signals received by the first row of sub-pixels and the (n+1)th row of sub-pixels, thereby further improving the display effect.

[0047] It is worth noting that, such as Figure 6 As shown, since each of the first shift register units of the first gate driving circuit is sequentially connected to the display area, the first gate driving signal and the second gate driving signal output by the first stage second shift register unit of the second gate driving circuit are used as pseudo signals, and other gate driving signals are sequentially connected to the display area. Therefore, the third gate driving signal and the fourth gate driving signal output by the last stage first shift register unit of the first gate driving circuit are not connected to the display area and are also used as pseudo signals, namely Dummy-GL3 and Dummy-GL4.

[0048] To further compensate for the gate drive signal with the lowest potential, in an optional embodiment, at least one of the dual-sided gate drive circuits includes a multi-output shift register unit, i.e., a first gate drive signal with the lowest potential to be compensated; at least one of the dual-sided gate drive circuits includes a single-output shift register unit, i.e., an output gate drive signal with a higher potential; by compensating the gate drive signal with the lowest potential output by the multi-output shift register unit with the gate drive signal with the higher potential output by the single-output shift register unit, the potential of the gate drive signal received by the sub-pixel in that row can be increased, thereby further improving the display effect.

[0049] In a specific example, such as Figure 7 As shown, the bilateral gate drive circuit includes a third gate drive circuit on the left, comprising multiple cascaded third shift register unit groups, including a multi-output shift register unit GOA_L1 and a single-output shift register unit GOA_L2; the bilateral gate drive circuit also includes a fourth gate drive circuit on the right, comprising multiple cascaded fourth shift register unit groups, including a multi-output shift register unit GOA_R1 and a single-output shift register unit GOA_R2; the structure of the fourth shift register unit group is the same as that of the third shift register unit group; the first gate drive signal G output by the multi-output shift register unit GOA_R1 of the first stage fourth shift register unit group of the fourth gate drive circuit is... <1> _R serves as a pseudo-signal, and the other gate drive signals G output by the fourth gate drive circuit are... <2> _R、G <3> _R、G <4> _R, and G output by GOA_R2 <5> _R are sequentially connected to the display area so as to interact with the first gate drive signal G to be compensated output by the third gate drive circuit. <4> The _L-connected row of sub-pixels is also connected to the gate drive signal G output by the single-output shift register unit of the fourth gate drive circuit. <5> _R; that is, the first gate drive signal to be compensated with the lowest potential output by the multi-output shift register unit of the third shift register unit group of the third gate drive circuit. The row sub-pixel connected to this signal is simultaneously connected to the gate drive signal with a higher potential output by the single-output shift register unit of the fourth shift register unit group of the fourth gate drive circuit, thereby raising the potential of the gate drive signal received by the row sub-pixel, thereby further improving the display effect.

[0050] Specifically, the four gate drive signals output by the multi-output shift register unit GOA_L1 of the third shift register unit group of the third gate drive circuit and the one gate drive signal output by the single-output register unit GOA_L2 are sequentially connected to the display area; the first gate drive signal G output by the multi-output shift register unit GOA_R1 of the fourth shift register unit group of the fourth gate drive circuit is connected to the display area. <1> _R acts as a pseudo-signal; the signal with potential GR1 is not connected to the display area, for example, it is in a floating state, i.e., Dummy-GR1 as shown in the figure. The other three gate drive signals and one gate drive signal output from the single-output register unit GOA_R2 are connected to the display area in sequence; the gate drive signals output from the other third shift register unit group and the gate drive signals output from the fourth shift register unit group are connected to the display area in sequence. For example, the left side of the first row of sub-pixels receives G <1> _L signal and right side receive G <2> The _R signal, i.e., the potential of the gate drive signal received by the first row of sub-pixels, is GL1 and GR2; similarly, the potential of the gate drive signal received by the second row of sub-pixels is GL2 and GR3, the potential of the gate drive signal received by the third row of sub-pixels is GL3 and GR4, and the potential of the gate drive signal received by the fourth row of sub-pixels is GL4 and GR, all of which meet the brightness requirements of each row of sub-pixels on the display panel. That is, the lowest potential of the first gate drive signal to be compensated output by the multi-output shift register unit of the third shift register unit group of the third gate drive circuit is compensated by the higher potential of the gate drive signal output by the single-output shift register unit of the fourth shift register unit group of the fourth gate drive circuit, thereby raising the potential of the gate drive signal received by the fourth row of sub-pixels and the (n+4)th row of sub-pixels, solving the display abnormality problem caused by the different potentials of the gate drive signals received by different rows of sub-pixels in related technologies, and effectively improving the display effect.

[0051] It is worth noting that, such as Figure 7 As shown, since the gate drive signals output by each of the third shift register unit groups of the third gate drive circuit are sequentially connected to the display area, the first gate drive signal output by the multi-output shift register unit of the first stage fourth shift register unit group of the fourth gate drive circuit is used as a pseudo signal, and the other gate drive signals and the gate drive signals output by the single-output shift register unit group are sequentially connected to the display area; therefore, the gate drive signal output by the single-output register unit of the last stage third shift register unit group of the third gate drive circuit is not connected to the display area, that is, it is used as a pseudo signal, or the last stage third shift register unit group only includes multi-output register units and no longer includes single-output register units.

[0052] like Figure 8 As shown, considering the changing trend of the falling edge of the gate drive signal on different rows of sub-pixels of the display panel, the falling edge delay Tf2 of the gate drive signal near the bottom trace area of ​​the display area 10 is short, while the falling edge delay Tf1 of the gate drive signal far from the bottom trace area of ​​the display panel 10 is long. Here, the two sides of the display area 10 are dual-sided gate drive circuits 20 and 30. In a specific example, Tf1 is 1.5μs and Tf2 is 2.5μs. According to actual applications and simulation data, when the falling edge delay Tf is less than or equal to the preset value, for example, less than or equal to 2.0μs, the gate drive signal with the lowest potential output by the multi-output shift register unit meets the brightness requirements of the display panel and no compensation is required; when it is greater than the preset value, for example, greater than 2.0μs, the gate drive signal with the lowest potential output by the multi-output shift register unit does not meet the brightness requirements of the display panel and compensation is required.

[0053] In view of the above situation, in an optional embodiment, such as Figure 9 As shown, the display panel includes a fifth gate driving circuit and a sixth gate driving circuit arranged opposite to each other. The fifth gate driving circuit includes multiple cascaded fifth shift register units GOA_L1, GOA_L2, GOA_L(N), GOA_L(N+1), and GOA_L(M). The sixth gate driving circuit includes multiple cascaded sixth shift register units GOA_R1, GOA_R2, GOA_R(N), GOA_R(N+1), and GOA_R(M). The fifth and sixth shift register units are multi-output shift register units with the same structure.

[0054] In this embodiment, a compensation region requiring signal compensation and a non-compensation region not requiring signal compensation are set according to the falling edge delay Tf of the gate drive signal.

[0055] In the compensation region, the gate drive signals output by each stage of the shift register unit of the fifth gate drive circuit are sequentially connected to the display area, and the first gate drive signal G output by the first stage sixth shift register unit of the sixth gate drive circuit is... <1> _R and the second gate drive signal G <2> _R is a pseudo-signal and is not connected to the display area; other gate drive signals are connected to the display area sequentially. Specifically, the first row of sub-pixels receives the G signal output from the fifth shift register unit on the left. <1> The _L signal is received, and the G signal is also received from the output of the sixth shift register unit on the right. <3> The _R signal, i.e., the potential of the gate drive signal received by the first row of sub-pixels, is GL1 and GR3; similarly, the potential of the gate drive signal received by the second row of sub-pixels is GL2 and GR4, the potential of the gate drive signal received by the third row of sub-pixels is GL3 and GR1, and the potential of the gate drive signal received by the fourth row of sub-pixels is GL4 and GR2, all of which meet the brightness requirements of each row of sub-pixels in the display panel. Even if the row of sub-pixels connected to the first gate drive signal with the lowest potential output by the fifth gate drive circuit is simultaneously connected to the gate drive signal with a non-lowest potential output by the sixth gate drive circuit, in the compensation area, the third and fourth gate drive signals of the fifth gate drive circuit near the last stage fifth shift register unit GOA_L(N+1) in the non-compensation area are treated as pseudo-signals and are not connected to the display area.

[0056] In the uncompensated region, the shift register units of the fifth gate driving circuit and the shift register units of the sixth gate driving circuit are symmetrically arranged. Each row of sub-pixels is connected to the gate driving signal output by the shift register units GOA_L(M) of the fifth gate driving circuit and the gate driving signal output by the shift register units GOA_R(M) of the sixth gate driving circuit. For example, the potentials of the gate driving signals received by the sub-pixels in the (M+1)th row are GL1 and GR1, the potentials of the gate driving signals received by the sub-pixels in the (M+2)th row are GL2 and GR2, the potentials of the gate driving signals received by the sub-pixels in the (M+3)th row are GL3 and GR3, and the potentials of the gate driving signals received by the sub-pixels in the (M+4)th row are GL4 and GR4. That is, the gate driving signals output by the fifth gate driving circuit are the same as the gate driving signals output by the sixth gate driving circuit.

[0057] In this embodiment, considering the delay in the falling edge of the gate drive signal during actual operation of the display panel, the dual-sided gate drive circuits are staggered in the compensation area, and gate drive signals with different potentials are loaded on a row of sub-pixels. This achieves potential compensation for the sub-pixel row with the lowest loaded gate drive signal to be compensated. At the same time, the same gate drive signal is output by symmetrically arranged dual-sided gate drive circuits in the non-compensation area. Both meet the brightness requirements of each row of sub-pixels of the display panel, thereby overcoming the problems existing in the prior art and effectively improving the display effect.

[0058] In an optional embodiment, the multi-output shift register unit of the gate drive circuit includes an input sub-circuit, a node control sub-circuit, and an output sub-circuit. The input sub-circuit is configured to output a first input signal to a first node in response to a first input signal. The node control sub-circuit is configured to write a level to a second node that is inversely proportional to the level at the first node. The output sub-circuit is configured to output an input first clock signal to a cascaded signal terminal under the control of the level at the first node, and to output multiple second clock signals to multiple output signal terminals corresponding to the second clock signals under the control of the level at the first node. It is also configured to output an input inactive level signal to the cascaded signal terminal and the multiple output signal terminals under the control of the level at the second node.

[0059] In this embodiment, by coupling the node control sub-circuits of the first node and the second node respectively, the first node and the second node are controlled in opposite phases, thereby outputting valid cascaded signals and multiple output signals through the first node control output sub-circuit and outputting invalid signals through the second node control output sub-circuit.

[0060] In a specific example, such as Figure 2 As shown, the input sub-circuit 1100 includes a first transistor M1 and a second transistor M2, wherein the gate of the first transistor M1 and the first stage are connected to the first input signal CR. <n-2>The second stage of the first transistor M1 is connected to the first stage of the second transistor M2, and the gate of the second transistor M2 is connected to the first input signal CR. <n-2>The second stage of the second transistor M2 is connected to the first node Q. <n>Connection; Input sub-circuit responds to the first input signal CR <n-2>Effectively output the first input signal to the first node Q <n>That is, raise the first node Q. <n>The potential.

[0061] The node control sub-circuit 1200 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The gate and first stage of the third transistor M3 are connected to a first power supply signal GVDD3. The second stage of the third transistor M3 is connected to the first stage of the fourth transistor M4. The gate of the fourth transistor M4 is connected to the first node Q. <n>The fourth transistor M4 is connected to the second power supply signal VGL1 at its second stage, and the gate of the fifth transistor M5 is connected to the first stage of the fourth transistor M4. The first stage of the fifth transistor M5 is connected to the first node Q. <n>The second stage of the fifth transistor M5 is connected to the first stage of the sixth transistor M6, the gate of the sixth transistor M6 is connected to the first stage of the fourth transistor M4, and the second stage of the sixth transistor M6 is connected to the second power supply signal VGL1; the node control sub-circuit is an inverter, so that the level at the first node and the level at the second node are opposite to each other.

[0062] The output sub-circuit 1300 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5, wherein the gates of the seventh transistor M7 to the eleventh transistor M11 are connected to the first node Q. <n>The connections are as follows: the second stages of the seventh transistor M7 to the eleventh transistor M11 are connected to the second node QB; the first stage of the seventh transistor M7 is connected to the first clock signal CLKD3; the first stage of the first capacitor C1 is connected to the gate of the seventh transistor M7; the second stage of the first capacitor C1 is connected to the second terminal of the seventh transistor M7; the first stage of the eighth transistor M8 is connected to the first sub-signal of the second clock CLKE1; the first stage of the second capacitor C2 is connected to the gate of the eighth transistor M8; the second stage of the second capacitor C2 is connected to the second terminal of the eighth transistor M8; and the first stage of the ninth transistor M9 is connected to the second sub-signal of the second clock CLKE2. The first stage of the third capacitor C3 is connected to the gate of the ninth transistor M9, and the second stage of the third capacitor C3 is connected to the second terminal of the ninth transistor M9. The first stage of the tenth transistor M10 is connected to the second clock third sub-signal CLKE3. The first stage of the fourth capacitor C4 is connected to the gate of the tenth transistor M10, and the second stage of the fourth capacitor C4 is connected to the second terminal of the tenth transistor M10. The first stage of the eleventh transistor M11 is connected to the second clock fourth sub-signal CLKE4. The first stage of the fifth capacitor C5 is connected to the gate of the eleventh transistor M11, and the second stage of the fifth capacitor C5 is connected to the second terminal of the eleventh transistor M11. When the output sub-circuit is active at the first node, it outputs the input first clock signal CLKD3 to the cascaded signal CR.<N+2> The terminal outputs the cascaded signals of the shift register unit at this stage, and simultaneously outputs the multiple input second clock signals CLKE1-4 to the corresponding multiple output signals G.<N+1> G<N+2> G<N+3> and G<N+4> The terminal outputs four gate drive signals, where, due to the first node Q... <n>The voltage level changes in a "tower-like" pattern. Therefore, the fourth gate drive signal has the lowest potential and is the first gate drive signal to be compensated. When the voltage level at the first node is invalid while the voltage level at the second node is valid, an invalid signal VGL1 or VGL2 is applied, and the cascaded signal CR...<N+2> Multiple output signals G<N+1> G<N+2> G<N+3> and G<N+4> All of these are invalid signals.

[0063] like Figure 2 As shown, the shift register unit also includes a noise reduction sub-circuit 1400, comprising a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16. Under the control of the level at the second node, an invalid signal VGL2 is connected to the cascaded signal CR.<N+2> Multiple output signals G<N+1> G<N+2> G<N+3> and G<N+4> Noise reduction operations are performed separately.

[0064] like Figure 2 As shown, the shift register unit further includes an auxiliary pull-down circuit 1500, including a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19, which further responds to the cascaded signal CR output from the previous stage shift register unit. <n-2>Alternatively, under the control of the blanking control clock signal CLKA and the blanking control auxiliary signal H, the potential of the second node QB is pulled low to VGL1.

[0065] like Figure 2 As shown, the shift register unit further includes a blanking input sub-circuit 1600, comprising a 25th transistor M25, a 26th transistor M26, a 27th transistor M27, a 28th transistor M28, a 29th transistor M29, a 30th transistor M30, and a 6th capacitor C6, responding to the cascaded signal CR output from the previous stage shift register unit. <n-2>The blanking control signal OE and the blanking control clock signal CLKA are used to input the blanking signal.

[0066] like Figure 2 As shown, the shift register unit further includes a reset protection sub-circuit 1700, comprising a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24. The twenty-first transistor M21 and the twenty-second transistor M22 respond to the global reset control signal TRST to achieve a global reset of the gate drive circuit. The twenty-third transistor M23 and the twenty-fourth transistor M24 respond to the cascaded signal CR output from the next-stage shift register unit.<N+6> The 20th transistor M20 is used to reset the shift register unit at this stage, and it also performs leakage discharge function, thereby realizing the reset and protection of the shift register unit.

[0067] To further improve node control, such as Figure 10 As shown, the shift register unit includes: the input sub-circuit 2100 includes a thirty-first transistor M31, a thirty-second transistor M32, a thirty-third transistor M33, and a thirty-fourth transistor M34, wherein the gates of the thirty-first transistor M31 and the thirty-second transistor M32 are connected to the first input signal CR. <n-2>The first stage of the thirty-first transistor M31 is connected to the eleventh power supply signal GVDD1. The second stage of the thirty-first transistor M31 is connected to the first stage of the thirty-second transistor M32. The second stage of the thirty-second transistor M32 is connected to the first node Q. <n>The connection is as follows: the gate and first stage of the thirty-third transistor M33 are connected to the twelfth power supply signal GVDD2; the second stage of the thirty-third transistor M33 is connected to the first stage of the thirty-fourth transistor M34; the gate of the thirty-fourth transistor M34 is connected to the twelfth power supply signal GVDD2; and the second stage of the thirty-fourth transistor M34 is connected to the first stage of the thirty-second transistor M32. The thirty-third transistors M33 and M34 form an auxiliary input sub-circuit, further ensuring that the output potentials of the thirty-first transistor M31 and the thirty-second transistor M32 are high. The input sub-circuit responds to the first input signal CR. <n-2>Effectively output the first input signal to the first node Q <n>That is, raise the first node Q. <n>The potential.

[0068] like Figure 10 As shown, the node control sub-circuit 2200 includes a 35th transistor M35, a 36th transistor M36, a 37th transistor M37, a 38th transistor M38, a 39th transistor M39, a 40th transistor M40, and a 41st transistor M41. The gate of the 35th transistor M35 is connected to the second stage of the 40th transistor M40. The first stage of the 35th transistor M35 is connected to the 13th power supply signal GVDD3. The second stage of the 35th transistor M35 is connected to the first stage of the 36th transistor M36. The gate of the 36th transistor M36 is connected to the first node Q. <n>The connection is as follows: the second stage of the thirty-sixth transistor M37 is connected to the fourteenth power supply signal VGL1; the gate of the thirty-seventh transistor M37 is connected to the first stage of the thirty-sixth transistor M36; and the first stage of the thirty-seventh transistor M37 is connected to the first node Q. <n>The connection is as follows: the second stage of the thirty-seventh transistor M37 is connected to the first stage of the thirty-eighth transistor M38; the gate of the thirty-eighth transistor M38 is connected to the first stage of the thirty-sixth transistor M36; the second stage of the thirty-eighth transistor M38 is connected to the fourteenth power supply signal VGL1; the gate and first stage of the thirty-ninth transistor M39 are connected to the thirteenth power supply signal GVDD3; the second stage of the thirty-ninth transistor M39 is connected to the first stage of the fortieth transistor M40; the gate of the fortieth transistor M40 is connected to the thirteenth power supply signal GVDD3; the second stage of the fortieth transistor M40 is connected to the first stage of the forty-first transistor M41; the gate of the forty-first transistor M41 is connected to the first node Q. <n>The connection is made such that the second stage of the forty-first transistor M41 is connected to the fourteenth power supply signal VGL3. The node control sub-circuit is an inverter, making the levels at the first node and the second node opposite to each other. Specifically, the thirty-fifth transistor M35, the thirty-sixth transistor M36, the thirty-seventh transistor M37, and the thirty-eighth transistor M38 form an inverter. The thirty-ninth transistor M39 and the fortieth transistor M40 ensure a high input potential, and the fortieth transistor M40 ensures a low input potential, thereby further ensuring the node control sub-circuit's control over the potentials of the first and second nodes.

[0069] like Figure 10 As shown, the output sub-circuit 2300 includes a forty-second transistor M42, a forty-third transistor M43, a forty-fourth transistor M44, a forty-fifth transistor M45, a forty-sixth transistor M46, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, and a fifteenth capacitor C15. The gates of the forty-second to forty-sixth transistors M42 and M46 are connected to the first node Q. <n>The connections are as follows: the second stage of transistors M42 to M46 is connected to the second node QB; the first stage of transistor M42 is connected to the first clock signal CLKD3; the first stage of capacitor C11 is connected to the gate of transistor M42; the second stage of capacitor C11 is connected to the second terminal of transistor M42; the first stage of transistor M43 is connected to the first sub-signal CLKE1 of the second clock; the first stage of capacitor C12 is connected to the gate of transistor M43; the second stage of capacitor C12 is connected to the second terminal of transistor M43; the first stage of transistor M44 is connected to the second sub-signal CLKE2 of the second clock; and the first stage of capacitor C13 is connected to the second node QB. The gate of the forty-fourth transistor M44 is connected to the second terminal of the thirteenth capacitor C13. The first terminal of the forty-fifth transistor M45 is connected to the second clock third sub-signal CLKE3. The first terminal of the fourteenth capacitor C14 is connected to the gate of the forty-fifth transistor M45, and the second terminal of the fourteenth capacitor C14 is connected to the second terminal of the forty-fifth transistor M45. The first terminal of the forty-sixth transistor M46 is connected to the second clock fourth sub-signal CLKE4. The first terminal of the fifteenth capacitor C15 is connected to the gate of the forty-sixth transistor M46, and the second terminal of the fifteenth capacitor C15 is connected to the second terminal of the forty-sixth transistor M46. The first clock signal CLKD3 and the second clock third sub-signal CLKE3 are synchronized during display. When the output sub-circuit is active at the first node, it outputs the input first clock signal CLKD3 to the cascaded signal CR.<N+2> The terminal outputs the cascaded signals of the shift register unit at this stage, and simultaneously outputs the multiple input second clock signals CLKE1-4 to the corresponding multiple output signals G.<N+1> G<N+2> G<N+3> and G<N+4> The terminal outputs four gate drive signals, where, due to the first node Q... <n>The voltage level changes in a "tower-like" pattern. Therefore, the fourth gate drive signal has the lowest potential and is the first gate drive signal to be compensated. When the voltage level at the first node is invalid while the voltage level at the second node is valid, an invalid signal VGL1 or VGL2 is applied, and the cascaded signal CR...<N+2> Multiple output signals G<N+1> G<N+2> G<N+3> and G<N+4> All of these are invalid signals.

[0070] like Figure 10 As shown, the shift register unit also includes a noise reduction sub-circuit 2400, comprising transistors M47 (47th), M48 (48th), M49 (49th), M50 (50th), and M51 (51st). Under the control of the level at the second node, an invalid signal VGL2 is connected to the cascaded signal CR.<N+2> Multiple output signals G<N+1> G<N+2> G<N+3> and G<N+4> Noise reduction operations are performed separately.

[0071] like Figure 10 As shown, the shift register unit further includes an auxiliary pull-down circuit 2500, comprising transistors M52 (52nd), M53 (53rd), and M54 (54th), which further responds to the cascaded signal CR output from the previous stage shift register unit. <n-2>Alternatively, under the control of the blanking control clock signal CLKA and the blanking control auxiliary signal H, the potential of the second node QB is pulled low to VGL1.

[0072] like Figure 10 As shown, the shift register unit further includes a blanking input sub-circuit 2600, comprising a 60th transistor M60, a 61st transistor M61, a 62nd transistor M62, a 63rd transistor M63, a 64th transistor M64, a 65th transistor M65, and a 16th capacitor C16, responding to the cascaded signal CR output from the previous stage shift register unit. <n-2>The blanking control signal OE and the blanking control clock signal CLKA are used to input the blanking signal.

[0073] like Figure 10 As shown, the shift register unit further includes a reset protection sub-circuit 2700, comprising transistors M55 (55), M56 (56), M57 (57), M58 (58), and M59 (59). Transistors M56 and M57 respond to the global reset control signal TRST to perform a global reset of the gate drive circuit. Transistors M58 and M59 respond to the cascaded signal CR output from the next-stage shift register unit.<N+6> The 55th transistor M55 is used to reset the shift register unit at this stage, thereby realizing the reset and protection of the shift register unit.

[0074] To further alleviate the problem of the low potential of the last gate output signal of the multi-output shift register unit, in a specific embodiment, such as Figure 11 As shown, the shift register unit includes: an input sub-circuit 2100, which responds to the first input signal CR. <n-2>Effectively output the first input signal to the first node Q <n>That is, raise the first node Q. <n>The voltage level at the first node and the voltage level at the second node are the same. The specific structure of the input sub-circuit is the same as in the previous embodiment and will not be described again here. The node control sub-circuit 2200 is an inverter, which makes the voltage level at the first node and the voltage level at the second node opposite to each other. The specific structure of the node control sub-circuit is the same as in the previous embodiment and will not be described again here. When the voltage level at the first node is active, the output sub-circuit 2300 outputs the input first clock signal CLKD4 to the cascaded signal CR.<N+2> The terminal outputs the cascaded signals of the shift register unit at this stage, and simultaneously outputs the multiple input second clock signals CLKE1-4 to the corresponding multiple output signals G.<N+1> G<N+2> G<N+3> and G<N+4> The terminal outputs four gate drive signals, among which the first clock signal CLKD4 and the second clock fourth sub-signal CLKE4 are synchronized during the display process.

[0075] In this embodiment, by using the first clock signal CLKD4, which is synchronized with the fourth sub-signal CLKE4 of the second clock, the eleventh capacitor C11 and the fifteenth capacitor C15 are connected in parallel, thereby improving the Q of the first node. <n>The potential is used to compensate for the fourth gate drive signal of the shift register unit. Furthermore, by using a clock signal corresponding to the last gate drive signal of the multi-output shift register unit to synchronize with the first clock signal, two capacitors are coupled to increase the capacitance and improve the Q of the first node. <n>The potential of the first gate drive signal to be compensated is adjusted to compensate for the lowest potential of the shift register unit, that is, the first node Q is adjusted. <n>The "tower-like" shape of the voltage level; thereby, based on the aforementioned embodiment where the first gate drive signal with the lowest potential is compensated by a staggered bilateral gate drive circuit, the display effect of the display panel is further improved, and the user experience is enhanced.

[0076] It is worth noting that the above embodiments are all for illustrating specific implementation methods of this application. This application does not specifically limit the structure of the bilateral gate drive circuit. It can be the same structure or different structures. Those skilled in the art should set it according to actual application requirements, with the design principle of using the non-lowest potential gate drive signal connected on one side to compensate the lowest potential gate drive signal connected to the sub-pixel in the same row on the other side. It will not be elaborated here. Corresponding to the display panel provided in the above embodiments, one embodiment of this application also provides a driving method for using the above-described display panel, comprising: The multi-output shift register unit outputs multiple gate drive signals according to the input signal. The multiple gate drive signals include the first gate drive signal to be compensated with the lowest potential. The multi-output shift register unit is included in at least one of two gate drive circuits arranged opposite to each other. At least one row sub-pixel is connected to the first gate drive signal to be compensated, and simultaneously connected to the gate drive signal output by the shift register unit of another gate drive circuit, which has a potential higher than the first gate drive signal to be compensated.

[0077] This embodiment addresses the problem in a dual-side gate drive circuit including a multi-output shift register unit where the potential of the first node changes in a "tower-like" pattern during operation, resulting in a low potential for the last output gate drive signal. By loading gate drive signals with different potentials onto a row of sub-pixels, potential compensation is achieved for the sub-pixel row with the lowest loaded potential (the first gate drive signal to be compensated). Specifically, the dual-side gate drive circuits are staggered, so that the sub-pixel row with the lowest loaded potential (the first gate drive signal to be compensated) is simultaneously loaded with another gate drive signal that is not the lowest. This staggered dual-side gate drive circuit achieves potential compensation, overcoming the problems in the prior art, effectively improving display performance, and has broad application prospects.

[0078] Since the driving method provided in this application corresponds to the display panel provided in the above embodiments, the driving method provided in this embodiment is also applicable to the previous implementation methods, and will not be described in detail in this embodiment.

[0079] In an optional embodiment, such as Figure 11 As shown, the multi-output shift register unit is configured to output a cascaded signal CR in response to the input first clock signal CLKD4.<N+2> And in response to the input of multiple second clock signals, CLKE1-4 outputs multiple output signals G corresponding to the second clock signals respectively.<N+1> G<N+2> G<N+3> and G<N+4> The multi-output shift register unit outputs multiple gate drive signals according to the input signal, further comprising: the first clock signal and the second clock signal corresponding to the first gate drive signal to be compensated are synchronized during the display process.

[0080] In this embodiment, by using the first clock signal CLKD4, which is synchronized with the fourth sub-signal CLKE4 of the second clock, the eleventh capacitor C11 and the fifteenth capacitor C15 are connected in parallel, thereby improving the Q of the first node. <n>The potential is used to compensate for the fourth gate drive signal of the shift register unit. Furthermore, by using a clock signal corresponding to the last gate drive signal of the multi-output shift register unit to synchronize with the first clock signal, two capacitors are coupled to increase the capacitance and improve the Q of the first node. <n>The potential of the first gate drive signal to be compensated is adjusted to compensate for the lowest potential of the shift register unit, that is, the first node Q is adjusted. <n>The "tower-like" shape of the voltage level; thereby, based on the aforementioned embodiment where the first gate drive signal with the lowest potential is compensated by a staggered bilateral gate drive circuit, the display effect of the display panel is further improved, and the user experience is enhanced.

[0081] Based on the aforementioned display panel, another embodiment of the present invention provides a display device including the aforementioned display panel, wherein the display device is a liquid crystal display device or an electroluminescent diode display device. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0082] This invention addresses existing problems by providing a display panel, display device, and driving method. It achieves potential compensation for the sub-pixel row with the lowest-potential first gate driving signal by loading gate driving signals of different potentials onto a row of sub-pixels. Specifically, the dual-sided gate driving circuits are staggered, so that the sub-pixel row with the lowest-potential first gate driving signal is simultaneously loaded with another gate driving signal that is not the lowest-potential. This staggered dual-sided gate driving circuitry achieves potential compensation, overcoming the problems in existing technologies, effectively improving display performance, and has broad application prospects.

[0083] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display panel, comprising a display area and a non-display area, characterized in that, The display area includes multiple rows of sub-pixels, and the non-display area includes two gate driving circuits arranged opposite each other. Each gate driving circuit includes multiple cascaded shift register units, and each row of sub-pixels receives gate driving signals output from the two gate driving circuits respectively. At least one of the two gate drive circuits arranged opposite each other includes at least one multi-output shift register unit, which outputs multiple gate drive signals; The gate drive signals output by one of the two gate drive circuits that are arranged opposite to each other are staggered from the gate drive signals output by the other gate drive circuit.

2. The display panel according to claim 1, characterized in that, The two gate driving circuits arranged opposite to each other are a first gate driving circuit arranged on the left side of the multi-row sub-pixels in the display area and a second gate driving circuit arranged on the right side of the multi-row sub-pixels in the display area. The first gate driving circuit includes a plurality of cascaded first shift register units, and the second gate driving circuit includes a plurality of cascaded second shift register units. The gate drive signal output by the first shift register unit connected to the left side of each row of sub-pixels is different from the gate drive signal output by the second shift register unit connected to the right side, which has the same structure as the first shift register unit.

3. The display panel according to claim 2, characterized in that, Before the sub-pixel is accessed, the number of pseudo-signals output by the first shift register unit is different from the number of pseudo-signals output by the second shift register unit.

4. The display panel according to claim 2, characterized in that, The number of pseudo signals output by the last stage first shift register unit of the first gate driving circuit is different from the number of pseudo signals output by the last stage second shift register unit of the second gate driving circuit.

5. The display panel according to claim 1, characterized in that, The plurality of gate drive signals includes the first gate drive signal to be compensated with the lowest potential. At least one row sub-pixel is connected to the first gate drive signal to be compensated, and simultaneously connected to the gate drive signal output by the shift register unit of another gate drive circuit, which has a potential higher than the first gate drive signal to be compensated.

6. The display panel according to claim 5, characterized in that, The two gate drive circuits arranged opposite each other are a first gate drive circuit and a second gate drive circuit. The first gate driving circuit includes multiple cascaded first shift register units, and the second gate driving circuit includes multiple cascaded second shift register units. The first shift register units and the second shift register units are multi-output shift register units with the same structure. At least one gate drive signal output by the first stage second shift register unit of the second gate drive circuit is used as a pseudo signal, and at least one gate drive signal is connected to the display area. The gate drive signals output by other stages of the second shift register unit are connected to the display area in sequence, so that the row sub-pixel connected to the first gate drive signal to be compensated output by the first gate drive circuit is connected to the gate drive signal other than the first gate drive signal to be compensated output by the second gate drive circuit.

7. The display panel according to claim 5, characterized in that, The two gate drive circuits arranged opposite each other are a third gate drive circuit and a fourth gate drive circuit. The third gate drive circuit includes at least one multi-output shift register unit, and the fourth gate drive circuit includes multiple single-output shift register units. The row sub-pixel is connected to the first gate drive signal to be compensated output by the third gate drive circuit, and is also connected to the gate drive signal output by the single output shift register unit of the fourth gate drive circuit.

8. The display panel according to claim 5, characterized in that, This includes a compensation region connected to the first-stage shift register unit of the gate drive circuit, and a non-compensation region connected to the last-stage shift register unit of the gate drive circuit, wherein... In the compensation region, the row sub-pixel connected to the first gate drive signal to be compensated has a potential output by the shift register unit of another gate drive circuit that is higher than the gate drive signal of the first gate drive signal to be compensated.

9. The display panel according to any one of claims 5-8, characterized in that, The multi-output shift register unit of the gate drive circuit includes an input sub-circuit, a node control sub-circuit, and an output sub-circuit, wherein... The input sub-circuit is configured to output a first input signal to a first node in response to a first input signal; The node control sub-circuit is configured to write a level to the second node that is opposite to the level at the first node; The output sub-circuit is configured to output the input first clock signal to the cascaded signal terminal under the control of the level at the first node, and to output multiple second clock signals to multiple output signal terminals corresponding to the second clock signals under the control of the level at the first node, and is configured to output the input inactive level signal to the cascaded signal terminal and the multiple output signal terminals under the control of the level at the second node.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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