A display panel, display device and apparatus

Abstract

This application provides a display panel, display device, and apparatus. The display panel includes a display area and a non-display area. The display area includes a plurality of signal lines arranged along a first direction, and the non-display area includes a plurality of shift register units electrically connected to the signal lines. The display area includes a first display area and a second display area arranged along the first direction. The second display area includes a chamfered area, and the boundary line between the chamfered area and the non-display area is a first boundary line. The non-display area includes a first region and a second region adjacent to each other along the first direction. The first region and the first display area, and the second region and the second display area are respectively adjacent along a second direction, and the second direction intersects the first direction. The boundary line between the second region and the display area is a second boundary line, and the first boundary line covers the second boundary line. The projection of the shift register units along a third direction does not overlap with the second region, and the third direction is perpendicular to the first and second directions. At least some of the shift register units are disposed within the first region.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel, display device, and equipment. Background Technology

[0002] As consumer demand increases, there is a growing need for increasingly narrow bezels on display panels. However, while existing display panels achieve extremely narrow top, bottom, left, and right bezels, the corner bezels cannot be reduced to the ideal width due to limitations in circuit layout. Therefore, the circuit layout at the corners of display panels requires further optimization. Summary of the Invention

[0003] The purpose of this application is to provide a display panel, display device, and apparatus. This application aims to address the problem in the prior art where the bezel width at the corners of the display panel needs further optimization.

[0004] This application provides a display panel, including a display area and a non-display area. The display area includes a plurality of signal lines arranged along a first direction, and the non-display area includes a plurality of shift register units, which are electrically connected to their corresponding signal lines. The display area includes a first display area and a second display area, which are arranged along the first direction. The second display area includes a chamfered area, and the boundary line between the chamfered area and the non-display area is a first boundary line. The non-display area includes a first region and a second region, where the first region and the first display area are adjacent along a second direction, and the second region and the second display area are adjacent along the second direction. The second direction intersects the first direction, and the first region and the second region are adjacent along the first direction. The boundary line between the second region and the display area is a second boundary line, and the first boundary line covers the second boundary line. The projection of the shift register units along a third direction does not overlap with the second region, and the third direction is perpendicular to both the first and second directions. At least some of the shift register units are disposed within the first region.

[0005] In one possible implementation of the first aspect, a plurality of pixel circuits are disposed within the display area. Each pixel circuit includes a plurality of transistors, and signal lines are electrically connected to the gates of at least some of the transistors. The projection of the pixel circuit along a third direction is a first projection, and the length of the first projection along the first direction is a first length. The projection of at least some of the shift register units along a third direction is a second projection, and the length of the second projection along the first direction is a second length. The first length is greater than the second length.

[0006] In one possible implementation of the first aspect, the first region includes a first sub-region and a second sub-region, with the second sub-region located between the first and second regions. The projection of a shift register unit located within the first sub-region along a third direction is the first sub-projection. The projection of a shift register unit located within the second sub-region along a third direction is the second sub-projection. The length of the first sub-projection along a first direction is the first sub-length, and the length of the second sub-projection along the first direction is the second sub-length. The first sub-length and the second sub-length are not equal, and the first sub-length is less than the first length, and the second sub-length is less than the first length.

[0007] In one possible implementation of the first aspect, the first region includes a third sub-region and a fourth sub-region, with the fourth sub-region located between the third sub-region and the second region. The projection of a shift register unit located within the third sub-region along a third direction is a first sub-projection. The projection of a shift register unit located within the fourth sub-region along a third direction is a second sub-projection. The distance between two adjacent first sub-projections along a first direction is a first distance. The distance between two adjacent second sub-projections along a first direction is a second distance. The second distance is less than or equal to the first distance.

[0008] In one possible implementation of the first aspect, the first distance is greater than zero, and the second distance is greater than or equal to zero. The second distance is less than the first distance.

[0009] In one possible implementation of the first aspect, a plurality of pixel circuits are provided in the display area, each pixel circuit including a plurality of transistors, and signal lines are electrically connected to the gates of at least some of the transistors; the projection of the pixel circuit along a third direction is a first projection, and the length of the first projection along a first direction is a first length; the first length is the sum of a second length and a first distance.

[0010] In one possible implementation of the first aspect, both the first distance and the second distance are zero.

[0011] In one possible implementation of the first aspect, a dummy shift register is further included, located on the side of the shift register closer to the second region. The dummy shift register is electrically isolated from any signal line.

[0012] In one possible implementation of the first aspect, some of the shift register units among a plurality of shift register units are electrically connected to corresponding signal lines via a first connecting line. The first connecting line includes a first connecting portion and a second connecting portion, which are electrically connected. The first connecting portion is located in a non-display area, and the second connecting portion is located in a display area. The second connecting portion includes a first sub-portion and a second sub-portion, which are electrically connected. The first sub-portion extends along a second direction, and the second sub-portion extends along a first direction.

[0013] In one possible implementation of the first aspect, one end of the second sub-part is connected to the first sub-part, and the other end of the second sub-part is connected to the corresponding signal line.

[0014] In one possible implementation of the first aspect, the second sub-part includes a first node, which is a connection point connecting the second sub-part and the first sub-part. The first node is located between the two endpoints of the second sub-part.

[0015] In one possible implementation of the first aspect, the second connection portion further includes a third sub-portion extending along the second direction. One end of the third sub-portion is connected to the second sub-portion, and the other end of the third sub-portion is electrically connected to a corresponding signal line.

[0016] In one possible implementation of the first aspect, some of the shift register units are electrically connected to corresponding signal lines via a second connection line. The second connection line includes a third connection portion and a fourth connection portion, which are electrically connected. The third connection portion is located in a first region and is electrically connected to the shift register unit, while the fourth connection portion is located in a second region and is electrically connected to the signal line.

[0017] In one possible implementation of the first aspect, some of the shift register units are electrically connected to corresponding signal lines via a third connection line. The third connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the second sub-connection line. The resistivity of the first sub-connection line is different from that of the second sub-connection line.

[0018] In one possible implementation of the first aspect, some of the shift register units are electrically connected to corresponding signal lines via a common connection line. One end of the common connection line is electrically connected to at least two shift register units, and the other end of the common connection line is electrically connected to at least two corresponding signal lines.

[0019] In a second aspect, this application provides a display panel, comprising: a display area and a non-display area. The display area includes a plurality of signal lines arranged along a first direction, and the non-display area includes a plurality of shift register units, each shift register unit being electrically connected to a corresponding signal line. The display area includes a first display area and a second display area, which are arranged along the first direction. The second display area includes a chamfered area, and the boundary line between the chamfered area and the non-display area is a first boundary line. The non-display area includes a first region and a second region, where the first region and the first display area are adjacent along a second direction, and the second region and the display area are adjacent along the second direction, intersecting the first direction. The boundary line between the second region and the display area is a second boundary line, which covers the first boundary line. Within the second region, a plurality of common connecting lines are provided, one end of each common connecting line being electrically connected to at least two shift register units, and the other end of each common connecting line being electrically connected to at least two corresponding signal lines.

[0020] In one possible implementation of the second aspect, among a plurality of shared connecting lines, at least a portion of the shared connecting lines include a first sub-connecting line and a second sub-connecting line, the first sub-connecting line and the second sub-connecting line being electrically connected. The resistivity of the first sub-connecting line is different from that of the second sub-connecting line.

[0021] In one possible implementation of the second aspect, the first region includes multiple shift register units, and the second region includes multiple shift register units.

[0022] In one possible implementation of the second aspect, the signal lines include data write control scan signal lines. A common connection line is electrically insulated from any data write control scan signal lines.

[0023] Thirdly, this application provides a display device, which includes a display panel as described in the first or second aspect.

[0024] Fourthly, this application provides an apparatus, which includes a display panel of the first or second aspect or a display device of the third aspect.

[0025] Compared to existing technologies, this application does not include a shift register unit in the second region; that is, no shift register unit is provided in the area near the corner of the display area within the non-display area of ​​the display panel. Because no shift register unit is provided in the second region, the width of the second region at the corner can be reduced, thereby lowering the width of the region at the corner. Alternatively, this application can merge multiple shared connecting lines located within the second region, reducing the total number of shared connecting lines within the second region, thus further reducing the width of the second region at the corner and optimizing the width of the region at the corner. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the corner area of ​​a display panel in the prior art.

[0027] Figure 2 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0028] Figure 3 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0029] Figure 4 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0030] Figure 5 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0031] Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0032] Figure 7 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0033] Figure 8 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0034] Figure 9 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0035] Figure 10 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0036] Figure 11 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0037] Figure 12 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0038] Figure 13 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0039] Figure 14 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0040] Figure 15 Provided for the embodiments of this application Figure 14 A magnified view of a portion of region B in the middle.

[0041] Figure 16 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0042] Figure 17 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region C.

[0043] Figure 18 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region C.

[0044] Figure 19 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region D.

[0045] Figure 20 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region D.

[0046] Figure 21 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region D.

[0047] Figure 22 This is a schematic diagram of a display device provided in an embodiment of this application.

[0048] Explanation of reference numerals in the attached figures

[0049] NA - Non-display area; NA1 - First area; NA11 - First sub-area; NA12 - Second sub-area; NA13 - Third sub-area; NA131 - First sub-area; NA132 - Second sub-area; NA14 - Fourth sub-area; NA2 - Second area; AA - Display area; AA1 - First display area; AA2 - Second display area; 100 - Display panel; 101 - Shift register unit; 102 - Signal line; 103 - Dummy Shift register unit; 104-Pixel circuit; 110-First connecting line; 111-First connecting part; 112-Second connecting part; 1121-First sub-part; 1122-Second sub-part; 1123-Third sub-part; 120-Second connecting line; 121-Third connecting part; 122-Fourth connecting part; 130-Third connecting line; 131-First sub-connecting line; 132-Second sub-connecting line; 140-Common connecting line; 200-Display device. Detailed Implementation

[0050] Figure 1This is a schematic diagram of the corner area of ​​a display panel in the prior art.

[0051] Please see Figure 1 To reduce the width of the corner areas, existing display panels employ chamfered corners in both the display and non-display areas. Furthermore, to further reduce the width of these chamfered areas, the shift register circuits within the chamfered areas of the non-display areas are arranged in a fan-shaped or arc-shaped pattern along the chamfer. Based on this, the applicant's research reveals that the main reason why the width of the bezel at the corners of the display panel is difficult to reduce is that the corner areas of the non-display areas have numerous and complex wiring lines, and also contain shift register units 101 for driving the pixel circuits 104 at the corners of the display area. Both the complex wiring lines and the shift register units 101 occupy a significant amount of space, and to ensure the normal operation of the pixel circuits 104 at the corners of the display panel, the width of this area cannot be further reduced.

[0052] Figure 2 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 3 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0053] like Figures 2 to 3 As shown, this application provides a display panel 100, including a display area AA and a non-display area NA. The display area AA includes a plurality of signal lines 102 arranged along a first direction X, and the non-display area NA includes a plurality of shift register units 101. The shift register units 101 are electrically connected to the corresponding signal lines 102. The display area AA includes a first display area AA1 and a second display area AA2, which are arranged along the first direction X. The second display area AA2 includes a chamfered area, and the boundary line between the chamfered area and the non-display area NA is a first boundary line. The non-display area NA includes a first region NA1 and a second region NA2. The first region NA1 is adjacent to the first display area AA1 along a second direction Y, and the second region NA2 is adjacent to the second display area AA2 along the second direction Y. The second direction Y intersects with the first direction X, and the first region NA1 and the second region NA2 are adjacent along the first direction X. The boundary line between the second region NA2 and the display area AA is a second boundary line, and the first boundary line covers the second boundary line. The projection of the shift register unit 101 along a third direction does not overlap with the second region NA2, and the third direction is perpendicular to the first direction X and the second direction Y. Furthermore, at least a portion of the shift register units 101 are disposed within the first region NA1.

[0054] like Figure 2 As shown, the shift register unit 101 can be disposed within the first region NA1 on one side of the first display area AA1. Figure 3 As shown, the shift register unit 101101 can be disposed in the first area NA1 on both sides of the first display area AA1.

[0055] Compared with the prior art, the second region NA2 in this application does not have a shift register unit 101, that is, the non-display area NA of the display panel 100 near the corner of the display area AA does not have a shift register unit 101. Since the second region NA2 does not have a shift register unit 101, the width of the second region NA2 at the corner can be reduced, thereby reducing the width of the region at the corner.

[0056] In some embodiments of this application, signal line 102 can be a scan signal line 102, such as a light emission control scan signal line 102, a reset control scan signal line 102, and a data write control scan signal line 102; the first direction X is perpendicular to the second direction Y. The light emission control scan signal line 102 is electrically connected to the gate of the light emission control transistor in the corresponding pixel circuit 104, and is used to control the activation of the pixel circuit 104 to make the light-emitting element emit light. The reset control scan signal line 102 is electrically connected to the gate of the reset transistor in the corresponding pixel circuit 104, and is used to control the reset of the pixel circuit 104. The data write control scan signal line 102 is electrically connected to the gate of the data write transistor in the corresponding pixel circuit 104, and is used to control the writing of data voltage. The pixel circuit 104 refers to a driving circuit electrically connected to the light-emitting element, under the drive of the pixel circuit 104, the light-emitting element can emit light.

[0057] In one embodiment of this application, the first boundary line coincides with the second boundary limit.

[0058] In one implementation of this embodiment, the first boundary line is an arc, and the boundary line of the first region NA1 is a rectangle. That is, the chamfer of the display area AA is rounded, and its chamfered area is a rounded area.

[0059] In one embodiment of this application, among the plurality of shift register units 101 located in the first region NA1, at least a portion of the shift register units 101 are electrically connected to signal lines 102 located in the second display area AA2. That is, the shift register units 101 that are at least partially electrically connected to signal lines 102 in the second display area AA2 are located in the first region NA1, thereby reducing the number of shift register units 101 in the corner areas of the display panel 100, which is beneficial to reducing the width of the display panel 100 at the corner positions.

[0060] Figure 4 A schematic diagram of a display panel provided in an embodiment of this application; Figure 5 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0061] like Figures 4 to 5 As shown, in one embodiment of this application, a plurality of pixel circuits 104 are disposed within the display area AA. Each pixel circuit 104 includes a plurality of transistors, and signal lines 102 are electrically connected to the gates of at least a portion of the transistors. The projection of the pixel circuit 104 along a third direction is a first projection, and the length of the first projection along the first direction X is a first length L1. The projection of at least a portion of the shift register units 101 along a third direction is a second projection, and the length of the second projection along the first direction X is a second length L2. The first length L1 is greater than the second length L2.

[0062] In this embodiment, the first length L1 is greater than the second length L2, which ensures that there is a difference in the space length occupied by the shift register unit 101 and the pixel circuit in the first direction X. This difference provides space for the shift register unit 101 corresponding to the pixel circuit 104 located in the corner area to be inserted in the first region NA1.

[0063] In such Figure 4 As shown, in one embodiment of this application, the first region NA1 includes a first sub-region NA11 and a second sub-region NA12, with the second sub-region NA12 located between the first sub-region NA11 and the second region NA2. The projection of the shift register unit 101 located in the first sub-region NA11 along a third direction is the first sub-projection. The projection of the shift register unit 101 located in the second sub-region NA12 along a third direction is the second sub-projection. The length of the first sub-projection along the first direction X is the first sub-length L21, and the length of the second sub-projection along the first direction X is the second sub-length L22. The first sub-length L21 and the second sub-length L2 are not equal, and the first sub-length L21 is less than the first length L1, and the second sub-length L22 is less than the first length L1.

[0064] In this embodiment, the shift register unit 101 has a differentiated design in terms of size. This differentiated design can better improve space utilization.

[0065] In one embodiment of this application, a plurality of pixel circuits 104 are disposed within the display area AA. Each pixel circuit 104 includes a plurality of transistors, and signal lines 102 are electrically connected to the gates of at least a portion of the transistors. The projection of the pixel circuit 104 along a third direction is a first projection, and the length of the first projection along the first direction X is a first length L1. The projection of at least a portion of the shift register units 101 along a third direction is a second projection, and the length of the second projection along the first direction X is a second length L2. The first length L1 is less than or equal to the second length L2.

[0066] In one possible implementation of this embodiment, the first sub-length L21 is greater than the second sub-length L22. That is, the size of the shift register unit that provides the driving signal for the pixel circuit 104 in the chamfered area is smaller than the shift register circuit that provides the driving signal for the pixel circuit 104 in the first display area AA1. Since the number of pixel circuits 104 in the chamfered area is small, the size of the shift register unit 101 that provides the driving signal for it (i.e., the shift register unit 101 located in the second sub-region NA12) can be made smaller, thereby making more reasonable use of space and improving space utilization.

[0067] like Figure 5 As shown, the length of the second projection along the first direction X is equal. This design facilitates manufacturing processes.

[0068] like Figure 5 As shown, in one embodiment of this application, the first region NA1 includes a third sub-region NA13 and a fourth sub-region NA14, with the fourth sub-region NA14 located between the third sub-region NA13 and the second region NA2. The projection of the shift register unit 101 located in the third sub-region NA13 along a third direction is a first sub-projection. The projection of the shift register unit 101 located in the fourth sub-region NA14 along a third direction is a second sub-projection. The distance between two adjacent first sub-projections along the first direction X is a first distance D1. The distance between two adjacent second sub-projections along the first direction X is a second distance D2. The second distance D2 is less than or equal to the first distance D1.

[0069] In this embodiment, the third sub-region NA13 is located in the middle of the first region NA1, and the fourth sub-region NA14 is located at the end of the first region NA1. For example, the third sub-region NA13 is located on the outer periphery of the first display area AA1, and the fourth sub-region NA14 is located on one side of the second display area AA2. The first display area AA1 is the straight section of display area AA. The second display area AA2 is located on the side near the inner corner of display area AA. The arrangement density of the first shift register unit 101 in the third sub-region NA13 is less than or equal to the arrangement density of the second shift register unit 101 in the fourth sub-region NA14. This design facilitates the placement of all shift register units 101 within the first region NA1 without affecting the display effect.

[0070] In one embodiment of this application, the first distance D1 is greater than zero, and the second distance D2 is greater than or equal to zero. The second distance D2 is less than the first distance D1.

[0071] In this embodiment, the arrangement density of the shift register units 101 is differentiated within the first region NA1: the arrangement density of the shift register units 101 located in the middle of the first region NA1 is less than the arrangement density at both ends of the first region NA1. This differentiation further facilitates the realization that all the shift register units 101 can be placed within the first region NA1 without affecting the display effect.

[0072] In one embodiment of this application, the first distance D1 is equal to the second distance D2, and both the first distance D1 and the second distance D2 are greater than zero.

[0073] In this embodiment, the shift register units 101 in the first region NA1 are uniformly distributed, which can simplify the manufacturing process and reduce the manufacturing cost.

[0074] In one embodiment of this application, a plurality of pixel circuits 104 are provided in the display area AA. Each pixel circuit 104 includes a plurality of transistors, and a signal line 102 is electrically connected to the gate of at least a portion of the transistors. The projection of the pixel circuit 104 along a third direction is a first projection, and the length of the first projection along the first direction X is a first length. The first length L1 is the sum of a second length L2 and a first distance D1.

[0075] In this embodiment, the first length L1 is the sum of the second length L2 and the first distance D1. This design enables a one-to-one correspondence between the shift register unit 101 located in the middle of the first region NA1 along the first direction X and the pixel in the first display area AA1. This design facilitates the wiring of the connection line between the shift register unit 101 located in the middle of the first region NA1 and the corresponding signal line 102.

[0076] Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0077] like Figure 6 As shown in one embodiment of this application, both the first distance D1 and the second distance D2 are zero.

[0078] In this embodiment, the shift register units 101 are closely arranged in the first region NA1 along the first direction X. This close arrangement saves space and ensures that these shift register units 101 are located only within the first region NA1.

[0079] In one embodiment of this application, each shift register unit 101 within the first region NA1 is electrically connected to its corresponding signal line 102. That is, all shift register units 101 within the first region NA1 are valid and can output valid signals to their corresponding signal lines 102. This design maximizes the utilization of the space in the first region NA1.

[0080] In one embodiment of this application, the display panel 100 further includes a dummy shift register unit 103, which is located on the side of the shift register unit 101 near the second region NA2. The dummy shift register unit 103 is electrically insulated from any signal line 102.

[0081] In this embodiment, the dummy shift register does not output any valid signals. The purpose of the dummy shift register 103 is to ensure the stability of the operation of the shift register 101, which is electrically connected to the signal line 102 at the edge of the first region NA1.

[0082] Figure 7 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0083] like Figure 6 or Figure 7 As shown, in one embodiment of this application, the display panel 100 further includes a dummy shift register unit 103. The dummy shift register unit 103 is located within the third sub-region NA13 and on the side of the shift register unit 101 closest to the fourth sub-region NA14. The dummy shift register unit 103 is electrically insulated from any signal line 102.

[0084] In this embodiment, the purpose of the dummy shift register unit 103 is to compensate for the difference in the total length of the pixel circuit in the first display area AA1 and the shift register unit 101 in the third sub-region NA13 in the first direction X, so as to facilitate the wiring of the shift register in the fourth sub-region.

[0085] In one possible implementation of this embodiment, all shift register units 101 within the third sub-region NA13 are arranged uniformly in the first direction X, and a dummy shift register unit 103 is provided between the shift register units 101 in the third sub-region NA13 and the shift register units 101 in the fourth sub-region NA14. This dummy shift register unit 103 can ensure the performance of the shift register units 101 located near the edge of the fourth sub-region NA14, and improve the stability of the shift register units 101 during operation.

[0086] like Figure 7 As shown, in one embodiment of this application, the third sub-region NA13 includes a first sub-region NA131 and a second sub-region NA132. The second sub-region NA132 is located between the third sub-region 1123 and the fourth sub-region NA14. All shift register units 101 within the third sub-region NA13 are located within the first sub-region NA131. It can be understood that no shift register unit 101 is provided within the second sub-region NA132.

[0087] In this embodiment, no shift register unit 101 is provided in the second sub-region NA132. This design facilitates the realization that, within a predetermined length in the first direction X, the shift register unit 101 in the third sub-region NA13 corresponds to the area of ​​the pixel circuit 104 in the first display area AA1. This design enables isolation between the shift register unit 101 in the third sub-region NA13 and the shift register unit 101 in the fourth sub-region NA14. The arrangement spacing of the shift register units 101 in the first sub-region NA131 and the arrangement spacing of the shift register units 101 in the fourth sub-region NA14 may not be the same; this isolation can effectively reduce the adverse effects caused by this difference in arrangement spacing.

[0088] like Figure 7 As shown, in one implementation of this embodiment, a dummy shift register 103 is provided in both the first sub-region NA131 and the second sub-region NA12. Specifically, the dummy shift register 103 in the first sub-region NA131 is located on the side of the shift register 101 (the effective shift register 101) closer to the second sub-region NA132; the dummy shift register 103 in the fourth sub-region is also located on the side of the shift register 101 (the effective shift register 101) closer to the second sub-region NA132. This design ensures the electrical stability of the effective shift register 101 in both the first sub-region NA131 and the second sub-region NA12 when they are in operation.

[0089] Figure 8 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle. Figure 9 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle. Figure 10 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0090] like Figures 8 to 10As shown, in one embodiment of this application, some of the shift register units 101 are electrically connected to corresponding signal lines 102 via a first connection line 110. The first connection line 110 includes a first connection portion 111 and a second connection portion 112, which are electrically connected. The first connection portion 111 is located within the non-display area NA, and the second connection portion 112 is located within the display area AA. The second connection portion 112 includes a first sub-part 1121 and a second sub-part 1122, which are electrically connected. The first sub-part 1121 extends along a second direction Y, and the second sub-part 1122 extends along a first direction X.

[0091] like Figures 8 to 10 As shown, in one implementation of this embodiment, the first sub-part 1121 and the second sub-part 1122 are electrically connected through a wire hole.

[0092] In one implementation of this embodiment, the first connecting portion 111 is located within the fourth sub-region NA14.

[0093] like Figures 8 to 10 As shown, in this embodiment, the first connecting portion 111 is located within the non-display area NA, and the second connecting portion 112 is located within the display area AA. This allows the first connecting line 110 to bypass the second area NA2 and electrically connect to the corresponding signal line 102, thereby reducing the width of the second area NA2 at its corners. The first direction X intersects the second direction Y. The first sub-portion 1121 extends along the second direction Y, and the second sub-portion 1122 extends along the first direction X. This design facilitates wiring and manufacturing processes.

[0094] like Figure 8 As shown, in one embodiment of this application, one end of the second sub-part 1122 is connected to the first sub-part 1121, and the other end of the second sub-part 1122 is connected to the corresponding signal line 102.

[0095] In this embodiment, one end of the first sub-part 1121 is a connection point to the first sub-part 1121, and the other end of the second sub-part 1122 is a connection point to the corresponding signal line 102. One end of the second sub-part 1122 is electrically connected to the first sub-part 1121, and the other end of the second sub-part 1122 is electrically connected to the corresponding signal line 102. The second sub-part 1122 is entirely used to transmit electrical signals, meaning its effective length is equal to its actual length. The effective length refers to the length used for transmitting electrical signals. The second sub-part 1122 is directly electrically connected to the signal line 102, meaning the endpoint of the second sub-part 1122 electrically connected to the signal line 102 can be located between the two endpoints of the signal line 102. Therefore, the solution provided in this embodiment ensures that the entire length of the second connecting part 1122 is an effective length, which helps save on the manufacturing materials of the second sub-part 1122 and reduces production costs.

[0096] like Figure 9 As shown, in one embodiment of this application, the second sub-part 1122 includes a first node, which is the connection point connecting the second sub-part 1122 and the first sub-part 1121. The first node is located between the two endpoints of the second sub-part 1122.

[0097] In this embodiment, the first node can be a through hole. The second sub-part 1122 extends from the first node along the second direction Y to both ends, that is, the actual length of the second sub-part 1122 is greater than the effective length of the second sub-part 1122. This design can ensure the uniformity of metal density within the display area AA where multiple second sub-parts 1122 are located. Metal density refers to the percentage of area occupied by metal per unit area.

[0098] like Figure 10 As shown, in one embodiment of this application, the second connecting portion 112 further includes a third sub-portion 1123, which extends along the second direction Y. One end of the third sub-portion 1123 is connected to the second sub-portion 1122, and the other end of the third sub-portion 1123 is electrically connected to the corresponding signal line 102.

[0099] like Figure 10 As shown, in one implementation of this embodiment, the third sub-part 1123 and the second sub-part 1122 are electrically connected through a wire hole.

[0100] In this embodiment, the third sub-part 1123 is electrically connected to the signal line 102 through a wire hole. The third sub-part 1123 extends along the second direction Y, which makes it easy to set the position of the wire hole for electrically connecting the third sub-part 1123 and the signal line 102 at the end of the signal line 102, thus reducing the difficulty of the process.

[0101] Figure 11 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0102] like Figure 11 As shown in one embodiment of this application, some of the shift register units 101 are electrically connected to corresponding signal lines 102 via a second connection line 120. The second connection line 120 includes a third connection portion 121 and a fourth connection portion 122, which are electrically connected. The third connection portion 121 is located in a first region NA1 and is electrically connected to the shift register unit 101, while the fourth connection portion 122 is located in a second region NA2 and is electrically connected to the signal line 102.

[0103] In one implementation of this embodiment, the third connecting part 121 is located within the fourth sub-region NA14, and the fourth connecting part 122 is located within the second region NA2 and is close to the first boundary line.

[0104] In this embodiment, some connecting lines within the non-display area NA are routed through the second area NA2 near the first boundary line. This design ensures improved utilization of the border area while maintaining the border width within the target width.

[0105] Figure 12 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0106] like Figure 12 As shown, in one embodiment of this application, some of the shift register units 101 are electrically connected to corresponding signal lines 102 via a third connection line 130. The third connection line 130 includes a first sub-connection line 131 and a second sub-connection line 132. The first sub-connection line 131 and the second sub-connection line 132 are electrically connected. The resistivity of the first sub-connection line 131 is different from that of the second sub-connection line 132.

[0107] In this embodiment, the lengths of the connecting lines between different shift register units 101 and their corresponding signal lines 102 are different, and the resistivity of the first sub-connecting line 131 is different from that of the second sub-connecting line 132. This can effectively compensate for the resistance differences caused by the length differences of the different connecting lines, and ensure that the resistance differences between multiple shift register units 101 and their corresponding signal lines 102 are within the allowable error range, thereby improving the stability of the driving effect of multiple shift register units 101.

[0108] In one implementation of this embodiment, both the first sub-connection line 131 and the second sub-connection line 132 are located in the non-display area NA. For example, at least one of the first sub-connection line 131 and the second sub-connection line 132 is located within the fourth sub-region NA14.

[0109] In one implementation of this embodiment, the resistivity of the first sub-connecting line 131 is less than the resistivity of the second sub-connecting line 132. Among the plurality of third connecting lines 130, the longer the length of the third connecting line 130, the longer the length of the first sub-connecting line 131. That is, the plurality of third connecting lines 130 includes third connecting lines 130a and third connecting lines 130b, the length of third connecting line 130a is greater than the length of third connecting line 130b, and the length of the first sub-connecting line 131 in third connecting line 130a is greater than the length of the first sub-connecting line 131 in third connecting line 130b.

[0110] Figure 13 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0111] like Figure 13 As shown in one embodiment of this application, some of the shift register units 101 are electrically connected to corresponding signal lines 102 via a common connection line 140. One end of the common connection line 140 is electrically connected to at least two shift register units 101, and the other end of the common connection line 140 is electrically connected to at least two corresponding signal lines 102.

[0112] In this embodiment, at least two of the multiple shift register units 101 share a common connection line 140. This design can effectively reduce the total number of connection lines between the multiple shift register units 101 and the signal line 102, thereby further reducing the width of the second region NA2 at the corner position to optimize the width of the region at the corner position.

[0113] In one implementation of this embodiment, signal line 102 includes a data write control scan signal line 102. A common connection line 140 is electrically insulated from any data write control scan signal line 102.

[0114] In this implementation, the common connection line 140 is electrically isolated from the arbitrary data write control scan signal line 102, meaning that the drive signals required for the gates of the write transistors of each pixel circuit 104 are independent. The shift register units 101 connected to the gates of the write transistors of different pixel circuits 104 are different. This design ensures that the resolution of the display panel 100 is not reduced.

[0115] In embodiments of this application, at least two of the first connecting line 110, the third connecting line 130, and the common connecting line 140 can be the same connecting line. Similarly, at least two of the second connecting line 120, the third connecting line 130, and the common connecting line 140 can be the same connecting line. For example, as... Figure 13 As shown, the common connecting line 140 and the third connecting line 130 are the same connecting line.

[0116] Figure 14 A schematic diagram of a display panel provided in an embodiment of this application; Figure 15 Provided for the embodiments of this application Figure 14 A magnified view of a portion of region B in the middle.

[0117] like Figures 14 to 15As shown, this application also provides a display panel 100, including a display area AA and a non-display area NA. The display area AA includes a plurality of signal lines 102 arranged along a first direction X, and the non-display area NA includes a plurality of shift register units 101, which are electrically connected to the corresponding signal lines 102. The display area AA includes a first display area AA1 and a second display area AA2, which are arranged along the first direction X. The second display area AA2 includes a chamfered area, and the boundary line between the chamfered area and the non-display area NA is a first boundary line. The non-display area NA includes a first area NA1 and a second area NA2, where the first area NA1 is adjacent to the first display area AA1 along a second direction Y, and the second area NA2 is adjacent to the display area AA along the second direction Y. The second direction Y intersects with the first direction X, and the first area NA1 and the second area NA2 are adjacent along the first direction X. The boundary line between the second area NA2 and the display area AA is a second boundary line, which covers the first boundary line. The second region NA2 is provided with a number of common connection lines 140. One end of the common connection line 140 is electrically connected to at least two shift register units 101, and the other end of the common connection line 140 is electrically connected to at least two corresponding signal lines 102.

[0118] This application combines multiple shared connecting lines 140 located in the second region NA2, which can reduce the total number of shared connecting lines 140 located in the second region NA2, thereby reducing the width of the second region NA2 at the corners and optimizing the width of the region at the corners.

[0119] In one embodiment of this application, the first boundary line coincides with the second boundary limit.

[0120] In one implementation of this embodiment, the first boundary line is an arc, and the boundary line of the first region NA1 is a rectangle. That is, the chamfer of the display area AA is rounded, and its chamfered area is a rounded area.

[0121] Figure 16 A schematic diagram of a display panel provided in an embodiment of this application; Figure 17 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region C. Figure 14 and Figure 16 The difference is: Figure 14 The shift register cells in the second region NA2 are arranged in a fan shape or arc shape.

[0122] Figure 16 The shift register cells in the second region NA2 are arranged in the same way as the shift register cells in the first region NA1: both are arranged in a straight line.

[0123] like Figures 16 to 17 As shown, in one embodiment of this application, a common connection line 140 is included within the first region NA1 and / or the display area AA. That is, the connection line electrically connected to the register unit within the first region NA1 can be the common connection line 140, and the connection line located within the display area AA (which is used to electrically connect the signal line 102 and the shift register unit 101) can also be the common connection line 140. One end of the common connection line 140 is electrically connected to at least two shift register units 101, and the other end of the common connection line 140 is electrically connected to at least two corresponding signal lines 102.

[0124] Figure 18 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region C.

[0125] like Figure 15 or Figure 18 As shown in one embodiment of this application, among a plurality of common connection lines 140, at least a portion of the common connection lines 140 include a first sub-connection line 131 and a second sub-connection line 132, and the first sub-connection line 131 and the second sub-connection line 132 are electrically connected. The resistivity of the first sub-connection line 131 is different from the resistivity of the second sub-connection line 132.

[0126] In one implementation of this embodiment, the resistivity of the first sub-connecting line 131 is less than the resistivity of the second sub-connecting line 132. Among the plurality of common connecting lines 140, the longer the length of the common connecting line 140, the longer the length of the first sub-connecting line 131. That is, the plurality of common connecting lines 140 includes a common connecting line 140a and a common connecting line 140b, the length of the common connecting line 140a is greater than the length of the common connecting line 140b, and the length of the first sub-connecting line 131 in the common connecting line 140a is greater than the length of the first sub-connecting line 131 in the common connecting line 140b.

[0127] like Figure 14 or Figure 16 As shown, in one embodiment of this application, the first region NA1 includes a plurality of shift register units 101, and the second region NA2 includes a plurality of shift register units 101.

[0128] In one embodiment of this application, signal line 102 includes a data write control scan signal line. A common connection line 140 is electrically insulated from any data write control scan signal line.

[0129] In one embodiment of this application, the projection of the shift register unit 101 along a third direction does not overlap with the second region NA2, and the third direction is perpendicular to the first direction X and the second direction Y. Furthermore, at least a portion of the shift register units 101 are disposed within the first region NA1.

[0130] In this embodiment, no shift register unit 101 is provided in the second region NA2, that is, no shift register unit 101 is provided in the area of ​​the non-display area NA of the display panel 100 near the corner of the display area AA. Since no shift register unit 101 is provided in the second region NA2, the width of the second region NA2 at the corner can be reduced, thereby reducing the width of the area at the corner.

[0131] In some embodiments of this application, signal line 102 can be a scan signal line, such as a light emission control scan signal line, a reset control scan signal line, and a data write control scan signal line; the first direction X is perpendicular to the second direction Y. The light emission control scan signal line is electrically connected to the gate of the light emission control transistor in the corresponding pixel circuit 104, and is used to control the activation of the pixel circuit to make the light-emitting element emit light. The reset control scan signal line is electrically connected to the gate of the reset transistor in the corresponding pixel circuit 104, and is used to control the reset of the pixel circuit 104. The data write control scan signal line is electrically connected to the gate of the data write transistor in the corresponding pixel circuit 104, and is used to control the writing of data voltage. The pixel circuit 104 refers to a driving circuit electrically connected to the light-emitting element, under the drive of the pixel circuit 104, the light-emitting element can emit light.

[0132] like Figures 4 to 5 As shown, in one embodiment of this application, a plurality of pixel circuits 104 are disposed within the display area AA. Each pixel circuit 104 includes a plurality of transistors, and signal lines 102 are electrically connected to the gates of at least a portion of the transistors. The projection of the pixel circuit 104 along a third direction is a first projection, and the length of the first projection along the first direction X is a first length L1. The projection of at least a portion of the shift register units 101 along a third direction is a second projection, and the length of the second projection along the first direction X is a second length L2. The first length L1 is greater than the second length L2.

[0133] In this embodiment, the first length L1 is greater than the second length L2, which ensures that there is a difference in the space length occupied by the shift register unit 101 and the pixel circuit in the first direction X. This difference provides space for the shift register unit 101 corresponding to the pixel circuit 104 located in the corner area to be inserted in the first region NA1.

[0134] like Figure 4As shown, in one embodiment of this application, the first region NA1 includes a first sub-region NA11 and a second sub-region NA12, with the second sub-region NA12 located between the first sub-region NA11 and the second region NA2. The projection of the shift register unit 101 located in the first sub-region NA11 along a third direction is the first sub-projection. The projection of the shift register unit 101 located in the second sub-region NA12 along a third direction is the second sub-projection. The length of the first sub-projection along the first direction X is the first sub-length L21, and the length of the second sub-projection along the first direction X is the second sub-length L22. The first sub-length L21 and the second sub-length L2 are not equal, and the first sub-length L21 is less than the first length L1, and the second sub-length L22 is less than the first length L1.

[0135] In this embodiment, the shift register unit 101 has a differentiated design in terms of size. This differentiated design can better improve space utilization.

[0136] In one possible implementation of this embodiment, the first sub-length L21 is greater than the second sub-length L22. That is, the size of the shift register unit that provides the driving signal for the pixel circuit 104 in the chamfered area is smaller than the shift register circuit that provides the driving signal for the pixel circuit 104 in the first display area AA1. Since the number of pixel circuits 104 in the chamfered area is small, the size of the shift register unit 101 that provides the driving signal for it (i.e., the shift register unit 101 located in the second sub-region NA12) can be made smaller, thereby making more reasonable use of space and improving space utilization.

[0137] like Figure 5 As shown, the length of the second projection along the first direction X is equal. This design facilitates manufacturing processes.

[0138] like Figure 5 As shown, in one embodiment of this application, the first region NA1 includes a third sub-region NA13 and a fourth sub-region NA14, with the fourth sub-region NA14 located between the third sub-region NA13 and the second region NA2. The projection of the shift register unit 101 located in the third sub-region NA13 along a third direction is a first sub-projection. The projection of the shift register unit 101 located in the fourth sub-region NA14 along a third direction is a second sub-projection. The distance between two adjacent first sub-projections along the first direction X is a first distance D1. The distance between two adjacent second sub-projections along the first direction X is a second distance D2. The second distance D2 is less than or equal to the first distance D1.

[0139] In this embodiment, the third sub-region NA13 is located in the middle of the first region NA1, and the fourth sub-region NA14 is located at the end of the first region NA1. For example, the third sub-region NA13 is located on the outer periphery of the first display area AA1, and the fourth sub-region NA14 is located on one side of the second display area AA2. The first display area AA1 is the straight section of display area AA. The second display area AA2 is located on the side near the inner corner of display area AA. The arrangement density of the first shift register unit 101 in the third sub-region NA13 is less than or equal to the arrangement density of the second shift register unit 101 in the fourth sub-region NA14. This design facilitates the placement of all shift register units 101 within the first region NA1 without affecting the display effect.

[0140] In one embodiment of this application, the first distance D1 is greater than zero, and the second distance D2 is greater than or equal to zero. The second distance D2 is less than the first distance D1.

[0141] In this embodiment, the arrangement density of the shift register units 101 is differentiated within the first region NA1: the arrangement density of the shift register units 101 located in the middle of the first region NA1 is less than the arrangement density at both ends of the first region NA1. This differentiation further facilitates the realization that all the shift register units 101 can be placed within the first region NA1 without affecting the display effect.

[0142] In one embodiment of this application, the first distance D1 is equal to the second distance D2, and both the first distance D1 and the second distance D2 are greater than zero.

[0143] In this embodiment, the shift register units 101 in the first region NA1 are uniformly distributed, which can simplify the manufacturing process and reduce the manufacturing cost.

[0144] In one embodiment of this application, the first length L1 is the sum of the second length L2 and the first distance D1.

[0145] In this embodiment, the first length L1 is the sum of the second length L2 and the first distance D1. This design enables a one-to-one correspondence between the shift register unit 101 located in the middle of the first region NA1 along the first direction X and the pixel in the first display area AA1. This design facilitates the wiring of the connection line between the shift register unit 101 located in the middle of the first region NA1 and the corresponding signal line 102.

[0146] Figure 6 A schematic diagram of a display panel provided in an embodiment of this application;

[0147] like Figure 6 As shown in one embodiment of this application, both the first distance D1 and the second distance D2 are zero.

[0148] In this embodiment, the shift register units 101 are closely arranged in the first region NA1 along the first direction X. This close arrangement saves space and ensures that these shift register units 101 are located only within the first region NA1.

[0149] In one embodiment of this application, each shift register unit 101 within the first region NA1 is electrically connected to its corresponding signal line 102. That is, all shift register units 101 within the first region NA1 are valid and can output valid signals to their corresponding signal lines 102. This design maximizes the utilization of the space in the first region NA1.

[0150] In one embodiment of this application, the display panel 100 further includes a dummy shift register unit 103, which is located on the side of the shift register unit 101 near the second region NA2. The dummy shift register unit 103 is electrically insulated from any signal line 102.

[0151] In this embodiment, the dummy shift register does not output any valid signals. The purpose of the dummy shift register 103 is to ensure the stability of the operation of the shift register 101, which is electrically connected to the signal line 102 at the edge of the first region NA1.

[0152] Figure 7 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0153] like Figure 6 or Figure 7 As shown, in one embodiment of this application, the display panel 100 further includes a dummy shift register unit 103. The dummy shift register unit 103 is located within the third sub-region NA13 and on the side of the shift register unit 101 closest to the fourth sub-region NA14. The dummy shift register unit 103 is electrically insulated from any signal line 102.

[0154] In this embodiment, the purpose of the dummy shift register unit 103 is to compensate for the difference in the total length of the pixel circuit in the first display area AA1 and the shift register unit 101 in the third sub-region NA13 in the first direction X, so as to facilitate the wiring of the shift register in the fourth sub-region NA14.

[0155] In one possible implementation of this embodiment, all shift register units 101 within the third sub-region NA13 are arranged uniformly in the first direction X, and a dummy shift register unit 103 is provided between the shift register units 101 in the third sub-region NA13 and the shift register units 101 in the fourth sub-region NA14. This dummy shift register unit 103 can ensure the performance of the shift register units 101 located near the edge of the fourth sub-region NA14, and improve the stability of the shift register units 101 during operation.

[0156] like Figure 7 As shown, in one embodiment of this application, the third sub-region NA13 includes a first sub-region NA131 and a second sub-region NA132. The second sub-region NA132 is located between the third sub-region NA13 and the fourth sub-region NA14. All shift register units 101 within the third sub-region NA13 are located within the first sub-region NA131. It can be understood that no shift register unit 101 is provided within the second sub-region NA132.

[0157] In this embodiment, no shift register unit 101 is provided in the second sub-region NA132. This design facilitates the realization that, within a predetermined length in the first direction X, the shift register unit 101 in the third sub-region NA13 corresponds to the area of ​​the pixel circuit 104 in the first display area AA1. This design enables isolation between the shift register unit 101 in the third sub-region NA13 and the shift register unit 101 in the fourth sub-region NA14. The arrangement spacing of the shift register units 101 in the first sub-region NA131 and the arrangement spacing of the shift register units 101 in the fourth sub-region NA14 may not be the same; this isolation can effectively reduce the adverse effects caused by this difference in arrangement spacing.

[0158] like Figure 7 As shown, in one implementation of this embodiment, a dummy shift register 103 is provided in both the first sub-region NA131 and the second sub-region NA12. Specifically, the dummy shift register 103 in the first sub-region NA131 is located on the side of the shift register 101 (the effective shift register 101) closer to the second sub-region NA132; the dummy shift register 103 in the fourth sub-region is also located on the side of the shift register 101 (the effective shift register 101) closer to the second sub-region NA132. This design ensures the electrical stability of the effective shift register 101 in both the first sub-region NA131 and the second sub-region NA12 when they are in operation.

[0159] Figure 19 Provided for the embodiments of this application Figure 16A magnified view of a portion of region D. Figure 20 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region D. Figure 21 Provided for the embodiments of this application Figure 16 A magnified view of a portion of region D.

[0160] like Figures 8 to 10 , Figures 19 to 21 As shown, in one embodiment of this application, some of the shift register units 101 are electrically connected to corresponding signal lines 102 via a first connection line 110. The first connection line 110 includes a first connection portion 111 and a second connection portion 112, which are electrically connected. The first connection portion 111 is located within the non-display area NA, and the second connection portion 112 is located within the display area AA. The second connection portion 112 includes a first sub-part 1121 and a second sub-part 1122, which are electrically connected. The first sub-part 1121 extends along a second direction Y, and the second sub-part 1122 extends along a first direction X.

[0161] like Figures 8 to 10 , Figures 19 to 21 As shown, in one implementation of this embodiment, the first sub-part 1121 and the second sub-part 1122 are electrically connected through a wire hole.

[0162] In one implementation of this embodiment, the first connecting portion 111 is located within the fourth sub-region NA14.

[0163] like Figures 8 to 10 , Figures 19 to 21 As shown, in this embodiment, the first connecting portion 111 is located within the non-display area NA, and the second connecting portion 112 is located within the display area AA. This allows the first connecting line 110 to bypass the second area NA2 and electrically connect to the corresponding signal line 102, thereby reducing the width of the second area NA2 at its corners. The first direction X intersects the second direction Y. The first sub-portion 1121 extends along the second direction Y, and the second sub-portion 1122 extends along the first direction X. This design facilitates wiring and manufacturing processes.

[0164] like Figure 8 and Figure 19 As shown, in one embodiment of this application, one end of the second sub-part 1122 is connected to the first sub-part 1121, and the other end of the second sub-part 1122 is connected to the corresponding signal line 102.

[0165] In this embodiment, one end of the first sub-part 1121 is a connection point to the first sub-part 1121, and the other end of the second sub-part 1122 is a connection point to the corresponding signal line 102. One end of the second sub-part 1122 is electrically connected to the first sub-part 1121, and the other end of the second sub-part 1122 is electrically connected to the corresponding signal line 102. The second sub-part 1122 is entirely used to transmit electrical signals, meaning its effective length is equal to its actual length. The effective length refers to the length used for transmitting electrical signals. The second sub-part 1122 is directly electrically connected to the signal line 102, meaning the endpoint of the second sub-part 1122 electrically connected to the signal line 102 can be located between the two endpoints of the signal line 102. Therefore, the solution provided in this embodiment ensures that the entire length of the second connecting part 1122 is an effective length, which helps save on the manufacturing materials of the second sub-part 1122 and reduces production costs.

[0166] like Figure 9 or Figure 20 As shown, in one embodiment of this application, the second sub-part 1122 includes a first node, which is the connection point connecting the second sub-part 1122 and the first sub-part 1121. The first node is located between the two endpoints of the second sub-part 1122.

[0167] In this embodiment, the first node can be a through hole. The second sub-part 1122 extends from the first node along the second direction Y to both ends, that is, the actual length of the second sub-part 1122 is greater than the effective length of the second sub-part 1122. This design can ensure the uniformity of metal density within the display area AA where multiple second sub-parts 1122 are located. Metal density refers to the percentage of area occupied by metal per unit area.

[0168] like Figure 10 or Figure 21 As shown, in one embodiment of this application, the second connecting portion 112 further includes a third sub-portion 1123, which extends along the second direction Y. One end of the third sub-portion 1123 is connected to the second sub-portion 1122, and the other end of the third sub-portion 1123 is electrically connected to the corresponding signal line 102.

[0169] like Figure 10 or Figure 21 As shown, in one implementation of this embodiment, the third sub-part 1123 and the second sub-part 1122 are electrically connected through a wire hole.

[0170] In this embodiment, the third sub-part 1123 is electrically connected to the signal line 102 through a wire hole. The third sub-part 1123 extends along the second direction Y, which makes it easy to set the position of the wire hole for electrically connecting the third sub-part 1123 and the signal line 102 at the end of the signal line 102, thus reducing the difficulty of the process.

[0171] like Figure 11As shown in one embodiment of this application, some of the shift register units 101 are electrically connected to corresponding signal lines 102 via a second connection line 120. The second connection line 120 includes a third connection portion 121 and a fourth connection portion 122, which are electrically connected. The third connection portion 121 is located in a first region NA1 and is electrically connected to the shift register unit 101, while the fourth connection portion 122 is located in a second region NA2 and is electrically connected to the signal line 102.

[0172] In one implementation of this embodiment, the third connecting part 121 is located within the fourth sub-region NA14, and the fourth connecting part 122 is located within the second region NA2 and is close to the first boundary line.

[0173] In this embodiment, some connecting lines within the non-display area NA are routed through the second area NA2 near the first boundary line. This design ensures improved utilization of the border area while maintaining the border width within the target width.

[0174] Figure 12 Provided for the embodiments of this application Figure 2 or Figure 3 A magnified view of a portion of region A in the middle.

[0175] like Figure 12 As shown, in one embodiment of this application, some of the shift register units 101 are electrically connected to corresponding signal lines 102 via a third connection line 130. The third connection line 130 includes a first sub-connection line 131 and a second sub-connection line 132. The first sub-connection line 131 and the second sub-connection line 132 are electrically connected. The resistivity of the first sub-connection line 131 is different from that of the second sub-connection line 132.

[0176] In this embodiment, the lengths of the connecting lines between different shift register units 101 and their corresponding signal lines 102 are different, and the resistivity of the first sub-connecting line 131 is different from that of the second sub-connecting line 132. This can effectively compensate for the resistance differences caused by the length differences of the different connecting lines, and ensure that the resistance differences between multiple shift register units 101 and their corresponding signal lines 102 are within the allowable error range, thereby improving the stability of the driving effect of multiple shift register units 101.

[0177] In one implementation of this embodiment, both the first sub-connection line 131 and the second sub-connection line 132 are located in the non-display area NA. For example, at least one of the first sub-connection line 131 and the second sub-connection line 132 is located within the fourth sub-region NA14.

[0178] In one implementation of this embodiment, the resistivity of the first sub-connecting line 131 is less than the resistivity of the second sub-connecting line 132. Among the plurality of third connecting lines 130, the longer the length of the third connecting line 130, the longer the length of the first sub-connecting line 131. That is, the plurality of third connecting lines 130 includes third connecting lines 130a and third connecting lines 130b, the length of third connecting line 130a is greater than the length of third connecting line 130b, and the length of the first sub-connecting line 131 in third connecting line 130a is greater than the length of the first sub-connecting line 131 in third connecting line 130b.

[0179] In embodiments of this application, at least two of the first connecting line 110, the third connecting line 130, and the common connecting line 140 may be the same connecting line. At least two of the second connecting line 120, the third connecting line 130, and the common connecting line 140 may be the same connecting line.

[0180] Figure 22 This is a schematic diagram of a display device provided in an embodiment of this application.

[0181] like Figure 22 As shown, this application also provides a display device 200, which includes a display panel 100 of a first aspect or a second aspect.

[0182] Compared with the prior art, the second region NA2 of the display panel 100 in the display device 200 does not have a shift register unit 101, that is, the shift register unit 101 is not provided in the area of ​​the non-display area NA of the display panel 100 near the corner of the display area AA. Since the shift register unit 101 is not provided in the second region NA2, the width of the second region NA2 at the corner can be reduced, thereby reducing the width of the area at the corner. Alternatively, in the display device 200 provided in this application embodiment, the display panel 100 in the second region NA2 merges multiple common connecting lines 140 located in the second region NA2, which can reduce the total number of common connecting lines 140 located in the second region NA2, thereby reducing the width of the second region NA2 at the corner, and optimizing the width of the area at the corner.

[0183] This application also provides an apparatus, which includes a display panel or a display device.

[0184] Compared with the prior art, the device provided in this application does not have a shift register unit 101 in the second region NA2 of the display panel 100, that is, no shift register unit 101 is provided in the area of ​​the non-display area NA of the display panel 100 near the corner of the display area AA. Since no shift register unit 101 is provided in the second region NA2, the width of the second region NA2 at the corner can be reduced, thereby reducing the width of the area at the corner. Alternatively, in the device provided in this application, the display panel 100 merges multiple common connecting lines 140 located in the second region NA2, which can reduce the total number of common connecting lines 140 located in the second region NA2, thereby reducing the width of the second region NA2 at the corner and optimizing the width of the area at the corner.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area. The display area includes a plurality of signal lines arranged along a first direction. The non-display area includes a plurality of shift register units. The shift register units are electrically connected to the corresponding signal lines. The display area includes a first display area and a second display area, which are arranged along a first direction; the second display area includes a chamfered area, and the boundary line between the chamfered area and the non-display area is a first boundary line; The non-display area includes a first area and a second area. The first area is adjacent to the first display area along a second direction, and the second area is adjacent to the second display area along the second direction. The second direction intersects the first direction, and the first area and the second area are adjacent along the first direction. The boundary line between the second area and the display area is a second boundary line, and the first boundary line covers the second boundary line. Wherein, the projection of the shift register unit along a third direction does not overlap with the second region, and the third direction is perpendicular to the first direction and the second direction; and at least a portion of the shift register units are disposed within the first region; The display area is provided with a plurality of pixel circuits, each pixel circuit including a plurality of transistors, and the signal line is electrically connected to the gate of at least a portion of the transistors; The projection of the pixel circuit along the third direction is a first projection, and the length of the first projection along the first direction is a first length; at least a portion of the shift register units are projected along the third direction as a second projection, and the length of the second projection along the first direction is a second length; the first length is greater than the second length.

2. The display panel according to claim 1, characterized in that, The first region includes a first sub-region and a second sub-region, wherein the second sub-region is located between the first sub-region and the second region; The projection of the shift register unit located in the first sub-region along the third direction is the first sub-projection; the projection of the shift register unit located in the second sub-region along the third direction is the second sub-projection; the length of the first sub-projection along the first direction is the first sub-length, the length of the second sub-projection along the first direction is the second sub-length, the first sub-length and the second length are not equal, and the first sub-length is less than the first length, and the second sub-length is less than the first length.

3. The display panel according to claim 1, characterized in that, The first region includes a third sub-region and a fourth sub-region, the fourth sub-region being located between the third sub-region and the second region; the projection of the shift register unit located within the third sub-region along the third direction is a first sub-projection; the projection of the shift register unit located within the fourth sub-region along the third direction is a second sub-projection; the distance between two adjacent first sub-projections along the first direction is a first distance; the distance between two adjacent second sub-projections along the first direction is a second distance; the second distance is less than or equal to the first distance.

4. The display panel according to claim 3, characterized in that, The first distance is greater than zero, and the second distance is greater than or equal to zero; the second distance is less than the first distance.

5. The display panel according to claim 3, characterized in that, The display area is provided with a plurality of pixel circuits, each pixel circuit including a plurality of transistors, and the signal line is electrically connected to the gate of at least a portion of the transistors; The projection of the pixel circuit along the third direction is a first projection, and the length of the first projection along the first direction is a first length; the first length is the sum of the second length and the first distance.

6. The display panel according to claim 3, characterized in that, Both the first distance and the second distance are zero.

7. The display panel according to claim 1, characterized in that, It also includes a dummy shift register unit, which is located on the side of the shift register unit closer to the second region; the dummy shift register unit is electrically insulated from any of the signal lines.

8. The display panel according to claim 1, characterized in that, Some of the shift register units are electrically connected to the corresponding signal lines via a first connection line; The first connecting line includes a first connecting portion and a second connecting portion, the first connecting portion and the second connecting portion are electrically connected, the first connecting portion is located in the non-display area, and the second connecting portion is located in the display area; The second connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion and the second sub-portion being electrically connected; the first sub-portion extends along the second direction, and the second sub-portion extends along the first direction.

9. The display panel according to claim 8, characterized in that, One end of the second sub-part is connected to the first sub-part, and the other end of the second sub-part is connected to the corresponding signal line.

10. The display panel according to claim 8, characterized in that, The second sub-part includes a first node, which is a connection point connecting the second sub-part and the first sub-part; the first node is located between the two endpoints of the second sub-part.

11. The display panel according to any one of claims 8, characterized in that, The second connection portion further includes a third sub-portion, which extends along the second direction; one end of the third sub-portion is connected to the second sub-portion, and the other end of the third sub-portion is electrically connected to the corresponding signal line.

12. The display panel according to claim 1, characterized in that, Some of the shift register units are electrically connected to the corresponding signal lines via a second connecting line; the second connecting line includes a third connecting portion and a fourth connecting portion, the third connecting portion and the fourth connecting portion being electrically connected; the third connecting portion is located in the first region and is electrically connected to the shift register unit, and the fourth connecting portion is located in the second region and is electrically connected to the signal lines.

13. The display panel according to claim 1, characterized in that, Some of the shift register units are electrically connected to the corresponding signal lines via a third connection line; the third connection line includes a first sub-connection line and a second sub-connection line; the first sub-connection line and the second sub-connection line are electrically connected; the resistivity of the first sub-connection line is different from that of the second sub-connection line.

14. The display panel according to claim 1, characterized in that, Some of the shift register units are electrically connected to the corresponding signal lines via a common connection line; one end of the common connection line is electrically connected to at least two shift register units, and the other end of the common connection line is electrically connected to at least two corresponding signal lines.

15. A display panel, characterized in that, include: It includes a display area and a non-display area; the display area includes a plurality of signal lines arranged along a first direction, and the non-display area includes a plurality of shift register units, wherein the shift register units are electrically connected to the corresponding signal lines; The display area includes a first display area and a second display area, which are arranged along a first direction; the second display area includes a chamfered area, and the boundary line between the chamfered area and the non-display area is a first boundary line; The non-display area includes a first area and a second area. The first area is adjacent to the first display area along a second direction, and the second area is adjacent to the display area along the second direction. The second direction intersects the first direction, and the first area and the second area are adjacent to each other along the first direction. The boundary line between the second area and the display area is a second boundary line, and the second boundary line covers the first boundary line. In the second area, a plurality of common connection lines are provided. One end of each common connection line is electrically connected to at least two shift register units, and the other end of each common connection line is electrically connected to at least two corresponding signal lines. In the plurality of said common connection lines, at least a portion of the common connection lines include a first sub-connection line and a second sub-connection line, the first sub-connection line being electrically connected to the second sub-connection line; the resistivity of the first sub-connection line is different from the resistivity of the second sub-connection line.

16. The display panel according to claim 15, characterized in that, The first region includes multiple shift register units, and the second region includes multiple shift register units.

17. The display panel according to claim 15, characterized in that, The signal lines include data write control scan signal lines; the common connection line is electrically insulated from any data write control scan signal line.

18. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-17.

19. An electronic device, characterized in that, The electronic device includes the display panel according to any one of claims 1-17 or the display device according to claim 18.

Images