Shift register, gate drive circuit and display device

Abstract

A shift register, a gate drive circuit and a display device. The shift register comprises a first input sub-circuit (11), an output sub-circuit (3), a first pull-down control sub-circuit (41), a second pull-down control sub-circuit (42), a first pull-down sub-circuit (51), and a second pull-down sub-circuit (52). A connection node between the first input sub-circuit (11) and the output sub-circuit (3) is a pull-up node, a connection node between the first pull-down control sub-circuit (41) and the first pull-down sub-circuit (51) is a first pull-down node, and a connection node between the second pull-down control sub-circuit (42) and the second pull-down sub-circuit (52) is a second pull-down node. The shift register further comprises a first auxiliary sub-circuit (91) and a second auxiliary sub-circuit (92). The first auxiliary sub-circuit (91) is configured to pull down the potential of the first pull-down node to a non-working level signal when a second power supply voltage is a working level signal. The second auxiliary sub-circuit (92) is configured to pull down the potential of the second pull-down node to the non-working level signal when a first power supply voltage is the working level signal.

Description

Shift register, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit and a display device. BACKGROUND

[0002] With the continuous development of display technology, the development of display in recent years gradually presents a development trend of high integration and low cost. One of the very important technologies is the realization of mass production of GOA (Gate Driver on Array) technology. The TFT (Thin Film Transistor) gate switch circuit integrated on the array substrate of the display panel by using the GOA technology to form the scanning driving of the display panel, so that the gate driving integrated circuit part can be omitted. It not only can reduce the product cost from the aspects of material cost and manufacturing process, but also the display panel can be designed to be symmetrical and narrow frame. At the same time, the Gate direction bonding process can be omitted, which is beneficial to the improvement of production capacity and yield. The gate switch circuit integrated on the array substrate by using the GOA technology is also called GOA circuit or shift register circuit. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provide a shift register, a gate driving circuit and a display device.

[0004] The shift register provided by the present disclosure comprises a first input sub-circuit, an output sub-circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, a first pull-down sub-circuit and a second pull-down sub-circuit.

[0005] The first input sub-circuit is configured to pre-charge a pull-up node by a first scanning signal in response to a first input signal.

[0006] The output sub-circuit is configured to output a clock signal through a signal output end in response to the potential of the pull-up node.

[0007] The first pull-down control sub-circuit is configured to control the potential of a first pull-down node by a first power voltage in response to the first power voltage.

[0008] The second pull-down control sub-circuit is configured to control the potential of a second pull-down node by a second power voltage in response to the second power voltage.

[0009] The first pull-down sub-circuit is configured to pull down the first pull-down node in response to the potential of the pull-up node.

[0010] The second pull-down sub-circuit is configured to pull down the second pull-down node in response to the potential of the pull-up node; wherein

[0011] The shift register further comprises a first auxiliary sub-circuit and a second auxiliary sub-circuit.

[0012] The first auxiliary sub-circuit is configured to pull down the potential of the first pull-down node to the non-working level signal when the second power voltage is the working level signal.

[0013] The second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node to the non-working level signal when the first power voltage is the working level signal.

[0014] The shift register further comprises a global reset sub-circuit configured to globally reset the output of the pull-up node and the signal output terminal by the non-working level signal in response to a global reset signal.

[0015] The first auxiliary sub-circuit is specifically configured to pull down the non-working level signal by the first power voltage when the second power voltage is the working level signal in response to the global reset signal.

[0016] The second auxiliary sub-circuit is specifically configured to pull down the potential of the second pull-down node to the non-working level signal by the second power voltage when the first power voltage is the working level signal in response to the global reset signal.

[0017] The first auxiliary sub-circuit and the second auxiliary sub-circuit both comprise a seventeenth transistor.

[0018] The first pole of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power voltage terminal, the second pole is connected to the first pull-down node, and the control pole is connected to the global reset signal terminal.

[0019] The first pole of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second power voltage terminal, the second pole is connected to the second pull-down node, and the control pole is connected to the global reset signal terminal.

[0020] The global reset sub-circuit comprises a fourth transistor and a seventh transistor.

[0021] The first pole of the fourth transistor is connected to the pull-up node, the second pole is connected to the non-working level signal terminal, and the control pole is connected to the global reset signal terminal.

[0022] The first pole of the seventh transistor is connected to the signal output terminal, the second pole is connected to the non-working level signal terminal, and the control pole is connected to the global reset signal terminal.

[0023] The first auxiliary sub-circuit is specifically configured to, when the second power supply voltage is a working level signal, pull down the first pull-down node to a non-working voltage through the first power supply voltage in response to a frame start signal.

[0024] The second auxiliary sub-circuit is specifically configured to, when the first power supply voltage is a working level signal, pull down the second pull-down node to a non-working voltage through the second power supply voltage in response to the frame start signal.

[0025] The first auxiliary sub-circuit and the second auxiliary sub-circuit both include a seventeenth transistor.

[0026] The first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected with the first power supply voltage terminal, the second electrode is connected with the first pull-down node, and the control electrode is connected with the frame start signal terminal.

[0027] The first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected with the second power supply voltage terminal, the second electrode is connected with the second pull-down node, and the control electrode is connected with the frame start signal terminal.

[0028] The first auxiliary sub-circuit is specifically configured to, when the second power supply voltage is a working level signal, pull down the first pull-down node through a non-working level signal in response to the second power supply voltage.

[0029] The second auxiliary sub-circuit is specifically configured to, when the first power supply voltage is a working level signal, pull down the second pull-down node through a non-working level signal in response to the first power supply voltage.

[0030] The first auxiliary sub-circuit and the second auxiliary sub-circuit both include a seventeenth transistor.

[0031] The first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected with the first pull-down node, the second electrode is connected with a non-working level signal terminal, and the control electrode is connected with the second power supply voltage terminal.

[0032] The first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected with the second pull-down node, the second electrode is connected with a non-working level signal terminal, and the control electrode is connected with the first power supply voltage terminal.

[0033] The first auxiliary sub-circuit is specifically configured to, when the second power supply voltage is a working level signal, pull down the potential of the first pull-down node through a non-working level signal in response to the potential of the second pull-down node.

[0034] The second auxiliary sub-circuit is specifically configured to, when the first power supply voltage is a working level signal, pull down the potential of the second pull-down node through a non-working level signal in response to the potential of the first pull-down node.

[0035] The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor.

[0036] The first pole of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first pull-down node, the second pole is connected to a non-working level signal terminal, and the control pole is connected to the second pull-down node.

[0037] The first pole of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second pull-down node, the second pole is connected to the non-working level signal terminal, and the control pole is connected to the first pull-down node.

[0038] The shift register further includes a pull-up reset sub-circuit configured to reset the output of the pull-up node by the non-working level signal in response to a pull-up reset signal.

[0039] The pull-up reset sub-circuit includes a second transistor, the first pole of the second transistor is connected to the pull-up node, the second pole is connected to the non-working level signal terminal, and the control pole is connected to the pull-up reset signal terminal.

[0040] The first input signal is multiplexed as the first scan signal; the first input sub-circuit includes a first transistor.

[0041] The first pole and the control pole of the first transistor are connected to the first input signal terminal, and the second pole is connected to the pull-up node.

[0042] The shift register further includes a second input sub-circuit configured to pre-charge the pull-up node by a second scan signal in response to a second input signal.

[0043] The second input sub-circuit includes a second transistor.

[0044] The first pole of the second transistor is connected to the pull-up node, the second pole is connected to a second scan signal terminal, and the control pole is connected to a second input signal terminal.

[0045] The first input sub-circuit includes a first transistor.

[0046] The first pole of the first transistor is connected to a first scan signal terminal, the second pole is connected to the pull-up node, and the control pole is connected to a first input signal terminal.

[0047] The shift register further includes two first noise reduction sub-circuits and two second noise reduction sub-circuits.

[0048] One of the two first noise reduction sub-circuits is configured to reduce the output of the pull-up node by the non-working level signal in response to the potential of the first pull-down node, and the other is configured to reduce the output of the pull-up node by the non-working level signal in response to the potential of the second pull-down node.

[0049] One of the two second noise reduction sub-circuits is configured to reduce the output of the signal output terminal by the non-working level signal in response to the potential of the first pull-down node, and the other is configured to reduce the output of the signal output terminal by the non-working level signal in response to the potential of the second pull-down node.

[0050] The two first noise reduction sub-circuits each include a tenth transistor.

[0051] The first electrode of the tenth transistor in one of the first noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the first pull-down node; the first electrode of the tenth transistor in the other of the first noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the second pull-down node.

[0052] The two second noise reduction sub-circuits each include an eleventh transistor.

[0053] The first electrode of the eleventh transistor in one of the second noise reduction sub-circuits is connected to the signal output terminal, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the first pull-down node; the first electrode of the eleventh transistor in the other of the second noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the signal output terminal.

[0054] The shift register further includes a cascade sub-circuit configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

[0055] The cascade sub-circuit includes a thirteenth transistor.

[0056] The first electrode of the thirteenth transistor is connected to the clock signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

[0057] The shift register further includes two third noise reduction sub-circuits.

[0058] One of the two third noise reduction sub-circuits is configured to reduce the output of the cascade signal terminal by the non-working level signal under the control of the first pull-down node, and the other is configured to reduce the output of the cascade signal terminal by the non-working level signal under the control of the second pull-down node.

[0059] The first pull-down control sub-circuit and the second pull-down control sub-circuit each include a fifth transistor and a ninth transistor.

[0060] For the first pull-down control sub-circuit, a first electrode of the fifth transistor is connected to a first electrode of the ninth transistor, a control electrode of the ninth transistor and a first power supply voltage terminal, and a second electrode of the fifth transistor is connected to the first pull-down node.

[0061] For the second pull-down control sub-circuit, a first electrode of the fifth transistor is connected to a first electrode of the ninth transistor, a control electrode of the ninth transistor and a second power supply voltage terminal, and a second electrode of the fifth transistor is connected to the second pull-down node.

[0062] The first pull-down sub-circuit and the second pull-down sub-circuit each include a sixth transistor and an eighth transistor.

[0063] For the first pull-down sub-circuit, a first electrode of the sixth transistor is connected to the first pull-down node, a second electrode of the sixth transistor is connected to the non-working level signal terminal, and a control electrode of the sixth transistor is connected to the pull-up node; a first electrode of the eighth transistor is connected to a control electrode of the fifth transistor and a first electrode of the ninth transistor, a second electrode of the eighth transistor is connected to the non-working level signal terminal, and a control electrode of the eighth transistor is connected to the pull-up node.

[0064] For the second pull-down sub-circuit, a first electrode of the sixth transistor is connected to the second pull-down node, a second electrode of the sixth transistor is connected to the non-working level signal terminal, and a control electrode of the sixth transistor is connected to the pull-up node; a first electrode of the eighth transistor is connected to a control electrode of the fifth transistor and a first electrode of the ninth transistor, a second electrode of the eighth transistor is connected to the non-working level signal terminal, and a control electrode of the eighth transistor is connected to the pull-up node.

[0065] The first pull-down control sub-circuit and the second pull-down control sub-circuit each include a fifth transistor.

[0066] For the first pull-down control sub-circuit, a first electrode and a control electrode of the fifth transistor are connected to a first power supply voltage terminal, and a second electrode of the fifth transistor is connected to the first pull-down node.

[0067] For the first pull-down control sub-circuit, a first electrode and a control electrode of the fifth transistor are connected to a second power supply voltage terminal, and a second electrode of the fifth transistor is connected to the second pull-down node.

[0068] The first pull-down sub-circuit and the second pull-down sub-circuit each include a sixth transistor.

[0069] A first electrode of the sixth transistor is connected to the first pull-down node, a second electrode of the sixth transistor is connected to the non-working level signal terminal, and a control electrode of the sixth transistor is connected to the pull-up node.

[0070] The first electrode of the sixth transistor is connected to the second pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node.

[0071] The embodiment of the present disclosure provides a gate drive circuit, which comprises a plurality of cascaded shift registers, and the shift registers adopt any one of the shift registers described above.

[0072] The embodiment of the present disclosure provides a display device, which comprises the gate drive circuit described above. BRIEF DESCRIPTION OF DRAWINGS

[0073] Fig. 1 is a circuit diagram of an exemplary shift register.

[0074] Fig. 2 is a working timing diagram of the shift register shown in Fig. 1.

[0075] Fig. 3 is a circuit diagram of a first exemplary shift register according to an embodiment of the present disclosure.

[0076] Fig. 4 is a circuit diagram of a second exemplary shift register according to an embodiment of the present disclosure.

[0077] Fig. 5 is a circuit diagram of a third exemplary shift register according to an embodiment of the present disclosure.

[0078] Fig. 6 is a circuit diagram of a fourth exemplary shift register according to an embodiment of the present disclosure.

[0079] Fig. 7 is a circuit diagram of a fifth exemplary shift register according to an embodiment of the present disclosure.

[0080] Fig. 8 is a circuit diagram of a sixth exemplary shift register according to an embodiment of the present disclosure.

[0081] Fig. 9 is a circuit diagram of a seventh exemplary shift register according to an embodiment of the present disclosure.

[0082] Fig. 10 is a circuit diagram of an eighth exemplary shift register according to an embodiment of the present disclosure.

[0083] Fig. 11 is a circuit diagram of a ninth exemplary shift register according to an embodiment of the present disclosure.

[0084] Fig. 12 is a circuit diagram of a tenth exemplary shift register according to an embodiment of the present disclosure.

[0085] Fig. 13 is a circuit diagram of an eleventh exemplary shift register according to an embodiment of the present disclosure.

[0086] Fig. 14 is a circuit diagram of a twelfth exemplary shift register according to an embodiment of the present disclosure.

[0087] Fig. 15 is a circuit diagram of a thirteenth exemplary shift register according to an embodiment of the present disclosure.

[0088] Fig. 16 is a circuit diagram of a fourteenth exemplary shift register according to embodiments of the present disclosure.

[0089] Fig. 17 is a circuit diagram of a fifteenth exemplary shift register according to embodiments of the present disclosure.

[0090] Fig. 18 is a circuit diagram of a sixteenth exemplary shift register according to embodiments of the present disclosure.

[0091] Fig. 19 is a circuit diagram of a seventeenth exemplary shift register according to embodiments of the present disclosure.

[0092] Fig. 20 is a circuit diagram of an eighteenth exemplary shift register according to embodiments of the present disclosure.

[0093] Fig. 21 is a circuit diagram of a nineteenth exemplary shift register according to embodiments of the present disclosure.

[0094] Fig. 22 is a circuit diagram of a twentieth exemplary shift register according to embodiments of the present disclosure.

[0095] Fig. 23 is a circuit diagram of a twenty-first exemplary shift register according to embodiments of the present disclosure.

[0096] Fig. 24 is a circuit diagram of a twenty-second exemplary shift register according to embodiments of the present disclosure.

[0097] Fig. 25 is a circuit diagram of a twenty-third exemplary shift register according to embodiments of the present disclosure.

[0098] Fig. 26 is a circuit diagram of a twenty-fourth exemplary shift register according to embodiments of the present disclosure.

[0099] Fig. 27 is a circuit diagram of a twenty-fifth exemplary shift register according to embodiments of the present disclosure.

[0100] Fig. 28 is a circuit diagram of a twenty-sixth exemplary shift register according to embodiments of the present disclosure.

[0101] Fig. 29 is a circuit diagram of a twenty-seventh exemplary shift register according to embodiments of the present disclosure.

[0102] Fig. 30 is a circuit diagram of a twenty-eighth exemplary shift register according to embodiments of the present disclosure.

[0103] Fig. 31 is a circuit diagram of a twenty-ninth exemplary shift register according to embodiments of the present disclosure.

[0104] Fig. 32 is a circuit diagram of a thirtieth exemplary shift register according to embodiments of the present disclosure.

[0105] Fig. 33 is a circuit diagram of a thirty-first exemplary shift register according to embodiments of the present disclosure.

[0106] FIG. 34 is a circuit diagram of a thirty-second exemplary shift register according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0107] In order to better understand the technical solutions of the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0108] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity limitation, but mean that at least one exists. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms do not limit to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positions, and when the absolute positions of the described objects change, the relative positions may also change accordingly.

[0109] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present application, one of the poles is referred to as the first pole and the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, the transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, N-type transistors are used for illustration. When N-type transistors are used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and when a high-level signal is input to the gate, the source and drain are turned on, and the P-type is the opposite. It is conceivable that P-type transistors can be used to achieve the same result without any creative effort, and therefore are within the scope of protection of the embodiments of the present application.

[0110] In the embodiments of the present application, since the transistors used are N-type transistors, the working level signal in the embodiments of the present application refers to a high-level signal, and the non-working level signal is a low-level signal. Correspondingly, the working level signal end is a high-level signal end, and the non-working level signal end is a low-level signal end VGL.

[0111] Generally, the display panel includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are arranged to cross to define a plurality of pixel regions, and each pixel region is provided with a pixel unit. Taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example, the structure of the display panel is described. When driving the display panel to display, the gate lines can be written with a gate scanning signal line by line according to a to-be-displayed picture, and each data line is written with a data voltage signal, so that the pixel units in the display panel are lit line by line.

[0112] The gate scanning signal is provided by a gate drive circuit, and the data voltage signal is provided by a source drive circuit. In the related art, the gate drive circuit can be integrated in a gate drive chip, and the source drive circuit can be integrated in a source drive chip. Currently, in order to reduce the number of chips and realize a narrow frame or no frame, a Gate On Array (GOA) technology is provided, in which the gate drive circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is connected one-to-one with a gate line, and is configured to provide a gate scanning signal for the gate line connected thereto.

[0113] In order to more clearly illustrate how the shift register outputs the gate scanning signal, the following describes a specific example of a shift register unit.

[0114] FIG. 1 is a circuit diagram of an exemplary shift register. As shown in FIG. 1, the shift register includes an input sub-circuit 1, an output sub-circuit 3, a pull-up reset sub-circuit 2, a global reset sub-circuit 6, two pull-down control sub-circuits 41 / 42, two pull-down sub-circuits 51 / 52, two first noise reduction sub-circuits 71 / 72, and two second noise reduction sub-circuits 81 / 82. For ease of description, the two pull-down control sub-circuits 41 / 42 are referred to as a first pull-down control sub-circuit 41 and a second pull-down control sub-circuit 42, and the two pull-down sub-circuits 51 / 52 are referred to as a first pull-down sub-circuit 51 and a second pull-down sub-circuit 52. The first pull-down control sub-circuit 41 and the first pull-down sub-circuit 51 are connected, and the connection node therebetween is referred to as a first pull-down node PD1. The second pull-down control sub-circuit 42 and the second pull-down sub-circuit 52 are connected, and the connection node therebetween is referred to as a second pull-down node PD2.

[0115] With continued reference to FIG. 1, the input sub-circuit 1 is configured to respond to the input signal and pre-charge the pull-up node PU with the input signal. The output sub-circuit 3 is configured to output the clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. The pull-up reset sub-circuit 2 is configured to reset the pull-up node PU with a low-level signal under the control of the pull-up reset signal. The global reset sub-circuit 6 is configured to reset the pull-up node PU and the signal output terminal G(N) with a low-level signal in response to the global reset signal. The output sub-circuit 3 is configured to output the clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. The first pull-down control sub-circuit 41 is configured to respond to the first power voltage signal and control the potential of the first pull-down node PD1 with the first power voltage signal. The second pull-down control sub-circuit 42 is configured to respond to the second power voltage signal and control the potential of the second pull-down node PD2 with the second power voltage signal. The first pull-down sub-circuit 51 is configured to pull down the potential of the first pull-down node PD1 with a low-level signal in response to the potential of the pull-up node PU. The second pull-down sub-circuit 52 is configured to pull down the potential of the second pull-down node PD2 with a low-level signal in response to the potential of the pull-up node PU. One of the two first noise reduction sub-circuits 71 responds to the potential of the first pull-down node PD1 and reduces the output of the pull-up node PU with a low-level signal, and the other 72 responds to the potential of the second pull-down node PD2 and reduces the output of the pull-up node PU with a low-level signal. One of the two second noise reduction sub-circuits 81 responds to the potential of the first pull-down node PD1 and reduces the output of the signal output terminal G(N) with a low-level signal, and the other 82 responds to the potential of the second pull-down node PD2 and reduces the output of the signal output terminal G(N) with a low-level signal.

[0116] Specifically, with continued reference to 1, the input sub-circuit 1 includes a first transistor M1, the pull-up reset sub-circuit 2 includes a second transistor M2, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1, the global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 each include a fifth transistor and a ninth transistor, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor and an eighth transistor, each of the first noise reduction sub-circuits includes a tenth transistor, and each of the second noise reduction sub-circuits includes an eleventh transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are denoted as M5A and M9A, respectively, the fifth transistor and the ninth transistor in the second pull-down sub-circuit 52 are denoted as M5B and M9B, respectively, the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are denoted as M6A and M8A, respectively, the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are denoted as M6B and M8B, respectively, the tenth transistor in the two first noise reduction sub-circuits are denoted as M10A and M10B, respectively, and the eleventh transistor in the two second noise reduction sub-circuits are denoted as M11A and M11B, respectively.

[0117] The source and gate of M1 are connected with a signal input end, and the drain of M1 is connected with a pull-up node PU. The source of M2 is connected with the pull-up node PU, the drain of M2 is connected with a low-level signal end VGL, and the gate of M2 is connected with a pull-up reset signal end. The source of M3 is connected with a clock signal end CLK, the drain of M3 is connected with a signal output end G(N), and the gate of M3 is connected with the pull-up node PU. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G(N). The source of M4 is connected with the pull-up node PU, the drain of M4 is connected with the low-level signal end VGL, and the gate of M4 is connected with a global reset signal end. The source of M7 is connected with the signal output end G(N), the drain of M7 is connected with the low-level signal end VGL, and the gate of M7 is connected with the global reset signal end. The source of M5A is connected with a first power voltage end VDDO, the drain of M5A is connected with a first pull-down node PD1, the gate of M5A is connected with the drain of M9A, the source and gate of M9A are connected with a second power voltage end VDDE. The source of M5B is connected with the second power voltage end VDDE, the drain of M5B is connected with a second pull-down node PD2, the gate of M5B is connected with the drain of M9B, and the source and gate of M9B are connected with the second power voltage end VDDE. The source of M6A is connected with the first pull-down node PD1, the drain of M6A is connected with the low-level signal end VGL, and the gate of M6A is connected with the pull-up node PU. The source of M8A is connected with the drain of M9A and the gate of M5A, the drain of M8A is connected with the low-level signal end VGL, and the gate of M8A is connected with the pull-up node PU. The source of M6B is connected with the second pull-down node PD2, the drain of M6B is connected with the low-level signal end VGL, and the gate of M6B is connected with the pull-up node PU. The source of M8B is connected with the drain of M9B and the gate of M5B, the drain of M8B is connected with the low-level signal end VGL, and the gate of M8B is connected with the pull-up node PU. The source of M10A is connected with the pull-up node PU, the drain of M10A is connected with the low-level signal end VGL, and the gate of M10A is connected with the first pull-down node PD1. The source of M10B is connected with the pull-up node PU, the drain of M10B is connected with the low-level signal end VGL, and the gate of M10B is connected with the second pull-down node PD2. The source of M11A is connected with the signal output end G(N), the drain of M11A is connected with the low-level signal end VGL, and the gate of M11A is connected with the first pull-down node PD1. The source of M11B is connected with the signal output end G(N), the drain of M11B is connected with the low-level signal end VGL, and the gate of M11B is connected with the second pull-down node PD2.

[0118] It should be noted that in the embodiments of the present disclosure, only the input sub-circuit 1 responds to the input signal and pre-charges the pull-up node PU through the input signal. In actual applications, the input sub-circuit 1 can also respond to the input signal and pre-charge the pull-up node PU through the independent first signal. Correspondingly, the source of M1 in the input sub-circuit 1 can also not be connected with the gate of M1, for example, the source of M1 is connected with the first signal end, the drain of M1 is connected with the pull-up node PU, and the gate of M1 is connected with the signal input end. At this time, the signal input end is written with a high-level signal, M1 is opened, and the high-level signal written in the first signal end pre-charges the pull-up node PU. In the embodiments of the present disclosure, only the case that the source of M1 is connected with the gate of M1 is taken as an example for description, but it should be understood that this does not constitute a limitation on the protection scope of the embodiments of the present disclosure.

[0119] When the shift register in the embodiments of the present disclosure is applied to the gate driving circuit, the signal input end of the Nth shift register is connected with the signal output end G(N-1) of the (N-1)th shift register, except for the first shift register; and the pull-up reset signal end of the Nth shift register is connected with the signal output end G(N+1) of the (N+1)th shift register, except for the last shift register. N≥2, and N is an integer.

[0120] Fig. 2 is a working timing diagram of the shift register shown in Fig. 1; as shown in Fig. 2, when the gate drive circuit is working, when G(N-1) is a high-level signal, G(N+1) and the signal input at the global reset signal end are low-level signals, M1 is opened, M2 is closed, the pull-up node PU starts to charge, when the pull-up node PU is a high-level signal, M6A / M6B / M8A / M8B are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low-level signals, it is ensured that the pull-up node PU remains a high-level signal, and normal output is ensured. However, during the Blanking time (blanking stage) between T1-T3, at the moment T2 when the first power voltage end VDDO and the second power voltage end VDDE switch between high-level signals and low-level signals, the first power voltage at the first power voltage end VDDO is switched from a low-level signal to a high-level signal, the second power voltage at the second power voltage end VDDE is switched from a high-level signal to a low-level signal, M5A / M9A is opened, the first pull-down node PD1 rises to a high potential, M5A / M9A is closed, and the second pull-down node PD2 is floating; or when the first power voltage at the first power voltage end VDDO is switched from a high-level signal to a low-level signal, and the second power voltage at the second power voltage end VDDE is switched from a low-level signal to a high-level signal, M5B / M9B is opened, the second pull-down node PD2 rises to a high potential, M5A / M9A is closed, and the first pull-down node PD1 is floating. During the period T2-T4, one of the first pull-down node PD1 and the second pull-down node PD2 is a high-level signal, and the other is in a floating state, and the signal voltage of the pull-down node in the floating state cannot be quickly pulled down, and the voltage is still relatively high. When the first pull-down node PD1 and the second pull-down node PD2 are both at a high potential and work simultaneously, M10 continuously discharges the pull-up node PU, the pull-up node PU is continuously pulled low, the gate drive circuit of the current row has no output, and a black line or a flashing screen is caused.

[0121] To solve the above problems, the embodiment of the present disclosure adds a first auxiliary sub-circuit and a second auxiliary sub-circuit on the basis of the above shift register. The first auxiliary sub-circuit is configured to pull down the potential of the first pull-down node to a low-level signal when the second power voltage is a high-level signal; and the second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node to a low-level signal when the first power voltage is a high-level signal.

[0122] Since the second power voltage is a high-level signal, the second pull-down node is a high-level signal, at this time, the first auxiliary sub-circuit pulls down the first pull-down sub-circuit to a low-level signal, so that it can be ensured that the first pull-down node and the second pull-down node will not be at a high-level signal at the same time before the pull-up node is charged, which helps to improve the charging capacity of the pull-up node.

[0123] Next, the technical solutions of the embodiments of the present disclosure are described in detail in combination with specific examples.

[0124] The first example: Fig. 3 is a circuit diagram of a shift register of the first example of the embodiments of the present disclosure; as shown in Fig. 3, the shift register includes a first input sub-circuit 11, a pull-up reset sub-circuit 2, an output sub-circuit 3, a global reset sub-circuit 6, a first pull-down control sub-circuit 41, a second pull-down control sub-circuit 42, a first pull-down sub-circuit 51, a second pull-down sub-circuit 52, a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92. Among them, the first input sub-circuit 11 is configured to respond to the first input signal and pre-charge the pull-up node PU through the first input signal. The output sub-circuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal G(N). The pull-up reset sub-circuit 2 is configured to respond to the pull-up reset signal and reset the output of the pull-up node through the low-level signal. The global reset sub-circuit 6 is configured to respond to the global reset signal and globally reset the output of the pull-up node PU and the signal output terminal G(N) through the low-level signal. The first pull-down control sub-circuit 41 is configured to respond to the first power voltage and control the potential of the first pull-down node PD1 through the first power voltage. The second pull-down control sub-circuit 42 is configured to respond to the second power voltage and control the potential of the second pull-down node PD2 through the second power voltage. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node and pull down the potential of the first pull-down node PD1 through the low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node and pull down the potential of the second pull-down node PD2 through the low-level signal. The first auxiliary sub-circuit 91 is configured to respond to the global reset signal and pull down the potential of the first pull-down node PD1 through the first power voltage when the second power voltage is a high-level signal. The second auxiliary sub-circuit 92 is configured to respond to the global reset signal and pull down the potential of the second pull-down node PD2 through the second power voltage when the first power voltage is a high-level signal.

[0125] In this example, by adding the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, the second power voltage is converted from a low level signal to a high level signal, and the first power voltage is converted from a high level signal to a low level signal, before the pull-up node is charged, the first auxiliary sub-circuit 91 is controlled to work by the global reset signal, and the first pull-down node PD1 is pulled down by the low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the second pull-down node PD2 competes with that of the pull-up node, which helps to improve the charging capability of the pull-up node. Similarly, when the first pull-down control sub-circuit 41 is working, that is, the first power voltage is converted from a low level signal to a high level signal, and the second power voltage is converted from a high level signal to a low level signal, before the pull-up node is charged, the second auxiliary sub-circuit 92 is controlled to work by the global reset signal, and the second pull-down node PD2 is pulled down by the low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the first pull-down node PD1 competes with that of the pull-up node, which helps to improve the charging capability of the pull-up node. In addition, in this example, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 are controlled by the global reset signal, that is, for the entire shift register, no control signal is added because of the addition of the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, so the control of the shift register is relatively simple.

[0126] Continuing to refer to FIG. 3, when the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, the first input signal end of the Nth shift register is connected to the signal output end G(N-1) of the (N-1)th shift register, and the pull-up reset signal end of the Nth shift register is connected to the signal output end G(N+1) of the (N+1)th shift register, N≥2, and N is an integer.

[0127] In some examples, continuing to refer to FIG. 3, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 each include a seventeenth transistor, for the convenience of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is denoted as M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is denoted as M17B. Wherein, the source of M17A is connected to the first power voltage end VDDO, the drain of M17A is connected to the first pull-down node PD1, and the gate of M17A is connected to the global reset signal end STV0. The source of M17B is connected to the second power voltage end VDDE, the drain of M17B is connected to the second pull-down node PD2, and the gate of M17B is connected to the global reset signal end STV0.

[0128] Specifically, the global reset signal terminal STV0 is used to introduce a global reset signal, the first power voltage terminal VDDO is used to introduce a first power voltage, and the second power voltage terminal VDDE is used to introduce a second power voltage. When the second power voltage of the second power voltage terminal VDDE is converted from a low level to a high level, the first power voltage of the first power voltage terminal VDDO is converted from a high level to a low level, and the global reset signal written by the global reset signal terminal STV0 is a high level signal, the M17A is turned on, and at this time, the first power voltage is a low level and the potential of the first pull-down node PD1 is pulled low. Similarly, when the first power voltage of the first power voltage terminal VDDO is converted from a low level to a high level, the second power voltage of the second power voltage terminal VDDE is converted from a high level to a low level, and the global reset signal written by the global reset signal terminal STV0 is a high level signal, the M17B is turned on, and at this time, the second power voltage is a low level and the potential of the second pull-down node PD2 is pulled low. This example can effectively avoid the competitive relationship of the pull-up node and the first pull-down node PD1 / second pull-down node PD2.

[0129] In some examples, continuing to refer to FIG. 3, the global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of the M4 is connected to the pull-up node PU, the drain of the M4 is connected to the low level signal terminal VGL, and the gate of the M4 is connected to the global reset signal terminal STV0. The source of the M7 is connected to the signal output terminal G(N), the drain of the M7 is connected to the low level signal terminal VGL, and the gate of the M7 is connected to the global reset signal terminal STV0.

[0130] Specifically, in the global reset phase, the global reset signal written by the global reset signal terminal STV0 is a high level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on. At this time, the low level signal written by the low level signal terminal VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output terminal G(N) through the seventh transistor M7.

[0131] In some examples, continuing to refer to FIG. 3, the shift register further includes two first noise reduction sub-circuits 71 / 72 and two second noise reduction sub-circuits 81 / 82. One (71) of the two first noise reduction sub-circuits 71 / 72 reduces the output of the pull-up node PU by a low level signal in response to the potential of the first pull-down node PD1, and the other (72) reduces the output of the pull-up node PU by a low level signal in response to the potential of the second pull-down node PD2. One (81) of the two second noise reduction sub-circuits 81 / 82 reduces the output of the signal output terminal G(N) by a low level signal in response to the potential of the first pull-down node PD1, and the other (82) reduces the output of the signal output terminal G(N) by a low level signal in response to the potential of the second pull-down node PD2.

[0132] The two first noise reduction sub-circuits 71 / 72 each include a tenth transistor, and the two second noise reduction sub-circuits 81 / 82 each include an eleventh transistor. The tenth transistors in the two first noise reduction sub-circuits 71 / 72 are denoted as M10A and M10B, respectively. The eleventh transistors in the two second noise reduction sub-circuits 81 / 82 are denoted as M11A and M11B, respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0133] Specifically, in the output noise reduction phase, when the potential of the first pull-down node PD1 is high, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written through the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is high, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written through the low-level signal terminal VGL.

[0134] In some examples, the first input sub-circuit 11 includes a first transistor M1, and the second input sub-circuit 12 includes a second transistor M2. The source and gate of M1 are connected to the first input signal terminal G(N-1), the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal G(N+1).

[0135] Specifically, in the input phase, the first input signal written into the first input signal terminal G(N-1) is a high-level signal, and M1 is turned on. At this time, the pull-up node PU is pre-charged by the high-level signal. In the pull-up reset phase, the pull-up reset signal written into the pull-up reset signal terminal G(N+1) is a high-level signal, and M2 is turned on. At this time, the pull-up node PU is discharged by the low-level signal, thereby achieving the reset of the pull-up node PU.

[0136] In some examples, the output sub-circuit 3 comprises a third transistor M3 and a storage capacitor C1; wherein a source of the M3 is connected to the clock signal end CLK, a drain of the M3 is connected to the signal output end G(N), and a gate of the M3 is connected to the pull-up node PU; a first end of the C1 is connected to the pull-up node PU, and a second end of the C1 is connected to the signal output end G(N).

[0137] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of the C1, the M3 is fully opened, and the clock signal written by the clock signal end CLK is a high-level signal in this stage, and at this time, the signal output end G(N) outputs a high-level signal.

[0138] In some examples, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 each comprise a fifth transistor and a ninth transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are denoted as M5A and M9A respectively, and the fifth transistor and the ninth transistor in the second pull-down control sub-circuit 42 are denoted as M5B and M9B respectively. A source of the M5A is connected to the first power voltage end VDDO, a drain of the M5A is connected to the first pull-down node PD1, a gate of the M5A is connected to a drain of the M9A, a source and a gate of the M9A are connected to the second power voltage end VDDE. A source of the M5B is connected to the second power voltage end VDDE, a drain of the M5B is connected to the second pull-down node PD2, a gate of the M5B is connected to a drain of the M9B, and a source and a gate of the M9B are connected to the second power voltage end VDDE.

[0139] Specifically, when the first power voltage is written into the first power voltage end VDDO, the M5A and the M9A are both opened, the potential of the first pull-down node PD1 is pulled high by the first power voltage, and the first pull-down node PD1 is at a high potential. When the second power voltage is written into the second power voltage end VDDE, the M5B and the M9B are both opened, the potential of the second pull-down node PD2 is pulled high by the second power voltage, and the second pull-down node PD2 is at a high potential. It should be noted that the first power voltage and the second power voltage can be the same power voltage. In the embodiments of the present disclosure, only the case where the first power voltage and the second power voltage are the same power voltage is described.

[0140] In some examples, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are denoted as M6A and M8A respectively, and the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are denoted as M6B and M8B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0141] Specifically, when the potential of the pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high to output normally.

[0142] The second example: FIG. 4 is a circuit diagram of a shift register of the second example of the embodiment of the present disclosure; as shown in FIG. 4, the structure of the shift register of this example is substantially the same as that of the first example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the first example.

[0143] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, and for ease of description, the fifth transistor in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 is denoted as M5A and M5B respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0144] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, the first pull-down node PD1 has the potential of the first power supply voltage, i.e. high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 has the potential of the second power supply voltage, i.e. high potential.

[0145] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0146] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0147] The other structures of the shift register in this example can be the same as those in the first example, and thus will not be repeated here.

[0148] The third example: Fig. 5 is a circuit diagram of a shift register of a third example of an embodiment of the present disclosure; as shown in Fig. 5, the structure of the shift register in this example is substantially the same as that in the first example, and the only difference is that the shift register in this example adds a cascade sub-circuit 111 to the shift register in the first example, and the cascade output sub-circuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0149] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascade signal terminal output_C(N), and the gate of M13 is connected to the pull-up node PU.

[0150] Specifically, in the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal in this phase, and at this time the cascade signal terminal output_C(N) outputs a high-level signal.

[0151] When the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, in addition to the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th stage shift register; in addition to the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th stage shift register. N≥2, and N is an integer.

[0152] In some examples, continuing to refer to FIG. 5, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the first pull-down node PD1, and the other of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the second pull-down node PD2.

[0153] Continuing to refer to FIG. 5, both of the third noise reduction sub-circuits can include twelfth transistors, denoted as M12A and M12B respectively. The source of M12A is connected to the cascade signal end, the drain of M12A is connected to the low-level signal end VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal end, the drain of M12B is connected to the low-level signal end VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0154] Specifically, in the output noise reduction phase, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12B.

[0155] Continuing to refer to FIG. 5, the shift register in this example can further include a first discharge sub-circuit 101 and a second discharge sub-circuit 102. The first discharge sub-circuit 101 is configured to discharge the first pull-down node PD1 by a low-level signal in response to a first input signal. The second discharge sub-circuit 102 is configured to discharge the second pull-down node PD2 by a low-level signal in response to the first input signal.

[0156] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 works to pre-charge the pull-up node PU, at which time the first discharge sub-circuit 101 discharges the first pull-down node PD1 and the second discharge sub-circuit 102 discharges the second pull-down node PD2, thereby avoiding competition between the potentials of the first pull-down node PD1, the second pull-down node PD2, and the pull-up node PU.

[0157] The first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 can each include a sixteenth transistor. For ease of description, the sixteenth transistor in the first pull-down sub-circuit 51 is denoted as M16A, and the sixteenth transistor in the second pull-down sub-circuit 52 is denoted as M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0158] In the input stage, the first input signal written into the first input signal terminal is a high-level signal, and M16A and M16B are both open. The low-level signal written in through the low-level signal terminal VGL pulls down the potential of the first pull-down node PD1 and the second pull-down node PD2.

[0159] The other structures of the shift register in this example can be the same as those in the first example, and thus are not repeated here.

[0160] The fourth example: FIG. 6 is a circuit diagram of a shift register of the fourth example of the embodiment of the present disclosure. As shown in FIG. 6, the structure of the shift register of this example is substantially the same as that of the third example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51, and the second pull-down sub-circuit 52 are different from those of the third example.

[0161] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistor in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 is denoted as M5A and M5B, respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0162] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is open, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is open, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0163] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0164] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0165] The other structures of the shift register in this example can be the same as those in the first example, and thus will not be repeated here.

[0166] Fifth example: FIG. 7 is a circuit diagram of a shift register of a fifth example of an embodiment of the present disclosure; as shown in FIG. 7, the structure of the shift register of this example is substantially the same as that of the first example, the only difference being that the shift register can realize bidirectional scanning. The first input sub-circuit 11 and the pull-up reset sub-circuit 2 in this example are different from those in the first example. In this example, since the shift register can realize bidirectional scanning, in forward scanning, the first input sub-circuit 11 is used for pre-charging the pull-up node PU, and the pull-up reset sub-circuit 2 is used for resetting the pull-up node PU; in reverse scanning, the first input sub-circuit 11 is used for resetting the pull-up node PU, and the pull-up reset sub-circuit 2 is used for pre-charging the pull-up node PU. Therefore, for ease of understanding, the first input sub-circuit 11 in the above example is still referred to as the first input sub-circuit 11, and the pull-up reset sub-circuit 2 is referred to as the second input sub-circuit 12. Since the first input sub-circuit 11 and the second input sub-circuit 12 are the main elements for supporting the shift register to realize bidirectional scanning, the connection relationship between the first input sub-circuit 11 and the second input sub-circuit 12 is different from that between the first input sub-circuit 11 and the pull-up reset sub-circuit 2.

[0167] Continuing to refer to FIG. 7, specifically, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU through a first scan signal in response to a first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU through a second scan signal in response to a second input signal.

[0168] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal end VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input end. The source of M2 is connected to the second scan signal end VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input end.

[0169] Specifically, when forward scanning, in the input stage, the first input signal written into the first input signal end is a high-level signal, M1 is turned on, the first scan signal written into the first scan signal end VDS is a high-level signal, and the pull-up node PU is pre-charged through the first scan signal at this time. In the pull-up reset stage, the second input signal written into the second input signal end is a high-level signal, M2 is turned on, the second scan signal written into the second scan signal end VSD is a low-level signal, and the pull-up node PU is discharged through the second scan signal at this time, so as to realize the reset of the pull-up node PU.

[0170] When reverse scanning, in the input stage, the second input signal written into the second input signal end is a high-level signal, M2 is turned on, the second scan signal written into the second scan signal end VSD is a high-level signal, and the pull-up node PU is pre-charged through the second scan signal at this time. In the pull-up reset stage, the first input signal written into the first input signal end is a high-level signal, M1 is turned on, the first scan signal written into the first scan signal end VDS is a low-level signal, and the pull-up node PU is discharged through the first scan signal at this time, so as to realize the reset of the pull-up node PU.

[0171] The other structures of the shift register in this example can be the same as those in the first example, and thus will not be repeated here.

[0172] The sixth example: Fig. 8 is a circuit diagram of a shift register of the sixth example of the embodiment of the present disclosure; as shown in Fig. 8, the structure of the shift register of this example is substantially the same as that of the fifth example, and the only difference is that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the fifth example.

[0173] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, and for the convenience of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented as M5A and M5B, respectively. The gate and the source of M5A are connected to the first power supply voltage end VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage end VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0174] When the first power voltage terminal VDDO is written with the first power voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power voltage, i.e., high potential. When the second power voltage terminal VDDE is written with the second power voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power voltage, i.e., high potential.

[0175] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, which are denoted as M6A and M6B, respectively, for ease of description. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0176] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0177] The other structures of the shift register in this example can be the same as those in the fifth example, and thus are not repeated here.

[0178] Seventh Example: FIG. 9 is a circuit diagram of a shift register of a seventh example of an embodiment of the present disclosure. As shown in FIG. 9, the structure of the shift register of this example is substantially the same as that of the fifth example, and the only difference is that the shift register adds a cascading sub-circuit 111 to the shift register of the first example, and the cascading output sub-circuit 3 is configured to output the clock signal through the cascading signal terminal in response to the potential of the pull-up node PU.

[0179] In some examples, the cascading sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascading signal terminal output_C(N), and the gate of M13 is connected to the pull-up node PU.

[0180] Specifically, in the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, the clock signal written by the clock signal terminal CLK is a high-level signal in this phase, and the cascading signal terminal output_C(N) outputs a high-level signal at this time.

[0181] When the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, the first input signal terminal of the Nth shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th shift register, and the second input signal terminal of the Nth shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th shift register, N≥2, and N is an integer.

[0182] In some examples, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the first pull-down node PD1, and the other of which is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the second pull-down node PD2.

[0183] Specifically, in the output noise reduction phase, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is pulled down to the output of the cascade signal terminal through M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is pulled down to the output of the cascade signal terminal through M12B.

[0184] Specifically, in the output noise reduction phase, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is pulled down to the output of the cascade signal terminal through M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is pulled down to the output of the cascade signal terminal through M12B.

[0185] The other structures of the shift register in this example can be the same as those in the fifth example, and thus are not repeated here.

[0186] The eighth example: FIG. 10 is a circuit diagram of a shift register in the eighth example of the embodiment of the present disclosure; as shown in FIG. 10, the structure of the shift register in this example is substantially the same as that in the seventh example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those in the seventh example.

[0187] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include fifth transistors, which are denoted as M5A and M5B respectively for the convenience of description. The gate and the source of M5A are connected to the first power voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0188] When the first power voltage terminal VDDO is written with the first power voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power voltage, i.e., high potential. When the second power voltage terminal VDDE is written with the second power voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power voltage, i.e., high potential.

[0189] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, which is denoted as M6A and M6B respectively for the convenience of description. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0190] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high for normal output.

[0191] The other structures of the shift register in this example can be the same as those in the seventh example, and thus are not repeated here.

[0192] The ninth example: Figure 11 is a circuit diagram of a shift register of the ninth example of the embodiment of the present disclosure; as shown in Figure 11, the shift register includes a first input sub-circuit 11, a pull-up reset sub-circuit 2, an output sub-circuit 3, a first pull-down control sub-circuit 41, a second pull-down control sub-circuit 42, a first pull-down sub-circuit 51, a second pull-down sub-circuit 52, a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92. Among them, the first input sub-circuit 11 is configured to respond to the first input signal, and pre-charge the pull-up node PU through the first input signal. The output sub-circuit 3 is configured to respond to the potential of the pull-up node PU, and output the clock signal through the signal output end. The pull-up reset sub-circuit 2 is configured to respond to the pull-up reset signal, and reset the output of the pull-up node PU through the low-level signal. The first pull-down control sub-circuit 41 is configured to respond to the first power voltage, and control the potential of the first pull-down node PD1 through the first power voltage. The second pull-down control sub-circuit 42 is configured to respond to the second power voltage, and control the potential of the second pull-down node PD2 through the second power voltage. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node PU, and pull down the potential of the first pull-down node PD1 through the low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node PU, and pull down the potential of the second pull-down node PD2 through the low-level signal. The first auxiliary sub-circuit 91 is configured to respond to the frame start signal, and pull down the potential of the first pull-down node PD1 through the first power voltage when the second power voltage is a high-level signal. The second auxiliary sub-circuit 92 is configured to respond to the frame start signal, and pull down the potential of the second pull-down node PD2 through the second power voltage when the first power voltage is a high-level signal.

[0193] In this example, by adding the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, the second power voltage is converted from a low level signal to a high level signal, and the first power voltage is converted from a high level signal to a low level signal, before the pull-up node PU is charged (except for the first stage shift register), the first auxiliary sub-circuit 91 is controlled to work by the frame start signal, and the first pull-down node PD1 is pulled down by a low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the second pull-down node PD2 competes with the potential of the pull-up node PU, which helps to improve the charging capability of the pull-up node PU. Similarly, when the first pull-down control sub-circuit 41 is working, that is, the first power voltage is converted from a low level signal to a high level signal, and the second power voltage is converted from a high level signal to a low level signal, before the pull-up node PU is charged, the second auxiliary sub-circuit 92 is controlled to work by the frame start signal, and the second pull-down node PD2 is pulled down by a low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the first pull-down node PD1 competes with the potential of the pull-up node PU, which helps to improve the charging capability of the pull-up node PU.

[0194] With continuous reference to FIG. 11, when the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, except for the first stage shift register, the first input signal end of the Nth stage shift register is connected to the signal output end G(N-1) of the (N-1)th shift register; except for the last stage shift register, the pull-up reset signal end of the Nth stage shift register is connected to the signal output end G(N+1) of the (N+1)th shift register. N≥2, and N is an integer. The first input signal end of the first stage shift register and the second input signal end of the last stage shift register are connected to the frame start signal. In this example, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 are controlled by the frame start signal, that is, for the gate drive circuit, no control signal is added because of the addition of the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, and therefore the control of the shift register is relatively simple.

[0195] In some examples, with continuous reference to FIG. 11, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 each include a seventeenth transistor, for the convenience of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is denoted as M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is denoted as M17B. Wherein, the source of M17A is connected to the first power voltage end VDDO, the drain of M17A is connected to the first pull-down node PD1, and the gate of M17A is connected to the frame start signal end STV. The source of M17B is connected to the second power voltage end VDDE, the drain of M17B is connected to the second pull-down node, and the gate of M17B is connected to the frame start signal end STV.

[0196] Specifically, the frame start signal terminal STV is used to introduce a frame start signal, the first power voltage terminal VDDO is used to introduce a first power voltage, and the second power voltage terminal VDDE is used to introduce a second power voltage. When the second power voltage of the second power voltage terminal VDDE is converted from a low level to a high level, the first power voltage of the first power voltage terminal VDDO is converted from a high level to a low level, and the frame start signal written by the frame start signal terminal STV is a high level signal, the M17A is opened, and at this time, the first power voltage is a low level to pull down the potential of the first pull-down node PD1. Similarly, when the first power voltage of the first power voltage terminal VDDO is converted from a low level to a high level, the second power voltage of the second power voltage terminal VDDE is converted from a high level to a low level, and the frame start signal written by the frame start signal terminal STV is a high level signal, the M17B is opened, and at this time, the second power voltage is a low level to pull down the potential of the second pull-down node PD2. The example can effectively avoid the competitive relationship of the pull-up node PU and the first pull-down node PD1 / second pull-down node PD2.

[0197] In some examples, continuing to refer to FIG. 11, the shift register of the embodiment of the present disclosure further includes a global reset sub-circuit 6, which is configured to globally reset the output of the pull-up node and the signal output terminal by a low level signal in response to a global reset signal.

[0198] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of the M4 is connected to the pull-up node PU, the drain of the M4 is connected to the low level signal terminal VGL, and the gate of the M4 is connected to the global reset signal terminal STV0. The source of the M7 is connected to the signal output terminal G(N), the drain of the M7 is connected to the low level signal terminal VGL, and the gate of the M7 is connected to the global reset signal terminal STV0.

[0199] Specifically, in the global reset phase, the global reset signal written by the global reset signal terminal STV0 is a high level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on, at this time, the low level signal written by the low level signal terminal VGL resets the pull-up node PU through the fourth transistor M4, and resets the signal output terminal G(N) through the seventh transistor M7.

[0200] In some examples, with continued reference to FIG. 11, the shift register further includes two first noise reduction sub-circuits 71 / 72 and two second noise reduction sub-circuits 81 / 82. One of the two first noise reduction sub-circuits 71 / 72 (71) is responsive to the potential of the first pull-down node PD1 to reduce the output of the pull-up node PU by a low-level signal, and the other (72) is responsive to the potential of the second pull-down node PD2 to reduce the output of the pull-up node PU by a low-level signal. One of the two second noise reduction sub-circuits 81 / 82 (81) is responsive to the potential of the first pull-down node PD1 to reduce the output of the signal output terminal G(N) by a low-level signal, and the other (82) is responsive to the potential of the second pull-down node PD2 to reduce the output of the signal output terminal G(N) by a low-level signal.

[0201] In some examples, the two first noise reduction sub-circuits 71 / 72 each include a tenth transistor, and the two second noise reduction sub-circuits 81 / 82 each include an eleventh transistor. The tenth transistors in the two first noise reduction sub-circuits are denoted as M10A and M10B, respectively. The eleventh transistors in the two second noise reduction sub-circuits are denoted as M11A and M11B, respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0202] In particular, in the output noise reduction phase, when the potential of the first pull-down node PD1 is high, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is high, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL.

[0203] In some examples, the first input sub-circuit 11 includes a first transistor M1, and the second input sub-circuit 12 includes a second transistor M2. The source and gate of M1 are connected to the first input signal terminal, the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal.

[0204] Specifically, in the input stage, the first input signal written into the first input signal terminal is a high level signal, M1 is opened, at this time, the pull-up node PU is pre-charged by the high level signal. In the pull-up reset stage, the pull-up reset signal written into the pull-up reset signal terminal is a high level signal, M2 is opened, at this time, the pull-up node PU is discharged by the low level signal, so as to realize the reset of the pull-up node PU.

[0205] In some examples, the output sub-circuit 3 comprises a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0206] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, the clock signal written into the clock signal terminal CLK is a high level signal, at this time, the signal output terminal G(N) outputs a high level signal.

[0207] In some examples, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 each comprise a fifth transistor and a ninth transistor, for the convenience of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are denoted as M5A and M9A respectively, and the fifth transistor and the ninth transistor in the second pull-down control sub-circuit 42 are denoted as M5B and M9B respectively. The source of M5A is connected to the first power voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and the gate of M9A are connected to the second power voltage terminal VDDE. The source of M5B is connected to the second power voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and the gate of M9B are connected to the second power voltage terminal VDDE.

[0208] Specifically, when the first power voltage is written into the first power voltage terminal VDDO, M5A and M9A are both opened, the potential of the first pull-down node PD1 is pulled high by the first power voltage, that is, at a high potential. When the second power voltage is written into the second power voltage terminal VDDE, M5B and M9B are both opened, the potential of the second pull-down node PD2 is pulled high by the second power voltage, that is, at a high potential. It should be noted that the first power voltage and the second power voltage can be the same power voltage. In the embodiments of the present disclosure, only the case that the first power voltage and the second power voltage are the same power voltage is described.

[0209] In some examples, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are denoted as M6A and M8A respectively, and the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are denoted as M6B and M8B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0210] Specifically, when the potential of the pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high to output normally.

[0211] The tenth example: FIG. 12 is a circuit diagram of a shift register of the tenth example of the embodiment of the present disclosure; as shown in FIG. 12, the structure of the shift register of this example is substantially the same as that of the ninth example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the ninth example.

[0212] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, and for ease of description, the fifth transistor in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 is denoted as M5A and M5B respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0213] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, the first pull-down node PD1 has the potential of the first power supply voltage, i.e. high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 has the potential of the second power supply voltage, i.e. high potential.

[0214] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0215] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high, and normal output is ensured.

[0216] The other structures of the shift register in this example can be the same as those in the ninth example, and thus will not be repeated here.

[0217] Eleventh example: FIG. 13 is a circuit diagram of a shift register of an eleventh example of an embodiment of the present disclosure. As shown in FIG. 13, the structure of the shift register in this example is substantially the same as that in the ninth example, and the only difference is that the shift register in this example adds a cascade sub-circuit 111 to the shift register in the ninth example, and the cascade output sub-circuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0218] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascade signal terminal output_C(N), and the gate of M13 is connected to the pull-up node PU.

[0219] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, the clock signal written by the clock signal terminal CLK is a high-level signal in this stage, and the cascade signal terminal output_C(N) outputs a high-level signal at this time.

[0220] When the shift register in the embodiment of the present disclosure is applied to a gate driving circuit, in addition to the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th stage shift register; in addition to the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th stage shift register. N≥2, and N is an integer.

[0221] In some examples, continuing to refer to FIG. 13, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the first pull-down node PD1, and the other of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the second pull-down node PD2.

[0222] Continuing to refer to FIG. 13, both of the third noise reduction sub-circuits can include twelfth transistors, denoted as M12A and M12B respectively. The source of M12A is connected to the cascade signal end, the drain of M12A is connected to the low-level signal end VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal end, the drain of M12B is connected to the low-level signal end VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0223] Specifically, in the output noise reduction phase, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12B.

[0224] Continuing to refer to FIG. 13, the shift register in this example can also include a first discharge sub-circuit 101 and a second discharge sub-circuit 102. The first discharge sub-circuit 101 is configured to discharge the first pull-down node PD1 by a low-level signal in response to a first input signal. The second discharge sub-circuit 102 is configured to discharge the second pull-down node PD2 by a low-level signal in response to the first input signal.

[0225] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 works to pre-charge the pull-up node PU, at which time the first discharge sub-circuit 101 discharges the first pull-down node PD1 and the second discharge sub-circuit 102 discharges the second pull-down node PD2, thereby avoiding competition between the potentials of the first pull-down node PD1, the second pull-down node PD2, and the pull-up node PU.

[0226] The first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 can each include a sixteenth transistor. For ease of description, the sixteenth transistor in the first pull-down sub-circuit 51 is denoted as M16A, and the sixteenth transistor in the second pull-down sub-circuit 52 is denoted as M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0227] In the input stage, the first input signal written into the first input signal terminal is a high-level signal, and M16A and M16B are both turned on, so that the low-level signal written in through the low-level signal terminal VGL pulls down the potentials of the first pull-down node PD1 and the second pull-down node PD2.

[0228] The other structures of the shift register in this example can be the same as those in the ninth example, and thus are not repeated here.

[0229] Twelfth example: FIG. 14 is a circuit diagram of a shift register of a twelfth example of an embodiment of the present disclosure. As shown in FIG. 14, the structure of the shift register of this example is substantially the same as that of the eleventh example, and the only difference is that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51, and the second pull-down sub-circuit 52 are different from those of the eleventh example.

[0230] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistor in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 is denoted as M5A and M5B, respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0231] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 has the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 has the potential of the second power supply voltage, i.e., a high potential.

[0232] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0233] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0234] For other structures of the shift register in this example, they can be the same as those in the eleventh example, and thus will not be repeated here.

[0235] Thirteenth example: FIG. 15 is a circuit diagram of a shift register of a thirteenth example of an embodiment of the present disclosure. As shown in FIG. 15, the structure of the shift register of this example is substantially the same as that of the ninth example, and the only difference is that the shift register can realize bidirectional scanning. The first input sub-circuit 11 and the pull-up reset sub-circuit 2 in this example are different from those in the ninth example. In this example, since the shift register can realize bidirectional scanning, in forward scanning, the first input sub-circuit 11 is used for pre-charging the pull-up node PU, and the pull-up reset sub-circuit 2 is used for resetting the pull-up node PU; in reverse scanning, the first input sub-circuit 11 is used for resetting the pull-up node PU, and the pull-up reset sub-circuit 2 is used for pre-charging the pull-up node PU. Therefore, for ease of understanding, the first input sub-circuit 11 in the above example is still called the first input sub-circuit 11, and the pull-up reset sub-circuit 2 is called the second input sub-circuit 12. Since the first input sub-circuit 11 and the second input sub-circuit 12 are the main elements for supporting the shift register to realize bidirectional scanning, the connection relationship between the first input sub-circuit 11 and the second input sub-circuit 12 is different from that between the first input sub-circuit 11 and the pull-up reset sub-circuit 2.

[0236] Continuing to refer to FIG. 15, specifically, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU through the first scan signal in response to the first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU through the second scan signal in response to the second input signal.

[0237] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal end VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input end. The source of M2 is connected to the second scan signal end VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input end.

[0238] Specifically, when forward scanning, in the input stage, the first input signal written into the first signal input end is a high-level signal, M1 is turned on, the first scan signal written into the first scan signal end VDS is a high-level signal, and the pull-up node PU is pre-charged through the first scan signal at this time. In the pull-up reset stage, the second input signal written into the second signal input end is a high-level signal, M2 is turned on, the second scan signal written into the second scan signal end VSD is a low-level signal, and the pull-up node PU is discharged through the second scan signal at this time, so as to realize the reset of the pull-up node PU.

[0239] When reverse scanning, in the input stage, the second input signal written into the second signal input end is a high-level signal, M2 is turned on, the second scan signal written into the second scan signal end VSD is a high-level signal, and the pull-up node PU is pre-charged through the second scan signal at this time. In the pull-up reset stage, the first input signal written into the first signal input end is a high-level signal, M1 is turned on, the first scan signal written into the first scan signal end VDS is a low-level signal, and the pull-up node PU is discharged through the first scan signal at this time, so as to realize the reset of the pull-up node PU.

[0240] The other structures of the shift register in this example can be the same as those in the ninth example, and thus will not be repeated here.

[0241] The fourteenth example: Fig. 16 is a circuit diagram of a shift register of the fourteenth example of the embodiment of the present disclosure; as shown in Fig. 16, the structure of the shift register of this example is substantially the same as that of the thirteenth example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the thirteenth example.

[0242] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include fifth transistors, which are denoted as M5A and M5B respectively for ease of description. The gate and the source of M5A are connected to the first power voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0243] When the first power voltage terminal VDDO is written with the first power voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power voltage, i.e., high potential. When the second power voltage terminal VDDE is written with the second power voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power voltage, i.e., high potential.

[0244] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, which is denoted as M6A and M6B respectively for ease of description. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0245] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high to output normally.

[0246] The other structures of the shift register in this example can be the same as those in the thirteenth example, and thus will not be repeated here.

[0247] Fifteenth example: FIG. 17 is a circuit diagram of a shift register of a fifteenth example of an embodiment of the present disclosure. As shown in FIG. 17, the structure of the shift register of this example is substantially the same as that of the fourteenth example, and the only difference is that the shift register of this example adds a cascaded sub-circuit 111 to the shift register of the fourteenth example, and the cascaded output sub-circuit 3 is configured to output the clock signal through the cascaded signal terminal in response to the potential of the pull-up node PU.

[0248] In some examples, the cascaded sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascaded signal terminal output C(N), and the gate of M13 is connected to the pull-up node PU. In some examples, the cascaded sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascaded signal terminal output C(N), and the gate of M13 is connected to the pull-up node PU.

[0249] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal end CLK is a high-level signal in this stage. At this time, the cascade signal end output_C(N) outputs a high-level signal.

[0250] When the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, the first input signal end of the Nth shift register is connected to the cascade signal end output_C(N-1) of the (N-1)th shift register, and the second input signal end of the Nth shift register is connected to the cascade signal end output_C(N+1) of the (N+1)th shift register, except for the first shift register and the last shift register. N≥2, and N is an integer.

[0251] In some examples, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits. One of the two third noise reduction sub-circuits is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the first pull-down node PD1. The other third noise reduction sub-circuit is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the second pull-down node PD2.

[0252] Specifically, referring back to FIG. 17, both of the two third noise reduction sub-circuits can include twelfth transistors, denoted as M12A and M12B respectively. The source of M12A is connected to the cascade signal end, the drain of M12A is connected to the low-level signal end VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal end, the drain of M12B is connected to the low-level signal end VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0253] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is opened, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12A. When the second pull-down node PD2 is a high-level signal, M12B is opened, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12B.

[0254] The other structures of the shift register in this example can be the same as those in the fourteenth example, and thus are not repeated here.

[0255] Sixteenth example: Fig. 18 is a circuit diagram of a shift register of a sixteenth example of an embodiment of the present disclosure; as shown in Fig. 18, the structure of the shift register of this example is substantially the same as that of the fifteenth example, the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the fifteenth example.

[0256] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, for the convenience of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are denoted as M5A and M5B respectively. The gate and the source of M5A are connected to the first power voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0257] Wherein, when the first power voltage terminal VDDO is written with the first power voltage, M5A is open, and the first pull-down node PD1 is at the potential of the first power voltage, i.e. high potential. When the second power voltage terminal VDDE is written with the second power voltage, M5B is open, and the second pull-down node PD2 is at the potential of the second power voltage, i.e. high potential.

[0258] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for the convenience of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B respectively. Wherein, the source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0259] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is open, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0260] The other structures of the shift register in this example can be the same as those in the fifteenth example, and therefore will not be repeated here.

[0261] The seventeenth example: Figure 19 is a circuit diagram of a shift register of the seventeenth example of the embodiment of the present disclosure; as shown in Figure 19, the shift register includes a first input sub-circuit 11, a pull-up reset sub-circuit 2, an output sub-circuit 3, a first pull-down control sub-circuit 41, a second pull-down control sub-circuit 42, a first pull-down sub-circuit 51, a second pull-down sub-circuit 52, a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92. Among them, the first input sub-circuit 11 is configured to respond to the first input signal, and pre-charge the pull-up node PU through the first input signal. The output sub-circuit 3 is configured to respond to the potential of the pull-up node PU, and output the clock signal through the signal output end. The pull-up reset sub-circuit 2 is configured to respond to the pull-up reset signal, and reset the output of the pull-up node PU through the low-level signal. The first pull-down control sub-circuit 41 is configured to respond to the first power voltage, and control the potential of the first pull-down node PD1 through the first power voltage. The second pull-down control sub-circuit 42 is configured to respond to the second power voltage, and control the potential of the second pull-down node PD2 through the second power voltage. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node PU, and pull down the potential of the first pull-down node PD1 through the low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node PU, and pull down the potential of the second pull-down node PD2 through the low-level signal. The first auxiliary sub-circuit 91 is configured to pull down the potential of the first pull-down node PD1 through the low-level signal in response to the second power voltage when the second power voltage is a high-level signal. The second auxiliary sub-circuit 92 is configured to pull down the potential of the second pull-down node PD2 through the low-level signal in response to the first power voltage when the first power voltage is a high-level signal.

[0262] In this example, by adding the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, the second power voltage is converted from a low level signal to a high level signal, and the first power voltage is converted from a high level signal to a low level signal, before the pull-up node PU is charged (except for the first stage shift register), the first auxiliary sub-circuit 91 is controlled to work by the second power voltage, and the first pull-down node PD1 is pulled down by the low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the second pull-down node PD2 competes with that of the pull-up node PU, which helps to improve the charging capability of the pull-up node PU. Similarly, when the first pull-down control sub-circuit 41 is working, that is, the first power voltage is converted from a low level signal to a high level signal, and the second power voltage is converted from a high level signal to a low level signal, before the pull-up node PU is charged, the second auxiliary sub-circuit 92 is controlled to work by the first power voltage, and the second pull-down node PD2 is pulled down by the low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the first pull-down node PD1 competes with that of the pull-up node PU, which helps to improve the charging capability of the pull-up node PU. In this example, the first auxiliary sub-circuit 91 is controlled by the second power voltage, and the second auxiliary sub-circuit 92 is controlled by the first power voltage, that is, for the entire shift register, no additional control signals are added because of the addition of the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, so the control of the shift register is relatively simple.

[0263] With continuous reference to FIG. 19, when the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, the first input signal end of the Nth stage shift register is connected to the signal output end G(N-1) of the (N-1)th shift register, and the pull-up reset signal end of the Nth stage shift register is connected to the signal output end G(N+1) of the (N+1)th shift register. N≥2, and N is an integer. The first input signal end of the first stage shift register and the second input signal end of the last stage shift register are connected to a frame start signal.

[0264] In some examples, with continuous reference to FIG. 19, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 each include a seventeenth transistor, for the convenience of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is denoted as M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is denoted as M17B. Wherein, the source of M17A is connected to the first pull-down node PD1, the drain of M17A is connected to the low level signal end VGL, and the gate of M17A is connected to the second power voltage end VDDE. The source of M17B is connected to the second pull-down node PD2, the drain of M17B is connected to the low level signal end, and the gate of M17B is connected to the first power voltage end VDDO.

[0265] Specifically, the first power voltage terminal VDDO is configured to introduce the first power voltage, and the second power voltage terminal VDDE is configured to introduce the second power voltage. When the second power voltage of the second power voltage terminal VDDE is converted from a low level to a high level, and the first power voltage of the first power voltage terminal VDDO is converted from a high level to a low level, the M17A is turned on, and the low level signal written by the low level signal terminal VGL pulls the potential of the first pull-down node PD1 low. Similarly, when the first power voltage of the first power voltage terminal VDDO is converted from a low level to a high level, and the second power voltage of the second power voltage terminal VDDE is converted from a high level to a low level, the M17B is turned on, and the low level signal written by the low level signal terminal VGL pulls the potential of the second pull-down node PD2 low. This example can effectively avoid the competitive relationship between the pull-up node PU and the first pull-down node PD1 / second pull-down node PD2.

[0266] In some examples, continuing to refer to FIG. 19, the shift register of the embodiment of the present disclosure further includes a global reset sub-circuit 6, which is configured to globally reset the output of the pull-up node PU and the signal output terminal by a low level signal in response to a global reset signal.

[0267] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of the M4 is connected to the pull-up node PU, the drain of the M4 is connected to the low level signal terminal VGL, and the gate of the M4 is connected to the global reset signal terminal STV0. The source of the M7 is connected to the signal output terminal G(N), the drain of the M7 is connected to the low level signal terminal VGL, and the gate of the M7 is connected to the global reset signal terminal STV0.

[0268] Specifically, in the global reset phase, the global reset signal written by the global reset signal terminal STV0 is a high level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on. At this time, the low level signal written by the low level signal terminal VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output terminal G(N) through the seventh transistor M7.

[0269] In some examples, continuing to refer to FIG. 19, the shift register further includes two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits reduces the output of the pull-up node PU by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the pull-up node PU by the low-level signal in response to the potential of the second pull-down node PD2. One of the two second noise reduction sub-circuits reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the second pull-down node PD2.

[0270] In some examples, continuing to refer to FIG. 19, the shift register further includes two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits reduces the output of the pull-up node PU by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the pull-up node PU by the low-level signal in response to the potential of the second pull-down node PD2. One of the two second noise reduction sub-circuits reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the second pull-down node PD2.

[0271] Specifically, in the output noise reduction phase, when the potential of the first pull-down node PD1 is high, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is high, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL.

[0272] In some examples, the first input sub-circuit 11 includes a first transistor M1, and the second input sub-circuit 12 includes a second transistor M2. The source and gate of M1 are connected to the first input signal terminal, the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal.

[0273] Specifically, in the input stage, the first input signal written into the first input signal terminal is a high level signal, M1 is opened, at this time, the pull-up node PU is pre-charged by the high level signal. In the pull-up reset stage, the pull-up reset signal written into the pull-up reset signal terminal is a high level signal, M2 is opened, at this time, the pull-up node PU is discharged by the low level signal, so as to realize the reset of the pull-up node PU.

[0274] In some examples, the output sub-circuit 3 comprises a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0275] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, the clock signal written into the clock signal terminal CLK is a high level signal, at this time, the signal output terminal G(N) outputs a high level signal.

[0276] In some examples, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 each comprise a fifth transistor and a ninth transistor, for the convenience of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are denoted as M5A and M9A respectively, and the fifth transistor and the ninth transistor in the second pull-down control sub-circuit 42 are denoted as M5B and M9B respectively. The source of M5A is connected to the first power voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and the gate of M9A are connected to the second power voltage terminal VDDE. The source of M5B is connected to the second power voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and the gate of M9B are connected to the second power voltage terminal VDDE.

[0277] Specifically, when the first power voltage is written into the first power voltage terminal VDDO, M5A and M9A are both opened, the potential of the first pull-down node PD1 is pulled high by the first power voltage, that is, at a high potential. When the second power voltage is written into the second power voltage terminal VDDE, M5B and M9B are both opened, the potential of the second pull-down node PD2 is pulled high by the second power voltage, that is, at a high potential. It should be noted that the first power voltage and the second power voltage can be the same power voltage. In the embodiments of the present disclosure, only the case that the first power voltage and the second power voltage are the same power voltage is described.

[0278] In some examples, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are denoted as M6A and M8A respectively, and the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are denoted as M6B and M8B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0279] Specifically, when the potential of the pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high to output normally.

[0280] The eighteenth example: Fig. 20 is a circuit diagram of a shift register of the eighteenth example of the embodiment of the present disclosure; as shown in Fig. 20, the structure of the shift register of this example is substantially the same as that of the seventeenth example, and the only difference is that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the seventeenth example.

[0281] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, and for ease of description, the fifth transistor in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 is denoted as M5A and M5B respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0282] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 has the potential of the first power supply voltage, i.e. high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 has the potential of the second power supply voltage, i.e. high potential.

[0283] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0284] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0285] The other structures of the shift register in this example can be the same as those in the seventeenth example, and thus will not be repeated here.

[0286] The nineteenth example: FIG. 21 is a circuit diagram of a shift register of the nineteenth example of the embodiments of the present disclosure; as shown in FIG. 21, the structure of the shift register in this example is substantially the same as that in the seventeenth example, and the only difference is that the shift register in this example adds a cascade sub-circuit 111 to the shift register in the seventeenth example, and the cascade output sub-circuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0287] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascade signal terminal output_C(N), and the gate of M13 is connected to the pull-up node PU.

[0288] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, the clock signal written by the clock signal terminal CLK is a high-level signal in this stage, and at this time the cascade signal terminal output_C(N) outputs a high-level signal.

[0289] When the shift register in the embodiments of the present disclosure is applied to a gate driving circuit, in addition to the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th stage shift register; in addition to the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th stage shift register. N≥2, and N is an integer.

[0290] In some examples, continuing to refer to FIG. 21, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the first pull-down node PD1, and the other of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the second pull-down node PD2.

[0291] In which, continuing to refer to FIG. 21, both of the third noise reduction sub-circuits can include twelfth transistors, denoted as M12A and M12B respectively; the source of M12A is connected to the cascade signal end, the drain of M12A is connected to the low-level signal end VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal end, the drain of M12B is connected to the low-level signal end VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0292] Specifically, in the output noise reduction phase, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12B.

[0293] Continuing to refer to FIG. 21, the shift register in this example can also include a first discharge sub-circuit 101 and a second discharge sub-circuit 102; the first discharge sub-circuit 101 is configured to discharge the first pull-down node PD1 by a low-level signal in response to the first input signal. The second discharge sub-circuit 102 is configured to discharge the second pull-down node PD2 by a low-level signal in response to the first input signal.

[0294] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 works to pre-charge the pull-up node PU, at which time the first discharge sub-circuit 101 discharges the first pull-down node PD1 and the second discharge sub-circuit 102 discharges the second pull-down node PD2, thereby avoiding competition between the potentials of the first pull-down node PD1, the second pull-down node PD2 and the pull-up node PU.

[0295] The first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 can each include a sixteenth transistor. For ease of description, the sixteenth transistor in the first pull-down sub-circuit 51 is denoted as M16A, and the sixteenth transistor in the second pull-down sub-circuit 52 is denoted as M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0296] In the input stage, the first input signal written into the first input signal terminal is a high-level signal, and M16A and M16B are both open. The low-level signal written in through the low-level signal terminal VGL pulls down the potential of the first pull-down node PD1 and the second pull-down node PD2.

[0297] The other structures of the shift register in this example can be the same as those in the seventeenth example, and thus are not repeated here.

[0298] The twentieth example: FIG. 22 is a circuit diagram of a shift register of a twentieth example of an embodiment of the present disclosure. As shown in FIG. 22, the structure of the shift register of this example is substantially the same as that of the nineteenth example, and the only difference is that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51, and the second pull-down sub-circuit 52 are different from those in the nineteenth example.

[0299] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistor in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 is denoted as M5A and M5B, respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0300] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is open, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is open, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0301] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0302] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0303] For other structures of the shift register in this example, they can be the same as those in the nineteenth example, and thus will not be repeated here.

[0304] The twenty-first example: FIG. 23 is a circuit diagram of a shift register of the twenty-first example of an embodiment of the present disclosure; as shown in FIG. 23, the structure of the shift register of this example is substantially the same as that of the seventeenth example, the only difference is that the shift register can realize bidirectional scanning, and the first input sub-circuit 11 and the pull-up reset sub-circuit 2 in this example are different from those in the seventeenth example. In this example, since the shift register can realize bidirectional scanning, in forward scanning, the first input sub-circuit 11 is used for pre-charging the pull-up node PU, and the pull-up reset sub-circuit 2 is used for resetting the pull-up node PU; in reverse scanning, the first input sub-circuit 11 is used for resetting the pull-up node PU, and the pull-up reset sub-circuit 2 is used for pre-charging the pull-up node PU. Therefore, for ease of understanding, the first input sub-circuit 11 in the above example is still called the first input sub-circuit 11, and the pull-up reset sub-circuit 2 is called the second input sub-circuit 12. Since the first input sub-circuit 11 and the second input sub-circuit 12 are the main elements for supporting the shift register to realize bidirectional scanning, the connection relationship between the first input sub-circuit 11 and the second input sub-circuit 12 is different from that between the first input sub-circuit 11 and the pull-up reset sub-circuit 2.

[0305] Continuing to refer to FIG. 23, specifically, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU through the first scan signal in response to the first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU through the second scan signal in response to the second input signal.

[0306] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal end VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input end. The source of M2 is connected to the second scan signal end VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input end.

[0307] Specifically, when forward scanning, in the input stage, the first input signal written into the first input signal end is a high-level signal, M1 is opened, the first scan signal written into the first scan signal end VDS is a high-level signal, and the pull-up node PU is pre-charged through the first scan signal at this time. In the pull-up reset stage, the second input signal written into the second input signal end is a high-level signal, M2 is opened, the second scan signal written into the second scan signal end VSD is a low-level signal, and the pull-up node PU is discharged through the second scan signal at this time, so as to realize the reset of the pull-up node PU.

[0308] When reverse scanning, in the input stage, the second input signal written into the second input signal end is a high-level signal, M2 is opened, the second scan signal written into the second scan signal end VSD is a high-level signal, and the pull-up node PU is pre-charged through the second scan signal at this time. In the pull-up reset stage, the first input signal written into the first input signal end is a high-level signal, M1 is opened, the first scan signal written into the first scan signal end VDS is a low-level signal, and the pull-up node PU is discharged through the first scan signal at this time, so as to realize the reset of the pull-up node PU.

[0309] For other structures of the shift register in this example, they can be the same as those in the seventeenth example, and thus will not be repeated here.

[0310] The twenty-second example: FIG. 24 is a circuit diagram of a shift register of the twenty-second example of the embodiment of the present disclosure; as shown in FIG. 24, the structure of the shift register of this example is substantially the same as that of the twenty-first example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the twenty-first example.

[0311] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include fifth transistors, which are denoted as M5A and M5B respectively for ease of description. The gate and the source of M5A are connected to the first power voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0312] When the first power voltage terminal VDDO is written with the first power voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power voltage, i.e., high potential. When the second power voltage terminal VDDE is written with the second power voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power voltage, i.e., high potential.

[0313] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, which is denoted as M6A and M6B respectively for ease of description. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0314] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high to output normally.

[0315] The other structures of the shift register in this example can be the same as those in the twenty-first example, and thus will not be repeated here.

[0316] The twenty-third example: FIG. 25 is a circuit diagram of a shift register of the twenty-third example of the embodiments of the present disclosure. As shown in FIG. 25, the structure of the shift register of this example is substantially the same as that of the fourteenth example, and the only difference is that the shift register of this example adds a cascading sub-circuit 111 to the shift register of the twenty-second example, and the cascading output sub-circuit 3 is configured to output the clock signal through the cascading signal terminal in response to the potential of the pull-up node PU.

[0317] In some examples, the cascading sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascading signal terminal output C(N), and the gate of M13 is connected to the pull-up node PU.

[0318] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage, at this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0319] When the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, in addition to the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th stage shift register; in addition to the last stage shift register, the second input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th stage shift register. N≥2, and N is an integer.

[0320] In some examples, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the first pull-down node PD1; the other is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the second pull-down node PD2.

[0321] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage, at this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0322] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage, at this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0323] For other structures of the shift register in this example, they can be the same as those in the twenty-second example, and thus will not be repeated here.

[0324] The twenty-fourth example is shown in FIG. 26, which is a circuit diagram of a shift register according to the twenty-fourth example of the embodiments of the present disclosure. As shown in FIG. 26, the structure of the shift register according to the twenty-fourth example is substantially the same as that of the twenty-third example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the twenty-third example.

[0325] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are denoted as M5A and M5B, respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0326] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 has a potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 has a potential of the second power supply voltage, i.e., a high potential.

[0327] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor. For ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B, respectively. Specifically, the source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0328] Specifically, when the potential of the pull-up node PU is a high level, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, and the pull-up node PU is ensured to remain at a high level for normal output.

[0329] The other structures of the shift register in this example can be the same as those in the twenty-third example, and thus will not be repeated here.

[0330] The first input sub-circuit 11 is configured to respond to the first input signal and pre-charge the pull-up node PU by the first input signal. The output sub-circuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output end. The pull-up reset sub-circuit 2 is configured to respond to the pull-up reset signal and reset the output of the pull-up node PU by the low-level signal. The first pull-down control sub-circuit 41 is configured to respond to the first power voltage and control the potential of the first pull-down node PD1 by the first power voltage. The second pull-down control sub-circuit 42 is configured to respond to the second power voltage and control the potential of the second pull-down node PD2 by the second power voltage. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node PU and pull down the potential of the first pull-down node PD1 by the low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node PU and pull down the potential of the second pull-down node PD2 by the low-level signal. The first auxiliary sub-circuit 91 is configured to respond to the potential of the second node and pull down the potential of the first pull-down node PD1 by the low-level signal when the second power voltage is a high-level signal. The second auxiliary sub-circuit 92 is configured to respond to the potential of the first node and pull down the potential of the second pull-down node PD2 by the low-level signal when the first power voltage is a high-level signal.

[0331] In this example, by adding the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, when the second pull-down control sub-circuit works, that is, the second power voltage is converted from a low level signal to a high level signal, the first power voltage is converted from a high level signal to a low level signal, and the second pull-down node PD2 is pulled up to the high potential of the second power voltage, before the pull-up node PU is charged (except for the first stage shift register), the first auxiliary sub-circuit 91 is controlled to work by the high potential of the second node, and the first pull-down node PD1 is pulled down by a low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the second pull-down node PD2 competes with that of the pull-up node PU, which helps to improve the charging capacity of the pull-up node PU. Similarly, when the first pull-down control sub-circuit works, that is, the first power voltage is converted from a low level signal to a high level signal, the second power voltage is converted from a high level signal to a low level signal, and the first pull-down node PD1 is pulled up to the high potential of the first power voltage, before the pull-up node PU is charged, the second auxiliary sub-circuit 92 is controlled to work by the high potential of the first pull-down node PD1, and the second pull-down node PD2 is pulled down by a low level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear high level at the same time, and only the potential of the first pull-down node PD1 competes with that of the pull-up node PU, which helps to improve the charging capacity of the pull-up node PU. In this example, the first auxiliary sub-circuit 91 is controlled by the potential of the second pull-down node PD2, and the second auxiliary sub-circuit 92 is controlled by the voltage of the first pull-down node PD1, that is, for the entire shift register, no additional control signals are added due to the addition of the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, and therefore the control of the shift register is relatively simple.

[0332] With continuous reference to FIG. 27, when the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, the first input signal end of the Nth stage shift register is connected to the signal output end G(N-1) of the (N-1)th shift register, and the pull-up reset signal end of the Nth stage shift register is connected to the signal output end G(N+1) of the (N+1)th shift register, except for the last stage shift register. N≥2, and N is an integer. The first input signal end of the first stage shift register and the second input signal end of the last stage shift register are connected to a frame start signal.

[0333] In some examples, continuing to refer to FIG. 27, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 each include a seventeenth transistor, for ease of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is denoted as M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is denoted as M17B. The source of M17A is connected to the first pull-down node PD1, the drain of M17A is connected to the low-level signal terminal VGL, and the gate of M17A is connected to the second pull-down node PD2. The source of M17B is connected to the second pull-down node PD2, the drain of M17B is connected to the low-level signal terminal VGL, and the gate of M17B is connected to the first pull-down node PD1.

[0334] Specifically, the first power voltage terminal VDDO is used to introduce a first power voltage, and the second power voltage terminal VDDE is used to introduce a second power voltage. When the second power voltage of the second power voltage terminal VDDE is converted from a low level to a high level, and the first power voltage of the first power voltage terminal VDDO is converted from a high level to a low level, M17A is turned on, and at this time, the low-level signal written by the low-level signal terminal VGL pulls down the potential of the first pull-down node PD1. Similarly, when the first power voltage of the first power voltage terminal VDDO is converted from a low level to a high level, and the second power voltage of the second power voltage terminal VDDE is converted from a high level to a low level, M17B is turned on, and at this time, the low-level signal written by the low-level signal terminal VGL pulls down the potential of the second pull-down node PD2. This example can effectively avoid the competition relationship between the pull-up node PU and the first pull-down node PD1 / second pull-down node PD2.

[0335] In some examples, continuing to refer to FIG. 27, the shift register of the embodiment of the present disclosure further includes a global reset sub-circuit 6, which is configured to respond to a global reset signal and globally reset the output of the pull-up node PU and the signal output terminal G(N) by a low-level signal.

[0336] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal STV0. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal STV0.

[0337] Specifically, in the global reset phase, the global reset signal written by the global reset signal terminal STV0 is a high-level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on, and at this time, the low-level signal written by the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output terminal G(N) through the seventh transistor M7.

[0338] In some examples, continuing to refer to FIG. 19, the shift register further includes two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits reduces the output of the pull-up node PU by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the pull-up node PU by the low-level signal in response to the potential of the second pull-down node PD2. One of the two second noise reduction sub-circuits reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the second pull-down node PD2.

[0339] In some examples, continuing to refer to FIG. 19, the shift register further includes two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits reduces the output of the pull-up node PU by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the pull-up node PU by the low-level signal in response to the potential of the second pull-down node PD2. One of the two second noise reduction sub-circuits reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the first pull-down node PD1, and the other reduces the output of the signal output terminal G(N) by the low-level signal in response to the potential of the second pull-down node PD2.

[0340] Specifically, in the output noise reduction phase, when the potential of the first pull-down node PD1 is high, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is high, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL.

[0341] In some examples, the first input sub-circuit 11 includes a first transistor M1, and the second input sub-circuit 12 includes a second transistor M2. The source and gate of M1 are connected to the first input signal terminal, the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal.

[0342] Specifically, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is opened, and at this time, the pull-up node PU is pre-charged by the high-level signal. In the pull-up reset stage, the pull-up reset signal written into the pull-up reset signal terminal is a high-level signal, M2 is opened, and at this time, the pull-up node PU is discharged by the low-level signal, so as to realize the reset of the pull-up node PU.

[0343] In some examples, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0344] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, the clock signal written into the clock signal terminal CLK is a high-level signal, and at this time, the signal output terminal G(N) outputs a high-level signal.

[0345] In some examples, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 each include a fifth transistor and a ninth transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are denoted as M5A and M9A respectively, and the fifth transistor and the ninth transistor in the second pull-down control sub-circuit 42 are denoted as M5B and M9B respectively. The source of M5A is connected to the first power voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and the gate of M9A are connected to the second power voltage terminal VDDE. The source of M5B is connected to the second power voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and the gate of M9B are connected to the second power voltage terminal VDDE.

[0346] Specifically, when the first power voltage is written into the first power voltage terminal VDDO, M5A and M9A are both opened, the potential of the first pull-down node PD1 is pulled high by the first power voltage, that is, at a high potential. When the second power voltage is written into the second power voltage terminal VDDE, M5B and M9B are both opened, the potential of the second pull-down node PD2 is pulled high by the second power voltage, that is, at a high potential. It should be noted that the first power voltage and the second power voltage can be the same power voltage. In the embodiments of the present disclosure, only the case where the first power voltage and the second power voltage are the same power voltage is described as an example.

[0347] In some examples, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are denoted as M6A and M8A respectively, and the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are denoted as M6B and M8B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0348] Specifically, when the potential of the pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high to output normally.

[0349] The twenty-sixth example is a shift register circuit as shown in FIG. 28. The structure of the shift register of this example is substantially the same as that of the twenty-fifth example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the twenty-fifth example.

[0350] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, and for ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are denoted as M5A and M5B respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0351] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 has the potential of the first power supply voltage, i.e. high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 has the potential of the second power supply voltage, i.e. high potential.

[0352] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0353] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0354] The other structures of the shift register in this example can be the same as those in the twenty-fifth example, and thus will not be repeated here.

[0355] The twenty-seventh example: FIG. 29 is a circuit diagram of a shift register in the twenty-seventh example of the embodiments of the present disclosure; as shown in FIG. 21, the structure of the shift register in this example is substantially the same as that in the twenty-fifth example, and the only difference is that the shift register in this example adds a cascading sub-circuit 111 to the shift register in the twenty-fifth example, and the cascading output sub-circuit 3 is configured to output the clock signal through the cascading signal terminal in response to the potential of the pull-up node PU.

[0356] In some examples, the cascading sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascading signal terminal output_C(N), and the gate of M13 is connected to the pull-up node PU.

[0357] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage, and at this time the cascading signal terminal output_C(N) outputs a high-level signal.

[0358] When the shift register in the embodiments of the present disclosure is applied to a gate driving circuit, in addition to the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascading signal terminal output_C(N-1) of the (N-1)th stage shift register; in addition to the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascading signal terminal output_C(N+1) of the (N+1)th stage shift register. N≥2, and N is an integer.

[0359] In some examples, continuing to refer to FIG. 21, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the first pull-down node PD1, and the other of which is configured to pull down the output of the cascade signal end by a low-level signal in response to the potential of the second pull-down node PD2.

[0360] Continuing to refer to FIG. 21, both of the third noise reduction sub-circuits can include twelfth transistors, denoted as M12A and M12B respectively. The source of M12A is connected to the cascade signal end, the drain of M12A is connected to the low-level signal end VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal end, the drain of M12B is connected to the low-level signal end VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0361] Specifically, in the output noise reduction phase, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal end VGL is pulled down to the output of the cascade signal end through M12B.

[0362] Continuing to refer to FIG. 29, the shift register in this example can further include a first discharge sub-circuit 101 and a second discharge sub-circuit 102. The first discharge sub-circuit 101 is configured to discharge the first pull-down node PD1 by a low-level signal in response to the first input signal. The second discharge sub-circuit 102 is configured to discharge the second pull-down node PD2 by a low-level signal in response to the first input signal.

[0363] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 works to pre-charge the pull-up node PU, at which time the first discharge sub-circuit 101 discharges the first pull-down node PD1 and the second discharge sub-circuit 102 discharges the second pull-down node PD2, thereby avoiding competition between the potentials of the first pull-down node PD1, the second pull-down node PD2, and the pull-up node PU.

[0364] The first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 can each include a sixteenth transistor. For ease of description, the sixteenth transistor in the first pull-down sub-circuit 51 is denoted as M16A, and the sixteenth transistor in the second pull-down sub-circuit 52 is denoted as M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0365] In the input stage, the first input signal written into the first input signal terminal is a high-level signal, and M16A and M16B are both turned on, so that the low-level signal written in through the low-level signal terminal VGL pulls down the potentials of the first pull-down node PD1 and the second pull-down node PD2.

[0366] The other structures of the shift register in this example can be the same as those in the twenty-fifth example, and thus are not repeated here.

[0367] The twenty-eighth example: FIG. 30 is a circuit diagram of a shift register of the twenty-eighth example of the embodiments of the present disclosure. As shown in FIG. 30, the structure of the shift register of this example is substantially the same as that of the twenty-seventh example, and the only difference is that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51, and the second pull-down sub-circuit 52 are different from those of the twenty-seventh example.

[0368] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistor in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 is denoted as M5A and M5B, respectively. The gate and the source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0369] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0370] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for ease of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0371] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0372] The other structures of the shift register in this example can be the same as those in the twenty-seventh example, and thus will not be repeated here.

[0373] The twenty-ninth example: FIG. 31 is a circuit diagram of a shift register of the twenty-ninth example of the embodiments of the present disclosure; as shown in FIG. 31, the structure of the shift register of this example is substantially the same as that of the twenty-fifth example, and the only difference is that the shift register can realize bidirectional scanning. The first input sub-circuit 11 and the pull-up reset sub-circuit 2 in this example are different from those in the seventeenth example. In this example, since the shift register can realize bidirectional scanning, in forward scanning, the first input sub-circuit 11 is used for pre-charging the pull-up node PU, and the pull-up reset sub-circuit 2 is used for resetting the pull-up node PU; in reverse scanning, the first input sub-circuit 11 is used for resetting the pull-up node PU, and the pull-up reset sub-circuit 2 is used for pre-charging the pull-up node PU. Therefore, for ease of understanding, the first input sub-circuit 11 in the above example is still called the first input sub-circuit 11, and the pull-up reset sub-circuit 2 is called the second input sub-circuit 12. Since the first input sub-circuit 11 and the second input sub-circuit 12 are the main elements for supporting the shift register to realize bidirectional scanning, the connection relationship between the first input sub-circuit 11 and the second input sub-circuit 12 is different from that between the first input sub-circuit 11 and the pull-up reset sub-circuit 2.

[0374] Continuing to refer to FIG. 31, specifically, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU through the first scan signal in response to the first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU through the second scan signal in response to the second input signal.

[0375] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal end VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input end. The source of M2 is connected to the second scan signal end VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input end.

[0376] Specifically, when forward scanning, in the input stage, the first input signal written into the first signal input end is a high-level signal, M1 is turned on, the first scan signal written into the first scan signal end VDS is a high-level signal, and the pull-up node PU is pre-charged through the first scan signal at this time. In the pull-up reset stage, the second input signal written into the second signal input end is a high-level signal, M2 is turned on, the second scan signal written into the second scan signal end VSD is a low-level signal, and the pull-up node PU is discharged through the second scan signal at this time, so as to realize the reset of the pull-up node PU.

[0377] When reverse scanning, in the input stage, the second input signal written into the second signal input end is a high-level signal, M2 is turned on, the second scan signal written into the second scan signal end VSD is a high-level signal, and the pull-up node PU is pre-charged through the second scan signal at this time. In the pull-up reset stage, the first input signal written into the first signal input end is a high-level signal, M1 is turned on, the first scan signal written into the first scan signal end VDS is a low-level signal, and the pull-up node PU is discharged through the first scan signal at this time, so as to realize the reset of the pull-up node PU.

[0378] The other structures of the shift register in this example can be the same as those in the twenty-fifth example, and thus will not be repeated here.

[0379] The thirtieth example: FIG. 32 is a circuit diagram of a shift register of the thirtieth example of the embodiment of the present disclosure; as shown in FIG. 32, the structure of the shift register of this example is substantially the same as that of the thirtieth example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51, and the second pull-down sub-circuit 52 are different from those in the twenty-ninth example.

[0380] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include fifth transistors, which are denoted as M5A and M5B respectively for ease of description. The gate and the source of M5A are connected to the first power voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and the source of M5B are connected to the second power voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0381] When the first power voltage terminal VDDO is written with the first power voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power voltage, i.e., high potential. When the second power voltage terminal VDDE is written with the second power voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power voltage, i.e., high potential.

[0382] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, which is denoted as M6A and M6B respectively for ease of description. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0383] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high to output normally.

[0384] The other structures of the shift register in this example can be the same as those in the twenty-ninth example, and thus will not be repeated here.

[0385] The thirty-first example: FIG. 33 is a circuit diagram of a shift register of the thirty-first example of the embodiments of the present disclosure. As shown in FIG. 33, the structure of the shift register of this example is substantially the same as that of the fourteenth example, and the only difference is that the shift register of this example adds a cascaded sub-circuit 111 to the shift register of the thirtieth example, and the cascaded output sub-circuit 3 is configured to output the clock signal through the cascaded signal terminal in response to the potential of the pull-up node PU.

[0386] In some examples, the cascaded sub-circuit 111 includes a thirteenth transistor M13, the source of M13 is connected to the clock signal terminal CLK, the drain of M13 is connected to the cascaded signal terminal output_C(N), and the gate of M13 is connected to the pull-up node PU.

[0387] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal end CLK is a high-level signal in this stage, at this time, the cascade signal end output_C(N) outputs a high-level signal.

[0388] When the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, the first input signal end of the Nth shift register is connected to the cascade signal end output_C(N-1) of the (N-1)th shift register, and the second input signal end of the Nth shift register is connected to the cascade signal end output_C(N+1) of the (N+1)th shift register, N≥2, and N is an integer.

[0389] In some examples, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal end through a low-level signal in response to the potential of the first pull-down node PD1, and the other of which is configured to pull down the output of the cascade signal end through a low-level signal in response to the potential of the second pull-down node PD2.

[0390] Specifically, with continued reference to FIG. 33, both of the third noise reduction sub-circuits can include twelfth transistors, denoted as M12A and M12B respectively. The source of M12A is connected to the cascade signal end, the drain of M12A is connected to the low-level signal end VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal end, the drain of M12B is connected to the low-level signal end VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0391] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is opened, and the low-level signal written by the low-level signal end VGL is pulled down through M12A to pull down the output of the cascade signal end. When the second pull-down node PD2 is a high-level signal, M12B is opened, and the low-level signal written by the low-level signal end VGL is pulled down through M12B to pull down the output of the cascade signal end.

[0392] The other structures of the shift register in this example can be the same as those in the thirtieth example, and thus are not repeated here.

[0393] The thirty-second example: Fig. 34 is a circuit diagram of a shift register of the thirty-second example of the embodiment of the present disclosure; as shown in Fig. 34, the structure of the shift register of this example is substantially the same as that of the thirty-first example, the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the thirty-first example.

[0394] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, for the convenience of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are denoted as M5A and M5B respectively. The gate and source of M5A are connected to the first power voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0395] Wherein, when the first power voltage terminal VDDO is written with the first power voltage, M5A is open, and the first pull-down node PD1 is at the potential of the first power voltage, that is, high potential. When the second power voltage terminal VDDE is written with the second power voltage, M5B is open, and the second pull-down node PD2 is at the potential of the second power voltage, that is, high potential.

[0396] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, for the convenience of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are denoted as M6A and M6B respectively. Wherein, the source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0397] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is open, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0398] The other structures of the shift register in this example can be the same as those in the thirty-first example, and therefore will not be repeated here.

[0399] It is understood that the above embodiments are only exemplary for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. A shift register comprising: The first input sub-circuit, the output sub-circuit, the first pull-down control sub-circuit, the second pull-down control sub-circuit, the first pull-down sub-circuit and the second pull-down sub-circuit; The first input sub-circuit is configured to pre-charge the pull-up node by the first scan signal in response to the first input signal; The output sub-circuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node; The first pull-down control sub-circuit is configured to control the potential of the first pull-down node by the first power voltage in response to the first power voltage; The second pull-down control sub-circuit is configured to control the potential of the second pull-down node by the second power voltage in response to the second power voltage; The first pull-down sub-circuit is configured to pull down the first pull-down node in response to the potential of the pull-up node; The second pull-down sub-circuit is configured to pull down the second pull-down node in response to the potential of the pull-up node; wherein The shift register further comprises a first auxiliary sub-circuit and a second auxiliary sub-circuit; The first auxiliary sub-circuit is configured to pull down the potential of the first pull-down node to the non-working voltage level signal when the second power voltage is the working voltage level signal; The second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node to the non-working voltage level signal when the first power voltage is the working voltage level signal.

2. The shift register of claim 1, wherein, The shift register further comprises a global reset sub-circuit configured to globally reset the pull-up node and the output of the signal output terminal by the non-working voltage level signal in response to a global reset signal.

3. The shift register of claim 2, wherein, The first auxiliary sub-circuit is specifically configured to pull down the non-working voltage level signal by the first power voltage when the second power voltage is the working voltage level signal in response to the global reset signal; The second auxiliary sub-circuit is specifically configured to pull down the potential of the second pull-down node to the non-working voltage level signal by the second power voltage when the first power voltage is the working voltage level signal in response to the global reset signal.

4. The shift register of claim 3, wherein, The first auxiliary sub-circuit and the second auxiliary sub-circuit each comprise a seventeenth transistor; The first pole of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power voltage terminal, the second pole is connected to the first pull-down node, and the control pole is connected to the global reset signal terminal; The first pole of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second power voltage terminal, the second pole is connected to the second pull-down node, and the control pole is connected to the global reset signal terminal.

5. The shift register of claim 2, wherein, The global reset sub-circuit comprises a fourth transistor and a seventh transistor; The first pole of the fourth transistor is connected to the pull-up node, the second pole is connected to the non-working voltage level signal terminal, and the control pole is connected to the global reset signal terminal; The first pole of the seventh transistor is connected to the signal output terminal, the second pole is connected to the non-working voltage level signal terminal, and the control pole is connected to the global reset signal terminal.

6. The shift register of claim 1, wherein, The first auxiliary sub-circuit is specifically configured to pull down the first pull-down node to the non-working voltage by the first power voltage in response to the frame start signal when the second power voltage is the working voltage level signal. The second auxiliary sub-circuit is specifically configured to, when the first supply voltage is a working level signal, pull down the second pull-down node to a non-working voltage through the second supply voltage in response to a frame start signal.

7. The shift register of claim 6, wherein, The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor. The first pole of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first supply voltage terminal, the second pole is connected to the first pull-down node, and the control pole is connected to the frame start signal terminal. The first pole of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second supply voltage terminal, the second pole is connected to the second pull-down node, and the control pole is connected to the frame start signal terminal.

8. The shift register of claim 1, wherein, The first auxiliary sub-circuit is specifically configured to, when the second supply voltage is a working level signal, pull down the first pull-down node through a non-working level signal in response to the second supply voltage. The second auxiliary sub-circuit is specifically configured to, when the first supply voltage is a working level signal, pull down the second pull-down node through a non-working level signal in response to the first supply voltage.

9. The shift register of claim 8, wherein, The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor. The first pole of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first pull-down node, the second pole is connected to a non-working level signal terminal, and the control pole is connected to the second supply voltage terminal. The first pole of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second pull-down node, the second pole is connected to a non-working level signal terminal, and the control pole is connected to the first pull-down node.

10. The shift register of claim 1, wherein, The first auxiliary sub-circuit is specifically configured to, when the second supply voltage is a working level signal, pull down the first pull-down node through a non-working level signal in response to the potential of the second pull-down node. The second auxiliary sub-circuit is specifically configured to, when the first supply voltage is a working level signal, pull down the second pull-down node through a non-working level signal in response to the potential of the first pull-down node.

11. The shift register of claim 10, wherein, The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor. The first pole of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first pull-down node, the second pole is connected to a non-working level signal terminal, and the control pole is connected to the second pull-down node. The first pole of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second pull-down node, the second pole is connected to a non-working level signal terminal, and the control pole is connected to the first pull-down node.

12. The shift register of any one of claims 1-11, wherein, The pull-up reset sub-circuit is further configured to reset the output of the pull-up node through a non-working level signal in response to a pull-up reset signal.

13. The shift register of claim 12, wherein, The pull-up reset sub-circuit includes a second transistor, the first pole of the second transistor is connected to the pull-up node, the second pole is connected to a non-working level signal terminal, and the control pole is connected to a pull-up reset signal terminal.

14. The shift register of claim 12, wherein, The first input signal is multiplexed as the first scan signal; the first input sub-circuit includes a first transistor; The first pole and the control pole of the first transistor are connected to the first input signal terminal, and the second pole is connected to the pull-up node.

15. The shift register of any one of claims 1-11, wherein, The second input sub-circuit is further configured to pre-charge the pull-up node through a second scan signal in response to a second input signal.

16. The shift register of claim 15, wherein, The second input sub-circuit comprises a second transistor; The first electrode of the second transistor is connected to the pull-up node, the second electrode is connected to a second scan signal terminal, and the control electrode is connected to a second input signal terminal.

17. The shift register of claim 15, wherein, The first input sub-circuit comprises a first transistor; The first electrode of the first transistor is connected to a first scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to a first input signal terminal.

18. The shift register of any one of claims 1-11, wherein, Two first noise reduction sub-circuits and two second noise reduction sub-circuits are further included; One of the two first noise reduction sub-circuits is configured to reduce the output of the pull-up node by a non-working level signal in response to the potential of the first pull-down node, and the other is configured to reduce the output of the pull-up node by a non-working level signal in response to the potential of the second pull-down node; One of the two second noise reduction sub-circuits is configured to reduce the output of the signal output terminal by a non-working level signal in response to the potential of the first pull-down node, and the other is configured to reduce the output of the signal output terminal by a non-working level signal in response to the potential of the second pull-down node.

19. The shift register of claim 18, wherein, The two first noise reduction sub-circuits each comprise a tenth transistor; The first electrode of the tenth transistor in one of the first noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to a non-working voltage terminal, and the control electrode is connected to the first pull-down node; the first electrode of the tenth transistor in the other first noise reduction sub-circuit is connected to the pull-up node, the second electrode is connected to a non-working voltage terminal, and the control electrode is connected to the second pull-down node.

20. The shift register of claim 18, wherein, The two second noise reduction sub-circuits each comprise an eleventh transistor; The first electrode of the eleventh transistor in one of the second noise reduction sub-circuits is connected to the signal output terminal, the second electrode is connected to a non-working voltage terminal, and the control electrode is connected to the first pull-down node; the first electrode of the eleventh transistor in the other second noise reduction sub-circuit is connected to the pull-up node, the second electrode is connected to a non-working voltage terminal, and the control electrode is connected to the signal output terminal.

21. The shift register of any one of claims 1-11, wherein, A cascade sub-circuit is further included and is configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

22. The shift register of claim 21, wherein, The cascade sub-circuit comprises a thirteenth transistor; The first electrode of the thirteenth transistor is connected to a clock signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

23. The shift register of claim 21, wherein, Two third noise reduction sub-circuits are further included; One of the two third noise reduction sub-circuits is configured to reduce the output of the cascade signal terminal by a non-working level signal under the control of the first pull-down node; The other is configured to reduce the output of the cascade signal terminal by a non-working level signal under the control of the second pull-down node.

24. The shift register of any one of claims 1-11, wherein, The first pull-down control sub-circuit and the second pull-down control sub-circuit each comprise a fifth transistor and a ninth transistor; For the first pull-down control sub-circuit, the first electrode of the fifth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor, and a first power supply voltage terminal, and the second electrode is connected to the first pull-down node; For the second pull-down control sub-circuit, a first electrode of the fifth transistor is connected to a first electrode of the ninth transistor, a control electrode of the ninth transistor and a second power supply voltage terminal, and a second electrode is connected to the second pull-down node.

25. The shift register of claim 24, wherein, The first pull-down sub-circuit and the second pull-down sub-circuit both include a sixth transistor and an eighth transistor; For the first pull-down sub-circuit, a first electrode of the sixth transistor is connected to the first pull-down node, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the pull-up node; a first electrode of the eighth transistor is connected to a control electrode of the fifth transistor and a first electrode of the ninth transistor, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the pull-up node. For the second pull-down sub-circuit, a first electrode of the sixth transistor is connected to the second pull-down node, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the pull-up node; a first electrode of the eighth transistor is connected to a control electrode of the fifth transistor and a first electrode of the ninth transistor, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the pull-up node.

26. The shift register of any one of claims 1-11, wherein, The first pull-down control sub-circuit and the second pull-down control sub-circuit both include a fifth transistor; For the first pull-down control sub-circuit, a first electrode and a control electrode of the fifth transistor are connected to a first power supply voltage terminal, and a second electrode is connected to the first pull-down node; For the first pull-down control sub-circuit, a first electrode and a control electrode of the fifth transistor are connected to a second power supply voltage terminal, and a second electrode is connected to the second pull-down node.

27. The shift register of any one of claims 1-11, wherein, The first pull-down sub-circuit and the second pull-down sub-circuit both include a sixth transistor; A first electrode of the sixth transistor is connected to the first pull-down node, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the pull-up node; A first electrode of the sixth transistor is connected to the second pull-down node, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the pull-up node.

28. A gate drive circuit comprising a plurality of cascaded shift registers, the shift registers being the shift register of any one of claims 1-27.

29. A display device comprising the gate drive circuit of claim 28.

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