Multi-channel data acquisition and storage method for preventing channel string based on PXI (PCI eXtensions for Instrumentation) system

Abstract

The invention relates to a multi-channel data acquisition and storage method for preventing channel string based on a PXI (PCI eXtensions for Instrumentation) system. The method comprises the following steps: acquiring the channel number of data acquisition channels and the data bit width of each channel of the data acquisition channels; the storage module is only defined as a single storage chip, the reading and writing of the storage module are in a 1 bust Q mode, and the data bit width, the total address space and the one-time reading and writing address number of the storage module are set; the data bit width of each channel of the data acquisition channel is an integral multiple of the data bit width of the storage module; obtaining the channel number of data acquisition channels, the ratio of the data bit width of each channel of the data acquisition channels to the data bit width of the storage module, and the least common multiple of the one-time read-write address number; obtaining a remainder obtained by dividing the total address space by the least common multiple, and taking a difference value between the total address space and the remainder as a storage module end address; and when the terminal address of the storage module is read and written each time, turning back to the initial address of the storage module to form circular reading and writing. According to the invention, string data acquisition channel acquisition is avoided.

Description

Technical Field

[0001] This invention relates to the technical field of the testing industry, specifically to a multi-channel data acquisition and storage method based on a PXI system to prevent crosstalk. Background Technology

[0002] In the test and measurement industry, PXI systems sometimes need to monitor the collaborative processing capabilities of various devices within a system under test (SUT) at high data acquisition speeds to assess the long-term stability of the SUT. The status of these measured data are presented as analog signals such as voltage, current, temperature, and sound. Monitoring the status of each device within the SUT is accomplished by a multi-channel data acquisition system with multiple devices within the PXI system.

[0003] The multi-channel data acquisition system mainly consists of four parts: a data acquisition module, a storage module, a data upload module, a host computer, and a human-computer interaction display interface. The data flow direction is that the data acquired by the data acquisition module is stored by the storage module and then uploaded to the host computer through the data upload module. After the host computer parses, analyzes, and processes the data, it is displayed through the human-computer interaction interface.

[0004] In PXI systems, based on the current maximum operating speed of 80 MB / s for a single PCI device, theoretically, the data acquisition speed of a single device in multi-channel parallel or polling mode should be controlled within 80 MB / s to achieve stable transmission. However, in extreme high and low temperature, humidity environments, or when multiple devices share the PXI bus in a PXI system, the PXI bus transmission rate will decrease to varying degrees. Furthermore, during continuous acquisition, if individual devices do not process the multi-channel data storage method, the data storage module will experience a short period where the write rate exceeds the read rate after the PXI bus loses control. If the storage space of the storage module is full and the module flips to the starting address to continue writing, any unread data will be overwritten to varying degrees. Ultimately, the data allocated to each channel by the host computer after analysis and processing will be disordered, and the monitoring data waveforms displayed on the human-machine interface will also be chaotic. This will manifest as data strings with different frequencies and waveforms displayed on different channels.

[0005] The traditional approach involves framing each level of data acquired by the data acquisition module in a multi-channel acquisition process. This involves adding fixed frame flags to the beginning and end of the data before storing it in the data storage module, and then uploading it to the host computer. The host computer then parses the data based on the frame flags and displays it on the human-machine interface. Because of the added frame flags, the channel parsing data no longer produces errors, preventing cross-channel errors. However, adding frame flags increases the data bit width of the transmitted data, which to some extent occupies logical resources and space, and wastes PXI bus space.

[0006] Another approach is to divide the storage space of the storage module according to the size of the acquisition channel, and put the values ​​of different channels into the corresponding storage space. This will prevent channel crosstalk. However, when storing in this way, it is necessary to constantly switch between the storage space addresses of different channels, which will reduce the performance of the storage module. The system logic control is more complex and cumbersome, and the reliability of the entire system will also be reduced.

[0007] Another approach is to continuously select larger or more storage modules within the "long time" required by the testers to ensure no data loss during front-end acquisition and back-end transmission, thereby enabling correct and stable data transmission. However, this method means that the storage space of the storage modules restricts the data acquisition time, and the so-called "long time" acquisition becomes a "long time" limited point acquisition. Summary of the Invention

[0008] This invention aims to address the above-mentioned problems by proposing a multi-channel data acquisition and storage method based on a PXI system to prevent crosstalk.

[0009] The technical solution of this invention is as follows: A multi-channel data acquisition and storage method based on a PXI system with anti-interference channels is as follows: Obtain the number of data acquisition channels N and the data bit width M of each data acquisition channel; The storage module is defined as a single storage chip, with read and write operations in 1-brust-Q mode. The storage module has a data bit width W, a total address space P, and a number of read / write addresses Q. The data bit width M of each data acquisition channel is an integer multiple of the storage module's data bit width W. Obtain the number of data acquisition channels N, the ratio of the data bit width M of each data acquisition channel to the data bit width W of the storage module, and the least common multiple X of the number of read / write addresses Q at one time; obtain the remainder Y of the total address space P divided by the least common multiple X, and use the difference between the total address space P and the remainder Y as the end address R of the storage module; Each time the read / write operation reaches the last address R of the storage module, it flips back to the first address of the storage module, forming a loop read / write operation.

[0010] Furthermore, if the data bit width M of each data acquisition channel is not an integer multiple of the data bit width W of the storage module, then the highest bit is padded with 0. More preferably, the data bit width M of each data acquisition channel is equal to the data bit width W of the storage module.

[0011] The storage chip is a DDR chip; the data acquisition channel is an AD data acquisition module.

[0012] It also includes a host computer. Data stored in the storage module is read by the PCI data upload module and uploaded to the host computer. When reading data from the storage chip, the host computer reads the value of each data acquisition channel in turn, using the number of data acquisition channels N as a loop unit.

[0013] The technical effects of this invention are as follows: In the data acquisition process of this invention, if a data overlay problem occurs, it will be that each data acquisition channel overlays the data it acquires. Therefore, when the host computer sequentially and cyclically categorizes and parses the data according to the N data acquisition channels, there will be no data from the data acquisition channels being overwritten. In this way, if the front-end sampling is error-free, the PXI system can be compatible with multiple devices and multiple channels with different frequencies and amplitudes, and various waveform data can be truly monitored and displayed for a long time.

[0014] This invention is not limited by the monitoring time or the storage capacity of the memory chip, does not affect the performance of the DDR memory chip, does not increase the unnecessary resource consumption of the data acquisition system, improves the stability of the test system, and can provide long-term and stable system stability monitoring for the system under test in a PXI system with a maximum acquisition speed of 80M / B. Detailed Implementation

[0015] Example 1 A multi-channel data acquisition and storage method based on a PXI system with anti-interference channels is as follows: Obtain the number of data acquisition channels N and the data bit width M of each data acquisition channel; The storage module is defined as a single storage chip, with read and write operations in 1-brust-Q mode. The storage module has a data bit width W, a total address space P, and a number of read / write addresses Q. The data bit width M of each data acquisition channel is an integer multiple of the storage module's data bit width W. Obtain the number of data acquisition channels N, the ratio of the data bit width M of each data acquisition channel to the data bit width W of the storage module, and the least common multiple X of the number of read / write addresses Q at one time; obtain the remainder Y of the total address space P divided by the least common multiple X, and use the difference between the total address space P and the remainder Y as the end address R of the storage module; Each time the read / write operation reaches the last address R of the storage module, it flips back to the first address of the storage module, forming a loop read / write operation.

[0016] Example 2 Based on Embodiment 1, the method further includes: if the data bit width M of each data acquisition channel is not an integer multiple of the data bit width W of the storage module, then the highest bit is padded with 0. More preferably, the data bit width M of each data acquisition channel is equal to the data bit width W of the storage module.

[0017] Example 3 Based on Embodiment 2, the method further includes, wherein the storage chip is a DDR chip; and the data acquisition channel is an AD data acquisition module. It also includes a host computer, to which data stored in the storage module is read and uploaded after being processed by the PCI data upload module.

[0018] Specific experimental cases A multi-channel data acquisition and storage method based on a PXI system with anti-interference channels is as follows: The data acquisition channel is an AD data acquisition module with 62 channels N and a data bit width M of 16 bits for each channel. The storage module is a single DDR chip with a storage space of 1 Gbit and a data bit width W of 16 bits. That is, one address of the DDR chip stores the data bit width of one sampling point of the data acquisition channel, and the total address space P is 67,108,864.

[0019] Considering that frequent switching of read and write instructions will affect the read and write efficiency of the DDR chip, the read and write of the DDR chip is set to a 1-brust-8 mode according to specific needs, that is, the number of addresses Q read and written at one time is 8, and the data read and written is 128 bits.

[0020] Under the above conditions, first find the least common multiple X of the number of data acquisition channels (62) and the number of one-time read / write addresses (8), which is 248. Then find the remainder w of the total address space (67108864) divided by the least common multiple 248, which is 64 (67108864 / 248=270600……64). Use the difference between the total address space P and the remainder Y, which is 67108800 (67108864-64=67108800), as the end address R of the storage module. 67108800 is an integer multiple of the number of channels (62) and the number of read / write addresses of the storage module at one time (8). When data is written from the first address of the storage module, the data of the first data acquisition channel is written, then the data of the second data acquisition channel is written, and so on until the 62nd data acquisition channel is written. Then it starts from the first data acquisition channel again, and so on, until the end address of the storage module (67108800) is reached. Then it flips back to the first address of the storage module and starts reading and writing data from the first data acquisition channel again. If read / write overwrite occurs, the new data of the current data acquisition channel will overwrite the old data, and it will not affect the frequency and amplitude of the original waveform acquired by the data acquisition channel.

[0021] After this batch of data is read from the DDR chip and uploaded to the host computer via the PCI data upload module, the host computer extracts the values ​​of each data acquisition channel in 62 16-bit intervals, and then displays the waveform diagram of the data conversion of each data acquisition channel through the human-machine interface.

Claims

1. A multi-channel data acquisition and storage method based on a PXI system with anti-interference capabilities, characterized in that, The method is as follows: Obtain the number of data acquisition channels N and the data bit width M of each data acquisition channel; The storage module is defined as a single storage chip, with read and write operations in 1-brust-Q mode. The storage module has a data bit width W, a total address space P, and a number of read / write addresses Q. The data bit width M of each data acquisition channel is an integer multiple of the storage module's data bit width W. Obtain the number of data acquisition channels N, the ratio of the data bit width M of each data acquisition channel to the data bit width W of the storage module, and the least common multiple X of the number of read / write addresses Q at one time; The remainder Y obtained by dividing the total address space P by the least common multiple X is used as the end address R of the storage module. Each time the read / write operation reaches the last address R of the storage module, it flips back to the first address of the storage module, forming a loop read / write operation.

2. The multi-channel data acquisition and storage method based on a PXI system for preventing crosstalk as described in claim 1, characterized in that, If the data bit width M of each data acquisition channel is not an integer multiple of the data bit width W of the storage module, then the highest bit is padded with 0.

3. The multi-channel data acquisition and storage method based on a PXI system for preventing crosstalk as described in claim 2, characterized in that, The data bit width M of each data acquisition channel is equal to the data bit width W of the storage module.

4. The multi-channel data acquisition and storage method based on a PXI system for preventing crosstalk as described in claim 1, characterized in that, The memory chip is a DDR chip.

5. The multi-channel data acquisition and storage method based on a PXI system for preventing crosstalk as described in claim 1, characterized in that, The data acquisition channel is an AD data acquisition module.

6. The multi-channel data acquisition and storage method based on a PXI system for preventing crosstalk as described in claim 1, characterized in that, It also includes a host computer. The data stored in the storage module is read by the PCI data upload module and then uploaded to the host computer.

7. The multi-channel data acquisition and storage method based on a PXI system for preventing crosstalk as described in claim 6, characterized in that, When the host computer reads data from the storage chip, it reads the value of each data acquisition channel in turn, using the number of data acquisition channels N as the loop unit.