A current limiting protection circuit and a CAN bus transceiver

Abstract

The application relates to the field of CAN bus transceivers, in particular to a current-limiting protection circuit and a CAN bus transceiver, which comprises a high-voltage side current-limiting protection unit, a low-voltage side current-limiting protection unit and a driving unit; the high-voltage side current-limiting protection unit, the low-voltage side current-limiting protection unit and the driving unit are electrically connected with an external power supply VCC; the driving unit comprises a driving component, an enabling switch component and a current mirror component, the high-voltage side current-limiting protection unit and the low-voltage side current-limiting protection unit pull up the driving signal PDRIVER and the driving signal NDRIVER voltage when triggering the short-circuit current-limiting protection, limit the fault current, avoid relying on thermal shutdown, and through a common-gate amplifier, the CL or Rload can be reduced to obtain extremely high bandwidth and faster system response. Symmetrical high-voltage side current-limiting protection and low-voltage side current-limiting protection are arranged to ensure the consistency of the protection capability of CANH to ground short circuit and CANL to high-voltage short circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of CAN bus transceiver, in particular to a current limiting protection circuit and CAN bus transceiver. BACKGROUND

[0002] CAN bus transceiver is a key device in CAN (Controller Area Network) bus communication system, which serves as an interface between controller and physical bus, responsible for converting the logic level signal output by the controller into differential signal conforming to CAN protocol specification, and restoring the differential signal transmitted on the bus into logic level for the controller to process. Its core function is to realize the level conversion and electrical isolation of signal, ensuring the reliability and anti-interference ability of communication. In CAN network, transceiver usually adopts differential transmission mode, transmitting complementary voltage signals through two signal lines (CAN_H and CAN_L), which can effectively suppress common mode noise and improve the anti-electromagnetic interference ability, especially suitable for strong interference environment such as industrial automation and automotive electronics.

[0003] However, the current limiting protection mechanism of the existing CAN bus transceiver is based on the current limiting protection circuit of traditional voltage comparator, which requires stable reference voltage source, high gain amplifier and comparator, increasing the response delay, complexity of chip design and static power consumption, and relying on the slow response speed of thermal shutdown protection, which cannot prevent instantaneous overshoot. SUMMARY

[0004] The purpose of the present application is to provide a current limiting protection circuit and CAN bus transceiver, aiming at improving the slow protection response of conventional current limiting protection circuit and CAN bus transceiver, and relying on thermal shutdown and other problems.

[0005] To achieve the above purpose, the present application adopts the following technical scheme:

[0006] A current limiting protection circuit, comprising a high-voltage side current limiting protection unit, a low-voltage side current limiting protection unit and a driving unit; the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit and the driving unit are electrically connected with an external power supply VCC; the driving unit comprises a driving component, an enable switch component and a current mirror component;

[0007] The signal TXDP and the signal TXDN are input to the driving component, the signal STBP and the signal STBN are input to the enable switch component, the signal input end of the high-voltage side current limiting protection unit collects the current sensing signal PBACK of the high-voltage side, and the signal input end of the low-voltage side current limiting protection unit collects the current sensing signal NBACK of the low-voltage side; the output ends of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit are electrically connected with the driving component;

[0008] The enable switch assembly is electrically connected with the control end of the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit, the current mirror assembly and the driving assembly; the first output end of the current mirror assembly is electrically connected with the control end of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit, the second output end and the third output end of the current mirror assembly are both electrically connected with the output end of the driving assembly, and the output end of the driving assembly outputs a driving signal PDRIVER and a driving signal NDRIVER.

[0009] Further, the high-voltage side current limiting protection unit comprises MOS tubes P4, P5, P6, P7, N4, N5, N6, N7 and a resistor R4.

[0010] The source of the MOS tube P6, the source of the MOS tube P7 and one end of the resistor R4 are all electrically connected with an external power supply VCC; the source of the MOS tube P4 collects a high-voltage side current sensing signal PBACK; the gate of the MOS tube P6 is electrically connected with the first output end of the current mirror assembly.

[0011] The other end of the resistor R4 is electrically connected with the source of the MOS tube P5 and the low-voltage side current limiting protection unit, the gate and the drain of the MOS tube P5 are both electrically connected with the gate of the MOS tube P4 and the drain of the MOS tube N5, the drain of the MOS tube P4 is electrically connected with the drain of the MOS tube N4 and serves as an output end and is electrically connected with the driving assembly; the gate of the MOS tube N4 is electrically connected with the gate of the MOS tube N5, the drain of the MOS tube P6, the gate and the drain of the MOS tube N6 and the gate of the MOS tube N7, and is electrically connected with the enable switch assembly; the gate and the drain of the MOS tube P7 are both electrically connected with the drain of the MOS tube N7, and are electrically connected with the enable switch assembly and the low-voltage side current limiting protection unit.

[0012] The source of the MOS tube N4, the source of the MOS tube N5, the source of the MOS tube N6 and the source of the MOS tube N7 are all grounded.

[0013] Further, the low-voltage side current limiting protection unit comprises MOS tubes P8, P9, P10, P11, P14, N8, N9, N11, N12, N13 and a resistor R5.

[0014] The source of the MOS tube P8, the source of the MOS tube P9, the source of the MOS tube P10, the source of the MOS tube P11 and the source of the MOS tube P14 are electrically connected with an external power supply VCC; the source of the MOS tube N8 collects the low-voltage side current sensing signal NBACK; the gate of the MOS tube P14 is electrically connected with the first output end of the current mirror component;

[0015] The gate of the MOS tube P8 is electrically connected with the gate of the MOS tube P9 and the gate of the MOS tube P7, and is electrically connected with the enable switch component; the drain of the MOS tube P8 is electrically connected with the drain of the MOS tube N8, and is electrically connected with the driving component as an output end; the gate of the MOS tube N8 is electrically connected with the gate of the MOS tube N9 and the drain of the MOS tube P9; the source of the MOS tube N9 is electrically connected with one end of the resistor R5 and the drain of the MOS tube P10; the gate of the MOS tube P10 is electrically connected with the gate of the MOS tube P11 and the drain of the MOS tube N11, and is electrically connected with the enable switch component;

[0016] The drain of the MOS tube P14 is electrically connected with the gate of the MOS tube N13, the drain of the MOS tube N12 and the gate of the MOS tube N11, and is electrically connected with the enable switch component; the drain of the MOS tube N12 is electrically connected with the other end of the resistor R4;

[0017] The source of the MOS tube N11, the source of the MOS tube N12, the source of the MOS tube N13 and the other end of the resistor R5 are grounded.

[0018] Further, the following conditional expressions are satisfied,

[0019] (W / L) P4 = (W / L) P5 = (W / L) P6 = (W / L) P7 = (W / L) P8 = (W / L) P9 ;

[0020] (W / L) N4 = (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L) N8 = (W / L) N9 ;

[0021] Wherein, (W / L) P4 is the width-length ratio of the MOS tube P4, (W / L) P5 is the width-length ratio of the MOS tube P5, (W / L) P6width-length ratio of MOS transistor P6, (W / L) P7 width-length ratio of MOS transistor P7, (W / L) P8 width-length ratio of MOS transistor P8, (W / L) P9 width-length ratio of MOS transistor P9, (W / L) N4 width-length ratio of MOS transistor N4, (W / L) N5 width-length ratio of MOS transistor N5, (W / L) N6 width-length ratio of MOS transistor N6, (W / L) N7 width-length ratio of MOS transistor N7, (W / L) N8 width-length ratio of MOS transistor N8, (W / L) N9 width-length ratio of MOS transistor N9.

[0022] Further, the driving unit comprises MOS transistor P21, MOS transistor P22, MOS transistor P23 and MOS transistor N23, MOS transistor N25, MOS transistor N26;

[0023] The source of the MOS transistor P21, the source of the MOS transistor P22 and the source of the MOS transistor P23 are electrically connected with the external power supply VCC; the output end of the high-voltage side current-limiting protection unit is electrically connected with the gate of the MOS transistor P21, and the output end of the low-voltage side current-limiting protection unit is electrically connected with the gate of the MOS transistor N25; the signal TXDP is input to the gate of the MOS transistor P22, and the signal TXDN is input to the gate of the MOS transistor N26; the drain of the MOS transistor P23 is electrically connected with the drain of the MOS transistor N23, and is electrically connected with the enable switch assembly;

[0024] The drain of the MOS transistor P21 is electrically connected with the drain of the MOS transistor P22, the gate of the MOS transistor P23, the second output end of the current mirror assembly and the enable switch assembly, and outputs the driving signal PDRIVER as an output end; the drain of the MOS transistor N25 is electrically connected with the drain of the MOS transistor N26, the gate of the MOS transistor N23, the third output end of the current mirror assembly and the enable switch assembly, and outputs the driving signal NDRIVER as an output end;

[0025] The source of the MOS transistor N23, the source of the MOS transistor N25 and the source of the MOS transistor N26 are grounded.

[0026] Further, the enable switch assembly comprises MOS transistor P12, MOS transistor P13, MOS transistor P24, MOS transistor P25, MOS transistor P26, MOS transistor P27, MOS transistor N10, MOS transistor N15, MOS transistor N20, MOS transistor N21, MOS transistor N22 and transmission gate TG1, transmission gate TG2;

[0027] The signal STBP is input to the gate of MOS tube P12, the gate of MOS tube P13, the gate of MOS tube P24, the gate of MOS tube P25, the gate of MOS tube P26, the gate of MOS tube P27, and pin 1 of transmission gate TG1 and pin 1 of transmission gate TG2; the signal STBN is input to the gate of MOS tube N10, the gate of MOS tube N15, the gate of MOS tube N20, the gate of MOS tube N21, the gate of MOS tube N22, and pin 2 of transmission gate TG2 and pin 2 of transmission gate TG1; the source of MOS tube P12, the source of MOS tube P13, the source of MOS tube P24, the source of MOS tube P25, the source of MOS tube P26, and the source of MOS tube P27 are all electrically connected to external power supply VCC;

[0028] The drain of MOS tube P12 is electrically connected to the control end of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit, the drain of MOS tube P13 and the drain of MOS tube N15 are both electrically connected to the control end of the low-voltage side current limiting protection unit, and the drain of MOS tube N10 is electrically connected to the control end of the high-voltage side current limiting protection unit;

[0029] The drain of MOS tube P24, the drain of MOS tube P25, the drain of MOS tube P26, the drain of MOS tube N20, and the drain of MOS tube N21 are all electrically connected to the control end of the current mirror assembly; the drain of MOS tube P27 and pin 3 of transmission gate TG1 are both electrically connected to the gate of MOS tube P23, the drain of MOS tube N22 and pin 4 of transmission gate TG2 are both electrically connected to the gate of MOS tube N23, and pin 4 of transmission gate TG1 and pin 3 of transmission gate TG2 are both electrically connected to the drain of MOS tube P23 and the drain of MOS tube N23;

[0030] The source of MOS tube N10, the source of MOS tube N15, the source of MOS tube N20, the source of MOS tube N21, and the source of MOS tube N22 are all grounded.

[0031] Further, the current mirror assembly includes MOS tube P15, MOS tube P16, MOS tube P17, MOS tube P18, MOS tube P19, MOS tube P20, and MOS tube N14, MOS tube N16, MOS tube N17, MOS tube N18, MOS tube N19, and MOS tube N24;

[0032] The source of MOS tube P15, the source of MOS tube P16, the source of MOS tube P17, the source of MOS tube P18, the source of MOS tube P19, and the source of MOS tube P20 are all electrically connected to external power supply VCC;

[0033] The gate and the drain of the MOS tube P15 are electrically connected with the gate of the MOS tube P16, the drain of the MOS tube N14 and the drain of the MOS tube P24, and are electrically connected with the control end of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit as a first output end; an external constant bias voltage VB2 is input to the gate of the MOS tube N14; the drain of the MOS tube P16 is electrically connected with the gate of the MOS tube N16, the drain of the MOS tube N16, the gate of the MOS tube N17 and the drain of the MOS tube N20; the drain of the MOS tube N17 is electrically connected with the gate of the MOS tube P17, the drain of the MOS tube P17, the gate of the MOS tube P18 and the drain of the MOS tube P25; the drain of the MOS tube P18 is electrically connected with the gate of the MOS tube N18, the drain of the MOS tube N18, the gate of the MOS tube N19, the gate of the MOS tube N24 and the drain of the MOS tube N21; the drain of the MOS tube N19 is electrically connected with the gate of the MOS tube P19, the drain of the MOS tube P19, the gate of the MOS tube P20 and the drain of the MOS tube P26; the drain of the MOS tube P20 and the drain of the MOS tube N24 are respectively electrically connected with the drain of the MOS tube N25 and the drain of the MOS tube P21 as a third output end and a second output end;

[0034] The source of the MOS tube N14, the source of the MOS tube N16, the source of the MOS tube N17, the source of the MOS tube N18, the source of the MOS tube N19 and the source of the MOS tube N24 are grounded.

[0035] To achieve the above object, the application also adopts the following technical scheme:

[0036] A CAN bus transceiver comprising the current limiting protection circuit and a signal receiving module output module;

[0037] An external input signal TXD and an enable signal STB are input to a signal receiving module, and the signal receiving module outputs a signal TXDP and a signal TXDN to a driving component, and outputs a signal STBP and a signal STBN to an enable switch component; the output end of the driving component outputs a driving signal PDRIVER and a driving signal NDRIVER to an output module, and the output module outputs a signal CANH and a signal CANL.

[0038] Further, the signal receiving module comprises a MOS tube P2, a MOS tube P3, a MOS tube N2, a MOS tube N3, an inverter U100, an inverter U101, an inverter U103, an inverter U104, an inverter U105, an inverter U106, an NOR gate U102 and resistors R2 and R3.

[0039] The source of the MOS tube P2 and the source of the MOS tube P3 are electrically connected with an external power supply VCC; an external input signal TXD is input to one end of a resistor R2, and an external enable signal STB is input to one end of a resistor R3; an external bias voltage VB1 is input to the gate of a MOS tube N3;

[0040] The gate and the drain of the MOS tube P2 are electrically connected with the gate of the MOS tube P3 and the drain of the MOS tube N3, the drain of the MOS tube P3 is electrically connected with the gate, the source of the MOS tube N2 and the input end of an inverter U100, the other end of the resistor R2 is electrically connected with the drain of the MOS tube N2;

[0041] The output end of the inverter U100 is electrically connected with the input end of an inverter U101, the output end of the inverter U101 is electrically connected with the first input end of a NOR gate U102, the other end of the resistor R3 is electrically connected with the input end of an inverter U105 and the second input end of the NOR gate U102, the output end of the NOR gate U102 is electrically connected with the input end of an inverter U103;

[0042] The output end of the inverter U103 is electrically connected with the input end of an inverter U104, and outputs a signal TXDP to a driving assembly, the output end of the inverter U104 outputs a signal TXDN to the driving assembly; the output end of the inverter U105 is electrically connected with the input end of an inverter U106, and outputs a signal STBP to an enable switch assembly, the output end of the inverter U106 outputs a signal STBN to the enable switch assembly;

[0043] The source of the MOS tube N3 is grounded.

[0044] Further, the output module comprises a MOS tube P0, a MOS tube P1, a MOS tube N100, a MOS tube N0, a MOS tube N1, a MOS tube N101 and a resistor R0, a resistor R1;

[0045] The source of the MOS tube P1 and one end of the resistor R0 are electrically connected with an external power supply VCC, the other end of the resistor R0 is electrically connected with the source of the MOS tube P0, and is electrically connected with the signal input end of a high-voltage side current-limiting protection unit; the signal input end of a low-voltage side current-limiting protection unit is electrically connected with one end of the resistor R1 and the source of the MOS tube N0;

[0046] The output driving signal PDRIVER of the driving assembly is input to the gate of the MOS tube P0 and the gate of the MOS tube P1, the drain of the MOS tube P0 and the drain of the MOS tube P1 are electrically connected with the gate and the source of the MOS tube N100, and the drain of the MOS tube N100 outputs a signal CANH;

[0047] The output drive signal NDRIVER of the drive assembly is connected to the gate of MOS tube N0 and the gate of MOS tube N1, the drain of MOS tube N0 and the drain of MOS tube N1 are electrically connected to the drain of MOS tube N101, and the gate and source of MOS tube N101 output signal CANL.

[0048] The other end of the resistor R1 and the source of MOS tube N1 are grounded.

[0049] Compared with the prior art, the application has the following advantages:

[0050] 1. When the short-circuit current limiting protection is triggered, the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit pull up the voltage drop on the inductive resistor, pull up the drive signal PDRIVER and reduce the voltage of the drive signal NDRIVER, weaken the conduction of the drive tube, and limit the fault current. This current limiting protection is a continuous clamping process, and the drive tube still maintains a relatively small apparent current in the current limiting state. The bus physical layer is still in the apparent state, and will not cause bus error frames, retransmission or communication interruption due to node protection. The action of relying on thermal shutdown protection to directly shut off the current conduction is avoided, the system communication reliability is improved, the requirement of functional safety on communication continuity is met. Meanwhile, by using the characteristics of the common-gate amplifier that there is no Miller effect and the gain term does not appear in the denominator of the bandwidth formula, a very high bandwidth can be obtained by reducing CL or Rload to obtain a faster system response. The symmetric high-voltage side current limiting protection and low-voltage side current limiting protection are set to ensure the consistency of the protection capability of CANH to ground short circuit and CANL to high voltage short circuit.

[0051] 2. When the external input signal TXD is externally suspended, the constant current source current charges the pin, so that the voltage is pulled up to be close to VCC, and thus is reliably recognized as a logic high. Due to the existence of the constant current, as soon as the MCU loses the driving capability, the voltage of the external input signal TXD will be immediately and definitely pulled up, the CAN bus transceiver automatically enters the recessive state, so that the bus is prevented from being accidentally locked in the apparent state and paralyzed the entire network. When the external enable signal STB is a high-level signal, the CAN bus transceiver enters the recessive state; when STB is a low level, the CAN bus transceiver enters the apparent state. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 The circuit diagram of the current limiting protection circuit is shown in the following figure;

[0053] Figure 2 The circuit diagram of the CAN bus transceiver is shown in the following figure;

[0054] Figure 3 The circuit diagram of the signal receiving module of the CAN bus transceiver is shown in the following figure;

[0055] Figure 4 The simulation diagram of the CAN bus transceiver. DETAILED DESCRIPTION

[0056] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0057] In addition, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like are based on the orientation or positional relationship shown in the drawings and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements of the present application must have a particular orientation, and therefore cannot be understood as limiting the present application.

[0058] When an element is referred to as being "fixed to" or "set to" or "provided on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0059] Unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. EMBODIMENT

[0060] Please refer to Figure 1As shown, the embodiment provides a current limiting protection circuit, which comprises a high-voltage side current limiting protection unit, a low-voltage side current limiting protection unit and a driving unit; the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit and the driving unit are electrically connected with an external power supply VCC; the driving unit comprises a driving component, an enable switch component and a current mirror component. A signal TXDP and a signal TXDN are input to the driving component, a signal STBP and a signal STBN are input to the enable switch component, a signal input end of the high-voltage side current limiting protection unit collects a current sensing signal PBACK of the high-voltage side, and a signal input end of the low-voltage side current limiting protection unit collects a current sensing signal NBACK of the low-voltage side. Output ends of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit are electrically connected with the driving component. The enable switch component is electrically connected with control ends of the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit, the current mirror component and the driving component. A first output end of the current mirror component is electrically connected with control ends of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit, second and third output ends of the current mirror component are electrically connected with an output end of the driving component, and the output end of the driving component outputs a driving signal PDRIVER and a driving signal NDRIVER.

[0061] Specifically, the high-voltage side current limiting protection unit comprises MOS tubes P4, P5, P6, P7, N4, N5, N6, N7 and a resistor R4.

[0062] A source of the MOS tube P6, a source of the MOS tube P7 and one end of the resistor R4 are electrically connected with the external power supply VCC; a source of the MOS tube P4 collects the current sensing signal PBACK of the high-voltage side; a gate of the MOS tube P6 is electrically connected with a first output end of the current mirror component.

[0063] The other end of the resistor R4 is electrically connected with a source of the MOS tube P5 and the low-voltage side current limiting protection unit, a gate and a drain of the MOS tube P5 are electrically connected with a gate of the MOS tube P4 and a drain of the MOS tube N5, a drain of the MOS tube P4 is electrically connected with a drain of the MOS tube N4 and electrically connected with the driving component as an output end. A gate of the MOS tube N4 is electrically connected with a gate of the MOS tube N5, a drain of the MOS tube P6, a gate and a drain of the MOS tube N6 and a gate of the MOS tube N7, and is electrically connected with the enable switch component. A gate and a drain of the MOS tube P7 are electrically connected with a drain of the MOS tube N7, and are electrically connected with the enable switch component and the low-voltage side current limiting protection unit. A source of the MOS tube N4, a source of the MOS tube N5, a source of the MOS tube N6 and a source of the MOS tube N7 are grounded.

[0064] The MOS tube P4, the MOS tube P5, the MOS tube N4 and the MOS tube N5 constitute a common gate amplifier, the resistor R4 and the MOS tube P5 form an active load common source amplifier, and the gate of the MOS tube P4 is provided with voltage bias. The MOS tube P6, the MOS tube P7, the MOS tube N6 and the MOS tube N7 constitute a bias network for setting the working point of the MOS tube N4 and the MOS tube N5.

[0065] The low-voltage side current limiting protection unit comprises the MOS tube P8, the MOS tube P9, the MOS tube P10, the MOS tube P11, the MOS tube P14, the MOS tube N8, the MOS tube N9, the MOS tube N11, the MOS tube N12, the MOS tube N13 and the resistor R5.

[0066] The source of the MOS tube P8, the source of the MOS tube P9, the source of the MOS tube P10, the source of the MOS tube P11 and the source of the MOS tube P14 are electrically connected with the external power supply VCC; the source of the MOS tube N8 collects the low-voltage side current sensing signal NBACK; the gate of the MOS tube P14 is electrically connected with the first output end of the current mirror component.

[0067] The gate of the MOS tube P8 is electrically connected with the gate of the MOS tube P9 and the gate of the MOS tube P7, and is electrically connected with the enable switch component; the drain of the MOS tube P8 is electrically connected with the drain of the MOS tube N8, and is electrically connected with the driving component as an output end. The gate of the MOS tube N8 is electrically connected with the gate of the MOS tube N9, the drain of the MOS tube N9 and the drain of the MOS tube P9. The source of the MOS tube N9 is electrically connected with one end of the resistor R5 and the drain of the MOS tube P10; the gate of the MOS tube P10 is electrically connected with the gate of the MOS tube P11, the drain of the MOS tube P11 and the drain of the MOS tube N11, and is electrically connected with the enable switch component. The drain of the MOS tube P14 is electrically connected with the gate of the MOS tube N13, the drain of the MOS tube N13, the gate of the MOS tube N12 and the gate of the MOS tube N11, and is electrically connected with the enable switch component; the drain of the MOS tube N12 is electrically connected with the other end of the resistor R4.

[0068] The source of the MOS tube N11, the source of the MOS tube N12, the source of the MOS tube N13 and the other end of the resistor R5 are grounded.

[0069] The MOS tube P8, the MOS tube P9, the MOS tube N8 and the MOS tube N9 constitute a common gate amplifier, the resistor R5 and the MOS tube N9 form an active load common source amplifier, and the gate of the MOS tube N8 is provided with voltage bias. The MOS tube P10, the MOS tube P11, the MOS tube P14, the MOS tube N12 and the MOS tube N13 constitute a bias network for setting the working point of the MOS tube N11.

[0070] satisfy the following conditional expressions,

[0071] (W / L) P4 = (W / L) P5 = (W / L) P6 = (W / L) P7 = (W / L) P8 = (W / L) P9 ;

[0072] (W / L) N4 = (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L) N8 = (W / L) N9 ;

[0073] wherein (W / L) P4 is a width-length ratio of the MOS transistor P4, (W / L) P5 is a width-length ratio of the MOS transistor P5, (W / L) P6 is a width-length ratio of the MOS transistor P6, (W / L) P7 is a width-length ratio of the MOS transistor P7, (W / L) P8 is a width-length ratio of the MOS transistor P8, (W / L) P9 is a width-length ratio of the MOS transistor P9; (W / L) N4 is a width-length ratio of the MOS transistor N4, (W / L) N5 is a width-length ratio of the MOS transistor N5, (W / L) N6 is a width-length ratio of the MOS transistor N6, (W / L) N7 is a width-length ratio of the MOS transistor N7, (W / L) N8 is a width-length ratio of the MOS transistor N8, (W / L) N9 is a width-length ratio of the MOS transistor N9.

[0074] Specifically, the driving unit includes the MOS transistor P21, the MOS transistor P22, the MOS transistor P23, the MOS transistor N23, the MOS transistor N25, and the MOS transistor N26.

[0075] The source of the MOS tube P21, the source of the MOS tube P22 and the source of the MOS tube P23 are electrically connected with an external power supply VCC. The output of the high-voltage side current-limiting protection unit is electrically connected with the gate of the MOS tube P21, that is, the drain of the MOS tube P4 is electrically connected with the gate of the MOS tube P21; the output of the low-voltage side current-limiting protection unit is electrically connected with the gate of the MOS tube N25, that is, the drain of the MOS tube N8 is electrically connected with the gate of the MOS tube N25. The signal TXDP is input to the gate of the MOS tube P22, and the signal TXDN is input to the gate of the MOS tube N26; the drain of the MOS tube P23 is electrically connected with the drain of the MOS tube N23 and the enable switch assembly.

[0076] The drain of the MOS tube P21 is electrically connected with the drain of the MOS tube P22, the gate of the MOS tube P23, the second output of the current mirror assembly and the enable switch assembly, and outputs a driving signal PDRIVER as an output; the drain of the MOS tube N25 is electrically connected with the drain of the MOS tube N26, the gate of the MOS tube N23, the third output of the current mirror assembly and the enable switch assembly, and outputs a driving signal NDRIVER as an output.

[0077] The source of the MOS tube N23, the source of the MOS tube N25 and the source of the MOS tube N26 are grounded.

[0078] Specifically, the enable switch assembly comprises the MOS tube P12, the MOS tube P13, the MOS tube P24, the MOS tube P25, the MOS tube P26, the MOS tube P27, the MOS tube N10, the MOS tube N15, the MOS tube N20, the MOS tube N21, the MOS tube N22 and the transmission gate TG1 and the transmission gate TG2.

[0079] The signal STBP is input to the gate of the MOS tube P12, the gate of the MOS tube P13, the gate of the MOS tube P24, the gate of the MOS tube P25, the gate of the MOS tube P26, the gate of the MOS tube P27 and the pin 1 of the transmission gate TG1 and the pin 1 of the transmission gate TG2; the signal STBN is input to the gate of the MOS tube N10, the gate of the MOS tube N15, the gate of the MOS tube N20, the gate of the MOS tube N21, the gate of the MOS tube N22 and the pin 2 of the transmission gate TG2 and the pin 2 of the transmission gate TG1; the source of the MOS tube P12, the source of the MOS tube P13, the source of the MOS tube P24, the source of the MOS tube P25, the source of the MOS tube P26 and the source of the MOS tube P27 are electrically connected with the external power supply VCC.

[0080] The drain of the MOS tube P12 is electrically connected with the control end of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit. Specifically, the drain of the MOS tube P12 is electrically connected with the gate and drain of the MOS tube P7, the gate of the MOS tube P8 and the gate of the MOS tube P9. The drain of the MOS tube P13 and the drain of the MOS tube N15 are both electrically connected with the control end of the low-voltage side current limiting protection unit, that is, the drain of the MOS tube P13 is electrically connected with the gate and drain of the MOS tube P10, the gate of the MOS tube P11 and the drain of the MOS tube N11; the drain of the MOS tube N15 is electrically connected with the gate and drain of the MOS tube N13, the gate of the MOS tube N12 and the drain of the MOS tube P14. The drain of the MOS tube N10 is electrically connected with the control end of the high-voltage side current limiting protection unit, and the drain of the MOS tube N10 is electrically connected with the gate and drain of the MOS tube N6, the gate of the MOS tube N4, the gate of the MOS tube N5, the gate of the MOS tube N7 and the drain of the MOS tube P6.

[0081] The drain of the MOS tube P24, the drain of the MOS tube P25, the drain of the MOS tube P26, the drain of the MOS tube N20 and the drain of the MOS tube N21 are all electrically connected with the control end of the current mirror assembly. The drain of the MOS tube P27 and the pin 3 of the transmission gate TG1 are both electrically connected with the gate of the MOS tube P23, the drain of the MOS tube N22 and the pin 4 of the transmission gate TG2 are both electrically connected with the gate of the MOS tube N23, and the pin 4 of the transmission gate TG1 and the pin 3 of the transmission gate TG2 are both electrically connected with the drain of the MOS tube P23 and the drain of the MOS tube N23.

[0082] The source of the MOS tube N10, the source of the MOS tube N15, the source of the MOS tube N20, the source of the MOS tube N21 and the source of the MOS tube N22 are all grounded.

[0083] When the signal STB is 0, the enabling switch assembly is in the closed state, and the overall current limiting protection circuit is in the linear state; when STB=VCC, the enabling switch assembly is in the open state, the gates of the PMOS tubes of the current mirror assembly are all short-circuited to the power supply, and the gates of the NMOS tubes of the current mirror assembly are all short-circuited to the ground; so that the driving assembly and the current mirror assembly are closed, and the overall current limiting protection circuit is in the invisible state, effectively reducing the power consumption.

[0084] Specifically, the current mirror assembly includes the MOS tube P15, the MOS tube P16, the MOS tube P17, the MOS tube P18, the MOS tube P19, the MOS tube P20, the MOS tube N14, the MOS tube N16, the MOS tube N17, the MOS tube N18, the MOS tube N19 and the MOS tube N24.

[0085] The source of the MOS tube P15, the source of the MOS tube P16, the source of the MOS tube P17, the source of the MOS tube P18, the source of the MOS tube P19 and the source of the MOS tube P20 are electrically connected with an external power supply VCC.

[0086] The gate and the drain of the MOS tube P15 are electrically connected with the gate of the MOS tube P16, the drain of the MOS tube N14 and the drain of the MOS tube P24, and are electrically connected with the control end of the high-voltage side current-limiting protection unit and the low-voltage side current-limiting protection unit as the first output end; that is, the gate and the drain of the MOS tube P15 are electrically connected with the gate of the MOS tube P16, the drain of the MOS tube N14, the drain of the MOS tube P24, the gate of the MOS tube P14 and the gate of the MOS tube P6. An external constant bias voltage VB2 is input to the gate of the MOS tube N14; the external constant bias voltage VB2 is used to control the MOS tube N14 to provide a constant drain current I_BIAS, specifically, I_BIAS≈0.5*μn*Cox*(W / L) N14 *(VB2-Vth) 2 Wherein μn is the migration rate of electrons, Cox is the gate oxide layer capacitance per unit area, Vth is the threshold voltage of NMOS, (W / L) N14 is the width-length ratio of the MOS tube N14.

[0087] The drain of the MOS tube P16 is electrically connected with the gate and the drain of the MOS tube N16, the gate of the MOS tube N17 and the drain of the MOS tube N20. The drain of the MOS tube N17 is electrically connected with the gate and the drain of the MOS tube P17, the gate of the MOS tube P18 and the drain of the MOS tube P25. The drain of the MOS tube P18 is electrically connected with the gate and the drain of the MOS tube N18, the gate of the MOS tube N19, the gate of the MOS tube N24 and the drain of the MOS tube N21. The drain of the MOS tube N19 is electrically connected with the gate and the drain of the MOS tube P19, the gate of the MOS tube P20 and the drain of the MOS tube P26. The drain of the MOS tube P20 and the drain of the MOS tube N24 are respectively electrically connected with the drain of the MOS tube N25 and the drain of the MOS tube P21 as the third output end and the second output end.

[0088] The source of the MOS tube N14, the source of the MOS tube N16, the source of the MOS tube N17, the source of the MOS tube N18, the source of the MOS tube N19 and the source of the MOS tube N24 are grounded. The current mirror component provides a constant driving current for the driving component.

[0089] Further, please refer to the attached Figures 2-4 , the embodiment also discloses a CAN bus transceiver, which comprises the current-limiting protection circuit and the signal receiving module output module.

[0090] The external input signal TXD and the enable signal STB are input into a signal receiving module, and the signal receiving module output signals TXDP and TXDN are input into a driving component, and the signal receiving module output signals STBP and STBN are input into an enable switch component; the output end of the driving component outputs driving signals PDRIVER and NDRIVER to an output module, and the output module outputs signals CANH and CANL.

[0091] Please refer to the accompanying drawings Figure 3 Specifically, the signal receiving module comprises MOS tubes P2, P3, N2 and N3, inverters U100, U101, U103, U104, U105 and U106, and an NOR gate U102 and resistors R2 and R3.

[0092] The source of the MOS tube P2 and the source of the MOS tube P3 are electrically connected with an external power supply VCC; an external input signal TXD is input into one end of the resistor R2, and an external enable signal STB is input into one end of the resistor R3; an external bias voltage VB1 is input into the gate of the MOS tube N3 for setting the working point of the MOS tube N3.

[0093] The gate and the drain of the MOS tube P2 are electrically connected with the gate of the MOS tube P3 and the drain of the MOS tube N3, the drain of the MOS tube P3 is electrically connected with the gate, the source of the MOS tube N2 and the input end of the inverter U100, and the other end of the resistor R2 is electrically connected with the drain of the MOS tube N2.

[0094] The output end of the inverter U100 is electrically connected with the input end of the inverter U101, the output end of the inverter U101 is electrically connected with the first input end of the NOR gate U102, the other end of the resistor R3 is electrically connected with the input end of the inverter U105 and the second input end of the NOR gate U102, and the output end of the NOR gate U102 is electrically connected with the input end of the inverter U103.

[0095] The output end of the inverter U103 is electrically connected with the input end of the inverter U104, and outputs a signal TXDP to the driving component, and the output end of the inverter U104 outputs a signal TXDN to the driving component; the output end of the inverter U105 is electrically connected with the input end of the inverter U106, and outputs a signal STBP to the enable switch component, and the output end of the inverter U106 outputs a signal STBN to the enable switch component. The source of the MOS tube N3 is grounded.

[0096] The resistor R2, the MOS tube N2 and the resistor R3 constitute an input surge protection structure for protecting transient overvoltage. The MOS tube N3, the MOS tube P2 and the MOS tube P3 constitute a current mirror as a constant current source. When the external input signal TXD is externally suspended, the constant current source current charges the pin, so that the voltage is pulled up to be close to VCC, thereby being reliably recognized as a logic high. Due to the existence of the constant current, once the MCU loses the driving ability, the external input signal TXD voltage will be immediately and definitely pulled up, and the CAN bus transceiver automatically enters the recessive state, thereby avoiding the bus being accidentally locked in the dominant state and paralyzing the entire network. When the external enable signal STB is a high-level signal, the CAN bus transceiver enters the recessive state; when STB is low, the CAN bus transceiver enters the dominant state.

[0097] Please refer to the accompanying drawings Figure 2 Specifically, the output module includes the MOS tube P0, the MOS tube P1, the MOS tube N100, the MOS tube N0, the MOS tube N1, the MOS tube N101 and the resistor R0 and the resistor R1.

[0098] The source electrode of the MOS tube P1 and one end of the resistor R0 are electrically connected with the external power supply VCC, the other end of the resistor R0 is electrically connected with the source electrode of the MOS tube P0, and is electrically connected with the signal input end of the high-voltage side current limiting protection unit; that is, the other end of the resistor R0 is electrically connected with the source electrode of the MOS tube P0 and the source electrode of the MOS tube P4. The signal input end of the low-voltage side current limiting protection unit is electrically connected with one end of the resistor R1 and the source electrode of the MOS tube N0; that is, the source electrode of the MOS tube N8 is electrically connected with one end of the resistor R1 and the source electrode of the MOS tube N0.

[0099] The output driving signal PDRIVER of the driving component is connected to the gate electrode of the MOS tube P0 and the gate electrode of the MOS tube P1, the drain electrode of the MOS tube P0 and the drain electrode of the MOS tube P1 are electrically connected with the gate electrode and the source electrode of the MOS tube N100, and the drain electrode of the MOS tube N100 outputs a signal CANH. The output driving signal NDRIVER of the driving component is connected to the gate electrode of the MOS tube N0 and the gate electrode of the MOS tube N1, the drain electrode of the MOS tube N0 and the drain electrode of the MOS tube N1 are electrically connected with the drain electrode of the MOS tube N101, and the gate electrode and the source electrode of the MOS tube N101 output a signal CANL. The other end of the resistor R1 and the source electrode of the MOS tube N1 are grounded.

[0100] The MOS tube N100 and the MOS tube N101 are both diode-connected NMOS tubes, and the body diode is used as the output reverse protection. The resistor R0 and the resistor R1 are inductive resistors; the MOS tube P0 and the MOS tube N0 are current sampling tubes. The MOS tube P1 and the MOS tube N1 are output power tubes.

[0101] In this embodiment, all MOS transistors are SOI MOS transistors, i.e. Silicon-On-Insulator supplied SOI technology. Since in practical applications the CANH and CANL pins usually need to meet the working conditions of positive and negative high voltage resistance. The vertical DMOS structure in traditional bulk silicon CMOS usually has an inherent parasitic body diode, which will be turned on when the pin voltage is lower than the substrate potential. If a bulk silicon CMOS process is used, when the CANH and CANL pins are connected to negative high voltage, there will be a large leakage current from GND to the negative voltage pin, which will damage the high resistance state and normal function of the circuit. By adding a buried oxide layer to the traditional bulk silicon CMOS substrate to create a dielectric isolation, in SOI, each NMOS or PMOS is an isolated island surrounded by silicon dioxide. Its body region is insulated from the substrate, so there is no parasitic PN junction diode from the source / drain region to the common substrate, preventing large leakage current from forward conduction

[0102] Taking the high-voltage side current limiting protection as an example, V_PBACK is the induced voltage on the high-voltage side. In the small signal model, the voltage gain AV of the common-gate amplifier on the high-voltage side is AV = Vout / V_PBACK≈gm4*Rload, where Vout is the drain voltage of MOS transistor P4, which is also the output voltage of the common-gate amplifier, gm4 is the transconductance of MOS transistor P4, Rload is the equivalent load resistance seen from the drain of MOS transistor P4, and * is the multiplication operator.

[0103] Therefore, the drain voltage Vout of MOS transistor P4 is approximately equal to gm4*Rload*V_PBACK; since gm4*Rload is much greater than 1, a small voltage fluctuation of V_PBACK on the signal input end of the high-voltage side current limiting protection unit can be quickly amplified to a large voltage change, thereby increasing the ability to drive the subsequent MOS transistor P21.

[0104] When the short-circuit current limiting protection is triggered, the induced current on PBACK increases, the voltage drop of the sensing resistor R0 rises, V_PBACK decreases, and therefore the output voltage of the common-gate amplifier also instantaneously decreases, causing the negative absolute value of the gate voltage of MOS transistor P21 to increase, thereby enhancing the conduction of MOS transistor P21. The enhancement of the conduction of MOS transistor P21 will pull up the voltage of the drive signal PDRIVER. This causes the negative absolute value of the gate voltage of MOS transistors P0 and P1 to decrease, thereby weakening their conduction, and thus the fault current is limited. At this time, MOS transistors P0 and P1 are not completely turned off, but maintain a small explicit current. The bus physical layer is still in the explicit state and will not cause bus error frames, retransmission or communication interruption due to node protection. This continuous and smooth clamping regulation avoids the problem of oscillation caused by frequent flipping near the threshold value when a digital comparator is used, and also avoids the risk of voltage spikes on the bus caused by direct shutdown.

[0105] At the same time, the-3dB bandwidth f of the traditional comparator is −3dB ≈gm / (2pi*CM*AV), wherein pi is a circular constant parameter, gm is the transconductance of the comparator, CM is the Miller capacitance, and AV is the gain of the comparator. In order to realize high-precision comparison, high gain is required, which directly leads to narrow bandwidth and slow response. The-3dB bandwidth f of the common-gate amplifier composed of MOS tube P4, MOS tube P5, MOS tube N4 and MOS tube N5 is f≈1 / (2pi*Rload*CL). Wherein pi is a circular constant parameter, Rload is the equivalent load resistance viewed from the drain of MOS tube P4, and CL is the equivalent load capacitance of the output node. Thus, while obtaining the necessary gain, an extremely high bandwidth can be obtained by reducing CL or reducing Rload. Since the response time of the system is inversely proportional to the bandwidth, high bandwidth can obtain faster system response, effectively overcoming the slow response and dependence on thermal shutdown of the current limiting protection of the existing CAN bus transceiver. The low-voltage side current limiting protection is the same, and by setting the symmetric high-voltage side current limiting protection and low-voltage side current limiting protection, the consistency of the protection capability of CANH to ground short circuit and CANL to high voltage short circuit is ensured.

[0106] Please refer to the attached Figure 4 , the attached Figure 4 is a simulation diagram of the CAN bus transceiver using the current limiting protection circuit disclosed in the embodiment. In the embodiment, the external power supply voltage VCC=5V, the TXD accesses a square wave signal, the STB=0 is the enable state, the CANH is short-circuited to the ground, and the CANL is short-circuited to the high voltage 20V. As shown in the attached Figure 4 , at this time, the short-circuit current of the high-voltage side and the low-voltage side is basically the same, and the response speed is also basically the same. The high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit ensure the symmetry of the current limiting threshold, ensure that the maximum transient power consumption that the chip can withstand is balanced under different faults, and ensure the symmetry of the response speed, avoiding the accumulation and stress of additional heat due to slow response on one side.

[0107] The above describes only the preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical range disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A current limit protection circuit, characterized by, The application relates to a high-voltage side current limiting protection unit, a low-voltage side current limiting protection unit and a driving unit; the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit and the driving unit are electrically connected with an external power supply VCC; the driving unit comprises a driving component, an enabling switch component and a current mirror component; a signal TXDP and a signal TXDN are input to the driving component, a signal STBP and a signal STBN are input to the enabling switch component, a signal input end of the high-voltage side current limiting protection unit collects a high-voltage side current sensing signal PBACK, and a signal input end of the low-voltage side current limiting protection unit collects a low-voltage side current sensing signal NBACK; output ends of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit are electrically connected with the driving component; the enabling switch component is electrically connected with control ends of the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit, the current mirror component and the driving component; a first output end of the current mirror component is electrically connected with control ends of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit, second and third output ends of the current mirror component are electrically connected with output ends of the driving component, and the output ends of the driving component output a driving signal PDRIVER and a driving signal NDRIVER; the high-voltage side current limiting protection unit comprises MOS tubes P4, P5, P6, P7, N4, N5, N6, N7 and a resistor R4; a source electrode of the MOS tube P6, a source electrode of the MOS tube P7 and one end of the resistor R4 are electrically connected with the external power supply VCC; a source electrode of the MOS tube P4 collects the high-voltage side current sensing signal PBACK; a gate electrode of the MOS tube P6 is electrically connected with a first output end of the current mirror component; the other end of the resistor R4 is electrically connected with a source electrode of the MOS tube P5 and the low-voltage side current limiting protection unit, a gate electrode and a drain electrode of the MOS tube P5 are electrically connected with a gate electrode of the MOS tube P4 and a drain electrode of the MOS tube N5, a drain electrode of the MOS tube P4 is electrically connected with a drain electrode of the MOS tube N4 and is electrically connected with the driving component as an output end; a gate electrode of the MOS tube N4 is electrically connected with a gate electrode of the MOS tube N5, a drain electrode of the MOS tube P6, a gate electrode and a drain electrode of the MOS tube N6 and a gate electrode of the MOS tube N7, and is electrically connected with the enabling switch component; a gate electrode and a drain electrode of the MOS tube P7 are electrically connected with the drain electrode of the MOS tube N7, and are electrically connected with the enabling switch component and the low-voltage side current limiting protection unit; source electrodes of the MOS tube N4, the MOS tube N5, the MOS tube N6 and the MOS tube N7 are grounded. The low-voltage side current limiting protection unit comprises MOS tubes P8, P9, P10, P11, P14, N8, N9, N11, N12, N13 and a resistor R5; the source of the MOS tube P8, the source of the MOS tube P9, the source of the MOS tube P10, the source of the MOS tube P11 and the source of the MOS tube P14 are electrically connected with an external power supply VCC; the source of the MOS tube N8 collects a low-voltage side current sensing signal NBACK; the gate of the MOS tube P14 is electrically connected with the first output end of the current mirror component; the gate of the MOS tube P8 is electrically connected with the gate of the MOS tube P9 and the gate of the MOS tube P7, and is electrically connected with an enable switch component; the drain of the MOS tube P8 is electrically connected with the drain of the MOS tube N8, and is electrically connected with a driving component as an output end; the gate of the MOS tube N8 is electrically connected with the gate, the drain of the MOS tube N9 and the drain of the MOS tube P9; the source of the MOS tube N9 is electrically connected with one end of the resistor R5 and the drain of the MOS tube P10; the gate of the MOS tube P10 is electrically connected with the gate, the drain of the MOS tube P11 and the drain of the MOS tube N11, and is electrically connected with the enable switch component; the drain of the MOS tube P14 is electrically connected with the gate, the drain of the MOS tube N13, the gate of the MOS tube N12 and the gate of the MOS tube N11, and is electrically connected with the enable switch component; the drain of the MOS tube N12 is electrically connected with the other end of the resistor R4; the source of the MOS tube N11, the source of the MOS tube N12, the source of the MOS tube N13 and the other end of the resistor R5 are grounded.

2. The current limit protection circuit of claim 1, wherein: The following conditional expression is satisfied, (W / L) P4 = (W / L) P5 = (W / L) P6 = (W / L) P7 = (W / L) P8 = (W / L) P9 ; (W / L) N4 = (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L) N8 = (W / L) N9 ; wherein (W / L) P4 is the width-length ratio of MOS transistor P4, (W / L) P5 is the width-length ratio of MOS transistor P5, (W / L) P6 is the width-length ratio of MOS transistor P6, (W / L) P7 is the width-length ratio of MOS transistor P7, (W / L) P8 is the width-length ratio of MOS transistor P8, (W / L) P9 is the width-length ratio of MOS transistor P9; (W / L) N4 is the width-to-length ratio of MOS transistor N4, (W / L) N5 is the width-to-length ratio of MOS transistor N5, (W / L) N6 is the width-to-length ratio of MOS transistor N6, (W / L) N7 is the width-to-length ratio of MOS transistor N7, (W / L) N8 is the width-to-length ratio of MOS transistor N8, (W / L) N9 is the width-to-length ratio of MOS transistor N9.

3. The current limit protection circuit of claim 1, wherein: The driving component comprises MOS tubes P21, P22, P23, N23, N25 and N26; The source of the MOS tube P21, the source of the MOS tube P22 and the source of the MOS tube P23 are electrically connected with an external power supply VCC; the output end of the high-voltage side current limiting protection unit is electrically connected with the gate of the MOS tube P21, and the output end of the low-voltage side current limiting protection unit is electrically connected with the gate of the MOS tube N25; the signal TXDP is input to the gate of the MOS tube P22, and the signal TXDN is input to the gate of the MOS tube N26; the drain of the MOS tube P23 is electrically connected with the drain of the MOS tube N23, and is electrically connected with an enable switch component; The drain of the MOS tube P21 is electrically connected with the drain of the MOS tube P22, the gate of the MOS tube P23, the second output end of the current mirror component and the enable switch component, and outputs a driving signal PDRIVER as an output end; the drain of the MOS tube N25 is electrically connected with the drain of the MOS tube N26, the gate of the MOS tube N23, the third output end of the current mirror component and the enable switch component, and outputs a driving signal NDRIVER as an output end; The source of the MOS tube N23, the source of the MOS tube N25 and the source of the MOS tube N26 are grounded.

4. The current limit protection circuit of claim 3, wherein: The enabling switch assembly comprises MOS tubes P12, P13, P24, P25, P26, P27, N10, N15, N20, N21, N22 and transmission gates TG1, TG2. The signal STBP is input to the gate of the MOS tube P12, the gate of the MOS tube P13, the gate of the MOS tube P24, the gate of the MOS tube P25, the gate of the MOS tube P26, the gate of the MOS tube P27 and pin 1 of the transmission gate TG1, pin 1 of the transmission gate TG2; the signal STBN is input to the gate of the MOS tube N10, the gate of the MOS tube N15, the gate of the MOS tube N20, the gate of the MOS tube N21, the gate of the MOS tube N22 and pin 2 of the transmission gate TG2, pin 2 of the transmission gate TG1; the source of the MOS tube P12, the source of the MOS tube P13, the source of the MOS tube P24, the source of the MOS tube P25, the source of the MOS tube P26 and the source of the MOS tube P27 are electrically connected with the external power supply VCC; The drain of the MOS tube P12 is electrically connected with the control end of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit, the drain of the MOS tube P13 and the drain of the MOS tube N15 are electrically connected with the control end of the low-voltage side current limiting protection unit, and the drain of the MOS tube N10 is electrically connected with the control end of the high-voltage side current limiting protection unit; The drain of the MOS tube P24, the drain of the MOS tube P25, the drain of the MOS tube P26, the drain of the MOS tube N20 and the drain of the MOS tube N21 are electrically connected with the control end of the current mirror assembly; the drain of the MOS tube P27 and pin 3 of the transmission gate TG1 are electrically connected with the gate of the MOS tube P23, the drain of the MOS tube N22 and pin 4 of the transmission gate TG2 are electrically connected with the gate of the MOS tube N23, and pin 4 of the transmission gate TG1 and pin 3 of the transmission gate TG2 are electrically connected with the drain of the MOS tube P23 and the drain of the MOS tube N23; The source of the MOS tube N10, the source of the MOS tube N15, the source of the MOS tube N20, the source of the MOS tube N21 and the source of the MOS tube N22 are grounded.

5. The current limit protection circuit of claim 4, wherein: The current mirror assembly comprises MOS tubes P15, P16, P17, P18, P19, P20 and MOS tubes N14, N16, N17, N18, N19, N24; The source of the MOS tube P15, the source of the MOS tube P16, the source of the MOS tube P17, the source of the MOS tube P18, the source of the MOS tube P19 and the source of the MOS tube P20 are electrically connected with the external power supply VCC; The gate and the drain of the MOS tube P15 are electrically connected with the gate of the MOS tube P16, the drain of the MOS tube N14 and the drain of the MOS tube P24, and are electrically connected with the control end of the high-voltage side current-limiting protection unit and the low-voltage side current-limiting protection unit as a first output end; an external constant bias voltage VB2 is input to the gate of the MOS tube N14; the drain of the MOS tube P16 is electrically connected with the gate of the MOS tube N16, the drain of the MOS tube N16, the gate of the MOS tube N17 and the drain of the MOS tube N20; the drain of the MOS tube N17 is electrically connected with the gate of the MOS tube P17, the drain of the MOS tube P17, the gate of the MOS tube P18 and the drain of the MOS tube P25; the drain of the MOS tube P18 is electrically connected with the gate of the MOS tube N18, the drain of the MOS tube N18, the gate of the MOS tube N19, the gate of the MOS tube N24 and the drain of the MOS tube N21; the drain of the MOS tube N19 is electrically connected with the gate of the MOS tube P19, the drain of the MOS tube P19, the gate of the MOS tube P20 and the drain of the MOS tube P26; the drain of the MOS tube P20 and the drain of the MOS tube N24 are electrically connected with the drain of the MOS tube N25 and the drain of the MOS tube P21 as a third output end and a second output end respectively; The source of the MOS tube N14, the source of the MOS tube N16, the source of the MOS tube N17, the source of the MOS tube N18, the source of the MOS tube N19 and the source of the MOS tube N24 are grounded.

6. A CAN bus transceiver, characterized by The current-limiting protection circuit and the signal receiving module and the output module of any one of claims 1-5; The external input signal TXD and the enable signal STB are input to the signal receiving module, the signal receiving module outputs the signal TXDP and the signal TXDN to the driving assembly, and the signal receiving module outputs the signal STBP and the signal STBN to the enable switch assembly; the output end of the driving assembly outputs the driving signal PDRIVER and the driving signal NDRIVER to the output module, and the output module outputs the signal CANH and the signal CANL.

7. The CAN bus transceiver of claim 6, characterized in that: The signal receiving module comprises a MOS tube P2, a MOS tube P3, a MOS tube N2, a MOS tube N3, an inverter U100, an inverter U101, an inverter U103, an inverter U104, an inverter U105, an inverter U106, an NOR gate U102 and resistors R2 and R3; The source of the MOS tube P2 and the source of the MOS tube P3 are electrically connected with an external power supply VCC; an external input signal TXD is input to one end of the resistor R2, and an external enable signal STB is input to one end of the resistor R3; an external bias voltage VB1 is input to the gate of the MOS tube N3; The gate and the drain of the MOS tube P2 are electrically connected with the gate of the MOS tube P3 and the drain of the MOS tube N3, the drain of the MOS tube P3 is electrically connected with the gate and the source of the MOS tube N2 and the input end of the inverter U100, and the other end of the resistor R2 is electrically connected with the drain of the MOS tube N2; An output terminal of the inverter U100 is electrically connected with an input terminal of an inverter U101, an output terminal of the inverter U101 is electrically connected with a first input terminal of an NOR gate U102, another terminal of the resistor R3 is electrically connected with an input terminal of an inverter U105 and a second input terminal of the NOR gate U102, an output terminal of the NOR gate U102 is electrically connected with an input terminal of an inverter U103; An output terminal of the inverter U103 is electrically connected with an input terminal of an inverter U104, and outputs a signal TXDP to a driving assembly, an output terminal of the inverter U104 outputs a signal TXDN to the driving assembly, an output terminal of the inverter U105 is electrically connected with an input terminal of an inverter U106, and outputs a signal STBP to an enabling switch assembly, an output terminal of the inverter U106 outputs a signal STBN to the enabling switch assembly; A source terminal of the MOS tube N3 is grounded.

8. The CAN bus transceiver of claim 6, wherein: The output module comprises MOS tubes P0, P1, N100, N0, N1, N101 and resistors R0, R1. A source terminal of the MOS tube P1 and one terminal of the resistor R0 are electrically connected with an external power supply VCC, another terminal of the resistor R0 is electrically connected with a source terminal of the MOS tube P0, and is electrically connected with a signal input terminal of a high-voltage side current-limiting protection unit; a signal input terminal of a low-voltage side current-limiting protection unit is electrically connected with one terminal of the resistor R1 and a source terminal of the MOS tube N0; The driving assembly outputs a driving signal PDRIVER to a gate terminal of the MOS tube P0 and a gate terminal of the MOS tube P1, a drain terminal of the MOS tube P0 and a drain terminal of the MOS tube P1 are electrically connected with a gate terminal and a source terminal of the MOS tube N100, a drain terminal of the MOS tube N100 outputs a signal CANH; The driving assembly outputs a driving signal NDRIVER to a gate terminal of the MOS tube N0 and a gate terminal of the MOS tube N1, a drain terminal of the MOS tube N0 and a drain terminal of the MOS tube N1 are electrically connected with a drain terminal of the MOS tube N101, a gate terminal and a source terminal of the MOS tube N101 output a signal CANL; Another terminal of the resistor R1 and a source terminal of the MOS tube N1 are grounded.

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