Radio frequency signal generation method and generation system

Abstract

The invention relates to a radio frequency signal generation method and system, and belongs to the technical field of radio frequency signal generation, and the method comprises the steps: obtaining an external reference signal, generating a high-frequency reference signal, and carrying out the shunting processing of the high-frequency reference signal, and obtaining a first reference signal and a second reference signal; based on the second reference signal, generating an intermediate frequency signal through a preset digital fine frequency synthesis method; performing phase locking processing on the first reference signal to generate a local oscillation signal; performing frequency mixing processing on the intermediate frequency signal and the local oscillator signal to generate an initial radio frequency signal; and performing phase noise dynamic correction on the initial radio frequency signal or a signal in the process of generating the initial radio frequency signal to obtain a corrected signal, and outputting the corrected signal as a radio frequency signal. The invention has the effects of high stability, wide band, low noise and fast switching.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency signal generation, in particular to a radio frequency signal generation method and system. BACKGROUND

[0002] In modern wireless communication, electronic countermeasure and radar systems, the radio frequency signal generator is a core front-end component, and its performance directly determines the ability of the entire system. With the development of technology, the performance requirements for the signal source are increasingly stringent, not only requiring it to have wideband coverage capability, but also requiring it to have extremely high requirements for spectral purity (i.e. low phase noise). Phase noise is a key indicator for measuring the short-term frequency stability of a signal, and excessive phase noise can cause a series of system performance degradation such as rising communication error rate and declining radar resolution.

[0003] At present, the mainstream radio frequency signal generation scheme mainly relies on phase-locked loop technology. Although a single integer / fraction frequency division phase-locked loop can provide high frequency stability and certain spectral purity, its frequency switching speed is limited by the loop bandwidth, making it difficult to meet the requirement of fast frequency hopping, and the phase noise of its output signal deteriorates severely outside the loop bandwidth. In order to balance the frequency resolution and switching speed, the industry often uses a cascade architecture of phase-locked loop and direct digital frequency synthesizer. However, such traditional cascade architecture (such as DDS driving PLL or DDS placed in the PLL loop) often introduces the output phase noise and spurs of DDS into the system while improving the frequency resolution, and further deteriorates at high frequencies, making it difficult to simultaneously achieve ultra-low phase noise and fine frequency control.

[0004] Therefore, the existing radio frequency signal generation method faces significant technical bottlenecks in how to achieve deep suppression of phase noise in a wide frequency band range, thereby generating a high-purity radio frequency signal. SUMMARY

[0005] In order to effectively dynamically manage and correct the phase noise in the signal generation link without sacrificing the frequency agility and wideband performance, the present application provides a radio frequency signal generation method and system.

[0006] In a first aspect, the present application provides a radio frequency signal generation method, comprising: obtaining an external reference signal, generating a high-frequency reference signal, and branching the high-frequency reference signal to obtain a first reference signal and a second reference signal; generating a medium-frequency signal based on the second reference signal through a preset digital fine frequency synthesis method; performing phase-locked processing on the first reference signal to generate a local oscillator signal; mixing the medium-frequency signal and the local oscillator signal to generate an initial radio frequency signal; The phase noise of the initial radio frequency signal or the signal generated during the generation of the initial radio frequency signal is dynamically corrected to obtain a corrected signal, and the corrected signal is output as a radio frequency signal.

[0007] Optionally, the generation of the intermediate frequency signal through a preset digital fine frequency synthesis method includes: In response to a frequency switching command, a preset optimization calculation method is executed based on the target frequency in the frequency switching command to generate a target frequency control instruction, and frequency loading and signal path switching operations are executed simultaneously. The target frequency control instruction includes at least: a phase-locked loop frequency control word for controlling the phase-locked processing, and a fine frequency control word for controlling a target digital frequency synthesis unit; the target digital frequency synthesis unit is selected from a plurality of preset digital frequency synthesis units based on the target frequency. The frequency loading and signal path switching operation includes the following steps: The fine frequency control word in the target frequency control instruction is loaded into the target digital frequency synthesis unit; The second reference signal is guided to the target digital frequency synthesis unit through a preset first high-speed gating network, so that the target digital frequency synthesis unit executes the fine frequency control word and generates an intermediate frequency signal; The intermediate frequency signal is guided to the node of the hybrid processing through a preset second high-speed gating network.

[0008] Optionally, outputting the corrected signal as a radio frequency signal includes: The corrected signal is subjected to adaptive impedance matching adjustment to obtain an adjusted signal, wherein the adaptive impedance matching adjustment is used to dynamically adjust the impedance characteristics according to the current frequency of the corrected signal. The adjusted signal is subjected to gain flattening processing to balance the signal amplitude of the adjusted signal across the entire frequency band, so that the amplitude fluctuation of the signal obtained after gain flattening processing within the specified frequency band does not exceed a preset fluctuation amplitude, and the signal obtained after gain flattening processing is output as a radio frequency signal.

[0009] Optionally, the specified frequency band covered by the radio frequency signal output is pre-divided into at least two sub-bands with different frequency characteristics, and each sub-band is pre-configured with a band optimization strategy; wherein, the band optimization strategy for a sub-band includes at least: a preferred phase-locked loop local oscillator frequency value, phase-locked loop configuration parameters corresponding to the preferred phase-locked loop local oscillator frequency value, and a recommended digital frequency synthesis unit for the corresponding sub-band; The optimization calculation method includes the following steps: According to the target frequency in the frequency switching command, the subband to which the target frequency belongs is taken as the target subband, and the band optimization strategy corresponding to the target subband is called. Based on the preferred phase-locked loop local oscillator frequency value in the invoked band optimization strategy and the target frequency, the required target intermediate frequency is dynamically calculated, and a corresponding fine frequency control word is generated according to the target intermediate frequency. Based on the phase-locked loop configuration parameters in the invoked band optimization strategy and the preferred phase-locked loop local oscillator frequency value, a phase-locked loop frequency control word is generated, and the recommended digital frequency synthesis unit is used as the target digital frequency synthesis unit. Based on the generated fine frequency control word, phase-locked loop frequency control word, and target digital frequency synthesis unit, a target frequency control command is generated. The step of performing phase-locked processing on the first reference signal to generate a local oscillator signal includes: Based on the phase-locked loop frequency control word determined by the optimization calculation method, the phase-locked loop is configured to generate a local oscillator signal with the preferred phase-locked loop local oscillator frequency value.

[0010] Optionally, the method further includes: Based on the current target frequency, historical frequency hopping sequences, or preset frequency hopping patterns, the system can dynamically predict the target frequency contained in the frequency switching commands received in the future. For each predicted target frequency, it is determined whether it belongs to a different subband than the current target frequency. For predicted target frequencies that do not belong to the same subband as the current target frequency, the optimization calculation method is executed, and the calculation result is used as a predicted frequency entry and stored in a preset prediction cache for updating. The prediction cache stores at least one predicted frequency entry, and each predicted frequency entry includes at least: the predicted target frequency, the subband to which the predicted target frequency belongs, the target frequency control command generated by executing the optimization calculation method according to the subband to which the predicted target frequency belongs, and the determined target digital frequency synthesis unit. In response to a frequency switching command, based on the target frequency in the frequency switching command, a preset optimization calculation method is executed to generate a target frequency control instruction, and frequency loading and signal path switching operations are executed simultaneously, including: In response to a frequency switching command, based on the target frequency in the latest response frequency switching command, the relationship between the target frequency and the sub-band of the previous response frequency switching command, and the content of the prediction cache, different frequency switching implementation methods are selectively invoked; wherein, the frequency switching implementation method includes at least: based on the target frequency in the frequency switching command, executing a preset optimization calculation method to generate a target frequency control command, and simultaneously executing frequency loading and signal path switching operations.

[0011] Optionally, in response to a frequency switching command, based on the target frequency in the latest response frequency switching command, the relationship between the target frequency and the sub-band of the target frequency before the latest response frequency switching command, and the contents of the prediction cache, different frequency switching implementation methods are selectively invoked, including: In response to a frequency switching command, determine whether the target frequency in the frequency switching command and the target frequency before the latest response frequency switching command belong to the same sub-band; If yes, then the preset first frequency switching implementation method is invoked and executed; if no, then the prediction cache is queried to determine whether there is a prediction frequency entry associated with the target frequency in the current response frequency switching command. If it exists, the preset second frequency implementation method is invoked and executed; if it does not exist, the preset third frequency switching implementation method is invoked and executed. The first frequency switching is implemented by controlling the target digital frequency synthesis unit that is currently generating intermediate frequency signals to update the fine frequency control word of the target digital frequency synthesis unit to the fine frequency control word value corresponding to the target frequency in the current response frequency switching command in a phase-continuous manner. The second frequency switching implementation method is as follows: read and apply the target frequency control instruction and target digital frequency synthesis unit stored in the predicted frequency entry associated with the target frequency in the current response frequency switching command, and then execute the frequency loading and signal path switching operation; The third frequency switching implementation method is as follows: based on the target frequency in the current response frequency switching command, the optimization calculation method is executed to generate the target frequency control command, and frequency loading and signal path switching operations are executed simultaneously. The step of configuring the phase-locked loop (PLL) according to the PLL frequency control word determined by the optimization calculation method to generate a local oscillator signal having the preferred PLL local oscillator frequency value includes: If the preset first frequency implementation method is called and executed, the signal generated by the current phase-locked loop process will be used as the local oscillator signal. If the preset second frequency implementation method is invoked and executed, the phase-locked loop is configured based on the phase-locked loop frequency control word in the predicted frequency entry associated with the target frequency in the frequency switching command of the current response to generate the local oscillator signal. If the preset third frequency implementation method is invoked and executed, the phase-locked loop is configured according to the phase-locked loop frequency control word determined by the optimization calculation method to generate a local oscillator signal with the preferred phase-locked loop local oscillator frequency value.

[0012] Optionally, the method further includes: Real-time acquisition and recording of operating parameters, including at least the frequency switching implementation methods and their time consumption during historical sub-band switching; Based on the collected operating parameters, a visual chart is generated and output for users to see; wherein, the visual chart includes at least a timing diagram of the switching strategy with time as the horizontal axis and the switching implementation method of the current frequency as the identifier.

[0013] Secondly, this application provides a radio frequency signal generation system for performing the radio frequency signal generation method described in the first aspect, including, The first phase-locked loop is used to acquire an external reference signal and generate a high-frequency reference signal; A power divider is used to split the high-frequency reference signal to obtain a first reference signal and a second reference signal. The controller is used to generate an intermediate frequency signal based on the second reference signal using a preset digital fine frequency synthesis method; The second phase-locked loop is used to perform phase-locked processing on the first reference signal to generate a local oscillator signal; A mixer is used to mix the intermediate frequency signal with the local oscillator signal to generate an initial radio frequency signal; A dynamic phase correction unit is used to dynamically correct the phase noise of the initial radio frequency signal or the signal generated during the generation of the initial radio frequency signal to obtain a corrected signal. A reconfigurable impedance matching network is used to adaptively impedance match the corrected signal to obtain an regulated signal, wherein the adaptive impedance matching is used to dynamically adjust the impedance characteristics according to the current frequency of the corrected signal. A broadband distributed amplifier is used to perform gain flattening processing on the regulated signal to balance the signal amplitude of the regulated signal across the entire frequency band, so that the amplitude fluctuation of the signal obtained after gain flattening processing within a specified frequency band does not exceed a preset fluctuation amplitude, and the signal obtained after gain flattening processing is output as a radio frequency signal.

[0014] Thirdly, this application provides a radio frequency signal generation apparatus, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any of the first aspects.

[0015] Fourthly, this application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and executed as described in any of the first aspects.

[0016] In summary, this application includes at least one of the following beneficial technical effects: In this application, a closed-loop phase noise suppression mechanism is constructed by introducing dynamic phase noise correction as a core step. Compared with existing technologies, its significant effect lies in its ability to actively and dynamically cancel the phase jitter introduced by traditional phase-locked loops and mixing processes, thereby significantly reducing the phase noise of the output RF signal over a wide frequency band, significantly improving the spectral purity and frequency stability of the signal, and providing an effective solution to the technical challenge of generating high-purity signals.

[0017] Furthermore, building upon the achievement of low-phase-noise signal generation, the loading of frequency control commands, the switching of the reference clock, and the switching of the intermediate frequency signal path are highly coordinated. This synchronization mechanism compresses the delay of the entire frequency switching process to an extremely short level, thereby achieving sub-microsecond (e.g., less than 100 nanoseconds) rapid frequency hopping capability while ensuring the aforementioned high signal purity. This resolves the contradiction between frequency resolution / purity and switching speed in traditional architectures, enabling this method to simultaneously meet the stringent requirements of high-performance radar, frequency-hopping communication, and other applications demanding both signal purity and agility.

[0018] Furthermore, the signal amplitude characteristics are optimized through two subsequent steps: adaptive impedance matching and gain flattening. Adaptive impedance matching dynamically adjusts the impedance according to the real-time frequency, ensuring efficient signal power transmission across the entire frequency band and reducing amplitude fluctuations caused by mismatch. Gain flattening further compensates for the frequency response of the devices. The synergistic effect of these two steps ultimately ensures that the amplitude fluctuation of the output RF signal is strictly controlled within a very small range (e.g., ≤±1dB) within a specified wide frequency band (e.g., 2-18GHz), achieving extremely high amplitude consistency. This ensures the stability of the signal power, which is crucial for applications requiring constant power output, such as test and measurement, and multi-carrier communication. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of the radio frequency signal generation method disclosed in the embodiments of this application.

[0021] Figure 2 This is a structural block diagram of the radio frequency signal generation system disclosed in the embodiments of this application. Detailed Implementation

[0022] The following is in conjunction with the appendix Figures 1-2 This application will be described in further detail.

[0023] This application provides a method for generating radio frequency signals, the specific process of which is described in detail below. Figure 1 Its execution entity is the radio frequency signal generation system; for details, refer to... Figure 2 The radio frequency (RF) signal generation system specifically includes: an external reference oscillator, a first phase-locked loop (PLL1), a second phase-locked loop (PLL2), an array consisting of N direct digital synthesis units (specifically, direct digital frequency synthesizers (DDS)) (i.e., a DDS array), a first high-speed gating network, a second high-speed gating network, a mixer, a dynamic phase correction unit, a reconfigurable impedance matching network, a broadband distributed amplifier, and a controller (specifically, a field-programmable gate array (FPGA)) that serves as the core of the RF signal generation system. The specific execution steps of the RF signal generation method within the RF signal generation system will be described below.

[0024] S101, acquire an external reference signal, generate a high-frequency reference signal, and process the high-frequency reference signal by splitting it to obtain a first reference signal and a second reference signal; S102, Based on the second reference signal, an intermediate frequency signal is generated by a preset digital fine frequency synthesis method; S103, perform phase-locked processing on the first reference signal to generate a local oscillator signal; S104 mixes the intermediate frequency signal and the local oscillator signal to generate the initial radio frequency signal; S105 performs dynamic phase noise correction on the initial radio frequency signal or the signal generated during the initial radio frequency signal generation process to obtain the corrected signal, and outputs the corrected signal as a radio frequency signal.

[0025] Specifically, the process of generating the intermediate frequency signal using a preset digital fine frequency synthesis method in step S102 includes the following steps: S1021, in response to the frequency switching command, based on the target frequency in the frequency switching command, a preset optimization calculation method is executed to generate a target frequency control instruction, and frequency loading and signal path switching operations are executed simultaneously; wherein, the target frequency control instruction includes at least: a phase-locked loop frequency control word for controlling the phase-locked processing, and a fine frequency control word for controlling a target digital frequency synthesis unit; the target digital frequency synthesis unit is selected from a preset plurality of digital frequency synthesis units based on the target frequency; S1022, the frequency loading and signal path switching operation includes the following steps: The fine frequency control word in the target frequency control instruction is loaded into the target digital frequency synthesis unit.

[0026] The second reference signal is guided to the target digital frequency synthesis unit through a preset first high-speed gating network, so that the target digital frequency synthesis unit executes the fine frequency control word and generates an intermediate frequency signal.

[0027] The intermediate frequency signal is guided to the node of the hybrid processing through a preset second high-speed gating network.

[0028] The step of "outputting the corrected signal as an RF signal" in S105 specifically includes the following steps: S1051, the corrected signal is subjected to adaptive impedance matching adjustment to obtain the adjusted signal, wherein the adaptive impedance matching adjustment is used to dynamically adjust the impedance characteristics according to the current frequency of the corrected signal. S1052 performs gain flattening on the adjusted signal to balance the signal amplitude of the adjusted signal across the entire frequency band, so that the amplitude fluctuation of the signal obtained after gain flattening within the specified frequency band does not exceed the preset fluctuation amplitude, and outputs the signal obtained after gain flattening as an RF signal.

[0029] In practice, the specific implementation principle of S101 is as follows: S101.1: An external reference oscillator (e.g., a 100MHz oven-controlled crystal oscillator OCXO) generates a highly stable, low-phase-noise external reference signal Ref_in; S101.2: The first phase-locked loop receives the external reference signal Ref_in. The first phase-locked loop adopts a conventional integer-N or fractional frequency division architecture, and internally includes a phase detector, a loop filter, and a voltage-controlled oscillator. In this embodiment, the first phase-locked loop multiplies the 100MHz signal to 1GHz and outputs a high-frequency reference signal Ref_high.

[0030] S101.3: The high-frequency reference signal Ref_high is split by a preset power divider to obtain the first reference signal Ref1 and the second reference signal Ref2. Ref1 and Ref2 are consistent in frequency and phase.

[0031] For S102, the specific implementation principle (i.e., the specific implementation principle of the optimization calculation method, frequency loading, and signal path switching operation) is as follows: The controller's internal memory contains multiple pre-configured frequency hopping sequences, each consisting of a series of ordered (target frequency, dwell time) pairs. Each target frequency corresponds to a pre-calculated frequency control command.

[0032] S102.1: When the controller receives a frequency switching command from an external interface or triggers frequency hopping according to internal timing, it searches for the corresponding target frequency control instruction (i.e., corresponding to S1021) based on the target frequency. It should be noted that each frequency control instruction includes a division ratio control word (i.e., the PLL frequency control word) for the second phase-locked loop and a fine frequency control word (FCW) for the target DDS (i.e., the target digital frequency synthesis unit).

[0033] S102.2: (Corresponding to S1022: Frequency Loading and Signal Path Switching Operation): The controller, via its high-speed parallel bus (such as SPI or parallel LVDS interface), instantaneously (usually within a few clock cycles) loads the FCW of the target DDS (i.e., the target digital frequency synthesis unit) contained in the target frequency control command into the internal register of the target DDS. Simultaneously, the controller sends a set of TTL control levels, causing the first high-speed gating network (specifically composed of gallium arsenide (GaAs) PIN diode switching units with an on / off time of less than 50ns) to switch within approximately 50ns, directing the second reference signal Ref_high to the clock input of the target DDS. Synchronously, the controller sends a control command to the second high-speed gating network, which has the same GaAs PIN diode high-speed switching structure as the first high-speed gating network, and directs the newly output intermediate frequency signal IF from the target DDS to the input of the mixer within approximately 50ns. Because the parallel loading of the controller and the nanosecond-level responses of the first and second high-speed gating networks are synchronously triggered under unified timing control, the total time from the issuance of the switching command to the mixer obtaining the new intermediate frequency signal is controlled within 100ns. It should be noted that the first high-speed gating network is a single-pole N-throw RF switch matrix whose common terminal receives the second reference signal Ref_high, and its N gating terminals are respectively connected to the clock input ports of the N DDS. The second high-speed gating network is an N-to-1 RF switch matrix, whose N input ports are respectively connected to the RF signal output ports of the N DDS, and its output port is connected to the input terminal of the mixer. Furthermore, the control ports of both the first and second high-speed gating networks are connected to the controller's digital I / O ports, and the controller generates synchronous switching control signals according to the target frequency to select the corresponding signal path.

[0034] The specific process by which the target DDS generates an intermediate frequency (IF) signal based on the second reference signal Ref2 and the target frequency control command is as follows: The target DDS, based on its internally loaded frequency control word (FCW) and using Ref2 as the clock, generates an IF signal with high frequency accuracy and resolution through its internal phase accumulator, sine lookup table, and digital-to-analog converter. For example, the frequency range of the IF can be between 10MHz and 400MHz.

[0035] The specific implementation principle of S103 is as follows: the first reference signal Ref1 is input to the second phase-locked loop (PLL) as its reference input. The second PLL also uses a high-performance PLL chip to generate a variable-frequency local oscillator signal LO. For example, its output frequency range can cover a certain intermediate frequency from 2-18GHz or directly cover the required frequency band.

[0036] The specific implementation principle of S104 is as follows: The intermediate frequency (IF) signal is guided to one input of the mixer through a second high-speed gating network. The local oscillator (LO) signal is input to the other input of the mixer. The mixer up-converts and mixes IF and LO to generate the initial radio frequency (RF) signal RF_initial. Its frequency is the sum or difference frequency of LO and IF, covering the target frequency band of 2-18 GHz.

[0037] For the S105, the specific implementation principle is as follows: the initial radio frequency signal RF_initial is sent to the dynamic phase correction unit. The hardware core of the dynamic phase correction unit is a high-speed digital signal processor or a soft-core processor integrated in the controller. It executes a dynamic bandwidth synthesis algorithm based on a Kalman filter, and the specific steps are as follows: S105.1: RF_initial is sampled via a downconversion link and a high-speed ADC (analog-to-digital converter, which can be integrated into the dynamic phase correction unit), or the error signal provided to the second phase-locked loop is sampled directly to obtain a digital sequence containing phase jitter information. This is the "signal generated during the process of generating the initial RF signal".

[0038] S105.2: Input the sampled data into the Kalman filter. The Kalman filter establishes a state-space model of the phase-locked loop (state variables may include phase error, frequency error, etc.), and estimates the phase noise components in the current loop that cannot be filtered out by traditional loop filters in real time through two recursive steps: prediction and update.

[0039] Specifically, the dynamic phase correction unit corrects the phase noise of the second phase-locked loop. It acquires the analog phase error voltage output by the phase detector in the second phase-locked loop and converts it into a digital error sequence e(n) via a high-speed analog-to-digital converter.

[0040] The Kalman filter establishes a discrete state-space model for a second-order phase-locked loop system. The state variables are chosen as phase error θ(n) and frequency error Δω(n), i.e., the state vector X(n) = [θ(n), Δω(n)]^T. Its state prediction equation is: X(n|n-1) = A·X(n-1) + W(n), where A is the state transition matrix and W(n) is the system process noise. The measurement equation is: Z(n) = H·X(n) + V(n), where H is the observation matrix, V(n) is the measurement noise, and Z(n) is e(n).

[0041] The algorithm executes the following recursive steps: First, state prediction and covariance prediction are performed; then, the Kalman increment K(n) is calculated using the current measurement value e(n); next, the state is updated to obtain the optimal estimated state X(n|n); finally, the estimated covariance is updated. The phase error component θ_est(n) in the optimal estimated state is extracted, filtered by a digital filter, and converted into an analog correction voltage V_corr. This V_corr is fed back to the loop filter of the second phase-locked loop through a digital-to-analog converter, and superimposed with the original control voltage, thereby canceling the estimated phase jitter in real time and realizing closed-loop dynamic correction of phase noise.

[0042] S105.3: The optimal phase error component θ_est(n) estimated in S105.2 and its converted analog correction voltage V_corr are used together as the source and basis of the correction signal (i.e., the corrected signal) in this step. Specifically, this correction signal can be represented as the analog correction voltage V_corr, fed back to the loop filter tuning terminal of the second phase-locked loop in the form of an analog voltage to fine-tune the VCO control voltage in real time; or, the result of digital processing of θ_est(n) can be represented as the fine-tuning amount of the frequency control word sent to the DDS in a digital pre-distortion manner. Through this closed-loop real-time prediction and compensation, the phase noise of the output signal is significantly suppressed. Testing shows that at a 10kHz frequency offset, the phase noise is better than -110dBc / Hz. This step fully corresponds to and supports the step of "dynamically correcting the phase noise of the initial RF signal or the signal generated during the initial RF signal generation process to obtain the corrected signal" in S105.

[0043] The specific implementation principle of the S1051 is as follows: the corrected signal is input into a reconfigurable impedance matching network for adaptive impedance matching. Specifically, the reconfigurable impedance matching network consists of a microstrip transmission line ML and M adjustable capacitor arrays C1, C2, ..., CM connected in parallel to it. Each adjustable capacitor array consists of several binary-weighted MEMS varactors or MOS varactors connected in parallel, and its total capacitance value can be continuously or incrementally controlled by a digital signal. The controller stores a frequency-capacitance value lookup table. Based on the current operating frequency of the RF signal (i.e., the target frequency), the controller looks up a set of optimal capacitance control codes in the table and sends them to the reconfigurable impedance matching network via a digital interface (such as I2C or GPIO). Each capacitor array in the reconfigurable impedance matching network adjusts its capacitance value according to the control code, thereby dynamically changing the impedance characteristics of the entire network. This ensures that the network achieves conjugate matching with the preceding and following stage circuits (such as the output impedance of the dynamic phase correction unit and the input impedance of the broadband distributed amplifier) ​​at the current frequency point, maximizing power transfer and reducing amplitude fluctuations caused by mismatch.

[0044] For the S1052, the impedance-matched signal (the regulated signal) is input to a broadband distributed amplifier, which employs a distributed amplification structure where the gate and drain parasitic capacitances of its transistors are absorbed into artificial transmission lines. To compensate for high-frequency roll-off, the broadband distributed amplifier incorporates multiple gain compensation circuits (e.g., introducing peaking inductors or negative feedback networks at specific nodes). A controller, or a controller built into the broadband distributed amplifier, can fine-tune the bias or component values ​​of certain compensation network sections based on frequency information (e.g., by controlling digitally adjustable resistors or capacitors), implementing gain fine-tuning compensation. After this processing, gain fluctuations are effectively suppressed across the entire 2-18 GHz frequency band.

[0045] After processing by S1051 and S1052, the signal finally output from the broadband distributed amplifier is the radio frequency signal. Within the entire 2-18GHz (i.e., the specified frequency band) operating frequency band, its power fluctuation is strictly controlled within ±1dB (i.e., the preset fluctuation amplitude).

[0046] Optionally, the specified frequency band covered by the RF signal output is pre-divided into at least two sub-bands with different frequency characteristics, and each sub-band is pre-configured with a band optimization strategy; wherein, the band optimization strategy for a sub-band includes at least: a preferred phase-locked loop local oscillator frequency value, phase-locked loop configuration parameters corresponding to the preferred phase-locked loop local oscillator frequency value, and a recommended digital frequency synthesis unit for the corresponding sub-band; In addition, the radio frequency signal generation method also includes the following steps: S201 dynamically predicts the target frequency contained in the frequency switching command received in the future time based on the current target frequency, historical frequency hopping sequence, or preset frequency hopping pattern.

[0047] S202, for each predicted target frequency, determine whether it belongs to a different sub-band than the current target frequency; for predicted target frequencies that do not belong to the same sub-band as the current target frequency, execute the optimization calculation method, and store the calculation result as a predicted frequency entry in a preset prediction cache for updating; wherein, the prediction cache stores at least one predicted frequency entry, and each predicted frequency entry includes at least: the predicted target frequency, the sub-band to which the predicted target frequency belongs, the target frequency control command generated by executing the optimization calculation method according to the sub-band to which the predicted target frequency belongs, and the determined target digital frequency synthesis unit.

[0048] S1021 specifically includes the following steps: S1021-1, in response to a frequency switching command, determine whether the target frequency in the frequency switching command and the target frequency before the latest response frequency switching command belong to the same sub-band.

[0049] S1021-2, if yes, then call the preset first frequency switching implementation method; if no, then query the prediction cache to determine whether there is a prediction frequency entry associated with the target frequency in the current response frequency switching command.

[0050] S1021-3, if it exists, then the preset second frequency implementation method is called; if it does not exist, then the preset third frequency switching implementation method is called.

[0051] The first frequency switching is implemented by controlling the target digital frequency synthesis unit that is currently generating intermediate frequency signals to update the fine frequency control word of the target digital frequency synthesis unit to the fine frequency control word value corresponding to the target frequency in the current response frequency switching command in a phase-continuous manner. The second frequency switching implementation method is as follows: read and apply the target frequency control instruction and target digital frequency synthesis unit stored in the predicted frequency entry associated with the target frequency in the current response frequency switching command, and then execute the frequency loading and signal path switching operation; The third frequency switching is implemented as follows: based on the target frequency in the current response frequency switching command, the optimization calculation method is executed to generate the target frequency control command, and frequency loading and signal path switching operations are executed simultaneously.

[0052] Accordingly, based on S1021-1, S1021-2, and S1021-3 included in S1021 above, S103 includes the following sub-steps: S1031: If the first frequency implementation method is specifically called and executed during the execution of S1021, then the signal generated by the current phase-locked loop processing is used as the local oscillator signal; S1032: If the second frequency implementation method is specifically called and executed during the execution of S1021, the phase-locked loop is configured based on the phase-locked loop frequency control word in the predicted frequency entry associated with the target frequency in the frequency switching command of the current response to generate the local oscillator signal. S1032: If the third frequency implementation method is specifically called and executed during the execution of S1021, then the phase-locked loop is configured according to the phase-locked loop frequency control word determined by the optimization calculation method to generate a local oscillator signal with the preferred phase-locked loop local oscillator frequency value. Furthermore, the optimization calculation method mentioned in S1021-1, S1021-2, and S1021-3 specifically includes the following steps: S301, according to the target frequency in the frequency switching command, the sub-band to which the target frequency belongs is taken as the target sub-band, and the band optimization strategy corresponding to the target sub-band is called.

[0053] S302, based on the preferred phase-locked loop local oscillator frequency value in the invoked band optimization strategy and the target frequency, dynamically calculate the required target intermediate frequency, and generate the corresponding fine frequency control word according to the target intermediate frequency.

[0054] S303, based on the phase-locked loop configuration parameters in the invoked band optimization strategy and the preferred phase-locked loop local oscillator frequency value, generate a phase-locked loop frequency control word, and use the recommended digital frequency synthesis unit as the target digital frequency synthesis unit.

[0055] S304 generates the target frequency control command based on the generated fine frequency control word, phase-locked loop frequency control word, and target digital frequency synthesis unit.

[0056] In implementation, after the RF signal generation system is powered on or reset, the following initialization configuration is performed first: 1. Subband division: Divide the RF output frequency band to be covered (i.e., the specified frequency band range mentioned above, such as 2-18GHz) into K subbands. For example, it can be divided into: subband 1 (2-6GHz), subband 2 (6-12GHz), and subband 3 (12-18GHz). The division principle can be based on the optimal tuning curve of the voltage-controlled oscillator (VCO) of the phase-locked loop (PLL2) or the gain flat range of the distributed amplifier. 2. Create and configure the band optimization strategy lookup table: Create a record for each subband in the controller's non-volatile memory, i.e., the band optimization strategy. Each band optimization strategy includes at least: the preferred PLL local oscillator frequency value (F_LO_opt): This is one or more specific local oscillator frequencies that have the lowest phase noise and best spurious performance in the subband, obtained through experimental determination or simulation optimization. For example, for sub-band 1, the preferred local oscillator might be set to 5.5 GHz. Phase-locked loop (PLL) configuration parameters refer to a set of optimal loop parameters, such as loop bandwidth, charge pump current, and phase margin configuration word, when PLL2 operates at this preferred local oscillator frequency. It also includes a recommended digital frequency synthesis unit identifier, which specifies the default DDS associated with this sub-band. This can be selected based on the spurious performance of the DDS in the corresponding intermediate frequency range of this sub-band.

[0057] The above summarizes all the initialization configuration details, which can be manually set. After completing the initialization configuration, the RF signal generation method in practical applications also includes the following: I. Background Prediction and Cache Maintenance Tasks (corresponding to S201 and S202 above): This task, as a low-priority background process, runs continuously or periodically in the controller, independent of the main signal generation path. Its purpose is to prepare in advance for potential time-consuming cross-sub-band frequency hopping. Specifically, it includes the following steps: Step P1 (Prediction): The controller uses a preset prediction algorithm to calculate the target frequency (hereinafter referred to as the predicted target frequency) contained in the frequency switching command acquired in the future, based on the currently output target frequency (hereinafter referred to as the target frequency in use), the pre-stored frequency hopping sequence history, or a known frequency hopping pattern. For example, if the frequency hopping sequence is linear step, the next frequency can be predicted as A+ΔF; if it is a pseudo-random sequence, a small prior sequence window can be used for matching prediction. Specifically, this embodiment adopts a deterministic prediction method based on a fixed frequency hopping sequence lookup table: a complete and ordered list of frequency hopping frequency values, called the main frequency hopping sequence, is pre-stored in the controller's internal memory. This sequence contains all possible target frequencies that the system may request and their order. The controller maintains a current frequency pointer, pointing to the position of the currently used target frequency in the main frequency hopping sequence. Then, the following prediction steps are executed: P1-1: Read the current frequency pointer.

[0058] P1-2: Based on the preset prediction depth (e.g., predicting the next 1 jump), move the current frequency pointer backward by N positions (N=1).

[0059] P1-3: Read the frequency value in the main frequency hopping sequence pointed to by the current frequency pointer after the movement. This value is the predicted target frequency.

[0060] Example: If the primary frequency hopping sequence is [1GHz, 2GHz, 5GHz, 10GHz...], and the currently used target frequency is 2GHz (the pointer is at the second position), then the predicted next target frequency is 5GHz. Each time a frequency switching command is successfully responded to, the controller updates the current frequency pointer to the position corresponding to the new frequency.

[0061] Step P2 (Judgment and Filtering): For each predicted target frequency predicted in step P1, the controller determines whether it belongs to the same sub-band as the target frequency currently in use. For predicted target frequencies that do not belong to the same sub-band, the following steps P3 and P4 are executed.

[0062] Step P3 (Pre-calculation): For each target frequency requiring pre-calculation, the controller executes an optimization calculation method (corresponding to S301, S302, S303, and S304 mentioned above). The specific flow of the optimization calculation method is as follows: Based on the predicted target frequency, query the corresponding sub-band (referred to as the target sub-band), and read the preferred PLL local oscillator frequency value F_LO_opt (e.g., 10GHz) and related PLL configuration parameters from the band optimization strategy table.

[0063] The required intermediate frequency (i.e., the target intermediate frequency) is dynamically calculated as F_IF_calc = |predicted target frequency value - F_LO_opt|.

[0064] Generate the corresponding DDS fine frequency control word (FCW) and generate the PLL frequency control word (i.e., the frequency division ratio) that controls the PLL2 output target subband to select the local oscillator frequency value F_LO_opt of the PLL (i.e., the frequency division ratio).

[0065] Based on the recommended digital frequency synthesis unit identifier in the band optimization strategy table, the recommended target DDS unit (i.e., target digital frequency synthesis unit) for the target subband is determined.

[0066] The process of generating the DDS Fine Frequency Control Word (FCW) is as follows: The DDS output frequency F_out is determined by its system clock F_clk and the frequency control word FCW, using the formula: F_out = (FCW / 2^M) * F_clk, where M is the bit width of the DDS's internal phase accumulator (e.g., 32-bit or 48-bit), a known fixed value. Therefore, the FCW generation steps are as follows: Based on the calculated target intermediate frequency F_IF_calc and the current reference clock frequency F_clk provided to the DDS (i.e., the frequency of the second reference signal Ref_high, e.g., 1GHz), the theoretical value is calculated using the formula FCW = (F_IF_calc / F_clk) * 2^M, and then rounded to the nearest integer as the final FCW.

[0067] The generation process of the PLL frequency control word for the preferred PLL local oscillator frequency value F_LO_opt of the target sub-band output of PLL2 is as follows: The second PLL (PLL2) is usually a fractional-division PLL. Its output frequency F_lo is determined by the reference frequency F_ref (i.e., the frequency of the first reference signal Ref1) and the division ratio N (including the integer part Int and the fractional part Frac), with the formula: F_lo=(Int + Frac / 2^P)* F_ref, where P is the precision bits of the fractional divider. Therefore, the corresponding generation steps are: In order to generate the preferred PLL local oscillator frequency value F_LO_opt, the corresponding division ratio needs to be calculated. That is: First, calculate the total division ratio: N_total=F_LO_opt / F_ref. Decompose N_total into the integer part Int and the fractional part Frac: Int = floor(N_total), Frac=round((N_total-Int)* 2^P). The final generated phase-locked loop frequency control word consists of two digital fields, Int and Frac, which are combined and sent according to the programming format of the PLL2 chip (usually written to a specific register via the SPI interface).

[0068] Step P4 (Cache): The controller also packages the calculation results of step P3 (including: predicted target frequency, calculated fine frequency control word, phase-locked loop frequency control word, and target digital frequency synthesis unit identifier) ​​into a predicted frequency entry and stores it in a high-speed prediction cache (such as BRAM) inside the controller. This cache adopts an associative structure similar to a CPU cache, supporting fast lookup by target frequency. Old entries can be updated and replaced according to strategies such as LRU (Least Recently Used).

[0069] II. Real-time frequency switching command response process (corresponding to S1021-1, S1021-2, and S1021-3 above) mainly involves the following steps when the controller's communication interface receives an external frequency switching command containing the target frequency (hereinafter referred to as the target frequency to be used). This triggers a high-priority interrupt service routine, which executes the adaptive switching strategy (i.e., selectively calling different frequency switching implementation methods): Step R1 (Acquisition and Judgment): The controller reads the target frequency to be used and acquires the target frequency currently in use. First, it determines whether the target frequency currently in use and the target frequency to be used belong to the same sub-band. This is the first and fastest decision branch point.

[0070] If the target frequency being used and the target frequency to be used belong to the same sub-band, a preset first frequency switching implementation method is adopted: the controller keeps the local oscillator frequency of the target digital frequency synthesis unit (i.e., DDS) and PLL2 corresponding to the target frequency being used unchanged. This means that when performing the step of "performing phase-locked loop processing on the first reference signal to generate a local oscillator signal" (i.e., S103), the controller determines that this switching belongs to the first frequency implementation method. Therefore, it does not send a new phase-locked loop frequency control word to PLL2, nor does it trigger its relocking process. Instead, it directly uses the signal currently stably output by PLL2 as the local oscillator signal for this mixing process (i.e., corresponding to S1031). The controller updates a new, fine frequency control word corresponding to the target frequency to be used to the target digital frequency synthesis unit in a phase-continuous manner within a single reference clock cycle through the fast frequency modulation port (such as the parallel loading port) of DDS. The output frequency of the target digital frequency synthesis unit switches to the new value (i.e., the new fine frequency control word) almost without interruption. It should be noted that the DDS chip selected in this embodiment (such as AD9910, AD9959, etc.) supports fast switching between parallel data ports and digital ramp modulation (DRG) or profile pins. These functions are the hardware foundation for achieving nanosecond-level, phase-continuous frequency switching. Accordingly, the specific implementation process of phase-continuous fast switching is as follows: During the normal operation of the DDS outputting the currently used target frequency F_A, the controller pre-writes the calculated fine frequency control word FCW_B corresponding to the target frequency F_B to be used into a dedicated buffer register inside the DDS through the parallel data port of the DDS, instead of directly writing it to its working register. This operation does not affect the current output. The controller configures a dedicated I / O pin (such as IO_UPDATE) to trigger the frequency switching of the DDS. When a switch is required, the controller sends a high-level pulse to this pin. Inside the DDS chip, the edge of the IO_UPDATE pulse signal triggers a synchronization event, atomically and synchronously loading the FCW (FCW_B) corresponding to the target frequency to be used from the buffer register into the working register. Because the state of the internal phase accumulator of the DDS is not reset at the moment of switching, and the replacement of the old and new frequency control words is completed synchronously within one clock cycle, the frequency of its output signal changes from F_A to F_B, but the phase transitions continuously without any jump. The entire switching process is completed within one system clock cycle after receiving the trigger pulse.

[0071] This process avoids any RF switch switching and PLL relocking time, achieving sub-microsecond (or even nanosecond) switching, making it the fastest path.

[0072] If the target frequency being used and the target frequency to be used do not belong to the same subband, then proceed to step R2 (cache lookup).

[0073] Step R2: The controller queries the prediction buffer using the target frequency to be used as the key. If a prediction frequency entry matching the target frequency to be used is found in the prediction buffer (i.e., the predicted target frequency contained in the prediction frequency entry is consistent with the target frequency to be used, hereinafter referred to as the matched prediction frequency entry), the preset second frequency switching implementation method is adopted: the controller directly reads all the pre-calculated results in the matched prediction frequency entry: phase-locked loop frequency control word, fine frequency control word, and target digital frequency synthesis unit identifier.

[0074] Then, the controller performs frequency loading and signal path switching operations (the specific operation process has been disclosed above, i.e., S102.2): the phase-locked loop frequency control word is sent to the second phase-locked loop PLL2, instructing it to start switching to the preferred local oscillator frequency F_LO_opt; simultaneously, the controller controls the first and second high-speed gating networks to switch the clock and signal paths to the target digital frequency synthesis unit specified in the matched predicted frequency entry, and loads the corresponding fine-grained frequency control word. Since the complex calculations required for frequency hopping (preferred local oscillator selection, intermediate frequency calculation, etc.) have been completed in advance in the background, only hardware control actions need to be executed when responding to commands, thereby significantly shortening the delay of cross-subband switching and ensuring the signal quality after switching (due to the use of optimized parameters).

[0075] If no predicted frequency entry matching the target frequency is found in the prediction buffer, a preset third frequency switching implementation method is adopted: A complete optimization calculation method is executed (the specific principle has been disclosed previously): This involves determining the sub-band based on the target frequency, reading the preferred PLL local oscillator frequency value F_LO_opt (e.g., 10GHz) and related PLL configuration parameters from the band optimization strategy table. The required intermediate frequency (i.e., the target intermediate frequency) F_IF_calc = |predicted target frequency value - F_LO_opt| is dynamically calculated. The corresponding DDS fine frequency control word (FCW) is generated, along with the PLL frequency control word (i.e., the division ratio) that controls the PLL2 output of the preferred PLL local oscillator frequency value F_LO_opt for the target sub-band. Based on the recommended digital frequency synthesis unit identifier in the band optimization strategy table, the recommended target DDS unit (i.e., the target digital frequency synthesis unit) for the target sub-band is determined. Next, the frequency loading and signal path switching operations are performed: the phase-locked loop (PLL) frequency control word is sent to the second PLL2, instructing it to begin switching to the preferred local oscillator frequency F_LO_opt; simultaneously, the controller controls the first and second high-speed gating networks to switch the clock and signal paths to the target digital frequency synthesis unit specified in the matched predicted frequency entry, and loads the corresponding fine-grained frequency control word. This third frequency switching implementation serves as a backup or safety measure for the system, ensuring that the system can complete frequency switching with optimal performance under any circumstances (such as entirely new, unpredictable frequency hopping sequences), despite a slightly longer switching delay.

[0076] Optionally, the radio frequency signal generation method may further include the following steps: Real-time acquisition and recording of operating parameters, including at least the frequency switching implementation methods and their time consumption during historical sub-band switching; Based on the collected operating parameters, a visual chart is generated and output for user reference; wherein, the visual chart includes at least a switching strategy time sequence diagram with time as the horizontal axis and the currently used frequency switching implementation method as the identifier. During implementation, the monitoring software module in the controller collects and records multi-dimensional operating parameters in real time during system operation through the following methods, with all parameters bearing a timestamp: 1. Frequency Hopping Sequence and Dwell Time Recording: The controller captures each issued frequency switching command and its target frequency. This data is recorded chronologically to form a historical frequency hopping sequence. Simultaneously, a high-precision timer (such as a nanosecond-level counter inside the controller) records the actual dwell time at each frequency point—the time interval from when the frequency output stabilizes until the next switching command is responded to.

[0077] 2. Switching Strategy and Time Consumption Statistics: The controller acquires the actual frequency switching implementation method (first frequency switching method, second frequency switching method, or third frequency switching method) invoked for each switch and records the frequency switching method used for each switch. Simultaneously, for each switch, it records the total switching time (time from receiving the command to the stable output of the new frequency signal) and subdivided time consumption (e.g., decision time, PLL relocking time, DDS stabilization time, switch switching time). This is crucial for analyzing the performance bottlenecks of different strategies.

[0078] 3. RF Performance Monitoring: The digital signal processor inside the dynamic phase correction unit acquires or calculates the estimated phase noise of the current output signal at a specific frequency offset (e.g., 10kHz, 100kHz) in real time. A broadband RF power detector is coupled to the output of the broadband distributed amplifier. The analog voltage output by the detector is sampled by an ADC, and the real-time fluctuation value (dB) of the signal amplitude is calculated by the monitoring software. Real-time phase noise and amplitude fluctuation data at each frequency point are recorded at a certain sampling rate (e.g., several times per second).

[0079] 4. Prediction Algorithm Performance Statistics: Statistics on prediction cache hit rate (number of hits / total number of queries). Furthermore, prediction accuracy can be recorded, which is the proportion of the predicted "target frequency" that matches the actual received target frequency.

[0080] Next, the controller periodically (e.g., after each frequency hopping pattern is completed, or according to user instructions) summarizes, analyzes, and visualizes the massive amounts of raw data collected. The resulting visualizations are: 1. Handover Performance Heatmap: The entire radio frequency band (e.g., 2-18GHz) is used as the horizontal axis. The band is divided into a fine grid. For each grid cell, all handover records to the corresponding frequency point are counted, and the average handover success rate (number of successful handovers / number of attempts) and average handover time are calculated. Performance indicators are represented using color gradients. For example, a green-to-red gradient represents handover time from short to long, or light and dark colors represent handover success rates from high to low. The final result is a two-dimensional color heatmap covering the entire frequency band, visually displaying the system's handover performance health across different frequency bands.

[0081] 2. Switching Strategy Timing Diagram: The time axis is used as the horizontal axis. On the time axis, bars of different heights or colors are used to identify the actual frequency switching methods used by the system in each time period (e.g., short blue bars for the first frequency switching method, medium green bars for the second, and long red bars for the third). The length of the bars corresponds to the dwell time of the corresponding frequency. A bar chart is generated that scrolls over time. Users can clearly see how the intelligent switching strategy works dynamically during task execution (e.g., whether a large number of first frequency switching methods were successfully activated during rapid continuous frequency hopping, and the hit rate of second frequency switching methods during cross-band frequency hopping).

[0082] 3. Phase Noise Distribution Box Plot: The acquired phase noise data is grouped by sub-band. For each sub-band (e.g., sub-band 1: 2-6GHz), the minimum, first quartile, median, third quartile, and maximum values ​​of the phase noise data at all sampling points within that band are calculated, and discrete outliers can be marked. A vertical box plot is generated for each sub-band, and the box plots for all sub-bands are displayed side-by-side. This chart clearly and professionally demonstrates the overall phase noise level, stability, and consistency of the system across each sub-band, providing crucial visual evidence of its clean (low phase noise) performance.

[0083] Finally, an embedded graphical interface runs on the touchscreen of the RF signal generator device's front panel. This interface provides multiple tabs that display the aforementioned switching performance heatmap, switching strategy timing diagram, and bit noise distribution statistics box plot in real time, allowing users to interactively select and view statistical data for different time periods. Alternatively, the data stream and generated charts can be encapsulated into standard protocols (such as WebSocket, HTTP / JSON) and sent to the user's host computer control software or web browser via an Ethernet interface. Users can obtain the same monitoring experience on a remote computer as on a local display.

[0084] This application also discloses a radio frequency signal generation system, including: The first phase-locked loop is used to acquire an external reference signal and generate a high-frequency reference signal; A power divider is used to split the high-frequency reference signal to obtain a first reference signal and a second reference signal. The controller is used to generate an intermediate frequency signal based on the second reference signal using a preset digital fine frequency synthesis method; The second phase-locked loop is used to perform phase-locked processing on the first reference signal to generate a local oscillator signal; A mixer is used to mix the intermediate frequency signal with the local oscillator signal to generate an initial radio frequency signal; A dynamic phase correction unit is used to dynamically correct the phase noise of the initial radio frequency signal or the signal generated during the generation of the initial radio frequency signal to obtain a corrected signal. A reconfigurable impedance matching network is used to adaptively impedance match the corrected signal to obtain an regulated signal, wherein the adaptive impedance matching is used to dynamically adjust the impedance characteristics according to the current frequency of the corrected signal. A broadband distributed amplifier is used to perform gain flattening on the regulated signal to balance the signal amplitude of the regulated signal across the entire frequency band, ensuring that the amplitude fluctuation of the signal obtained after gain flattening within a specified frequency band does not exceed a preset fluctuation range. The signal obtained after gain flattening is then output as a radio frequency signal.

[0085] Optionally, the controller is configured to respond to a frequency switching command, and based on the target frequency in the frequency switching command, execute a preset optimization calculation method to generate a target frequency control instruction, and simultaneously execute frequency loading and signal path switching operations; wherein, the target frequency control instruction includes at least: a phase-locked loop frequency control word for controlling the phase-locked processing, and a fine frequency control word for controlling a target digital frequency synthesis unit; the target digital frequency synthesis unit is selected from a preset plurality of digital frequency synthesis units based on the target frequency; the frequency loading and signal path switching operation includes the following steps: loading the fine frequency control word in the target frequency control instruction into the target digital frequency synthesis unit; guiding the second reference signal to the target digital frequency synthesis unit through a preset first high-speed gating network, so that the target digital frequency synthesis unit executes the fine frequency control word and generates an intermediate frequency signal; guiding the intermediate frequency signal to the node of the mixing process through a preset second high-speed gating network.

[0086] Optionally, it also includes an optimization calculation module, used to determine the subband to which the target frequency belongs as the target subband based on the target frequency in the frequency switching command, and to call the band optimization strategy corresponding to the target subband; dynamically calculate the required target intermediate frequency based on the preferred phase-locked loop local oscillator frequency value in the called band optimization strategy and the target frequency, and generate a corresponding fine frequency control word based on the target intermediate frequency; generate a phase-locked loop frequency control word based on the phase-locked loop configuration parameters in the called band optimization strategy and the preferred phase-locked loop local oscillator frequency value, and use the recommended digital frequency synthesis unit as the target digital frequency synthesis unit; and generate a target frequency control instruction based on the generated fine frequency control word, phase-locked loop frequency control word, and target digital frequency synthesis unit.

[0087] The controller is used to configure the phase-locked loop (PLL) according to the PLL frequency control word determined by the optimization calculation method, so as to generate a local oscillator signal having the preferred PLL local oscillator frequency value.

[0088] Optionally, it also includes a frequency prediction module, used to dynamically predict the target frequency contained in the frequency switching command received in the future time based on the current target frequency, historical frequency hopping sequence or preset frequency hopping pattern; it is also used to determine whether each predicted target frequency belongs to a different subband than the current target frequency; for predicted target frequencies that do not belong to the same subband as the current target frequency, the optimization calculation method is executed, and the calculation result is stored as a predicted frequency entry in a preset prediction cache for updating; wherein, the prediction cache stores at least one predicted frequency entry, and each predicted frequency entry includes at least: the predicted target frequency, the subband to which the predicted target frequency belongs, the target frequency control command generated by executing the optimization calculation method according to the subband to which the predicted target frequency belongs, and the determined target digital frequency synthesis unit.

[0089] Optionally, the controller is also configured to respond to a frequency switching command by selectively invoking different frequency switching implementation methods based on the target frequency in the latest response frequency switching command, the relationship between the target frequency and the sub-band of the previous response frequency switching command, and the contents of the prediction cache; wherein the frequency switching implementation method includes at least: executing a preset optimization calculation method based on the target frequency in the frequency switching command to generate a target frequency control command, and simultaneously executing frequency loading and signal path switching operations.

[0090] Optionally, the controller is further configured to respond to a frequency switching command by determining whether the target frequency in the frequency switching command and the target frequency before the latest response frequency switching command belong to the same sub-band; if yes, then a preset first frequency switching implementation mode is invoked and executed; if no, then the prediction cache is queried to determine whether there is a prediction frequency entry associated with the target frequency in the currently responded frequency switching command; if there is, then a preset second frequency implementation mode is invoked and executed; if not, then a preset third frequency switching implementation mode is invoked and executed; wherein, the first frequency switching implementation mode is: controlling the target digital frequency synthesis unit currently generating the intermediate frequency signal, so as to... The fine frequency control word of the target digital frequency synthesis unit is updated in a phase-continuous manner to the fine frequency control word value corresponding to the target frequency in the current response frequency switching command; the second frequency switching implementation method is: reading and applying the target frequency control instruction and target digital frequency synthesis unit stored in the predicted frequency entry associated with the target frequency in the current response frequency switching command, and then performing the frequency loading and signal path switching operation; the third frequency switching implementation method is: according to the target frequency in the current response frequency switching command, the optimization calculation method is executed to generate the target frequency control instruction, and the frequency loading and signal path switching operation is executed synchronously.

[0091] The controller is further configured to, if a preset first frequency implementation mode is invoked and executed, use the signal generated by the current phase-locked loop (PLL) processing as the local oscillator signal; if a preset second frequency implementation mode is invoked and executed, configure the PLL based on the PLL frequency control word in the predicted frequency entry associated with the target frequency in the frequency switching command of the current response to generate the local oscillator signal; if a preset third frequency implementation mode is invoked and executed, configure the PLL according to the PLL frequency control word determined by the optimization calculation method to generate a local oscillator signal having the preferred PLL local oscillator frequency value.

[0092] Optionally, a visualization and statistics module is also included, which is used to collect and record operating parameters in real time. The operating parameters include at least the frequency switching implementation methods actually called during the switching of each sub-band in history and their time consumption. Based on the collected operating parameters, a visualization chart is generated and output for users to see. The visualization chart includes at least a switching strategy time sequence diagram with time as the horizontal axis and the currently used frequency switching implementation method as the identifier.

[0093] This application also discloses a radio frequency signal generation device, which includes a memory and a processor. The memory stores a computer program that can be loaded by the processor and executed as described above for generating radio frequency signals.

[0094] This application also discloses a computer-readable storage medium that stores a computer program that can be loaded by a processor and executed as described above in the radio frequency signal generation method. The computer-readable storage medium includes, for example, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

Claims

1. A method for generating radio frequency signals, characterized in that, include: An external reference signal is acquired, a high-frequency reference signal is generated, and the high-frequency reference signal is processed by splitting to obtain a first reference signal and a second reference signal. Based on the second reference signal, an intermediate frequency signal is generated using a preset digital fine frequency synthesis method; The first reference signal is subjected to phase-locked loop processing to generate a local oscillator signal; The intermediate frequency signal and the local oscillator signal are mixed to generate an initial radio frequency signal; The phase noise of the initial radio frequency signal or the signal generated during the generation of the initial radio frequency signal is dynamically corrected to obtain a corrected signal, and the corrected signal is output as a radio frequency signal.

2. The radio frequency signal generation method according to claim 1, characterized in that, The generation of the intermediate frequency signal through a preset digital fine frequency synthesis method includes: In response to a frequency switching command, a preset optimization calculation method is executed based on the target frequency in the frequency switching command to generate a target frequency control instruction, and frequency loading and signal path switching operations are executed simultaneously. The target frequency control instruction includes at least: a phase-locked loop frequency control word for controlling the phase-locked processing, and a fine frequency control word for controlling a target digital frequency synthesis unit; the target digital frequency synthesis unit is selected from a plurality of preset digital frequency synthesis units based on the target frequency. The frequency loading and signal path switching operation includes the following steps: The fine frequency control word in the target frequency control instruction is loaded into the target digital frequency synthesis unit; The second reference signal is guided to the target digital frequency synthesis unit through a preset first high-speed gating network, so that the target digital frequency synthesis unit executes the fine frequency control word and generates an intermediate frequency signal; The intermediate frequency signal is guided to the mixing node through a preset second high-speed gating network.

3. The radio frequency signal generation method according to claim 2, characterized in that, The step of outputting the corrected signal as a radio frequency signal includes: The corrected signal is subjected to adaptive impedance matching adjustment to obtain an adjusted signal, wherein the adaptive impedance matching adjustment is used to dynamically adjust the impedance characteristics according to the current frequency of the corrected signal. The adjusted signal is subjected to gain flattening processing to balance the signal amplitude of the adjusted signal across the entire frequency band, so that the amplitude fluctuation of the signal obtained after gain flattening processing within the specified frequency band does not exceed a preset fluctuation amplitude, and the signal obtained after gain flattening processing is output as a radio frequency signal.

4. The radio frequency signal generation method according to claim 2, characterized in that, The specified frequency band range covered by the radio frequency signal output is pre-divided into at least two sub-bands with different frequency characteristics, and each sub-band is pre-configured with a band optimization strategy; wherein, the band optimization strategy for a sub-band includes at least: a preferred phase-locked loop local oscillator frequency value, phase-locked loop configuration parameters corresponding to the preferred phase-locked loop local oscillator frequency value, and a recommended digital frequency synthesis unit for the corresponding sub-band. The optimization calculation method includes the following steps: According to the target frequency in the frequency switching command, the subband to which the target frequency belongs is taken as the target subband, and the band optimization strategy corresponding to the target subband is called. Based on the preferred phase-locked loop local oscillator frequency value in the invoked band optimization strategy and the target frequency, the required target intermediate frequency is dynamically calculated, and a corresponding fine frequency control word is generated according to the target intermediate frequency. Based on the phase-locked loop configuration parameters in the invoked band optimization strategy and the preferred phase-locked loop local oscillator frequency value, a phase-locked loop frequency control word is generated, and the recommended digital frequency synthesis unit is used as the target digital frequency synthesis unit. Based on the generated fine frequency control word, phase-locked loop frequency control word, and target digital frequency synthesis unit, a target frequency control instruction is generated; The step of performing phase-locked processing on the first reference signal to generate a local oscillator signal includes: Based on the phase-locked loop frequency control word determined by the optimization calculation method, the phase-locked loop is configured to generate a local oscillator signal with the preferred phase-locked loop local oscillator frequency value.

5. The radio frequency signal generation method according to claim 4, characterized in that, The method further includes: Based on the current target frequency, historical frequency hopping sequences, or preset frequency hopping patterns, the system can dynamically predict the target frequency contained in the frequency switching commands received in the future. For each predicted target frequency, it is determined whether it belongs to a different subband than the current target frequency. For predicted target frequencies that do not belong to the same subband as the current target frequency, the optimization calculation method is executed, and the calculation result is used as a predicted frequency entry and stored in a preset prediction cache for updating. The prediction cache stores at least one predicted frequency entry, and each predicted frequency entry includes at least: the predicted target frequency, the subband to which the predicted target frequency belongs, the target frequency control command generated by executing the optimization calculation method according to the subband to which the predicted target frequency belongs, and the determined target digital frequency synthesis unit. In response to a frequency switching command, based on the target frequency in the frequency switching command, a preset optimization calculation method is executed to generate a target frequency control instruction, and frequency loading and signal path switching operations are executed simultaneously, including: In response to a frequency switching command, based on the target frequency in the latest response frequency switching command, the relationship between the target frequency and the sub-band of the previous response frequency switching command, and the content of the prediction cache, different frequency switching implementation methods are selectively invoked; wherein, the frequency switching implementation method includes at least: based on the target frequency in the frequency switching command, executing a preset optimization calculation method to generate a target frequency control command, and simultaneously executing frequency loading and signal path switching operations.

6. The radio frequency signal generation method according to claim 5, characterized in that, In response to a frequency switching command, based on the target frequency in the latest response command, the relationship between the target frequency and the sub-band of the previous response command, and the contents of the prediction cache, different frequency switching implementation methods are selectively invoked, including: In response to a frequency switching command, determine whether the target frequency in the frequency switching command and the target frequency before the latest response frequency switching command belong to the same sub-band; If yes, then the preset first frequency switching implementation method is invoked and executed; if no, then the prediction cache is queried to determine whether there is a prediction frequency entry associated with the target frequency in the current response frequency switching command. If it exists, the preset second frequency switching implementation method is invoked and executed; if it does not exist, the preset third frequency switching implementation method is invoked and executed. The first frequency switching is implemented by controlling the target digital frequency synthesis unit that is currently generating intermediate frequency signals to update the fine frequency control word of the target digital frequency synthesis unit to the fine frequency control word value corresponding to the target frequency in the current response frequency switching command in a phase-continuous manner. The second frequency switching implementation method is as follows: read and apply the target frequency control instruction and target digital frequency synthesis unit stored in the predicted frequency entry associated with the target frequency in the current response frequency switching command, and then execute the frequency loading and signal path switching operation; The third frequency switching implementation method is as follows: based on the target frequency in the current response frequency switching command, the optimization calculation method is executed to generate the target frequency control command, and frequency loading and signal path switching operations are executed simultaneously. The step of configuring the phase-locked loop (PLL) according to the PLL frequency control word determined by the optimization calculation method to generate a local oscillator signal having the preferred PLL local oscillator frequency value includes: If the preset first frequency implementation method is called and executed, the signal generated by the current phase-locked loop process will be used as the local oscillator signal. If the preset second frequency implementation method is invoked and executed, the phase-locked loop is configured based on the phase-locked loop frequency control word in the predicted frequency entry associated with the target frequency in the frequency switching command of the current response to generate the local oscillator signal. If the preset third frequency implementation method is invoked and executed, the phase-locked loop is configured according to the phase-locked loop frequency control word determined by the optimization calculation method to generate a local oscillator signal with the preferred phase-locked loop local oscillator frequency value.

7. The radio frequency signal generation method according to claim 1, characterized in that, The method further includes: Real-time acquisition and recording of operating parameters, including at least the frequency switching implementation methods and their time consumption during historical sub-band switching; Based on the collected operating parameters, a visual chart is generated and output for users to see; wherein, the visual chart includes at least a timing diagram of the switching strategy with time as the horizontal axis and the switching implementation method of the current frequency as the identifier.

8. A radio frequency signal generation system for performing the radio frequency signal generation method of claim 3, characterized in that, include, The first phase-locked loop is used to acquire an external reference signal and generate a high-frequency reference signal; A power divider is used to split the high-frequency reference signal to obtain a first reference signal and a second reference signal. The controller is used to generate an intermediate frequency signal based on the second reference signal using a preset digital fine frequency synthesis method; The second phase-locked loop is used to perform phase-locked processing on the first reference signal to generate a local oscillator signal; A mixer is used to mix the intermediate frequency signal with the local oscillator signal to generate an initial radio frequency signal; A dynamic phase correction unit is used to dynamically correct the phase noise of the initial radio frequency signal or the signal generated during the generation of the initial radio frequency signal to obtain a corrected signal. A reconfigurable impedance matching network is used to adaptively impedance match the corrected signal to obtain an regulated signal, wherein the adaptive impedance matching is used to dynamically adjust the impedance characteristics according to the current frequency of the corrected signal. A broadband distributed amplifier is used to perform gain flattening processing on the regulated signal to balance the signal amplitude of the regulated signal across the entire frequency band, so that the amplitude fluctuation of the signal obtained after gain flattening processing within a specified frequency band does not exceed a preset fluctuation amplitude, and the signal obtained after gain flattening processing is output as a radio frequency signal.

9. A radio frequency signal generation device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 7.

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