A single-ended input successive approximation analog-to-digital converter and optical module chip

Abstract

The application provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. In a sampling stage, the upper plates of a plurality of first capacitors are connected to an input voltage Vin, and part of the lower plates are connected to the input voltage Vin and part of the lower plates are connected to a reference voltage Vref. The upper plates of a plurality of second capacitors are connected to the reference voltage Vref, and part of the lower plates are connected to the input voltage Vin and part of the lower plates are connected to the reference voltage Vref. In a pre-switching stage, the upper plate switch is disconnected, and the lower plate voltages of the plurality of first capacitors and the plurality of second capacitors are switched according to a predetermined mode, so that the upper plate voltages of the plurality of first capacitors become a first preset voltage Vp and the upper plate voltages of the plurality of second capacitors become a second preset voltage Vn. In a comparison stage, the first preset voltage Vp and the second preset voltage Vn are input into a comparator for first-stage comparison. Through the preset switching logic, the single-ended analog-to-digital converter input can be converted into a differential comparator input.

Description

Technical Field

[0001] This application relates to the field of chips, and more specifically, to a single-ended input successive approximation analog-to-digital converter and an optical module chip. Background Technology

[0002] Analog-to-digital converters (ADCs) are a core component of modern communication and data acquisition systems, and their performance directly determines the accuracy and efficiency of the entire system. In applications such as optical communication modules, successive-approximation register analog-to-digital converters (SAR ADCs) are widely used. Due to the specific requirements of signal transmission and processing, medium-to-high precision (e.g., 12-bit) SAR ADCs are often needed. However, due to limitations in the internal layout and wiring of the module, the structure of a SAR ADC is often restricted to single-ended input.

[0003] In related technologies, single-ended input SAR ADCs struggle to achieve 12-bit accuracy. Firstly, single-ended inputs have poor suppression of common-mode noise (such as power supply noise and substrate coupling noise), making it difficult to improve accuracy. Secondly, during capacitor array switching, the switching dynamics of single-ended inputs introduce significant nonlinear errors and charge injection mismatch, further limiting the signal-to-noise ratio and spurious-free dynamic range, making it difficult to stably achieve the 12-bit accuracy requirement.

[0004] To overcome the inherent limitations of single-ended inputs, existing technologies have introduced differential inputs. Specifically, these technologies incorporate an additional single-ended to differential conversion circuit. This circuit pre-converts the external single-ended input signal into a differential signal before providing it to the differential input SAR ADC for processing. Because differential inputs inherently possess excellent common-mode noise suppression and symmetrical switching characteristics, they can achieve high conversion accuracy. However, this comes at the cost of an additional conversion circuit, resulting in increased power consumption. In other words, existing technologies cannot achieve a balance between high accuracy and low power consumption. Summary of the Invention

[0005] This application provides at least one single-ended input successive approximation analog-to-digital converter and optical module chip. Through special sampling operations and additional pre-switching operations, it can convert a single input voltage Vin into a first preset voltage Vp and a second preset voltage Vn. That is, this application can convert a single-ended analog-to-digital converter input into a differential comparator input without adding additional conversion circuitry through preset switching logic, thereby achieving high accuracy while maintaining low power consumption.

[0006] In a first aspect, this application provides a single-ended input successive approximation analog-to-digital converter, including a plurality of first capacitors, a plurality of second capacitors, and a comparator;

[0007] During the sampling phase, the upper plates of multiple first capacitors are all connected to the input voltage Vin, and some of the lower plates are connected to the input voltage Vin and some of the lower plates are connected to the reference voltage Vref; the upper plates of multiple second capacitors are all connected to the reference voltage Vref, and some of the lower plates are connected to the input voltage Vin and some of the lower plates are connected to the reference voltage Vref.

[0008] During the pre-switching phase, the upper plate switches corresponding to the upper plates of multiple first capacitors and multiple second capacitors are disconnected, and the lower plate voltages of multiple first capacitors and multiple second capacitors are switched according to a predetermined mode, so that the upper plate voltages of multiple first capacitors all become the first preset voltage Vp and the upper plate voltages of multiple second capacitors all become the second preset voltage Vn, and the first preset voltage Vp and the second preset voltage Vn are different.

[0009] During the comparison phase, the first preset voltage Vp and the second preset voltage Vn are input to the comparator for a first-stage comparison, so that subsequent switching and comparison operations can be performed based on the first-stage comparison result.

[0010] Secondly, this application also provides an optical module chip, which includes a single-ended input successive approximation analog-to-digital converter as described in the foregoing embodiments.

[0011] In summary, this application provides a single-ended input successive approximation analog-to-digital converter and an optical module chip, including multiple first capacitors, multiple second capacitors, and a comparator. During the sampling phase, the upper plates of the multiple first capacitors are all connected to the input voltage Vin, and some of their lower plates are connected to both the input voltage Vin and the reference voltage Vref. Similarly, the upper plates of the multiple second capacitors are all connected to the reference voltage Vref, and some of their lower plates are connected to both the input voltage Vin and the reference voltage Vref. During the pre-switching phase, the upper plate switches corresponding to the upper plates of the multiple first and second capacitors are disconnected, and the lower plate voltages of the multiple first and second capacitors are switched according to a predetermined pattern, such that the upper plate voltages of the multiple first capacitors all become a first preset voltage Vp and the upper plate voltages of the multiple second capacitors all become a second preset voltage Vn, where the first preset voltage Vp and the second preset voltage Vn are different. During the comparison phase, the first preset voltage Vp and the second preset voltage Vn are input to the comparator for a first-stage comparison, so that subsequent switching and comparison operations can be performed based on the first-stage comparison result. In this application, through special sampling operations and additional pre-switching operations, a single input voltage Vin can be converted into a first preset voltage Vp and a second preset voltage Vn. That is, this application can convert a single-ended analog-to-digital converter input into a differential comparator input through preset switching logic without adding additional conversion circuitry, thereby achieving high precision while maintaining low power consumption.

[0012] Other advantages of this application will be explained in more detail in conjunction with the following description and figures.

[0013] It should be understood that the above description is merely an overview of the technical solution of this application, so as to enable a general understanding of the technical means of this application and to implement it in accordance with the contents of the specification. In order to make the above and other objects, features and advantages of this application more apparent and understandable, specific embodiments of this application are illustrated below. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. The accompanying drawings are incorporated in and constitute a part of this specification. These drawings illustrate embodiments conforming to this application and are used together with the specification to explain the technical solutions of this application. It should be understood that the drawings only illustrate certain embodiments of this application and should not be considered as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. Furthermore, the same reference numerals denote the same components throughout the drawings. In the drawings:

[0015] Figure 1 A schematic diagram of a circuit with differential input;

[0016] Figure 2 This is a schematic diagram illustrating the switching of differential inputs;

[0017] Figure 3 A circuit diagram illustrating the first ADC input range of a single-ended input successive approximation analog-to-digital converter provided in an embodiment of this application;

[0018] Figure 4 A circuit diagram illustrating a second ADC input range for a single-ended input successive approximation analog-to-digital converter provided in an embodiment of this application;

[0019] Figure 5 A circuit diagram of another single-ended input successive approximation analog-to-digital converter including a bridging capacitor, provided for embodiments of this application. Detailed Implementation

[0020] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0021] In the description of embodiments of this application, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the disclosed features, figures, steps, behaviors, components, portions or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, figures, steps, behaviors, components, portions or combinations thereof.

[0022] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A alone, A and B at the same time, and B alone.

[0023] The terms "first," "second," etc., are used only for ease of description to distinguish identical or similar technical features and should not be construed as indicating or implying the relative importance or number of these technical features. Therefore, a feature defined by "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, the term "multiple" means two or more.

[0024] In related technologies, single-ended input SAR ADCs struggle to achieve 12-bit accuracy. To overcome the inherent limitations of single-ended input, existing technologies introduce an additional single-ended to differential conversion circuit. This circuit pre-converts the external single-ended input signal into a differential signal before providing it to the differential input SAR ADC for processing.

[0025] Because differential inputs inherently possess excellent common-mode noise suppression capabilities and symmetrical switching characteristics, they are able to achieve high conversion accuracy.

[0026] like Figure 1 As shown, the differential input in the prior art is divided into a sampling stage and a comparison stage. The differential input in the prior art only samples from the upper electrode or only from the lower electrode, such as... Figure 1 As shown, in existing differential input technologies, the upper plate can be sampled, with the upper plates of the two circuit sections connected to the input voltage Vip and the input voltage Vin, respectively, and the lower plates connected to the reference voltage Vref or ground Gnd, respectively. Figure 1 As shown, a switch needs to be switched between the sampling and comparison phases. Specifically, the sampling switch is turned off, the upper plate becomes floating, and the upper plate maintains the input voltages Vip and Vin respectively, while the lower plate remains unchanged. Figure 1 As shown, during the comparison phase, the two input terminals of the comparator are connected to the upper plates of the two circuits respectively. In related technologies, after the sampling process is completed, the input terminals of the comparator will become the input voltage Vip and the input voltage Vin. Then, the first operation of the comparator will be performed, that is, comparing the input voltage Vip and the input voltage Vin.

[0027] like Figure 1 As shown, after the first comparison, the voltage of the lower plate will be switched according to the actual situation. Since the result of the first comparison is that the input voltage Vip is less than the input voltage Vin, the input voltage Vip is smaller, which means that the charge value of the upper plate of the upper capacitor is smaller. Therefore, the upper capacitor needs to switch the grounding of one lower plate to be connected to the reference voltage Vref. Conversely, since the input voltage Vin is larger, the lower capacitor needs to switch the lower plate connected to the reference voltage Vref to ground.

[0028] like Figure 2 As shown, the differential input allows setting the input voltages Vip and Vin, where Vin + Vip = Vref = Vcm / 2. Then, comparisons and switching can be performed sequentially. The specific workflow is: sampling - first comparison - first switching - second comparison - second switching - ... - last comparison - last switching. This is the underlying working logic of the SAR ADC. If there is too little, add; if there is too much, subtract. Multiple comparisons are performed, and the switching operation after each comparison ensures that the voltage of the upper plate of the two circuits always remains constant at the common-mode voltage.

[0029] However, existing technologies introduce additional conversion circuitry by converting single-ended inputs to differential inputs, resulting in additional power consumption. In other words, existing technologies cannot achieve a balance between high precision and low power consumption.

[0030] In view of this, this application provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. Through special sampling operations and additional pre-switching operations, it can convert a single input voltage Vin into a first preset voltage Vp and a second preset voltage Vn. That is, this application can convert a single-ended analog-to-digital converter input into a differential comparator input without adding additional conversion circuitry through preset switching logic, thereby achieving high accuracy while maintaining low power consumption.

[0031] The single-ended input successive approximation analog-to-digital converter provided in this application will be described below through circuit embodiments.

[0032] This application provides a single-ended input successive approximation analog-to-digital converter, including multiple first capacitors, multiple second capacitors, and a comparator. Figure 3 As shown, multiple first capacitors and multiple second capacitors respectively form two parts of the capacitor.

[0033] During the sampling phase, the upper plates of multiple first capacitors are all connected to the input voltage Vin, and some of the lower plates are connected to the input voltage Vin and some of the lower plates are connected to the reference voltage Vref; the upper plates of multiple second capacitors are all connected to the reference voltage Vref, and some of the lower plates are connected to the input voltage Vin and some of the lower plates are connected to the reference voltage Vref.

[0034] Specifically, the sampling stage in this application differs from that in related technologies where only the upper plate or only the lower plate is sampled. In this application, the upper plates of the first capacitor are all connected to the input voltage Vin, and some of the lower plates are also connected to the input voltage Vin. Similarly, the upper plates of the second capacitor are all connected to the reference voltage Vref, and some of the lower plates are connected to the input voltage Vin. In other words, both the upper and lower plates of the capacitors in this application participate in the sampling process, which provides a basis for the voltage cutoff in the subsequent pre-switching stage.

[0035] During the pre-switching phase, the upper plate switches corresponding to the upper plates of multiple first capacitors and multiple second capacitors are disconnected, and the lower plate voltages of multiple first capacitors and multiple second capacitors are switched according to a predetermined mode, so that the upper plate voltages of multiple first capacitors all become the first preset voltage Vp and the upper plate voltages of multiple second capacitors all become the second preset voltage Vn, wherein the first preset voltage Vp and the second preset voltage Vn are different.

[0036] Specifically, in addition to adopting a novel sampling mode, this application differs from SAR ADCs in related technologies in that it does not perform direct comparisons but instead conducts a pre-switching phase.

[0037] During the pre-switching phase, the upper plate switches corresponding to the upper plates of multiple first capacitors and multiple second capacitors are first disconnected, thereby allowing the upper plates of multiple first capacitors and multiple second capacitors to float. Then, the lower plate voltages of multiple first capacitors and multiple second capacitors are switched according to a predetermined mode, so that the upper plate voltages of multiple first capacitors all become the first preset voltage Vp and the upper plate voltages of multiple second capacitors all become the second preset voltage Vn. That is, by switching the lower plate voltages, the single-ended input voltage Vin is converted into two different first preset voltages Vp and second preset voltages Vn to achieve differential input.

[0038] During the comparison phase, the first preset voltage Vp and the second preset voltage Vn are input to the comparator for the first-stage comparison, so that subsequent switching and comparison operations can be performed based on the first-stage comparison result.

[0039] Specifically, after obtaining two different first preset voltages Vp and second preset voltages Vn through the pre-switching stage, the two different voltage input comparators can be compared in the first stage. Subsequent switching and comparison can adopt the differential input switching and comparison logic in existing technologies, such as... Figure 3 As shown, the second comparison stage can adopt the differential input switching in the prior art, that is, the differential input switching and comparison logic in the prior art can be used to keep the common mode of the comparator input at Vref / 2, which will not be elaborated here.

[0040] It should be emphasized that no additional conversion circuit is introduced in this application. Instead, the conversion from single-ended input to differential input is achieved by switching the voltage of the lower plate through a novel sampling stage and a pre-switching stage, thereby improving accuracy while ensuring low power consumption.

[0041] In one possible implementation, when the input voltage Vin is within the range of 0-Vref, the first preset voltage Vp is 1 / 2Vin + 1 / 4Vref, and the second preset voltage Vn is -1 / 2Vin + 3 / 4Vref; wherein, the common-mode voltage Vcm between the first preset voltage Vp and the second preset voltage Vn is Vref / 2, and the difference between the first preset voltage Vp and the second preset voltage Vn is equal to the difference between the input voltage Vin and the common-mode voltage Vcm.

[0042] Specifically, when the input voltage Vin is within the range of 0-Vref, the first preset voltage Vp can be set to 1 / 2Vin + 1 / 4Vref, and the second preset voltage Vn can be set to -1 / 2Vin + 3 / 4Vref.

[0043] At this point, the common-mode voltage Vcm = [Vp + Vn] / 2 = [(1 / 2Vin + 1 / 4Vref) + (-1 / 2Vin + 3 / 4Vref)] / 2 = Vref / 2, so that the comparator can be maintained at a fixed common-mode voltage in the future, thereby ensuring the stability of the comparator.

[0044] Simultaneously, the difference between the first preset voltage Vp and the second preset voltage Vn = (1 / 2Vin + 1 / 4Vref) - (-1 / 2Vin + 3 / 4Vref) = Vin - Vref / 2. This means that comparing the first preset voltage Vp and the second preset voltage Vn achieves the effect of comparing the input voltage Vin and the common-mode voltage Vcm. Specifically, a single-ended input comparator can ultimately compare the input voltage Vin and the common-mode voltage Vcm. However, in this application, the comparator's input is actually the common-mode voltage at Vref / 2, consisting of 1 / 2Vin + 1 / 4Vref and -1 / 2Vin + 3 / 4Vref. This is superior to the single-ended comparator in related technologies, where one input is the input voltage Vin and the other is Vref / 2. Differential input achieves better dynamic performance, lower power sensitivity, and stronger matching.

[0045] In one possible implementation, such as Figure 3 As shown, the successive approximation analog-to-digital converter in this application can achieve 12-bit precision. The multiple first capacitors include three first-stage comparison capacitors with a capacitance of 1024C and multiple first-stage comparison capacitors with capacitance values ​​halved at each stage. The multiple first-stage comparison capacitors with capacitance values ​​halved at each stage may include multiple first-stage comparison capacitors with capacitance values ​​halved at each stage from 512C to C. The multiple second capacitors include three second first-stage comparison capacitors with a capacitance of 1024C and multiple second-stage comparison capacitors with capacitance values ​​halved at each stage. The multiple second-stage comparison capacitors with capacitance values ​​halved at each stage may include multiple second-stage comparison capacitors with capacitance values ​​halved at each stage from 512C to C.

[0046] During the sampling phase, such as Figure 3As shown, the lower plates of two of the three first-stage comparison capacitors are connected to the input voltage Vin, and the lower plates of one first-stage comparison capacitor and multiple first-stage comparison capacitors are connected to the reference voltage Vref; the lower plates of two of the three second-stage comparison capacitors are connected to the input voltage Vin, and the lower plates of one second-stage comparison capacitor and the multiple second-stage comparison capacitors are connected to the reference voltage Vref.

[0047] During the pre-switching phase, such as Figure 3 As shown, the predetermined mode is to switch the lower plate voltage of the two first-stage comparison capacitors to the reference voltage Vref of the input voltage Vin, the lower plate voltage of the two second-stage comparison capacitors to ground of the input voltage Vin, and the lower plate voltage of the one first-stage comparison capacitor, the multiple first-stage comparison capacitors, the one second-stage comparison capacitor and the multiple second-stage comparison capacitors to the common-mode voltage Vcm of the reference voltage Vref.

[0048] Through the specific sampling and switching methods described above, the voltage of the upper plate of the first capacitor can be switched to 1 / 2Vin + 1 / 4Vref, and the voltage of the upper plate of the second capacitor can be switched to Vn = -1 / 2Vin + 3 / 4Vref.

[0049] In one possible implementation, when the input voltage Vin is in the range of 0-2Vref, the first preset voltage Vp is 1 / 4Vin + 1 / 4Vref, and the second preset voltage Vn is -1 / 4Vin + 3 / 4Vref; wherein, the common-mode voltage Vcm between the first preset voltage Vp and the second preset voltage Vn is Vref / 2, and the difference between the first preset voltage Vp and the second preset voltage Vn is equal to the difference between half the input voltage Vin / 2 and the common-mode voltage Vcm.

[0050] Specifically, the switching approach proposed in this application can support a larger ADC input range of 0-2Vref without making hardware modifications.

[0051] When the input voltage Vin is within the range of 0-2Vref, the first preset voltage Vp can be set to 1 / 4Vin+1 / 4Vref, and the second preset voltage Vn can be set to -1 / 4Vin+3 / 4Vref.

[0052] At this point, the common-mode voltage Vcm = [Vp + Vn] / 2 = [(1 / 4Vin + 1 / 4Vref) + (-1 / 4Vin + 3 / 4Vref)] / 2 = Vref / 2, so that the comparator can be maintained at a fixed common-mode voltage in the future, thereby ensuring the stability of the comparator.

[0053] Meanwhile, the difference between the first preset voltage Vp and the second preset voltage Vn is (1 / 4Vin + 1 / 4Vref) - (-1 / 4Vin + 3 / 4Vref) = (Vin - Vref) / 2, which means that the input voltages Vin and Vref can be compared by comparing the first preset voltage Vp and the second preset voltage Vn.

[0054] It should be noted that, based on the switching approach disclosed in this embodiment, two ADC input ranges can be flexibly implemented through subtle changes in the switching logic without any hardware modifications. In practical applications of this application, those skilled in the art can further expand the corresponding ADC input range according to actual needs, and this application does not impose any limitations on this.

[0055] In one possible implementation, such as Figure 4 As shown, the successive approximation analog-to-digital converter provided in this application can achieve 12-bit precision. The multiple first capacitors include three first-stage comparison capacitors with a capacitance of 1024C and multiple first-stage comparison capacitors with capacitance values ​​halved at each stage. These multiple first-stage comparison capacitors with capacitance values ​​halved at each stage may include multiple first-stage comparison capacitors with capacitance values ​​halved at each stage, ranging from 512C to C. The multiple second capacitors include three second first-stage comparison capacitors with a capacitance of 1024C and multiple second-stage comparison capacitors with capacitance values ​​halved at each stage. These multiple second-stage comparison capacitors with capacitance values ​​halved at each stage may include multiple second-stage comparison capacitors with capacitance values ​​halved at each stage, ranging from 512C to C.

[0056] During the sampling phase, the lower plates of the three first-stage comparison capacitors are connected to the input voltage Vin, and the lower plates of the multiple first-stage comparison capacitors are connected to the reference voltage Vref; among the three second-stage comparison capacitors, the lower plate of one second-stage comparison capacitor is connected to the input voltage Vin, and the lower plates of the two second-stage comparison capacitors and the multiple second-stage comparison capacitors are connected to the reference voltage Vref.

[0057] During the pre-switching phase, the predetermined mode is to switch the lower plate voltage of a first-stage comparator capacitor from the input voltage Vin to the reference voltage Vref, the lower plate voltage of a first-stage comparator capacitor from the input voltage Vin to ground, the lower plate voltage of a first-stage comparator capacitor from the input voltage Vin to the common-mode voltage Vcm, the lower plate voltage of a second-stage comparator capacitor from the input voltage Vin to ground, the lower plate voltage of a second-stage comparator capacitor maintaining the reference voltage Vref, and the lower plate voltages of multiple first-stage comparator capacitors, a second-stage comparator capacitor, and multiple second-stage comparator capacitors from the reference voltage Vref to the common-mode voltage Vcm.

[0058] Through the specific sampling and switching methods described above, the voltage of the upper plate of the first capacitor can be switched to 1 / 4Vin + 1 / 4Vref, and the voltage of the upper plate of the second capacitor can be switched to Vn = -1 / 4Vin + 3 / 4Vref.

[0059] It should be noted that the switching approach proposed in this application can support a larger ADC input range of 0-2Vref without hardware modifications. Specifically, it can be achieved by fine-tuning the voltage values ​​of the lower-level board during the sampling and pre-switching stages.

[0060] In one possible implementation, the successive approximation analog-to-digital converter further includes a first bridging capacitor and a second bridging capacitor.

[0061] The plurality of first capacitors include a plurality of first coarse capacitors and a plurality of first fine capacitors of the same number. The upper plates of the plurality of first coarse capacitors are connected to the upper plates of the first bridging capacitor, and the upper plates of the plurality of first fine capacitors are connected to the lower plates of the first bridging capacitor.

[0062] The multiple second capacitors include an equal number of second coarse capacitors and multiple second fine capacitors. The upper plates of the multiple second coarse capacitors are connected to the upper plate of the second bridging capacitor, and the upper plates of the multiple second fine capacitors are connected to the lower plate of the second bridging capacitor.

[0063] like Figure 5 As shown, in this embodiment, a bridging capacitor (C) can be introduced. bridge This reduces the chip area through a bridging segmentation structure. Specifically, the multiple first capacitors include an equal number of first coarse segment capacitors and multiple first fine segment capacitors, which are connected by a first bridging capacitor; the multiple second capacitors include an equal number of second coarse segment capacitors and multiple second fine segment capacitors, which are connected by a second bridging capacitor.

[0064] In one possible implementation, a successive approximation analog-to-digital converter can also achieve 12-bit precision in the presence of bridging capacitors, such as... Figure 5 As shown, the multiple first coarse capacitors include first coarse multi-stage comparison capacitor pairs whose capacitance values ​​are halved step by step from 16C to 1 / 2C, and the multiple first fine capacitors include first fine multi-stage comparison capacitor pairs whose capacitance values ​​are halved step by step from 16C to 1 / 2C.

[0065] The second coarse capacitors include pairs of second coarse multi-stage comparison capacitors whose capacitance values ​​are halved step by step from 16C to 1 / 2C, and the second fine capacitors include pairs of second fine multi-stage comparison capacitors whose capacitance values ​​are halved step by step from 16C to 1 / 2C.

[0066] In one possible implementation, when the input voltage Vin is in the range of 0-Vref, the first preset voltage Vp is 1 / 2Vin + 1 / 4Vref, and the second preset voltage Vn is -1 / 2Vin + 3 / 4Vref.

[0067] like Figure 5 As shown, during the sampling phase, the lower plates of the first coarse-grading multi-stage comparison capacitor pairs with a capacitance of 16C are all connected to the input voltage Vin. The lower plates of the remaining pairs of first coarse-grading multi-stage comparison capacitors are all connected to the reference voltage Vref. The lower plates of the multiple pairs of first sub-grading multi-stage comparison capacitors are all connected to the reference voltage Vref. The lower plates of the second coarse-grading multi-stage comparison capacitor pairs with a capacitance of 16C are all connected to the input voltage Vin. The lower plates of the remaining pairs of second coarse-grading multi-stage comparison capacitors are all connected to the reference voltage Vref. The lower plates of the multiple pairs of second sub-grading multi-stage comparison capacitors are all connected to the reference voltage Vref.

[0068] During the pre-switching phase, the predetermined mode is as follows: the lower plate voltage of the first coarse-division multi-stage comparator capacitor pair with a capacitance of 16C is referenced to the input voltage Vin by the reference voltage Vref. In each of the remaining pairs of first coarse-division multi-stage comparator capacitor pairs, one first coarse-division multi-stage comparator capacitor maintains the reference voltage Vref, while the other first coarse-division multi-stage comparator capacitor is grounded by the reference voltage Vref. Similarly, in each of the remaining pairs of first subdivision multi-stage comparator capacitor pairs, one first subdivision multi-stage comparator capacitor maintains the reference voltage Vref, while the other first subdivision multi-stage comparator capacitor is grounded by the reference voltage Vref.

[0069] In other words, when a bridging capacitor is introduced, if the input range of the input voltage Vin is 0-Vref, the differential input voltages 1 / 2Vin + 1 / 4Vref and -1 / 2Vin + 3 / 4Vref can also be obtained through the above sampling and switching logic.

[0070] In one possible implementation, when the input voltage Vin is in the range of 0-2Vref, the first preset voltage Vp is 1 / 4Vin + 1 / 4Vref, and the second preset voltage Vn is -1 / 4Vin + 3 / 4Vref.

[0071] like Figure 5As shown, during the sampling phase, the lower plates of the first coarse-division multi-stage comparison capacitor pairs with capacitance values ​​of 16C and 8C are both connected to the input voltage Vin. The lower plates of the remaining pairs of first coarse-division multi-stage comparison capacitors are all connected to the reference voltage Vref. The lower plates of the multiple pairs of first sub-division multi-stage comparison capacitors are also connected to the reference voltage Vref. The lower plate of one second coarse-division multi-stage comparison capacitor with a capacitance value of 16C is connected to the input voltage Vin. The lower plates of another second coarse-division multi-stage comparison capacitor with a capacitance value of 16C and the remaining pairs of second coarse-division multi-stage comparison capacitors are all connected to the reference voltage Vref. The lower plates of the multiple pairs of second sub-division multi-stage comparison capacitors are also connected to the reference voltage Vref.

[0072] During the pre-switching phase, the predetermined mode is as follows: the lower plate voltage of one first coarse-division multi-stage comparison capacitor pair with a capacitance of 16C and another with a capacitance of 8C is referenced to the input voltage Vin by the reference voltage Vref; the lower plate voltage of another first coarse-division multi-stage comparison capacitor pair with a capacitance of 16C and another with a capacitance of 8C is grounded by the input voltage Vin; in each of the remaining pairs of first coarse-division multi-stage comparison capacitors, one first coarse-division multi-stage comparison capacitor maintains the reference voltage Vref and the other first coarse-division multi-stage comparison capacitor is grounded by the reference voltage Vref; and in each of the remaining pairs of first subdivision multi-stage comparison capacitors, one first subdivision multi-stage comparison capacitor maintains the reference voltage Vref and the other first subdivision multi-stage comparison capacitor is grounded by the reference voltage Vref. The lower plate voltage of one pair of second coarse-division multi-stage comparator capacitors with a capacitance of 16C is grounded by the input voltage Vin. The lower plate voltage of another pair of second coarse-division multi-stage comparator capacitors with a capacitance of 16C maintains the reference voltage Vref. In each of the remaining pairs of second coarse-division multi-stage comparator capacitors, one second coarse-division multi-stage comparator capacitor maintains the reference voltage Vref and the other second coarse-division multi-stage comparator capacitor is grounded by the reference voltage Vref. In each of the remaining pairs of second subdivision multi-stage comparator capacitors, one second subdivision multi-stage comparator capacitor maintains the reference voltage Vref and the other second subdivision multi-stage comparator capacitor is grounded by the reference voltage Vref.

[0073] In other words, when a bridging capacitor is introduced, if the input range of the input voltage Vin is 0-2Vref, the differential input voltages 1 / 4Vin+1 / 4Vref and -1 / 4Vin+3 / 4Vref can also be obtained through the above sampling and switching logic.

[0074] In one possible implementation, the lower plate voltage of one capacitor in the first coarse-division multi-stage comparison capacitor pair, the first fine-division multi-stage comparison capacitor pair, the second coarse-division multi-stage comparison capacitor pair, and the second fine-division multi-stage comparison capacitor pair with a capacitance of 2C is switched to the reference voltage Vref, and the lower plate voltage of the other capacitor is switched to ground, so as to obtain a common-mode voltage Vcm with a value of Vref / 2.

[0075] In other words, the common-mode voltage Vcm, which is Vref / 2, can be obtained directly through capacitor splitting technology, thereby avoiding the introduction of an additional constant voltage source and thus avoiding additional static power consumption.

[0076] In summary, this application provides a single-ended input successive approximation analog-to-digital converter, including multiple first capacitors, multiple second capacitors, and a comparator. During the sampling phase, the upper plates of the multiple first capacitors are all connected to the input voltage Vin, and some of their lower plates are connected to both the input voltage Vin and the reference voltage Vref. Similarly, the upper plates of the multiple second capacitors are all connected to the reference voltage Vref, and some of their lower plates are connected to both the input voltage Vin and the reference voltage Vref. During the pre-switching phase, the upper plate switches corresponding to the upper plates of the multiple first and second capacitors are disconnected, and the lower plate voltages of the multiple first and second capacitors are switched according to a predetermined pattern, such that the upper plate voltages of the multiple first capacitors all become a first preset voltage Vp and the upper plate voltages of the multiple second capacitors all become a second preset voltage Vn, where the first preset voltage Vp and the second preset voltage Vn are different. During the comparison phase, the first preset voltage Vp and the second preset voltage Vn are input to the comparator for a first-stage comparison, so that subsequent switching and comparison operations can be performed based on the first-stage comparison result. In this application, through special sampling operations and additional pre-switching operations, a single input voltage Vin can be converted into a first preset voltage Vp and a second preset voltage Vn. That is, this application can convert a single-ended analog-to-digital converter input into a differential comparator input through preset switching logic without adding additional conversion circuitry, thereby achieving high precision while maintaining low power consumption.

[0077] In the description of this specification, references to terms such as "some possible implementations," "some implementations," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that implementation or example is included in at least one implementation or example of this application, and the aforementioned terms do not necessarily refer to the same implementation or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more implementations or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different implementations or examples described in this specification, as well as the features of different implementations or examples.

[0078] While the spirit and principles of this application have been described above with reference to several specific embodiments, it should be understood that this application is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined. This application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0079] Based on this, embodiments of this application also provide an optical module chip, which includes any of the single-ended input successive approximation analog-to-digital converters provided above.

[0080] It should be noted that the descriptions of the single-ended input successive approximation analog-to-digital converters provided above can all be applied to this optical module chip, and will not be repeated here in the embodiments of this application.

[0081] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A single-ended input successive approximation analog-to-digital converter, characterized in that, It includes multiple first capacitors, multiple second capacitors, and a comparator; During the sampling phase, the upper plates of the plurality of first capacitors are all connected to the input voltage Vin, and some of the lower plates are connected to the input voltage Vin and some of the lower plates are connected to the reference voltage Vref. The upper plates of the plurality of second capacitors are all connected to the reference voltage Vref, and some of the lower plates are connected to the input voltage Vin and some of the lower plates are connected to the reference voltage Vref. During the pre-switching phase, the upper plate switches corresponding to the upper plates of the plurality of first capacitors and the plurality of second capacitors are disconnected, and the lower plate voltages of the plurality of first capacitors and the plurality of second capacitors are switched according to a predetermined mode, so that the upper plate voltages of the plurality of first capacitors all become a first preset voltage Vp and the upper plate voltages of the plurality of second capacitors all become a second preset voltage Vn, wherein the first preset voltage Vp and the second preset voltage Vn are different; During the comparison phase, the first preset voltage Vp and the second preset voltage Vn are input to the comparator for the first-stage comparison, so that subsequent switching and comparison operations can be performed based on the first-stage comparison result, thereby allowing the comparator to operate at a fixed common-mode voltage Vcm.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that, When the input voltage Vin is within the range of 0-Vref, the first preset voltage Vp is 1 / 2Vin + 1 / 4Vref, and the second preset voltage Vn is -1 / 2Vin + 3 / 4Vref; wherein, the common-mode voltage Vcm between the first preset voltage Vp and the second preset voltage Vn is Vref / 2, and the difference between the first preset voltage Vp and the second preset voltage Vn is equal to the difference between the input voltage Vin and the common-mode voltage Vcm.

3. The successive approximation analog-to-digital converter according to claim 2, characterized in that, The successive approximation analog-to-digital converter has 12-bit precision. The plurality of first capacitors include three first-stage comparison capacitors with a capacitance of 1024C and a plurality of first multi-stage comparison capacitors with a capacitance value halved at each stage. The plurality of second capacitors include three second-stage comparison capacitors with a capacitance of 1024C and a plurality of second multi-stage comparison capacitors with a capacitance value halved at each stage. During the sampling phase, the lower plates of two of the three first-stage comparison capacitors are connected to the input voltage Vin, and the lower plates of one first-stage comparison capacitor and multiple first-stage comparison capacitors are connected to the reference voltage Vref. Of the three second-stage first-stage comparator capacitors, the lower plates of two second-stage first-stage comparator capacitors are connected to the input voltage Vin, and the lower plates of one second-stage first-stage comparator capacitor and multiple second-stage multi-stage comparator capacitors are connected to the reference voltage Vref. During the pre-switching phase, the predetermined mode is to switch the lower plate voltage of the two first-stage comparison capacitors to the reference voltage Vref instead of the input voltage Vin, the lower plate voltage of the two second-stage comparison capacitors to ground instead of the input voltage Vin, and the lower plate voltage of the one first-stage comparison capacitor, the plurality of first multi-stage comparison capacitors, the one second first-stage comparison capacitor, and the plurality of second multi-stage comparison capacitors to the common-mode voltage Vcm instead of the reference voltage Vref.

4. The successive approximation analog-to-digital converter according to claim 1, characterized in that, When the input voltage Vin is in the range of 0-2Vref, the first preset voltage Vp is 1 / 4Vin + 1 / 4Vref, and the second preset voltage Vn is -1 / 4Vin + 3 / 4Vref; wherein, the common-mode voltage Vcm between the first preset voltage Vp and the second preset voltage Vn is Vref / 2, and the difference between the first preset voltage Vp and the second preset voltage Vn is equal to the difference between half the input voltage Vin / 2 and the common-mode voltage Vcm.

5. The successive approximation analog-to-digital converter according to claim 4, characterized in that, The successive approximation analog-to-digital converter has 12-bit precision. The plurality of first capacitors include three first-stage comparison capacitors with a capacitance of 1024C and a plurality of first multi-stage comparison capacitors with a capacitance value halved at each stage. The plurality of second capacitors include three second-stage comparison capacitors with a capacitance of 1024C and a plurality of second multi-stage comparison capacitors with a capacitance value halved at each stage. During the sampling phase, the lower plates of the three first-stage comparison capacitors are connected to the input voltage Vin, and the lower plates of the multiple first-stage comparison capacitors are connected to the reference voltage Vref. Of the three second-stage first-stage comparator capacitors, the lower plate of one second-stage first-stage comparator capacitor is connected to the input voltage Vin, and the lower plates of the two second-stage first-stage comparator capacitors and the multiple second-stage multi-stage comparator capacitors are connected to the reference voltage Vref. During the pre-switching phase, the predetermined mode is as follows: the lower plate voltage of a first-stage comparator capacitor is switched from the input voltage Vin to the reference voltage Vref; the lower plate voltage of a first-stage comparator capacitor is switched from the input voltage Vin to ground; the lower plate voltage of a first-stage comparator capacitor is switched from the input voltage Vin to the common-mode voltage Vcm; the lower plate voltage of a second-stage comparator capacitor is switched from the input voltage Vin to ground; the lower plate voltage of a second-stage comparator capacitor is maintained at the reference voltage Vref; and the lower plate voltages of the plurality of first-stage comparator capacitors, the second-stage comparator capacitor, and the plurality of second-stage comparator capacitors are switched from the reference voltage Vref to the common-mode voltage Vcm.

6. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The successive approximation analog-to-digital converter also includes a first bridging capacitor and a second bridging capacitor. The plurality of first capacitors includes a plurality of first coarse capacitors and a plurality of first fine capacitors of the same number. The upper plates of the plurality of first coarse capacitors are connected to the upper plates of the first bridging capacitor, and the upper plates of the plurality of first fine capacitors are connected to the lower plates of the first bridging capacitor. The plurality of second capacitors includes a plurality of second coarse capacitors and a plurality of second fine capacitors of the same number. The upper plates of the plurality of second coarse capacitors are connected to the upper plates of the second bridging capacitors, and the upper plates of the plurality of second fine capacitors are connected to the lower plates of the second bridging capacitors.

7. The successive approximation analog-to-digital converter according to claim 6, characterized in that, The successive approximation analog-to-digital converter has 12-bit precision. The plurality of first coarse-division capacitors include first coarse-division multi-stage comparison capacitor pairs with capacitance values ​​halved stepwise from 16C to 1 / 2C. The plurality of first fine-division capacitors include first fine-division multi-stage comparison capacitor pairs with capacitance values ​​halved stepwise from 16C to 1 / 2C. The plurality of second coarse-division capacitors include second coarse-division multi-stage comparison capacitor pairs with capacitance values ​​halved stepwise from 16C to 1 / 2C. The plurality of second fine-division capacitors include second fine-division multi-stage comparison capacitor pairs with capacitance values ​​halved stepwise from 16C to 1 / 2C.

8. The successive approximation analog-to-digital converter according to claim 7, characterized in that, When the input range of the input voltage Vin is 0-Vref, the first preset voltage Vp is 1 / 2Vin + 1 / 4Vref, and the second preset voltage Vn is -1 / 2Vin + 3 / 4Vref; During the sampling phase, the lower plates of the first coarse-division multi-stage comparison capacitor pairs with a capacitance of 16C are all connected to the input voltage Vin, the lower plates of the remaining multiple first coarse-division multi-stage comparison capacitor pairs are all connected to the reference voltage Vref, and the lower plates of the multiple first subdivision multi-stage comparison capacitor pairs are all connected to the reference voltage Vref; the lower plates of the second coarse-division multi-stage comparison capacitor pairs with a capacitance of 16C are all connected to the input voltage Vin, the lower plates of the remaining multiple second coarse-division multi-stage comparison capacitor pairs are all connected to the reference voltage Vref, and the lower plates of the multiple second subdivision multi-stage comparison capacitor pairs are all connected to the reference voltage Vref. During the pre-switching phase, the predetermined mode is as follows: the lower plate voltage of the first coarse-division multi-stage comparison capacitor pair with a capacitance of 16C is referenced to the input voltage Vin by the reference voltage Vref; in each of the remaining pairs of first coarse-division multi-stage comparison capacitors, one first coarse-division multi-stage comparison capacitor maintains the reference voltage Vref while the other first coarse-division multi-stage comparison capacitor is grounded by the reference voltage Vref; in each of the remaining pairs of first subdivision multi-stage comparison capacitors, one first subdivision multi-stage comparison capacitor maintains the reference voltage Vref while the other first subdivision multi-stage comparison capacitor is grounded by the reference voltage Vref; in the second coarse-division multi-stage comparison capacitor pair with a capacitance of 16C, the lower plate voltage is grounded to the input voltage Vin; in each of the remaining pairs of second coarse-division multi-stage comparison capacitors, one second second coarse-division multi-stage comparison capacitor maintains the reference voltage Vref while the other second second coarse-division multi-stage comparison capacitor is grounded by the reference voltage Vref; in each of the remaining pairs of second subdivision multi-stage comparison capacitors, one second subdivision multi-stage comparison capacitor maintains the reference voltage Vref while the other second subdivision multi-stage comparison capacitor is grounded by the reference voltage Vref.

9. The successive approximation analog-to-digital converter according to claim 7, characterized in that, When the input range of the input voltage Vin is 0-2Vref, the first preset voltage Vp is 1 / 4Vin+1 / 4Vref, and the second preset voltage Vn is -1 / 4Vin+3 / 4Vref; During the sampling phase, the lower plates of the first coarse-division multi-stage comparison capacitor pairs with capacitance values ​​of 16C and 8C are both connected to the input voltage Vin. The lower plates of the remaining first coarse-division multi-stage comparison capacitor pairs are both connected to the reference voltage Vref. The lower plates of the multiple first subdivision multi-stage comparison capacitor pairs are both connected to the reference voltage Vref. The lower plate of a second coarse-division multi-stage comparison capacitor with capacitance value of 16C is connected to the input voltage Vin. The lower plates of another second coarse-division multi-stage comparison capacitor with capacitance value of 16C and the remaining multiple second coarse-division multi-stage comparison capacitor pairs are both connected to the reference voltage Vref. The lower plates of the multiple second subdivision multi-stage comparison capacitor pairs are both connected to the reference voltage Vref. During the pre-switching phase, the predetermined mode is as follows: the lower plate voltage of one pair of first coarse-division multi-stage comparator capacitors with capacitance values ​​of 16C and 8C is referenced to the input voltage Vin by the reference voltage Vref; the lower plate voltage of another pair of first coarse-division multi-stage comparator capacitors with capacitance values ​​of 16C and 8C is grounded to the input voltage Vin; in each of the remaining pairs of first coarse-division multi-stage comparator capacitors, one first coarse-division multi-stage comparator capacitor maintains the reference voltage Vref while the other first coarse-division multi-stage comparator capacitor is grounded to the reference voltage Vref; in each of the remaining pairs of first subdivision multi-stage comparator capacitors, one first subdivision multi-stage comparator capacitor maintains the reference voltage Vref while the other first subdivision multi-stage comparator capacitor is grounded to the reference voltage Vref. The multi-stage comparator capacitors are grounded by the reference voltage Vref; the lower plate voltage of one pair of second coarse-division multi-stage comparator capacitors with a capacitance of 16C is grounded by the input voltage Vin, the lower plate voltage of another pair of second coarse-division multi-stage comparator capacitors with a capacitance of 16C maintains the reference voltage Vref, one of the remaining pairs of second coarse-division multi-stage comparator capacitors in each pair maintains the reference voltage Vref and the other pair of second coarse-division multi-stage comparator capacitors is grounded by the reference voltage Vref, and one of the remaining pairs of second sub-division multi-stage comparator capacitors in each pair maintains the reference voltage Vref and the other pair of second sub-division multi-stage comparator capacitors is grounded by the reference voltage Vref.

10. The successive approximation analog-to-digital converter according to any one of claims 7-9, characterized in that, The voltage of the lower plate of one capacitor in the first coarse-division multi-stage comparison capacitor pair, the first fine-division multi-stage comparison capacitor pair, the second coarse-division multi-stage comparison capacitor pair, and the second fine-division multi-stage comparison capacitor pair with a capacitance of 2C is switched to the reference voltage Vref, and the voltage of the lower plate of the other capacitor is switched to ground, so as to obtain a common-mode voltage Vcm with a value of Vref / 2.

11. An optical module chip, characterized in that, The optical module chip includes a single-ended input successive approximation analog-to-digital converter as described in any one of claims 1-10.

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