Server clock synchronization system and method based on BMC

Abstract

The invention discloses a server clock synchronization system and method based on a BMC. The system comprises a real-time clock chip, a channel switching chip, a baseboard management controller and a server host. The real-time clock chip receives and stores BMC system time written by the baseboard management controller, maintains travel time based on the time and generates an interrupt signal through the interrupt output pin. And the channel switching chip switches an access channel to the real-time clock chip between the server host and the substrate management controller according to the level signal of the control pin. And the baseboard management controller obtains the access right by outputting the level signal, writes the BMC system time and sets the alarm clock time. And the server host responds to the interrupt signal, reads the hardware time data from the real-time clock chip and updates the system time. According to the invention, after the BMC modifies the time, the time synchronization can be completed without restarting the server host, the service interruption is effectively avoided, and the availability of a server system and the real-time performance of time management are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of server hardware management, and in particular to a server clock synchronization system and method based on a baseboard management controller (BMC). BACKGROUND

[0002] In a modern server hardware architecture, a baseboard management controller (BMC) and a server host usually share the same real-time clock (RTC) chip to provide a hardware clock reference for their respective operating systems. The common practice is that when an administrator updates the system time through the BMC, the new time will be written into the shared RTC chip. However, this operation has a significant defect: the server host operating system cannot perceive in real time that the time in the RTC chip has been modified. Since the server host only reads the initial time from the RTC chip once at startup, it thereafter relies on its own interrupts and counters to maintain the system time, resulting in the time change at the BMC end being unable to be actively and timely notified to the server host.

[0003] Therefore, in order to achieve consistency between the server host system time and the new time in the RTC chip, the existing technical solution often requires a forced restart of the server host. During the restart process, the host side will re-read the latest value in the RTC chip and set its system time based on the value. This synchronization mechanism that relies on physical restart is extremely unsuitable in business scenarios that require high availability and high continuity. Server restarts not only cause the interruption of operational business services, resulting in losses at the business level, but also bring additional complexity and cost to the operation and management of the data center.

[0004] Application Content

[0005] The present application provides a server clock synchronization system and method based on a BMC to solve the problem of business interruption and inefficient operation caused by the server host having to restart to synchronize the time after the BMC modifies the RTC time in the prior art.

[0006] In a first aspect, the present application provides a server clock synchronization system based on a BMC, comprising:

[0007] a real-time clock chip, a channel switching chip, a baseboard management controller, and a server host;

[0008] the real-time clock chip, configured to receive and store a BMC system time written by the baseboard management controller, and maintain the running time based on the BMC system time and output corresponding hardware time data; and generate an interrupt signal through an interrupt output pin of the real-time clock chip;

[0009] the channel switching chip, configured to switch the access channel to the real-time clock chip between the server host and the baseboard management controller according to a level signal received by a control pin of the channel switching chip.

[0010] The baseboard management controller is used to obtain access to the real-time clock chip by outputting a level signal to the control pin, so as to write the BMC system time to the real-time clock chip and set the alarm time corresponding to the interrupt signal.

[0011] The server host is used to respond to interrupt signals and read hardware time data from the real-time clock chip through the channel switching chip to update the system time corresponding to the server host based on the hardware time data.

[0012] Secondly, this application provides a server clock synchronization method based on BMC, including:

[0013] The baseboard management controller writes BMC system time data to the time register of the real-time clock chip, so that the real-time clock chip keeps time based on the BMC system time and outputs the corresponding hardware time data.

[0014] The delayed trigger time is written to the alarm register of the real-time clock chip to set the alarm time;

[0015] When the hardware time data in the time register reaches the alarm time, the real-time clock chip outputs an interrupt signal to the server host through the interrupt output pin.

[0016] The server host responds to the interrupt signal and sets the interrupt status flag;

[0017] When the interrupt status flag is detected as valid, the server host reads the hardware time data from the time register and sets the hardware time data as the system time corresponding to the server host.

[0018] Thirdly, this application provides a server clock synchronization device based on BMC, comprising:

[0019] The hardware time data output module is configured to write BMC system time data to the time register of the real-time clock chip through the baseboard management controller, so that the real-time clock chip maintains timekeeping based on the BMC system time and outputs the corresponding hardware time data.

[0020] The alarm time setting module is configured to write the delayed trigger time into the alarm register of the real-time clock chip to set the alarm time.

[0021] The interrupt signal output module is configured so that when the hardware time data in the time register reaches the alarm time, the real-time clock chip outputs an interrupt signal to the server host through the interrupt output pin.

[0022] The interrupt status flag setting module is configured to set the interrupt status flag when the server host responds to an interrupt signal;

[0023] The system time determination module is configured to read hardware time data from the time register and set the hardware time data as the system time corresponding to the server host when an interrupt status flag is detected as valid.

[0024] Fourthly, this application provides a readable medium including executable instructions, which, when executed by a processor of an electronic device, cause the electronic device to perform any of the methods described in the first aspect.

[0025] This application provides a server clock synchronization system and method based on BMC (Baseboard Management Controller), comprising: a real-time clock chip, a channel switching chip, a baseboard management controller, and a server host; the real-time clock chip is used to receive and store the BMC system time written by the baseboard management controller, maintain timekeeping based on the BMC system time, and output corresponding hardware time data; an interrupt signal is generated through the interrupt output pin of the real-time clock chip; the channel switching chip is used to switch the access channel to the real-time clock chip between the server host and the baseboard management controller according to the level signal received by the control pin of the channel switching chip; the baseboard management controller is used to obtain access rights to the real-time clock chip by outputting a level signal to the control pin, so as to write the BMC system time to the real-time clock chip and set the alarm time corresponding to the interrupt signal; the server host is used to respond to the interrupt signal and read the hardware time data from the real-time clock chip through the channel switching chip, so as to update the system time corresponding to the server host according to the hardware time data. This system enables time synchronization to be completed without restarting the server host after the BMC time is modified, effectively avoiding business interruption and improving the availability of the server system and the real-time performance of time management.

[0026] The further effects of the aforementioned non-conventional preferred method will be explained below in conjunction with specific embodiments. Attached Figure Description

[0027] To more clearly illustrate the embodiments of this application or the existing technical solutions, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a BMC-based server clock synchronization system provided in one embodiment of this application;

[0029] Figure 2 A schematic diagram of the structure of a real-time clock chip in a BMC-based server clock synchronization system provided in an embodiment of this application;

[0030] Figure 3 A schematic diagram of the structure of a channel switching chip in a BMC-based server clock synchronization system provided in an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of the structure of a baseboard management controller in a server clock synchronization system based on BMC, provided in one embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the structure of a server host in a BMC-based server clock synchronization system according to an embodiment of this application;

[0033] Figure 6 This is a schematic flowchart of a server clock synchronization method based on BMC provided in an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of a server clock synchronization device based on BMC, provided as an embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In modern server hardware architectures, the Baseboard Management Controller (BMC) and the server host typically share the same Real-Time Clock (RTC) chip to provide a hardware clock reference for their respective operating systems. Currently, the common practice is that when an administrator updates the system time via the BMC, the new time is written to the shared RTC chip. However, this operation has a significant drawback: the server host operating system cannot detect in real time that the time in the RTC chip has been modified. Because the server host only reads the initial time from the RTC chip once during startup and then relies on its own interrupts and counters to maintain the system time, time changes at the BMC cannot be proactively and promptly communicated to the server host.

[0037] Therefore, to ensure the server host system time is consistent with the new time in the RTC chip, existing solutions often require a forced restart of the server host. During the restart process, the host rereads the latest value from the RTC chip and sets its system time accordingly. This synchronization mechanism, which relies on a physical restart, is extremely unsuitable for business scenarios requiring high availability and high continuity. Server restarts not only cause interruptions to running business services, resulting in business losses, but also bring additional complexity and costs to data center operation and maintenance management.

[0038] To address this issue, this application proposes a server clock synchronization system based on a BMC (Browser Clock Management System). This system aims to resolve the business interruption and inefficient operation and maintenance problems caused by the server host needing to restart to synchronize time after the BMC modifies the RTC (Real-Time Control) time, as required by existing technologies. See also... Figure 1 The image shows a specific embodiment of a server clock synchronization system based on a BMC. In this embodiment, the server clock synchronization system based on a BMC includes: a real-time clock chip 101, a channel switching chip 102, a baseboard management controller 103, and a server host 104.

[0039] The real-time clock chip 101 is used to receive and store the BMC system time written by the baseboard management controller 103, maintain timekeeping based on the BMC system time, and output the corresponding hardware time data; and generate an interrupt signal through the interrupt output pin of the real-time clock chip 101.

[0040] The real-time clock chip 101 serves as the time reference source for the entire system, not only storing and maintaining the standard time but also possessing an active notification mechanism. When the baseboard management controller 103 writes new time data via the I2C bus, the crystal oscillator circuit inside the real-time clock chip 101 continuously keeps time based on that initial time, ensuring that even in the event of a system power outage, the backup battery maintains the continuity and accuracy of the time. The real-time clock chip 101 integrates complete calendar and clock functions, automatically handling complex time calculation logic such as differences in the number of days in a month and leap years, providing a reliable hardware time reference for the system.

[0041] The real-time clock chip 101 includes: a time register 1011, an alarm register 1012, an I2C communication interface 1013, and an interrupt output pin 1014. For example... Figure 2 The diagram shown is a schematic of the channel switching chip in a BMC-based server clock synchronization system in this embodiment.

[0042] Time register 1011 is used to maintain timekeeping based on the BMC system time and output hardware time data.

[0043] The time register 1011 typically stores time information in BCD (binary-encoded decimal) format, including multiple time fields such as seconds, minutes, hours, days, months, and years, with each field occupying an independent register location. This storage method allows software to directly read and parse time data without complex format conversions.

[0044] The time register 1011 works closely with the internal counter circuit of the chip. The counter increments at a fixed frequency (usually 1Hz), and automatically updates the corresponding field in the time register when the count overflows, thus achieving accurate timekeeping. The time register 1011 supports multi-byte continuous read operations, ensuring the consistency of time data during the reading process and avoiding read errors caused by time jumps.

[0045] The alarm clock register 1012 is used to store the alarm clock time set by the baseboard management controller 103. When the hardware time data matches the alarm clock time, an interrupt event is triggered.

[0046] The structure of the alarm register 1012 is similar to that of the time register 1011, but it has independent comparison logic circuitry. The baseboard management controller 103 can write the trigger time to the alarm register 1012, and the comparator inside the chip will compare the current time in the time register 1011 with the set time in the alarm register 1012 in each clock cycle.

[0047] When the two match perfectly, the comparator immediately activates the interrupt generation circuit, sending an interrupt signal to the external system via interrupt output pin 1014. The alarm register 1012 also supports partial field matching modes; for example, it can be set to match only the hours and minutes while ignoring the seconds, thus providing a flexible interrupt triggering strategy. In this embodiment, to achieve real-time time synchronization, the alarm time is typically set to the current BMC system time plus a short delay (e.g., 1 second) to ensure the server host receives the synchronization notification promptly.

[0048] The I2C communication interface 1013 is connected to the channel switching chip 102 and is used by the baseboard management controller 103 or the server host 104 to read and write access to the time register 1011 and the alarm clock register 1012.

[0049] The I2C communication interface 1013 follows the standard I2C bus protocol and includes two signal lines: a serial data line (SDA) and a serial clock line (SCL), supporting multi-master communication architectures. The I2C communication interface 1013 integrates an address recognition circuit, capable of responding to specific slave device addresses and directing subsequent read / write operations to the corresponding internal registers based on the received register address pointer.

[0050] During a write operation, the master device (board management controller 103 or server host 104) sends a start signal, device address, register address, and data content via the I2C bus. The real-time clock chip 101 receives and parses this information, then writes the data to the designated register. During a read operation, the master device first writes the register address and then sends a read request. The real-time clock chip 101 then returns the data for the corresponding register via the SDA line. The I2C communication interface 1013 also features bus arbitration and error detection functions to ensure the reliability and accuracy of data transmission in complex hardware environments.

[0051] Interrupt output pin 1014 is used to output an interrupt signal to server host 104 when an interrupt event is triggered.

[0052] Interrupt output pin 1014 is a dedicated hardware signal line that is directly connected to the interrupt controller or interrupt input pin of the processor in the server host 104. When the time condition set in the alarm register 1012 is met, the interrupt logic circuit inside the real-time clock chip 101 will pull the level of this pin down from the default high level (or pull it up from the low level, depending on the specific chip design), forming an edge-triggered signal.

[0053] This hardware-level interrupt signal can notify the server host 104 with extremely low latency, triggering the pre-registered interrupt service routine in its operating system kernel. The design of the interrupt output pin 1014 ensures the real-time performance and reliability of the time synchronization notification. Compared with software polling, the hardware interrupt mechanism does not consume processor resources and can respond instantly when an event occurs, making it a key technical means to achieve time synchronization.

[0054] The channel switching chip 102 is used to switch the access channel to the real-time clock chip 101 between the server host 104 and the baseboard management controller 103 according to the level signal received by the control pin of the channel switching chip 102.

[0055] The channel switching chip 102 solves the hardware conflict problem that a single real-time clock chip 101 needs to be accessed by two independent host systems simultaneously. Since the real-time clock chip 101 only has one set of I2C communication interfaces 1013, it cannot simultaneously respond to access requests from the baseboard management controller 103 and the server host 104. Therefore, time-division multiplexing is required through the channel switching chip 102.

[0056] The channel switching chip 102 integrates an analog switch array and logic control circuitry, enabling it to dynamically connect the I2C interface of the real-time clock chip 101 to different host devices based on the level state of the control pin 1024. This hardware-level channel switching mechanism offers fast response and minimal impact on the I2C bus signal quality during the switching process, ensuring the stability and reliability of clock data transmission.

[0057] The channel switching chip 102 includes: a first data interface 1021, a second data interface 1022, a third data interface 1023, and a control pin 1024. For example... Figure 3 The diagram shown is a schematic of the channel switching chip in a BMC-based server clock synchronization system in this embodiment.

[0058] The first data interface 1021 is connected to the server host 104, the second data interface 1022 is connected to the baseboard management controller 103, and the third data interface 1023 is connected to the I2C communication interface 1013.

[0059] All three data interfaces are standard I2C bus interfaces, each containing two signal lines: SDA and SCL. The first data interface 1021 and the second data interface 1022 serve as input terminals, receiving I2C bus signals from the server host 104 and the baseboard management controller 103, including clock signals, data signals, and bus control signals. The third data interface 1023 serves as an output terminal, connected to the I2C communication interface 1013 of the real-time clock chip 101, used to transmit selected master control device signals.

[0060] The switch matrix inside the channel switching chip 102 establishes an electrical connection between the first data interface 1021 or the second data interface 1022 and the third data interface 1023 according to the instructions of the control pin 1024, thereby realizing the dynamic switching of the signal path. This three-interface architecture design is simple and efficient, ensuring that the two main control systems can independently access the real-time clock chip 101, while avoiding bus conflicts and signal interference problems, providing a hardware foundation for the stable operation of the entire clock synchronization system.

[0061] The control pin 1024 is used to receive level signals; when the level signal is high, it connects the second data interface 1022 and the third data interface 1023; when the level signal is low, it connects the first data interface 1021 and the third data interface 1023.

[0062] Control pin 1024 is the control input terminal of channel switching chip 102, and is typically connected to the GPIO (General Purpose Input / Output) port of substrate management controller 103. Substrate management controller 103 remotely controls the operating state of channel switching chip 102 by controlling the output level of this GPIO port through software.

[0063] When the baseboard management controller 103 needs to access the real-time clock chip 101, it sets the control pin 1024 to a high level. At this time, the analog switch inside the channel switching chip 102 closes the path from the second data interface 1022 to the third data interface 1023, and disconnects the connection of the first data interface 1021, so that the baseboard management controller 103 obtains exclusive access to the real-time clock chip 101.

[0064] After completing the time setting and alarm configuration, the baseboard management controller 103 sets the control pin 1024 to a low level, and the channel switching chip 102 then switches the path, returning access to the real-time clock chip 101 to the server host 104. This level-controlled switching mechanism is simple and reliable, and the switching delay is typically in the microsecond range, which will not have a significant impact on the real-time performance of the system.

[0065] The baseboard management controller 103 is used to obtain access to the real-time clock chip 101 by outputting a level signal to the control pin, so as to write the BMC system time to the real-time clock chip 101 and set the alarm time corresponding to the interrupt signal.

[0066] The baseboard management controller 103 is typically integrated on the server motherboard and runs independently of the operating system of the server host 104. It has its own processor, memory, and operating system, and can continue to work when the server host 104 is powered off or malfunctions, providing management functions such as remote monitoring, hardware configuration, and system recovery.

[0067] In clock synchronization scenarios, the baseboard management controller 103 acts as the time source. Administrators can log in to the BMC system via a network interface or a dedicated management port to set or update the system time. The baseboard management controller 103 uses this time as the authoritative time benchmark and actively pushes it to the server host 104 through the synchronization mechanism provided in this embodiment to ensure time consistency throughout the server system.

[0068] The baseboard management controller 103 includes: a GPIO control module 1031 and a time synchronization management module 1032. For example... Figure 4 The diagram shown is a schematic of the baseboard management controller in a BMC-based server clock synchronization system in this embodiment.

[0069] The GPIO control module 1031 is used to generate and output level signals to the control pins.

[0070] The GPIO control module 1031 serves as a bridge between the baseboard management controller 103 and external hardware. It converts operating system-level logic control instructions into actual electrical signal outputs through a software interface. This module typically includes a GPIO driver and a hardware register interface. The time synchronization management module 1032 writes high-level or low-level instructions to specific GPIO ports by calling the API functions of the GPIO driver.

[0071] After receiving an instruction, the GPIO control module 1031 operates the underlying hardware registers to control the output circuit of the corresponding pin, causing it to generate a voltage signal conforming to TTL or CMOS level standards. This signal is transmitted through PCB traces to the control pin 1024 of the channel switching chip 102, completing the channel switching control. The GPIO control module 1031 also has a pin status reading function, which can monitor the actual level status of the control pins, providing feedback information to the software and ensuring the correct execution of the channel switching operation.

[0072] In the clock synchronization process, the GPIO control module 1031 needs to switch the channel to the BMC side before writing the time data, and then switch back to the server host side after completing the configuration. These two switching actions are prerequisites for the smooth operation of the entire synchronization mechanism.

[0073] The time synchronization management module 1032 is used to write the BMC system time into the time register 1011 and write the delayed trigger time into the alarm clock register 1012 to set the alarm time after obtaining access rights; wherein, the delayed trigger time is the BMC system time plus the preset delay duration.

[0074] The time synchronization management module 1032 is a software component in the baseboard management controller 103 specifically responsible for clock synchronization logic. It encapsulates the complete time synchronization operation process. When the administrator updates the system time through the BMC interface or command-line tool, the time synchronization management module 1032 will be automatically triggered or manually invoked to begin performing the synchronization operation.

[0075] First, the time synchronization management module 1032 calls the GPIO control module 1031 to set the control pin 1024 of the channel switching chip 102 to a high level, ensuring that the baseboard management controller 103 can access the real-time clock chip 101. Then, the time synchronization management module 1032 uses the I2C bus driver to write the current BMC system time into each field of the time register 1011 in the format required by the real-time clock chip 101 (usually BCD code), thus completing the setting of the time base.

[0076] Next, the time synchronization management module 1032 calculates the delay trigger time, which is to add a preset delay duration (e.g., 1 second) to the current BMC system time, and writes this future time point into the alarm clock register 1012. The design of this preset delay duration takes into account the time overhead required for channel switching, signal transmission, and system response, ensuring that when the real-time clock chip 101 triggers an interrupt, the server host 104 has completed the preparation work for channel switching and interrupt listening.

[0077] Finally, the time synchronization management module 1032 enables the interrupt function of the real-time clock chip 101, activates the alarm clock comparison circuit, and sets the control pin 1024 to a low level through the GPIO control module 1031, returning the access right of the real-time clock chip 101 to the server host 104, thus completing the entire configuration process on the BMC side.

[0078] Server host 104 is used to respond to interrupt signals and read hardware time data from real-time clock chip 101 through channel switching chip 102 to update the system time corresponding to server host 104 according to the hardware time data.

[0079] Server host 104 is the computing platform of the entire server system, running the server operating system and various business application software. In the traditional time management mode, server host 104 only reads the initial time from the real-time clock chip 101 once at startup, and then relies on the operating system kernel's timer interrupts to maintain the system clock. The drawback of this mode is that if the time of the real-time clock chip 101 is modified externally (e.g., through the BMC), server host 104 cannot detect this change and must restart to reread the updated time. This embodiment introduces a hardware interrupt notification mechanism, enabling server host 104 to respond to time change events in real time while running, completing time synchronization without a restart, greatly improving system availability and the flexibility of time management.

[0080] Server host 104 includes: driver module 1041 and monitoring module 1042. For example... Figure 5 The diagram shown is a schematic representation of the structure of a server host in a BMC-based server clock synchronization system in this embodiment.

[0081] The driver module 1041 is located in the operating system kernel corresponding to the server host 104 and is used to respond to interrupt signals and set interrupt status indicators.

[0082] Driver module 1041 is a device driver running in the operating system kernel space, responsible for managing the hardware resources and interrupt handling logic of real-time clock chip 101. During the system startup phase, driver module 1041 registers the interrupt service routine of real-time clock chip 101 with the kernel's interrupt management subsystem and binds it to the interrupt number corresponding to interrupt output pin 1014.

[0083] When the real-time clock chip 101 sends an interrupt signal through the interrupt output pin 1014, the interrupt controller of the server host 104 captures this hardware event, finds the corresponding interrupt service routine entry point according to the interrupt vector table, and calls the processing function registered in the driver module 1041. The interrupt service routine runs in kernel mode, has the highest execution priority, and can respond to hardware events with extremely low latency.

[0084] During the processing, the driver module 1041 first reads the status register of the real-time clock chip 101 to confirm the interrupt source and type, and then clears the interrupt flag to prevent repeated interrupt triggering. Next, the driver module 1041 sets a kernel-shared interrupt status flag (such as a global variable or synchronization object) to notify the user-space monitoring module 1042 that a new time synchronization event has occurred.

[0085] This interrupt status identifier can be a Boolean flag, a counter, or an event object, depending on the operating system's kernel mechanism. Driver module 1041 also provides a communication interface between user space and kernel space, such as through dev device files, the sysfs file system, or ioctl system calls, enabling monitoring module 1042 to query the value of the interrupt status identifier.

[0086] The monitoring module 1042, located in the user space corresponding to the server host 104, is used to continuously query the interrupt status identifier; when the interrupt status identifier is determined to be valid, it reads hardware time data from the real-time clock chip 101 to update the system time.

[0087] The monitoring module 1042 is an application or system service process running in user space. It works in conjunction with the driver module 1041 to complete the final step of time synchronization. The monitoring module 1042 typically runs continuously in the background as a daemon, monitoring the interrupt status flags set by the driver module 1041 through polling or blocking. For example, the monitoring module 1042 can periodically (e.g., every 100 milliseconds) read the dev device file using the read system call, or use multiplexing mechanisms such as poll / select to block and wait for kernel event notifications.

[0088] When the interrupt status flag is detected to become valid, the monitoring module 1042 immediately performs a time synchronization operation. First, it reads the current hardware time data from the time register 1011 of the real-time clock chip 101 via the I2C user space interface or a dedicated RTC device interface. After the read time data is formatted and verified, the monitoring module 1042 calls the system time setting interface to write the hardware time data into the operating system's system clock, completing the time synchronization update.

[0089] As can be seen from the above technical solutions, the beneficial effects of this embodiment are:

[0090] This application provides a server clock synchronization system based on a Base Clock Management Controller (BMC), comprising: a real-time clock chip, a channel switching chip, a baseboard management controller, and a server host. The real-time clock chip receives and stores the BMC system time written by the baseboard management controller, maintains timekeeping based on the BMC system time, and outputs corresponding hardware time data. It also generates an interrupt signal via an interrupt output pin. The channel switching chip switches the access channel to the real-time clock chip between the server host and the baseboard management controller based on the level signal received by its control pin. The baseboard management controller obtains access to the real-time clock chip by outputting a level signal to its control pin, thereby writing the BMC system time to the real-time clock chip and setting the alarm time corresponding to the interrupt signal. The server host responds to the interrupt signal and reads the hardware time data from the real-time clock chip via the channel switching chip to update the system time corresponding to the server host based on the hardware time data. This system enables time synchronization to be completed without restarting the server host after the BMC time is modified, effectively avoiding business interruptions and improving the availability and real-time performance of the server system's time management.

[0091] like Figure 6 The image shows a specific embodiment of a server clock synchronization method based on BMC according to this application.

[0092] In this embodiment, a server clock synchronization method based on BMC includes the following steps:

[0093] Step 601: Write BMC system time data to the time register of the real-time clock chip through the baseboard management controller, so that the real-time clock chip keeps running based on the BMC system time and outputs the corresponding hardware time data.

[0094] The baseboard management controller first obtains the current BMC system time. The BMC system time may be manually set by the administrator via a web interface or command line, or it may be automatically synchronized from a network time protocol server. Since real-time clock chips typically store time data in BCD format, the baseboard management controller needs to convert the BMC system time from a Unix timestamp or structured date and time object to BCD code format, that is, convert the decimal values ​​of the year, month, day, hour, minute, and second fields to their corresponding binary-coded decimal representations. After the conversion, the baseboard management controller initiates a write operation to the real-time clock chip via the I2C bus driver, sending a start signal, slave device address, time register address, and data bytes for each time field according to the standard I2C protocol. After each byte is transmitted, it waits for an acknowledgment signal from the real-time clock chip. Once all data transmissions are complete, a stop signal is sent to terminate the communication.

[0095] After determining the time data, the real-time clock chip stores it in its internal time register and immediately begins timing based on the newly set time. The high-precision crystal oscillator integrated within the chip typically operates at 32.768kHz. After multiple stages of binary frequency division, it generates a precise 1Hz clock signal to drive the time counter to increment. When the seconds field jumps from 59 to 00, the minutes field is automatically incremented by 1, and so on, achieving a complete calendar function. This hardware-based timekeeping mechanism has extremely high stability, maintaining accurate time even when the system is powered by a backup battery, providing a reliable time reference for the entire server platform. The hardware time data output by the real-time clock chip can be read and used by other systems at any time via the I2C bus.

[0096] Before writing BMC system time data to the time register of the real-time clock chip via the baseboard management controller, the process also includes: setting the control pin of the channel switching chip to a high level via the baseboard management controller to establish the first access channel between the baseboard management controller and the real-time clock chip.

[0097] Before performing a time write operation, it is essential to ensure that the baseboard management controller (BMC) has exclusive access to the I2C interface of the real-time clock chip. Since the real-time clock chip is shared by the server host and the BMC, both systems may attempt to access it simultaneously, leading to I2C bus signal conflicts and data transmission errors. To avoid access conflicts, the BMC's GPIO control module writes a logic high-level instruction to a designated GPIO port. This instruction, after being processed by the underlying hardware registers, causes the corresponding GPIO pin to output a high-level signal, which is transmitted to the control pin of the channel switching chip. Upon detecting the high level, the channel switching chip immediately activates its internal analog switch array, connecting the second data interface connected to the BMC to the third data interface connected to the real-time clock chip, while simultaneously disconnecting the server host's first data interface.

[0098] The switching process is completed within microseconds. After the switch, a dedicated I2C communication channel, namely the first access channel, is established between the baseboard management controller and the real-time clock chip. After the first access channel is established, the baseboard management controller's access requests to the real-time clock chip will not be interfered with by the server host. Even if the server host attempts to access the chip simultaneously, its I2C signal will be isolated by the channel switching chip and will not be able to reach the real-time clock chip.

[0099] This hardware-level access control mechanism ensures the atomicity and reliability of time write operations, avoiding time data corruption caused by concurrent access. After switching channels, the baseboard management controller usually delays for a few milliseconds to wait for the channel to stabilize completely before starting I2C communication. This short delay has a negligible impact on the overall time synchronization performance.

[0100] Step 602: Write the delayed trigger time into the alarm register of the real-time clock chip to set the alarm time.

[0101] After writing the time register, the baseboard management controller needs to configure the alarm function of the real-time clock chip to trigger an interrupt at an appropriate time to notify the server host to read the updated time. The baseboard management controller reads the BMC system time that was just written to the time register or directly uses the current BMC system time as a reference, and then adds a preset delay, usually 1 or 2 seconds. This delay must be long enough to ensure that the baseboard management controller completes all configuration operations and returns access to the server host, but not too long to avoid affecting the real-time synchronization.

[0102] After calculating the delayed trigger time, the baseboard management controller converts it into the BCD code format required by the alarm register of the real-time clock chip. The structure of the alarm register is similar to that of the time register, but each field is configured with an enable bit to specify the matching conditions. To ensure that the alarm is triggered precisely at the delayed trigger time, it is usually necessary to enable all time fields such as seconds, minutes, and hours.

[0103] The baseboard management controller writes data to the alarm register via the I2C bus. The writing process includes sending a start signal, device address, alarm register address, and data bytes for each alarm field. Some real-time clock chips also require setting the alarm enable bit and interrupt enable bit in the control register simultaneously. The former activates the alarm comparison function, causing the chip to start comparing the current time with the alarm time, while the latter allows alarm events to trigger external interrupt signals.

[0104] After receiving the alarm configuration, the real-time clock chip's internal comparator starts working. In each clock cycle, it performs a full field comparison between the current time in the time register and the target time in the alarm register. When all enable fields match completely, the comparator outputs a matching signal to trigger the interrupt generation logic. To avoid repeated triggering, the alarm is usually configured to a single-trigger mode or the alarm enable bit is cleared by software after the interrupt is triggered, ensuring that each time synchronization operation triggers only one interrupt event.

[0105] After writing the delayed trigger time into the alarm register of the real-time clock chip to set the alarm time, the following steps are also included: the baseboard management controller sets the control pin to a low level to establish a second access channel between the server host and the real-time clock chip.

[0106] After completing the configuration of the time register and alarm register, the baseboard management controller has completed all operations that require access to the real-time clock chip. At this point, access to the real-time clock chip should be returned to the server host so that the server host can respond to the upcoming interrupt signal and read the time data.

[0107] After the time synchronization management module confirms the successful completion of all I2C write operations, it calls the GPIO control module API function to write a logic low-level instruction to the GPIO port of the control channel switching chip. The GPIO control module translates the instruction into a hardware operation, causing the corresponding GPIO pin to output a low-level signal, which is then transmitted to the control pin of the channel switching chip. Upon detecting the change from high to low on the control pin, the channel switching chip immediately performs a reverse switch. Its internal analog switch array reconfigures its connections, connecting the server host's first data interface to the real-time clock chip's third data interface, while simultaneously disconnecting the baseboard management controller's second data interface. The switch is completed within microseconds.

[0108] After the second access channel is established, the server host regains access to the real-time clock chip. At this time, the real-time clock chip has started running based on the time set by the baseboard management controller and the alarm clock function is configured and waiting for the trigger conditions to be met.

[0109] Interrupt signals are transmitted directly to the server host interrupt controller through the interrupt output pin of the real-time clock chip. This signal transmission path is independent of the I2C channel and is not affected by channel switching, ensuring that interrupt signals can be reliably transmitted even during channel switching without losing critical synchronization notifications. This time-sharing access mode effectively solves the conflict problem of two independent systems sharing a single hardware resource.

[0110] Step 603: When the hardware time data in the time register reaches the alarm time, the real-time clock chip outputs an interrupt signal to the server host through the interrupt output pin.

[0111] After the channel switches to the server host side, the real-time clock chip continues to maintain accurate timekeeping based on its internal crystal oscillator. The hardware time data in the time register increments in seconds, and the alarm clock comparator performs a comparison operation every time the second field is updated. The comparison logic is implemented by digital circuits, including a comparator array composed of XOR gates and AND gates, which compares the corresponding fields of the time register and the alarm clock register bit by bit. The overall comparison result is true only when all enable fields match. This pure hardware comparison mechanism ensures the accuracy of interrupt triggering with a response speed at the nanosecond level.

[0112] When the hardware time data reaches the alarm time preset by the baseboard management controller, the comparator outputs a matching signal to trigger the interrupt control logic inside the real-time clock chip. The interrupt control logic first sets the alarm flag in the chip status register to indicate that the alarm event has occurred. At the same time, if the interrupt enable bit is enabled, the interrupt output circuit is activated.

[0113] The interrupt output circuit drives the interrupt output pin of the real-time clock chip to generate a level change. The most common design is active low or triggered by a falling edge, meaning the interrupt output pin normally remains high. When an interrupt occurs, the internal open-drain or push-pull output circuit pulls the pin low, creating a high-to-low transition edge. This level transition signal is transmitted directly to the server host interrupt controller input pin through PCB traces. After detecting the level change, the interrupt controller looks up the corresponding interrupt service routine entry address in the interrupt vector table based on the interrupt number bound to the pin, and then sends an interrupt request to the processor core. After the processor completes the current instruction, it saves the context and switches to the interrupt service routine for execution.

[0114] This hardware interrupt-based notification mechanism reduces the delay from alarm time to interrupt service routine execution to the microsecond to millisecond level, which is far superior to software polling. Furthermore, the high priority of hardware interrupts ensures timely response even under heavy system load, and continuous checks without occupying the processor significantly reduce system resource consumption.

[0115] Step 604: The server host responds to the interrupt signal and sets the interrupt status flag.

[0116] After receiving an interrupt request, the server host processor core jumps to the interrupt service routine entry point registered by the real-time clock chip driver module according to the interrupt vector table. The interrupt service routine runs in the operating system kernel space and has the highest execution privileges and priority.

[0117] The interrupt service routine first confirms the legality and type of the interrupt source. It then reads the real-time clock chip's status register via the I2C bus to check if the alarm flag is set. After confirming that the interrupt comes from an alarm event, it clears the alarm flag to prevent repeated interrupt triggering and the formation of an interrupt storm. The clearing operation is achieved by writing a specific setting mode to the status register.

[0118] After hardware-level interrupt confirmation and clearing are completed, the core task of the interrupt service routine is to set an interrupt status flag to notify the user space monitoring module that there is a new time synchronization event that needs to be processed. The interrupt status flag can be implemented by setting a global variable or an atomic variable, using the kernel wait queue wake-up mechanism, or updating the readable status through the character device poll mechanism.

[0119] In a typical implementation, the driver module maintains an atomic variable as an interrupt status identifier and provides a character device interface for user space access. After confirming an alarm interrupt, the interrupt service routine uses an atomic operation to set this variable to 1, indicating a valid status. Simultaneously, if any user space processes are blocked waiting for the device, a wake-up function is called to wake them up. This design ensures thread safety of the interrupt status through atomic operations and provides an efficient notification mechanism through the kernel wait queue, allowing the user space monitoring module to receive time synchronization notifications with minimal latency.

[0120] Step 605: When the interrupt status flag is detected as valid, the server host reads the hardware time data from the time register and sets the hardware time data to the system time corresponding to the server host.

[0121] The user space monitoring module runs continuously as a daemon or system service. Its main task is to monitor the interrupt status flags set by the kernel driver module and perform real-time synchronization operations when a valid status is detected.

[0122] The monitoring mechanism can use a polling mode to periodically check the status variables, but this will introduce response latency and processor resource consumption due to the polling cycle. A more efficient implementation is to use a blocking wait mode, in which the monitoring module calls the read system call to perform a blocking read. If there is no interrupt event at present, the process is suspended to the driver module's waiting queue and enters sleep without occupying processor resources. When the kernel interrupt service routine sets the interrupt status flag, it wakes up the waiting process and the read call returns immediately.

[0123] Another common implementation is to use the poll or epoll system call. The monitoring module adds the device file descriptor to the monitoring set, calls poll and waits. When an interrupt occurs, the driver module updates the device poll mask to make it readable. The poll call then returns to notify that an event has occurred. This approach is particularly suitable for scenarios that require monitoring multiple event sources simultaneously.

[0124] After detecting that the interrupt status is valid, the monitoring module begins the time synchronization operation. First, it reads the current hardware time data from the real-time clock chip. The read BCD-formatted hardware time data needs to be converted into a time representation that the operating system can recognize. This conversion process restores each field's BCD code to decimal values ​​and assembles them into a complete date and time object. After the format conversion is complete, the monitoring module calls system time setting interfaces such as `settimeofday` or `clock_settime` to write the hardware time data to the operating system's system clock, completing the time synchronization update.

[0125] As can be seen from the above technical solutions, the beneficial effects of this embodiment are:

[0126] This application provides a server clock synchronization method based on a Baseboard Management Controller (BMC). The BMC system time data is written to the time register of a real-time clock chip by a Baseboard Management Controller (BMC), enabling the real-time clock chip to maintain timekeeping based on the BMC system time and output corresponding hardware time data. A delayed trigger time is written to the alarm register of the real-time clock chip to set the alarm time. When the hardware time data in the time register reaches the alarm time, the real-time clock chip outputs an interrupt signal to the server host via an interrupt output pin. The server host responds to the interrupt signal and sets an interrupt status flag. When the interrupt status flag is detected as valid, the server host reads the hardware time data from the time register and sets the hardware time data as the corresponding system time of the server host. This achieves real-time synchronization between the server system time and the BMC time, effectively avoiding business interruptions and operational inefficiencies caused by the server host having to restart to complete time updates.

[0127] like Figure 7 The image shows a specific embodiment of a BMC-based server clock synchronization device according to this application. This embodiment is a BMC-based server clock synchronization device, used for performing... Figure 6 A physical device for a server clock synchronization method based on BMC is provided. Its technical solution is essentially the same as the above embodiments, and the corresponding descriptions in the above embodiments also apply to this embodiment. This embodiment of a server clock synchronization device based on BMC includes:

[0128] The hardware time data output module 701 is configured to write BMC system time data to the time register of the real-time clock chip through the baseboard management controller, so that the real-time clock chip maintains timekeeping based on the BMC system time and outputs the corresponding hardware time data.

[0129] The alarm clock time setting module 702 is configured to write the delayed trigger time into the alarm clock register of the real-time clock chip to set the alarm time.

[0130] The interrupt signal output module 703 is configured to output an interrupt signal to the server host through the interrupt output pin when the hardware time data in the time register reaches the alarm time.

[0131] The interrupt status flag setting module 704 is configured to set the interrupt status flag when the server host responds to an interrupt signal.

[0132] The system time determination module 705 is configured to read hardware time data from the time register and set the hardware time data as the system time corresponding to the server host when the interrupt status flag is detected to be valid.

[0133] Those skilled in the art will understand that the embodiments of this application can be provided as methods or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or a combination of software and hardware.

[0134] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0135] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0136] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A server clock synchronization system based on BMC, characterized in that, include: Real-time clock chip, channel switching chip, baseboard management controller, and server host; The real-time clock chip is used to receive and store the BMC system time written by the baseboard management controller, maintain timekeeping based on the BMC system time, and output the corresponding hardware time data. An interrupt signal is generated through the interrupt output pin of the real-time clock chip; The channel switching chip is used to switch the access channel to the real-time clock chip between the server host and the baseboard management controller according to the level signal received by the control pin of the channel switching chip. The baseboard management controller is used to obtain access to the real-time clock chip by outputting the level signal to the control pin, so as to write the BMC system time to the real-time clock chip and set the alarm time corresponding to the interrupt signal. The server host is used to respond to the interrupt signal and read the hardware time data from the real-time clock chip through the channel switching chip, so as to update the system time corresponding to the server host according to the hardware time data.

2. The system according to claim 1, characterized in that, The real-time clock chip includes: Time register, alarm register, I2C communication interface, and interrupt output pin; The time register is used to output the hardware time data based on the time maintenance of the BMC system. The alarm clock register is used to store the alarm clock time set by the baseboard management controller. When the hardware time data matches the alarm clock time, an interrupt event is triggered. The I2C communication interface is connected to the channel switching chip and is used by the baseboard management controller or the server host to read and write to the time register and the alarm clock register. The interrupt output pin is used to output the interrupt signal to the server host when the interrupt event is triggered.

3. The system according to claim 2, characterized in that, The channel switching chip includes: The first data interface, the second data interface, the third data interface, and the control pin; The first data interface is connected to the server host, the second data interface is connected to the baseboard management controller, and the third data interface is connected to the I2C communication interface; The control pin is used to receive the level signal; when the level signal is high, it connects the second data interface and the third data interface; when the level signal is low, it connects the first data interface and the third data interface.

4. The system according to claim 2, characterized in that, The substrate management controller includes: GPIO control module and time synchronization management module; The GPIO control module is used to generate and output the level signal to the control pin; The time synchronization management module is used to write the BMC system time into the time register and write the delayed trigger time into the alarm register to set the alarm time after obtaining the access right; wherein, the delayed trigger time is the BMC system time plus a preset delay duration.

5. The system according to claim 1, characterized in that, The server host includes: Driver module and monitoring module; The driver module is located in the operating system kernel corresponding to the server host and is used to respond to the interrupt signal and set the interrupt status flag. The monitoring module, located in the user space corresponding to the server host, is used to continuously query the interrupt status identifier; when the interrupt status identifier is determined to be valid, it reads the hardware time data from the real-time clock chip to update the system time.

6. A server clock synchronization method based on BMC, wherein the method is applied to the system described in any one of claims 1-5, characterized in that, include: The baseboard management controller writes BMC system time data to the time register of the real-time clock chip, so that the real-time clock chip keeps running based on the BMC system time and outputs the corresponding hardware time data. The delayed trigger time is written into the alarm register of the real-time clock chip to set the alarm time; When the hardware time data in the time register reaches the alarm time, the real-time clock chip outputs an interrupt signal to the server host through the interrupt output pin. The server host responds to the interrupt signal and sets the interrupt status flag; When the interrupt status flag is detected as valid, the server host reads the hardware time data from the time register and sets the hardware time data as the system time corresponding to the server host.

7. The method according to claim 6, characterized in that, Before writing BMC system time data to the time register of the real-time clock chip via the baseboard management controller, the following steps are also included: The control pin of the channel switching chip is set to a high level by the substrate management controller to establish a first access channel between the substrate management controller and the real-time clock chip.

8. The method according to claim 6, characterized in that, After writing the delayed trigger time into the alarm register of the real-time clock chip to set the alarm time, the method further includes: The baseboard management controller sets the control pin to a low level to establish a second access channel between the server host and the real-time clock chip.

9. A server clock synchronization device based on BMC, characterized in that, include: The hardware time data output module is configured to write BMC system time data to the time register of the real-time clock chip through the baseboard management controller, so that the real-time clock chip maintains timekeeping based on the BMC system time and outputs the corresponding hardware time data. The alarm clock time setting module is configured to write the delayed trigger time into the alarm clock register of the real-time clock chip to set the alarm time; The interrupt signal output module is configured such that when the hardware time data in the time register reaches the alarm time, the real-time clock chip outputs an interrupt signal to the server host through the interrupt output pin. The interrupt status flag setting module is configured so that the server host sets the interrupt status flag in response to the interrupt signal. The system time determination module is configured such that when the interrupt status identifier is detected to be valid, the server host reads the hardware time data from the time register and sets the hardware time data as the system time corresponding to the server host.

10. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to execute a BMC-based server clock synchronization method as described in any one of claims 6-8.

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