Ultrahigh-voltage isolating ring structure and manufacturing method thereof

Abstract

The invention provides an ultrahigh-voltage isolating ring structure and a manufacturing method thereof. The structure is composed of a plurality of high-voltage laterally diffused metal oxide semiconductors. In order to solve the problem of punch-through breakdown caused by junction isolation on a high-resistivity substrate in the prior art, a deep trench isolation structure is arranged between the high-voltage laterally diffused metal oxide semiconductors or between the high-voltage laterally diffused metal oxide semiconductors and a device of a high-voltage circuit. The deep trench isolation structure is filled with a dielectric material, a leakage path in the substrate is cut off in a physical isolation mode, the punch-through breakdown problem is fundamentally solved, the isolation voltage endurance capability and the device reliability in a high-voltage circuit are remarkably improved, the device area can be optimized, and the deep trench isolation structure is suitable for a high-voltage integrated circuit of 1,000 V or above.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an ultra-high voltage isolation ring structure and its manufacturing method. Background Technology

[0002] In high-voltage integrated circuits (HVICs), a key application is to effectively isolate circuit modules operating in different voltage domains. Figure 1 A schematic diagram of a typical dual-sided high-voltage gate drive circuit is shown, which is an important application scenario of this invention. Figure 1 As shown, a high-voltage integrated circuit chip is used to control external high-side and low-side power transistors. The drive control circuit for the high-side power transistors needs to operate in a high-voltage environment where the voltage level fluctuates relative to ground; therefore, this part of the circuit is placed in a region known as the "high-voltage floating basin." To achieve effective electrical isolation between this high-voltage floating basin region and other low-voltage circuits on the chip, and to withstand the high voltages of hundreds or even thousands of volts that may occur between them, a "high-voltage isolation ring" is typically placed around the high-voltage floating basin.

[0003] This high-voltage isolation ring typically consists of multiple high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) transistors. These LDMOS transistors generally function in two ways: one part is configured as level-shifting transistors to transmit signals between the high-voltage and low-voltage domains; while the other part of the ring consists of high-voltage withstand transistors, whose main function is to withstand high voltage differences.

[0004] Within the high-voltage isolation ring, i.e., the high-voltage circuit region (also known as the "high-voltage floating basin"), electrical isolation is also required between the high-voltage LDMOS transistors, or between the high-voltage LDMOS transistors and other devices in the high-voltage circuit, to ensure normal device operation. In the prior art, this internal isolation is typically achieved through a ring structure formed by doping with a second conductivity type (hereinafter referred to as the "second conductivity type ring"). This second conductivity type ring is typically composed of a second conductivity type well, a second conductivity type doped layer, and a second conductivity type buried layer.

[0005] However, as application areas (such as high-end home appliances) place increasingly higher demands on the performance of power devices, high-voltage integrated circuits need to withstand higher operating voltages; for example, the turn-off withstand voltage requirement has increased to the 1000V level. To achieve such high withstand voltage, ultra-high resistivity semiconductor substrates are typically required. When using ultra-high resistivity substrates, the traditional second conductivity type ring structure exposes new technical challenges. Specifically, within the high-voltage circuit region, local voltage differences may exist between different nodes; for example, there may be a voltage difference of approximately 20V between the VB terminal in the high-side region and the VD terminal of the level-shifting transistor. To ensure reliable device operation, the punch-through voltage (punch BV) between the two points must be much higher than this voltage difference, for example, at least 30V. However, for structures using ultra-high resistivity substrates, the main leakage current path between the VB and VD terminals flows precisely through the high-resistivity second conductivity type substrate (P-sub). This leakage path makes it highly susceptible to punch-through breakdown between the buried layer (PBL) and the substrate, leading to a "punch-through" problem and making it difficult to meet withstand voltage requirements above 30V. Furthermore, the depletion balance between the conventional second-conductivity ring and the surrounding PN junction is difficult to control precisely, further limiting the improvement of the isolation ring's withstand voltage performance.

[0006] Therefore, there is an urgent need in this field for a new isolation structure and its manufacturing process to solve the punch-through breakdown problem of traditional junction isolation ring structures in ultra-high voltage and ultra-high resistivity substrate applications, thereby effectively improving the reliability of isolation of internal devices in high voltage circuits and the overall withstand voltage capability. Summary of the Invention

[0007] The purpose of this invention is to provide an ultra-high voltage isolation ring structure and its manufacturing method, in order to solve the technical problem in the prior art that traditional junction isolation rings have a punch-through problem in high voltage and high resistivity substrate applications, which limits the voltage withstand capability and reliability of the device.

[0008] To achieve the above and other related objectives, the present invention provides an ultra-high voltage isolation ring structure, which is composed of multiple high-voltage laterally diffused metal-oxide semiconductors and is used to isolate a high-voltage circuit from a low-voltage circuit. The operating voltage of the high-voltage circuit is greater than the operating voltage of the low-voltage circuit. A deep trench isolation structure is provided between the high-voltage laterally diffused metal-oxide semiconductors or between the high-voltage laterally diffused metal-oxide semiconductors and the devices in the high-voltage circuit for electrically isolating the devices in the high-voltage circuit.

[0009] Preferably, the high-voltage laterally diffused metal-oxide semiconductor includes: a body region; a source region formed in the body region; a drift region; and a drain region formed in the drift region.

[0010] Preferably, the deep trench isolation structure has a preset lateral distance from the drain area to optimize the device area.

[0011] Preferably, the ultra-high voltage isolation ring structure is formed in a first conductivity type epitaxial layer on a second conductivity type semiconductor substrate.

[0012] Preferably, at least one of the high-voltage laterally diffused metal-oxide-semiconductor is configured as a level-shifting transistor.

[0013] Preferably, in the high-voltage laterally diffused metal-oxide semiconductor configured as a level-shifting transistor, a first conductivity type buried layer is not provided at the interface between the second conductivity type semiconductor substrate and the first conductivity type epitaxial layer.

[0014] Preferably, in at least one of the high-voltage laterally diffused metal-oxide semiconductors not configured as level-shifting transistors, a first conductivity type buried layer is further provided at the interface between the second conductivity type semiconductor substrate and the first conductivity type epitaxial layer and located below the drift region.

[0015] Preferably, both the source region and the drain region are heavily doped regions of the first conductivity type.

[0016] Preferably, a heavily doped take-out region of a second conductivity type is also formed within the body region.

[0017] Preferably, the body region includes a second conductivity type well formed in the first conductivity type epitaxial layer.

[0018] Preferably, the body region further includes a second conductivity type buried layer disposed at the interface between the second conductivity type semiconductor substrate and the first conductivity type epitaxial layer.

[0019] Preferably, it further includes a second conductivity type top layer disposed within the drift region, wherein the second conductivity type top layer is electrically connected to a second conductivity type doped region within the body region composed of a second conductivity type well and a second conductivity type buried layer.

[0020] Preferably, a drift region field oxygen is formed on the surface of the drift region.

[0021] Preferably, it further includes a gate structure that covers a portion of the surface of the body region and extends to the drift region field oxygen, wherein the source region is self-aligned with one side of the gate structure.

[0022] Preferably, the deep trench isolation structure is filled with dielectric material.

[0023] Preferably, the dielectric material includes a liner layer formed on the sidewalls and bottom of the deep trench isolation structure, and a filler material filled within the deep trench isolation structure.

[0024] Preferably, the liner layer comprises silicon oxide.

[0025] Preferably, the filler material includes one or more selected from polycrystalline silicon and deposited silicon dioxide.

[0026] Preferably, the high-voltage lateral diffusion metal oxide semiconductor is a triple-reduced surface electric field lateral diffusion metal oxide semiconductor structure.

[0027] Preferably, the two high-voltage laterally diffused metal-oxide-semiconductor transistors are configured as level-shifting transistors.

[0028] Preferably, the first conductivity type is N-type and the second conductivity type is P-type.

[0029] Preferably, the first conductivity type is P-type, and the second conductivity type is N-type.

[0030] Preferably, the turn-off breakdown voltage of the ultra-high voltage isolation ring structure is not less than 1000V.

[0031] This invention also provides a method for manufacturing an ultra-high voltage isolation ring structure, wherein the ultra-high voltage isolation ring structure is composed of multiple high-voltage laterally diffused metal-oxide-semiconductor components and is used to isolate a high-voltage circuit from a low-voltage circuit, wherein the operating voltage of the high-voltage circuit is greater than the operating voltage of the low-voltage circuit. The method includes the following steps:

[0032] Step 1: Provide a semiconductor substrate of a second conductivity type, and form a buried layer of a first conductivity type and / or a buried layer of a second conductivity type on the semiconductor substrate of the second conductivity type;

[0033] Step 2: On the second conductivity type semiconductor substrate covered with the first conductivity type buried layer and / or the second conductivity type buried layer, a first conductivity type epitaxial layer is formed;

[0034] Step 3: Form a deep trench isolation structure in the first conductivity type epitaxial layer for electrical isolation between the plurality of high voltage laterally diffused metal-oxide semiconductors or between the high voltage laterally diffused metal-oxide semiconductors and the devices of the high voltage circuit;

[0035] Step 4: In the first conductivity type epitaxial layer, form the active structure of the plurality of high-voltage laterally diffused metal oxide semiconductors.

[0036] Preferably, the method no longer requires the formation of a first conductivity type buried layer for exhausting a second conductivity type ring based on junction isolation.

[0037] Preferably, in step three, the step of forming the deep trench isolation structure includes: etching a deep trench in the first conductivity type epitaxial layer; and filling the deep trench with a dielectric material.

[0038] Preferably, in step three, the etching depth of the deep trench is sufficient to penetrate the epitaxial layer of the first conductivity type.

[0039] As described above, the ultra-high voltage isolation ring structure and its manufacturing method of the present invention have the following beneficial effects:

[0040] 1. By employing a deep trench isolation structure within the high-voltage circuit region, physical isolation with dielectric materials replaces the traditional PN junction isolation, completely cutting off the lateral leakage path through the high resistivity substrate. This fundamentally solves the punch-through problem faced by traditional junction isolation structures under high voltage differentials, significantly improving the reliability and withstand voltage capability of the device's internal isolation.

[0041] 2. Since deep trench isolation structures do not require complex PN junction depletion balancing, there is no need for a first conductivity type buried layer for auxiliary depletion junction isolation rings, which simplifies device structure and manufacturing process, and allows for a reduction in the distance between the isolation structure and the active region, effectively optimizing the chip layout area and reducing production costs.

[0042] 3. The structure and method provided by this invention can effectively support the design of ultra-high voltage integrated circuits at 1000V and above, meeting the urgent needs of high-end home appliances, industrial control and other fields for high-performance power devices. Attached Figure Description

[0043] Figure 1 The diagram shown is a schematic of a prior art dual-sided high-voltage gate drive circuit.

[0044] Figure 2 The diagram shown is a layout schematic of an embodiment of the ultra-high voltage isolation ring structure of the present invention.

[0045] Figure 3 The diagram shown is a cross-sectional schematic of an embodiment of the ultra-high voltage isolation ring structure of the present invention.

[0046] Figure 4 The diagram shows a process flow diagram of the manufacturing method of the ultra-high voltage isolation ring structure of the present invention. Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] This invention provides an ultra-high voltage isolation ring structure. The high voltage isolation ring structure is composed of multiple high-voltage laterally diffused metal-oxide-semiconductor (MODS) semiconductors and is used to isolate high-voltage circuits from low-voltage circuits, where the operating voltage of the high-voltage circuit is greater than that of the low-voltage circuit. The core feature is the provision of a deep trench isolation structure 101 between the high-voltage laterally diffused MODS semiconductors or between the high-voltage laterally diffused MODS semiconductors and devices in the high-voltage circuit, for electrical isolation of the devices within the high-voltage circuit.

[0049] Figure 2 A top view of a layout of an ultra-high voltage isolation ring structure according to an embodiment of the present invention is shown. Figure 2 As shown, the deep trench isolation structure 101 is disposed between the active regions of the level-shifting transistors, serving to isolate the two level-shifting transistors from each other. The deep trench isolation structure 101, filled with dielectric material, forms a physical dielectric isolation wall, effectively blocking lateral leakage paths in the substrate. This solves the punch-through problem that easily occurs in traditional junction isolation structures when using ultra-high resistivity substrates, and avoids complex PN junction depletion balance control, thereby improving the device's isolation performance and breakdown voltage.

[0050] High-voltage laterally diffused metal-oxide-semiconductor (MOSFET) serves as the basic unit for forming a high-voltage isolation ring. It typically includes a body region, a source region formed within the body region, a drift region, and a drain region formed within the drift region.

[0051] To more clearly illustrate the positional relationships between the various structures in the embodiments of the present invention, Figure 3A cross-sectional view of a level-shifting transistor is shown. This structure is formed on a second conductivity type semiconductor substrate 102, on which a first conductivity type epitaxial layer 103 is formed. This epitaxial layer 103 forms the drift region of the device. The body region of the LDMOS is composed of a second conductivity type well 106 formed in the epitaxial layer 103, a second conductivity type doped layer 105, and a second conductivity type buried layer 104 disposed at the interface between the substrate 102 and the epitaxial layer 103. Within the body region, a first conductivity type source region 111 and a second conductivity type body exit region 112 are formed. A gate structure 109 covers the channel region between the source region 111 and the drift region 103 and extends to the drift region field oxide 108 on the surface of the drift region. A first conductivity type drain region 110 is formed within the drift region 103. As a preferred feature of the invention, the second conductivity type top layer 113 is disposed at a deeper location within the drift region. As a core feature of the present invention, the deep trench isolation structure 101 extends downward from the surface of the epitaxial layer 103, passes through the epitaxial layer 103 and enters the semiconductor substrate 102, and is used to effectively electrically isolate the drain region 110 on the left side from the nodes (such as VB) in the highside region on the right side. Figure 3 The image also shows a first conductivity type buried layer 107 disposed at the interface between the substrate 102 and the epitaxial layer 103 in the right high edge region.

[0052] In some embodiments, the deep trench isolation structure 101 and the drain region 110 have a preset lateral distance. This design allows for a shorter distance between the isolation structure and the active device while ensuring sufficient isolation withstand voltage, thereby effectively reducing the overall chip area, achieving a compact device layout, and reducing manufacturing costs.

[0053] To construct the above structure, in some embodiments, the ultra-high voltage isolation ring structure is formed in a first conductivity type epitaxial layer 103 on a second conductivity type semiconductor substrate 102. This substrate-epitaxy structure is a common platform for constructing high-voltage devices, wherein the second conductivity type semiconductor substrate 102 provides mechanical support and basic electrical environment for the device, while the first conductivity type epitaxial layer 103 serves as the main region for forming the active region of the device. To achieve ultra-high withstand voltage, the second conductivity type semiconductor substrate 102 is preferably a high resistivity semiconductor substrate.

[0054] In some embodiments, at least one high-voltage laterally diffused metal-oxide-semiconductor is configured as a level-shifting transistor. This is a common configuration in applications such as high-voltage gate drives, used to reliably transmit control signals between high-voltage and low-voltage domains.

[0055] As a preferred aspect of the invention, in some embodiments, in a high-voltage laterally diffused metal-oxide-semiconductor configured as a level-shifting transistor, a first conductivity type buried layer is not provided at the interface between the second conductivity type semiconductor substrate 102 and the first conductivity type epitaxial layer 103. For example... Figure 3 As shown, no first conductivity type buried layer is provided at the interface between the substrate 102 and the epitaxial layer 103 below the drift region of the left-side level-shifting transistor. This is because the deep trench isolation structure 101 replaces the traditional junction isolation ring, thus eliminating the need for a first conductivity type buried layer to assist in the depletion of the junction isolation ring. This simplifies the device structure and manufacturing process, and further saves layout area.

[0056] Accordingly, in some embodiments, at least one high-voltage laterally diffused metal-oxide-semiconductor not configured as a level-shifting transistor further includes a first conductivity type buried layer 107 disposed at the interface between the second conductivity type semiconductor substrate 102 and the first conductivity type epitaxial layer 103, and located below the drift region. This first conductivity type buried layer 107 is used to achieve a reduced surface electric field (RESURF) effect, thereby improving the withstand voltage capability of these voltage-bearing transistors, which are primarily used to withstand high voltages, by optimizing the electric field distribution at the bottom of the drift region.

[0057] In some embodiments, both the source region 111 and the drain region 110 are heavily doped regions of a first conductivity type. Heavy doping is used to form good ohmic contacts, effectively reducing contact resistance and thus improving the device's conduction performance.

[0058] In some embodiments, a heavily doped lead-out region 112 of a second conductivity type is also formed within the body region. This lead-out region 112, also known as a body contact region, is used to provide a stable potential connection for the body region, effectively suppressing latch-up effects caused by parasitic bipolar transistor effects and improving device reliability.

[0059] In some embodiments, the body region includes a second conductivity type well 106 formed in a first conductivity type epitaxial layer 103. The second conductivity type well 106 constitutes the base region for source region formation and defines the channel region.

[0060] In some embodiments, the body region further includes a second conductivity type buried layer 104 disposed at the interface between the second conductivity type semiconductor substrate 102 and the first conductivity type epitaxial layer 103. The body region is formed by the second conductivity type well 106 and the second conductivity type buried layer 104, which can provide better vertical isolation effect.

[0061] In some embodiments, a second conductivity type top layer 113 disposed within the drift region is further included, wherein the second conductivity type top layer 113 is electrically connected to a second conductivity type doped region within the body region formed by the second conductivity type well 106 and the second conductivity type buried layer 104. For example... Figure 3 As shown, the top layer 113 of the second conductivity type serves as an electric field modulation structure, effectively optimizing the electric field distribution within the drift region and alleviating electric field concentration, thereby significantly improving the device's breakdown voltage without increasing the drift region length. The electrical connection can be continuous or discontinuous.

[0062] In some embodiments, a drift region field oxygen 108 is formed on the surface of the drift region. This drift region field oxygen 108, as a relatively thick dielectric layer, helps to reduce the electric field strength on the surface of the drift region below, and is an auxiliary structure for achieving high withstand voltage. It is typically formed by a local oxidation (LOCOS) process or a shallow trench isolation (STI) process.

[0063] In some embodiments, a gate structure 109 is also included, which covers a portion of the surface of the gate structure 109 and extends onto the drift region field oxide 108, wherein the source region 111 is self-aligned with one side of the gate structure 109. The gate structure 109 typically includes a gate oxide layer and a polysilicon layer formed thereon. The portion of the gate structure 109 extending onto the field oxide 108 can act as a field plate, helping to further optimize the electric field distribution at the junction of the channel end and the drift region. The self-alignment of the source region 111 with the gate structure 109 is a standard MOS process that allows for precise control of the channel length.

[0064] In some embodiments of the deep trench isolation structure, the deep trench isolation structure is filled with dielectric material.

[0065] In some embodiments, the dielectric material includes a padding layer formed on the sidewalls and bottom of the deep trench isolation structure, and a filler material filling the deep trench isolation structure. The padding layer serves to alleviate stress between the filler material and the semiconductor material, improve the interfacial electrical properties, and enhance the long-term reliability of the isolation structure.

[0066] In some embodiments, the padding layer comprises silicon oxide. Specifically, the silicon oxide padding layer can be formed by growing on the silicon surface of the trench using a thermal oxidation process or by deposition using a chemical vapor deposition (CVD) process. In other alternative embodiments, the padding layer may also be silicon nitride (SiN), silicon oxynitride (SiON), or a stacked structure (ONO) comprising silicon oxide and silicon nitride to meet different stress control or interface state density requirements.

[0067] In some embodiments, the filler material includes one or more selected from polycrystalline silicon and deposited silicon dioxide. For example, silicon dioxide can be deposited using a high-density plasma chemical vapor deposition (HDP-CVD) method, which has excellent trench filling capabilities and can avoid void formation. Alternatively, polycrystalline silicon can be deposited using a low-pressure chemical vapor deposition (LPCVD) process as the filler material. In other alternative embodiments, spin-on dielectric (SOG), amorphous silicon, or a combination of these materials can also be used.

[0068] In some embodiments, the high-voltage laterally diffused metal-oxide-semiconductor is a triple-reduced surface electric field laterally diffused metal-oxide-semiconductor structure. This advanced RESURF structure enables finer optimization of the electric field distribution in the drift region, thereby achieving higher breakdown voltage performance within a limited device size.

[0069] In some embodiments, two high-voltage laterally diffused metal-oxide-semiconductor transistors are configured as level-shifting transistors.

[0070] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. This corresponds to an N-channel high-voltage LDMOS, which is the most widely used device type in high-voltage integrated circuits.

[0071] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. This corresponds to a P-channel high-voltage LDMOS, which can be used to construct complementary high-voltage circuits.

[0072] Through the above structural optimizations, in some embodiments, the turn-off breakdown voltage of the ultra-high voltage isolation ring structure is not less than 1000V. This meets the stringent requirements of high-voltage gate driver chips in high-end home appliances, industrial control, and other application fields.

[0073] Please see Figure 4 The present invention also provides a method for manufacturing an ultra-high voltage isolation ring structure. The high voltage isolation ring structure is composed of multiple high voltage laterally diffused metal-oxide-semiconductor components and is used to isolate a high voltage circuit from a low voltage circuit. The operating voltage of the high voltage circuit is greater than that of the low voltage circuit. The method includes the following steps:

[0074] Step 1: Provide a second conductivity type semiconductor substrate 102, and form a first conductivity type buried layer 107 and / or a second conductivity type buried layer 104 on the second conductivity type semiconductor substrate 102. This step typically involves selecting a second conductivity type semiconductor wafer with a specific crystal orientation and high resistivity as the starting substrate 102, and then forming the first conductivity type buried layer 107 and / or the second conductivity type buried layer 104 in a predetermined area through photolithography and high-energy ion implantation processes. Afterward, high-temperature annealing is usually required to activate the implanted impurities and repair lattice damage.

[0075] Step 2: On a semiconductor substrate 102 of the second conductivity type covered with a first conductivity type buried layer 107 and / or a second conductivity type buried layer 104, a first conductivity type epitaxial layer 103 is formed. This step typically employs epitaxial growth techniques such as chemical vapor deposition (CVD) to grow a single-crystal first conductivity type epitaxial layer 103 with a predetermined thickness and doping concentration on the surface of the substrate 102. The quality of this epitaxial layer has a direct impact on the performance of the final device.

[0076] Step 3: A deep trench isolation structure 101 is formed in the first conductivity type epitaxial layer 103 for electrical isolation between multiple high voltage laterally diffused metal oxide semiconductors or between high voltage laterally diffused metal oxide semiconductors and devices in high voltage circuits.

[0077] Step 4: In the first conductivity type epitaxial layer 103, multiple high-voltage laterally diffused metal-oxide-semiconductor active structures are formed. This step includes a series of standard semiconductor manufacturing processes, such as forming the well region 106, source region 111, and drain region 110 by ion implantation, forming the gate structure 109 by thin film deposition and etching, forming the field oxide 108 by local oxidation or shallow trench isolation processes, and subsequent contact hole etching, metal interconnection, etc., to finally complete the fabrication of the high-voltage LDMOS device.

[0078] In some embodiments, the method no longer requires forming a first conductivity type buried layer for exhausting a second conductivity type ring based on junction isolation. This not only simplifies the number of photomasks and process steps but also provides greater freedom for optimizing device layout design.

[0079] In some embodiments, step three, forming the deep trench isolation structure 101, includes: etching a deep trench in the first conductivity type epitaxial layer 103; and filling the deep trench with a dielectric material. Specifically, this step may include: first, depositing and patterning a hard mask layer on the first conductivity type epitaxial layer 103, the hard mask layer being silicon nitride or a carbon-based material; second, using the hard mask layer as a mask, etching a deep trench with a high aspect ratio in the first conductivity type epitaxial layer 103 using anisotropic plasma etching processes, such as reactive ion etching (RIE) or deep reactive ion etching (DRIE); and third, after removing the hard mask layer, forming a pad layer on the inner surface of the trench using thermal oxidation or chemical vapor deposition (CVD) processes. Then, a filling material is deposited using methods such as high-density plasma chemical vapor deposition (HDP-CVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) until the deep trench is completely filled and the surface of the epitaxial layer 103 is covered. Finally, excess filling material on the surface of the first conductivity type epitaxial layer 103 is removed by chemical mechanical polishing (CMP) so that the top surface of the deep trench isolation structure 101 is flush with the surface of the first conductivity type epitaxial layer 103, thereby achieving global planarization and providing a good foundation for subsequent device manufacturing steps.

[0080] In some embodiments, in step three, the etching depth of the deep trench is sufficient to penetrate the epitaxial layer 103 of the first conductivity type. This ensures that the deep trench isolation structure 101 can extend from the chip surface all the way to the underlying semiconductor substrate 102, forming a complete dielectric isolation wall, thereby completely cutting off the lateral leakage path.

[0081] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An ultra-high voltage isolation ring structure, wherein the ultra-high voltage isolation ring structure is composed of multiple high-voltage laterally diffused metal-oxide-semiconductor components and is used to isolate a high-voltage circuit from a low-voltage circuit, wherein the operating voltage of the high-voltage circuit is greater than the operating voltage of the low-voltage circuit, characterized in that: A deep trench isolation structure is provided between the high-voltage laterally diffused metal-oxide semiconductors or between the high-voltage laterally diffused metal-oxide semiconductors and the devices in the high-voltage circuit to electrically isolate the devices in the high-voltage circuit.

2. The ultra-high voltage isolation ring structure according to claim 1, characterized in that: The high-voltage laterally diffused metal-oxide-semiconductor includes: a body region; a source region formed in the body region; a drift region; and a drain region formed in the drift region.

3. The ultra-high voltage isolation ring structure according to claim 2, characterized in that: The deep trench isolation structure and the drain area have a preset lateral distance to optimize the device area.

4. The ultra-high voltage isolation ring structure according to claim 2, characterized in that: The ultra-high voltage isolation ring structure is formed in a first conductivity type epitaxial layer on a second conductivity type semiconductor substrate.

5. The ultra-high voltage isolation ring structure according to claim 4, characterized in that: At least one of the high-voltage laterally diffused metal-oxide-semiconductor is configured as a level-shifting transistor.

6. The ultra-high voltage isolation ring structure according to claim 5, characterized in that: In the high-voltage laterally diffused metal-oxide-semiconductor configured as a level-shifting transistor, a first conductivity type buried layer is not provided at the interface between the second conductivity type semiconductor substrate and the first conductivity type epitaxial layer.

7. The ultra-high voltage isolation ring structure according to claim 5, characterized in that: In at least one of the high-voltage laterally diffused metal-oxide semiconductors not configured as level-shifting transistors, a first conductivity type buried layer is further included, disposed at the interface between the second conductivity type semiconductor substrate and the first conductivity type epitaxial layer, and located below the drift region.

8. The ultra-high voltage isolation ring structure according to claim 4, characterized in that: Both the source region and the drain region are heavily doped regions of the first conductivity type.

9. The ultra-high voltage isolation ring structure according to claim 8, characterized in that: The body region also contains a heavily doped take-out region of a second conductivity type.

10. The ultra-high voltage isolation ring structure according to claim 4, characterized in that: The body region includes a second conductivity type well formed in the first conductivity type epitaxial layer.

11. The ultra-high voltage isolation ring structure according to claim 10, characterized in that: The body region further includes a second conductivity type buried layer disposed at the interface between the second conductivity type semiconductor substrate and the first conductivity type epitaxial layer.

12. The ultra-high voltage isolation ring structure according to claim 11, characterized in that: It also includes a second conductivity type top layer disposed within the drift region, wherein the second conductivity type top layer is electrically connected to a second conductivity type doped region within the body region composed of a second conductivity type well and a second conductivity type buried layer.

13. The ultra-high voltage isolation ring structure according to claim 2, characterized in that: The surface of the drift region is covered with drift region field oxygen.

14. The ultra-high voltage isolation ring structure according to claim 13, characterized in that: It also includes a gate structure that covers a portion of the surface of the body region and extends to the drift region field oxygen, wherein the source region is self-aligned with one side of the gate structure.

15. The ultra-high voltage isolation ring structure according to claim 1, characterized in that: The deep trench isolation structure is filled with dielectric material.

16. The ultra-high voltage isolation ring structure according to claim 15, characterized in that: The dielectric material includes a liner layer formed on the sidewalls and bottom of the deep trench isolation structure, and a filler material filled within the deep trench isolation structure.

17. The ultra-high voltage isolation ring structure according to claim 16, characterized in that: The liner layer comprises silicon oxide.

18. The ultra-high voltage isolation ring structure according to claim 16, characterized in that: The filler material includes one or more selected from polycrystalline silicon and deposited silicon dioxide.

19. The ultra-high voltage isolation ring structure according to claim 1, characterized in that: The high-voltage laterally diffused metal-oxide semiconductor is a triple-reduced surface electric field laterally diffused metal-oxide semiconductor structure.

20. The ultra-high voltage isolation ring structure according to claim 1, characterized in that: The two high-voltage laterally diffused metal-oxide-semiconductor transistors are configured as level-shifting transistors.

21. The ultra-high voltage isolation ring structure according to claim 4, 6, 7, 8, 9, 10, 11, or 12, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type.

22. The ultra-high voltage isolation ring structure according to claim 4, 6, 7, 8, 9, 10, 11, or 12, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type.

23. The ultra-high voltage isolation ring structure according to claim 1, characterized in that: The turn-off breakdown voltage of the ultra-high voltage isolation ring structure is not less than 1000V.

24. A method for manufacturing an ultra-high voltage isolation ring structure, wherein the ultra-high voltage isolation ring structure is composed of multiple high-voltage laterally diffused metal-oxide-semiconductor components and is used to isolate a high-voltage circuit from a low-voltage circuit, wherein the operating voltage of the high-voltage circuit is greater than the operating voltage of the low-voltage circuit, characterized in that... At least including: Step 1: Provide a semiconductor substrate of a second conductivity type, and form a buried layer of a first conductivity type and / or a buried layer of a second conductivity type on the semiconductor substrate of the second conductivity type; Step 2: On the second conductivity type semiconductor substrate covered with the first conductivity type buried layer and / or the second conductivity type buried layer, a first conductivity type epitaxial layer is formed; Step 3: Form a deep trench isolation structure in the first conductivity type epitaxial layer for electrical isolation between the plurality of high voltage laterally diffused metal-oxide semiconductors or between the high voltage laterally diffused metal-oxide semiconductors and the devices of the high voltage circuit; Step 4: In the first conductivity type epitaxial layer, form the active structure of the plurality of high-voltage laterally diffused metal oxide semiconductors.

25. The manufacturing method of the ultra-high voltage isolation ring structure according to claim 24, characterized in that: The method no longer requires the formation of a first conductivity type buried layer for exhausting a second conductivity type ring based on junction isolation.

26. The manufacturing method of the ultra-high voltage isolation ring structure according to claim 24, characterized in that: In step three, the step of forming the deep trench isolation structure includes: etching a deep trench in the first conductivity type epitaxial layer; and filling the deep trench with a dielectric material.

27. The manufacturing method of the ultra-high voltage isolation ring structure according to claim 26, characterized in that: In step three, the etching depth of the deep trench is sufficient to penetrate the first conductivity type epitaxial layer.

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