Adaptive precision floating point multiply accumulate operation apparatus, method, medium, terminal and program product

Abstract

The application provides a self-adaptive precision floating-point multiply-accumulate operation device, method, medium, terminal and program product, comprising: an unpacking and feature extraction module which unpacks and performs feature extraction on the received floating-point number to be operated; a precision level prediction module which predicts an initial precision level according to the input key features and the pre-set energy consumption mode and error threshold; a precision control module which generates an effective precision bit number control signal according to the initial precision level; a multiplication module which performs multiplication operation on the floating-point number to be operated according to the received effective precision bit number control signal; an error upper bound module which calculates the error upper bound; and compares the error upper bound with the error threshold; and a fusion accumulation module which accumulates the final multiplication result after normalization and rounding operation when the error upper bound is less than or equal to the error threshold, and outputs the operation result. The application can improve operation efficiency, reduce energy consumption and cost, and enhance numerical stability and reliability.

Description

Technical Field

[0001] This application relates to the field of floating-point arithmetic technology, and in particular to an adaptive precision floating-point multiplication and accumulation arithmetic device, method, medium, terminal and program product. Background Technology

[0002] In modern computing architectures, the floating-point unit (FPU) and the fused multiply-accumulate (FMA) unit are core components for achieving efficient numerical computation, especially in high-performance computing fields such as deep learning and scientific computing, where the balance between accuracy, energy consumption, and performance is crucial. However, existing technologies have the following shortcomings, making it difficult to meet the growing demand for efficient, flexible, and energy-optimized computing.

[0003] On the one hand, existing FPUs / FMAs mostly follow the IEEE-754 standard, employing fixed-width structures such as Booth partial product, compressed trees, normalization, and rounding. While this fixed structure ensures computational stability and accuracy, it is difficult to dynamically adjust according to task tolerance requirements or energy consumption constraints. In scenarios such as deep learning, although low / mixed-precision computing (such as FP16, BF16, INT8, etc.) and Tensor Core-type hardware have emerged, their precision levels are limited, and they mostly switch precision statically or in a coarse-grained manner, lacking per-operation adaptive and precision-provable mechanisms.

[0004] On the other hand, while approximate multiplier techniques (such as truncation, partial product gating, and error compensation) can reduce energy consumption, they often rely on heuristic or statistical methods to determine errors, making it difficult to provide a strict upper bound on the error during runtime. Although some dynamic precision methods can switch between multiple modes, they are mostly based on static thresholds and lack online recalculation and adaptive tolerance control. Existing error assessments generally rely on comparison of full-precision results or redundant calculations, while interval arithmetic and other methods can provide theoretical upper bounds, but their hardware implementation costs are high, and a low-cost, online provable solution has not yet been developed.

[0005] In addition, energy consumption control technologies (such as DVFS, gating, etc.) are often separated from precision selection, making it difficult to achieve fine-grained coordinated scheduling of energy consumption, precision, and performance.

[0006] Therefore, it is necessary to provide an adaptive precision floating-point multiplication and accumulation device, method, medium, terminal, and program product to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this application is to provide an adaptive precision floating-point multiplication and accumulation operation device, method, medium, terminal and program product to solve the technical problems of the prior art that lacks an adaptive and precision verifiable mechanism for each operation, is difficult to give a strict upper bound on the runtime error, and is difficult to achieve fine-grained coordinated scheduling of energy consumption, precision and performance.

[0008] To achieve the above and other related objectives, a first aspect of this application provides an adaptive precision floating-point multiply-accumulate arithmetic device, comprising:

[0009] The unpacking and feature extraction module is used to unpack the received floating-point numbers to be operated on to obtain unpacked data in a unified format, and to extract features from the unpacked data to extract key features.

[0010] The accuracy level prediction module is used to predict the initial accuracy level based on the input key features and the preset energy consumption mode and error threshold; the accuracy level is preset to multiple levels.

[0011] The precision control module is used to receive the initial precision level and generate an effective precision bit control signal based on the initial precision level.

[0012] The multiplication module is used to perform multiplication operations on the floating-point number to be operated on according to the received effective precision bit control signal, output the final multiplication result, and perform normalization and rounding operations on the final multiplication result.

[0013] The error upper bound module is used to calculate the error upper bound during multiplication operations; and compare the calculated error upper bound with the error threshold; if the error upper bound is greater than the error threshold, it is fed back to the precision control module, which adjusts the precision level and recalculates.

[0014] The fusion accumulation module is used to accumulate the final multiplication result after normalization and rounding operations and output the calculation result when the upper bound of the error is less than or equal to the error threshold.

[0015] In some embodiments of the first aspect of this application, the multiplication module includes: a gated partial product unit, used to generate partial products based on the Booth algorithm and to mask irrelevant partial products corresponding to the less significant bits according to the effective precision bit control signal; a compression tree unit, used to merge multiple partial products corresponding to the more significant bits generated based on a Wallace tree or a CSA tree to obtain an intermediate multiplication result with carry retention; and a pre-shift unit, used to perform alignment shift on the intermediate multiplication result to obtain a normalized final multiplication result.

[0016] In some embodiments of the first aspect of this application, the execution process of the error upper bound module includes: performing a logical OR operation on the truncated bits in the multiplication module operation to obtain sticky bits; and calculating the number of consecutive zeros starting from the highest bit in the truncated bits to obtain the number of leading zeros; calculating the basic error upper bound and the dynamic error upper bound in parallel based on the obtained sticky bits and the number of leading zeros, and taking the minimum value between the calculated basic error upper bound and the dynamic error upper bound as the error upper bound; comparing the error upper bound with the error threshold, and if the error upper bound is less than or equal to the error threshold, performing a fusion accumulation operation; if the error upper bound is greater than the error threshold, feeding back to the precision control module, and the precision control module adjusting the precision level for recalculation.

[0017] In some embodiments of the first aspect of this application, the energy consumption mode includes an economic mode, a balanced mode, and a performance mode.

[0018] In some embodiments of the first aspect of this application, the key features include an exponent value, a mantissa high-order bit, a sticky bit, a sign bit, and a flag bit.

[0019] In some embodiments of the first aspect of this application, a special value detection module is further included, which is used to detect whether the received floating-point number to be operated is a special value; if the received floating-point number to be operated is detected as a special value, then the special value is specially processed or the result is returned in advance; if the received floating-point number to be operated is detected as a non-special value, then an unpacking operation is performed.

[0020] To achieve the above and other related objectives, a second aspect of this application provides an adaptive precision floating-point multiplication and accumulation method, comprising:

[0021] The received floating-point numbers to be processed are unpacked to obtain unpacked data in a unified format, and feature extraction is performed on the unpacked data to extract key features.

[0022] Based on the input key features and the preset energy consumption mode and error threshold, an initial accuracy level is predicted; multiple accuracy levels are preset.

[0023] Receive the initial precision setting and generate an effective precision bit control signal based on the initial precision setting;

[0024] The floating-point number to be operated on is multiplied according to the received effective precision bit control signal, the final multiplication result is output, and the final multiplication result is normalized and rounded.

[0025] During the multiplication operation, the upper bound of the error is calculated; and the calculated upper bound of the error is compared with the error threshold; if the upper bound of the error is greater than the error threshold, the error is fed back to the precision control module, and the precision control module adjusts the precision level and recalculates.

[0026] If the upper bound of the error is less than or equal to the error threshold, the final multiplication result after normalization and rounding is accumulated and the calculation result is output.

[0027] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method.

[0028] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to implement the method.

[0029] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the method.

[0030] As described above, the adaptive precision floating-point multiplication and accumulation apparatus, method, medium, terminal, and program product of this application have the following beneficial effects:

[0031] (1) Improve computational efficiency: By dividing the floating-point multiplication precision into multiple precision levels, and using the precision level prediction module to select the initial precision level based on the input key features and the preset energy consumption mode and error threshold, most calculations can be completed quickly at the low precision level, and the precision level is upgraded for recalculation only when necessary, thereby reducing the overall computational load, improving throughput, and improving the overall floating-point operation efficiency.

[0032] (2) Reduce energy consumption and cost: By designing the gated partial product unit of the multiplication module, the operation unit can be activated on demand, avoiding unnecessary power consumption. Furthermore, at the array level, the accuracy level is dynamically allocated according to the task relevance, which greatly reduces the average energy consumption, extends the chip life and reduces the operating cost.

[0033] (3) Enhance numerical stability and reliability: The upper bound module of the error performs self-verification of each approximate result. It can ensure that the result error does not exceed the set error threshold without relying on full precision comparison. Furthermore, higher or stricter error thresholds are forced to be used in numerically sensitive operators (such as normalization, residual accumulation, and gradient aggregation) to ensure the stability and reliability of the calculation results. Attached Figure Description

[0034] Figure 1 The diagram shown is a block diagram of an adaptive precision floating-point multiplication and accumulation device according to an embodiment of this application.

[0035] Figure 2 The diagram shown is a block diagram of the multiplication module in one embodiment of this application.

[0036] Figure 3 The diagram shown is a schematic representation of the execution flow of the error upper bound module in one embodiment of this application.

[0037] Figure 4 The diagram shows the workflow of an adaptive precision floating-point multiplication and accumulation device according to an embodiment of this application.

[0038] Figure 5 The diagram shown is a flowchart of an adaptive precision floating-point multiplication and accumulation method in one embodiment of this application.

[0039] Figure 6 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0040] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0041] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, "first XX" and "second XX" are merely used to distinguish different XXs and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0042] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0044] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0045] <1> The IEEE-754 standard defines the representation and operation rules of floating-point numbers.

[0046] <2> Booth algorithm: An efficient multiplication algorithm used to reduce the number of partial products, thereby improving the efficiency of multiplication operations. It achieves this by encoding the multiplier into fewer non-zero terms.

[0047] <3> Normalization refers to adjusting the mantissa of a floating-point number to a standard range to ensure that the representation of the result conforms to the IEEE 754 standard.

[0048] <4> Rounding refers to adjusting the result of a floating-point number to a specified precision, usually according to the IEEE 754 standard.

[0049] <5> Wallace tree: A hardware structure for fast parallel addition operations. It is widely used in computer architecture to perform addition of multiple binary numbers, especially when calculating the sum of partial products in floating-point multipliers. Wallace tree reduces the latency of addition operations by recursively combining multiple adders into a tree structure, thereby improving the speed of operation.

[0050] <6> CSA (Carry-Save Adder) tree: It is a hardware adder structure used to accelerate the addition of multiple binary numbers in parallel. Its core principle is to use the CSA adder to transform the sum of 3 N-digit numbers into the sum of 2 N-digit numbers. After processing layer by layer, the input numbers are accumulated and finally the operation is completed through a large adder, thereby improving the operation speed.

[0051] <7> ULP (Unit in the Last Place): Represents the distance between a floating-point number and its nearest significant floating-point number, which is the value represented by the last significant bit (the least significant bit of the mantissa) of the floating-point number. In computer science, it is used to evaluate the precision and error of floating-point operations.

[0052] <8> LZC (Leading Zero Count): refers to the number of consecutive "0"s in a binary number, starting from the most significant bit, until the first "1" is encountered.

[0053] <9> Multilayer Perceptron (MLP): A type of feedforward artificial neural network that consists of an input layer, one or more hidden layers, and an output layer. Its core idea is to map the original input data to a complex output through multiple nonlinear transformations.

[0054] Traditional floating-point multiply-accumulate (FMA) operations generally employ full-precision calculations. Even in scenarios where numerical precision requirements are not high, they still consume full hardware resources, resulting in high overall power consumption and low efficiency. Furthermore, existing low-precision optimization solutions typically use fixed bit widths (such as FP16, BF16, or INT8) instead of FP32 (single-precision floating-point numbers), but this approach lacks dynamic adjustment capabilities, easily introducing excessive errors in numerically sensitive calculations and lacking flexibility in precision selection. In addition, in approximate calculations, existing technologies mostly rely on pre-set fixed truncation or quantization strategies, lacking adaptive verification of errors for each calculation result, which can easily lead to uncontrollable cumulative errors and insufficient reliability of approximate results. At the same time, existing floating-point arithmetic units in large-scale MAC (Multiply-Accumulate) arrays or AI accelerators are difficult to dynamically schedule according to task requirements, data distribution, and energy consumption constraints, thus limiting the overall energy efficiency ratio of the system. Therefore, this application provides an adaptive precision floating-point multiplication and accumulation operation device, method, medium, terminal, and program product. By dividing the precision into multiple precision levels and combining a self-verification mechanism with prediction and error upper bound modules, it maximizes the reduction of energy consumption and hardware overhead while ensuring that the results meet the set error threshold. At the same time, through energy consumption sensing and dynamic scheduling, the multiplication module and the fusion accumulation module can flexibly select the appropriate precision level according to the real-time power status, data characteristics, and task requirements. Furthermore, the adaptive verification of the results through the error upper bound module avoids the loss of control over accumulated errors, enhances the reliability and applicability of computation, and supports fast path optimization to cover more computational scenarios. In large-scale arrays, the scheduling mechanism enables different operation units to run with differentiated precision, achieving high energy efficiency and stable numerical performance, and improving the overall performance of the device.

[0055] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 A block diagram of an adaptive precision floating-point multiplication and accumulation operation device according to an embodiment of the present invention is shown. The adaptive precision floating-point multiplication and accumulation operation device 100 in this embodiment includes: an unpacking and feature extraction module 101, a precision level prediction module 102, a precision control module 103, a multiplication module 104, an error upper bound module 105, and a fusion accumulation module 106. The main calculation path of the adaptive precision floating-point multiplication and accumulation operation device 100 will be described in detail below.

[0056] The unpacking and feature extraction module 101 is used to unpack the received floating-point number to be operated to obtain unpacked data in a unified format, and to extract features from the unpacked data to extract key features.

[0057] Specifically, the received floating-point numbers a, b, and acc (all 32-bit) to be processed are decomposed into sign bits, exponent bits, and mantissa bits conforming to the IEEE-754 standard, thus obtaining unpacked data in a unified format. The following will use the IEEE-754 standard single-precision interface as an example.

[0058] In some embodiments of this application, the key features include an exponent value, a mantissa high-order bit, a sticky bit, a sign bit, and a flag bit.

[0059] Key features are extracted from the unpacked data in a unified format. These key features include the exponent, mantissa (high-order bits), sticky bit, sign bit, and flag bit. The exponent determines the magnitude of the floating-point number; the mantissa is the significant digit part of the floating-point number; the sticky bit indicates whether any bits were discarded during rounding; the sign bit indicates whether the floating-point number is positive or negative; and the flag bit indicates a specific operation state or mode, such as overflow, underflow, or rounding error.

[0060] The accuracy level prediction module 102 is used to predict the initial accuracy level based on the input key features and the preset energy consumption mode and error threshold; the accuracy level is preset to multiple levels.

[0061] For example, four precision levels are preset: L0, L1, L2, and L3. The precision levels are designed to achieve different computational precision and energy consumption control by adjusting the number of significant mantissa bits (p_eff) involved before multiplication. Furthermore, to balance computational precision and resource usage in floating-point operations, a truncation feature is designed to control the precision of the calculation result and reduce computational energy consumption. The formula for truncation is shown below:

[0062] ;Formula (1)

[0063] in, Indicates the number of bits to be truncated; This indicates the output valid bits, including the hidden bits (i.e., 1 sign bit and several exponent bits). Indicates the significant digits of the mantissa.

[0064] Different precision levels are predefined based on the number of significant digits (p_eff) in the mantissa. Each level corresponds to a different partial product size, energy consumption, and upper bound of error, as detailed in the table below:

[0065]

[0066] Table 1 Examples of four precision levels

[0067] In some embodiments of this application, the energy consumption modes include an economic mode, a balanced mode, and a performance mode. By designing these three energy consumption modes—economic mode, balanced mode, and performance mode—the computational precision and energy consumption of floating-point operations are dynamically adjusted to adapt to different applicable scenarios and achieve energy consumption optimization.

[0068] Specifically, the Eco mode is designed for energy-saving scenarios, such as low-power edge devices or operation under high temperature / power constraints. In Eco mode, the initial accuracy level is biased towards low accuracy L0 / L1 to maximize energy saving. The pre-set error threshold (τ_ulp) in this mode is relatively lenient, allowing for larger approximation errors. Furthermore, the upgrade step size in this mode is strictly progressive, that is, only L0→L1→L2→L3 is allowed, avoiding skipping low levels directly.

[0069] Balanced mode is designed for scenarios that compromise between performance and energy efficiency, and is suitable for most routine computing tasks. In balanced mode, the initial accuracy level is generally L1 / L2, which can dynamically balance power consumption and accuracy. The pre-set error threshold (τ_ulp) in this mode is set to a medium range, which ensures numerical stability without excessive energy consumption. Furthermore, the upgrade strategy in this mode is a progressive upgrade, but it can accelerate the leap. For example, under certain sticky bits that trigger LZC determination, it can directly upgrade from L1 to L3.

[0070] Performance mode (Turbo mode) is designed for scenarios that prioritize high precision or performance, such as numerically sensitive tasks (normalization / residual accumulation) or scientific computing. In performance mode, the initial precision level is biased towards high precision L2 / L3 to reduce the probability of backtracking and recalculation. At this time, the pre-set error threshold (τ_ulp) in this mode is more stringent, and the allowable error range is tightened. In addition, the upgrade step size in this mode can be skipped directly: for example, when a risk is detected from L0 / L1, it can directly enter L2 without having to transition step by step.

[0071] The weighted bias of the probability distribution output by the accuracy level prediction module is determined by the energy consumption mode (e_mode), configuring the initial accuracy level. For example, in economy mode, the weight of L0 / L1 is increased; in performance mode, the weight of L2 / L3 is increased. Simultaneously, the pre-set error threshold (τ_ulp) range is adjusted according to the energy consumption mode. For instance, in economy mode, the error threshold is large, allowing for a wider error range (e.g., 16–32 ULP); in balanced mode, the error threshold is medium (e.g., 4–8 ULP); and in performance mode, the error threshold is small, strictly controlling the error (1–2 ULP). Furthermore, in economy mode, the upgrade step size is increased gradually, delaying the transition to higher energy consumption levels as much as possible; in balanced mode, one level can be skipped directly when necessary to improve efficiency; and in performance mode, large jumps are allowed, prioritizing accuracy and throughput.

[0072] Furthermore, integrated event counters, such as a toggle counter, count the number of toggles of critical registers / buses to estimate dynamic power consumption; and an active cycle counter, count the number of active cycles of the multiplier array. When cycle power consumption or cumulative power consumption exceeds the budget, the controller can relax the error threshold (τ_ulp), allowing for larger errors, thereby reducing the number of upgrade recalculations; or lower the initial selection level, causing the precision level prediction module to tend to select L0 / L1, reducing power consumption; or trigger a global power reduction strategy, such as further locking the level range in economy mode. By designing an energy consumption-precision closed-loop control mechanism, the computing device can automatically adjust under different operating conditions (power fluctuations, chip temperature changes, task load switching), ensuring both safe operation and high energy efficiency.

[0073] The precision gear prediction module provides initial gear predictions (L0-L3) to the adaptive precision floating-point multiplication unit without performing full-precision comparisons, thereby reducing average energy consumption while ensuring that the upper bound of the error meets the error threshold. For example, the precision gear prediction module is trained based on a multilayer perceptron. The training method specifically includes: offline simulation of a large number of inputs (a, b, acc), self-verification using the upper bound of the error module to obtain the "minimum pass gear"; training a miniature multilayer perceptron using the "minimum pass gear" as a label; and selecting cross-entropy + energy consumption regularization as the loss function to encourage the model to prioritize low-energy gears when constraints are met. The trained precision gear prediction module is then deployed and used, receiving various input data, including exponentially related data such as exponential differences (…). The system includes special flags such as sign bits (Sa, Sb) and special values, mantissa-related data such as high-order mantissa segments and OR / XOR features, error estimation features such as sticky approximations, and pre-set energy consumption modes and error thresholds (τ_ulp). Based on the input features, it calculates the precision level (one of L0, L1, L2, L3) of the highest probability distribution of the output, using it as the initial precision level. The precision level prediction module in this embodiment consumes very little power, yet it can reduce the multiplication stage energy consumption by 20-40%. Furthermore, in conjunction with the error upper bound module, it forms a "prediction + self-verification + upgrade" closed loop, ensuring that the result is strictly within the error threshold constraint.

[0074] The precision control module 103 is used to receive the initial precision level and generate an effective precision bit control signal based on the initial precision level.

[0075] By transmitting the initial accuracy level output from the accuracy level prediction module to the accuracy control module as its initial state, appropriate accuracy requirements can be set before computation begins, thereby optimizing energy consumption and performance. For example, the accuracy control module is a finite-state machine (FSM) responsible for controlling the accuracy level, whether recalculation is needed, and whether to upgrade the accuracy. It should be understood that a finite-state machine is an abstract machine used to model system behavior. At any given time, it can only be in one of a finite set of predetermined states. Based on the current input and the current state, it determines its next state (which may remain unchanged) and may produce an output.

[0076] The multiplication module 104 performs multiplication of the floating-point numbers to be computed based on the received effective precision bit control signal, outputs the final multiplication result, and performs normalization and rounding operations on the final multiplication result. By activating and calculating only the circuit parts that contribute to the final precision target according to the selected precision level, the multiplication module saves energy. The final multiplication result is aligned and normalized (which may require additional shifting), supports nearest rounding or other modes (configurable), and outputs a floating-point result conforming to the IEEE-754 standard.

[0077] In some embodiments of this application, such as Figure 2 As shown, the multiplication module 104 includes: a gated partial product unit 1041, a compression tree unit 1042, and a pre-shift unit 1043. The gated partial product unit 1041 generates partial products based on the Booth algorithm and masks irrelevant partial products corresponding to the less significant bits according to the effective precision bit control signal; the compression tree unit 1042 merges multiple partial products corresponding to the more significant bits generated based on a Wallace tree or a CSA tree to obtain an intermediate multiplication result with carry retention; the pre-shift unit 1043 aligns and shifts the intermediate multiplication result to obtain a normalized final multiplication result.

[0078] Specifically, the mantissas a.mant and b.mant of the input floating-point numbers a and b are received and used for multiplication. Based on the Booth algorithm, the multiplication operation is converted into multiple partial products, which are then grouped into an array, i.e., a partial product column. A precision level gating mask is generated based on the received effective precision bit control signal, determining which partial product columns are activated. The precision level gating mask masks irrelevant partial product columns corresponding to the less significant bits, saving computation. Using a Wallace tree or CSA tree, the partial product columns corresponding to the more significant bits are quickly compressed into two numbers and merged (the sum and the carry). These two numbers are combined to form an intermediate multiplication result in carry-save format. Since the carry-save format is usually not a normalized floating-point format, the intermediate multiplication result needs to be aligned and shifted to prepare for subsequent rounding, thus obtaining the final multiplication result y_hat (y is 32 bits). For example, the gating strategy uses both clock gating and operand gating to reduce unwanted flips and glitches.

[0079] Furthermore, when the predicted exponent of the result is very small (with the risk of underflow), a fast path parallel to the main computation path is triggered to bypass the main computation path. A fast path such as Flush To Zero (FTZ) is selected to directly return 0; or the smallest nonnormal number approximation is used to avoid complex calculations.

[0080] The upper bound error module 105 is used to calculate the upper bound error during the multiplication operation; and compare the calculated upper bound error with the error threshold; if the upper bound error is greater than the error threshold, it is fed back to the precision control module, and the precision control module adjusts the precision level for recalculation.

[0081] Through the design of the error upper bound module 105, real-time error analysis is performed during multiplication operations to verify whether the calculation result at the initial precision level meets the standard. If it does not meet the standard, it automatically upgrades and recalculates, ensuring a conservative and dynamically tightenable error upper bound as the sole approval criterion. This dynamically adjusts the calculation precision, ensuring the accuracy of the calculation results while optimizing the use of computing resources. The entire process does not compare with the full-precision result; instead, the error upper bound module provides a provable conservative error upper bound to determine whether the standard is met.

[0082] The fusion accumulation module 106 is used to accumulate the final multiplication result after normalization and rounding operations and output the calculation result when the upper bound of the error is less than or equal to the error threshold. By designing the fusion accumulation module 106 to perform an approximate multiplication result added to the accumulator, i.e., (a*b) + acc, and supporting compensation calculations (such as Kahan compensation) or guard / sticky bit mechanisms, the accumulation error is further controlled. Furthermore, it records gear usage and energy consumption statistics.

[0083] In some embodiments of this application, such as Figure 3 As shown, the execution process of the error upper bound module includes: Step S31: Performing a logical OR operation on the truncated bits in the multiplication module operation to obtain sticky bits; and calculating the number of consecutive zeros starting from the highest bit in the truncated bits to obtain the number of leading zeros; Step S32: Calculating the basic error upper bound and the dynamic error upper bound in parallel based on the obtained sticky bits and the number of leading zeros, and taking the minimum value between the calculated basic error upper bound and the dynamic error upper bound as the error upper bound; Step S33: Comparing the error upper bound with the error threshold. If the error upper bound is less than or equal to the error threshold, a fusion accumulation operation is performed; if the error upper bound is greater than the error threshold, feedback is sent to the precision control module, and the precision control module adjusts the precision level for recalculation.

[0084] In step S31, the error upper bound module analyzes the truncated or discarded low-order bits from the multiplication module in the main calculation path, extracting two features: the number of sticky bits and the number of leading zeros. Specifically, a logical OR operation is performed on all truncated bits, outputting the sticky bit, indicating whether any truncated bits are 1. If Sticky=0, it means all truncated bits are 0, implying no error was introduced by truncating; if Sticky=1, at least one truncated bit is 1, indicating an error exists. Furthermore, the number of consecutive 0s starting from the most significant bit in the truncated bits is calculated, outputting the number of leading zeros (LZC). A larger LZC value indicates a smaller potential error in the result.

[0085] In step S32, based on the features extracted in step S31, the upper bound of the basic error and the upper bound of the dynamic error are calculated in parallel, and the minimum value of the upper bound of the basic error and the upper bound of the dynamic error is taken as the upper bound of the error. The specific formula is as follows:

[0086] ;Formula (2)

[0087] ;Formula (3)

[0088] ;Formula (4)

[0089] in, This represents the upper bound of the basic error, which is a very conservative estimate in the worst case, assuming that all truncated bits are 1, thus producing the maximum possible error. Indicates the output valid bits; The "+1" in formula (2) indicates the significant digits of the mantissa; the "+1" in formula (2) is used to cover the uncertainty of the final rounding and the small cumulative deviation. This represents the upper bound of the dynamic error, which uses the LZC value of the discarded block to tighten the error range; Indicates the number of leading zeros in the "truncated window" from high to low; Indicates the upper bound of the error.

[0090] In step S33, the calculated upper bound of the conservative error is... The error is compared with the preset error threshold (τ_ulp). If the upper bound of the error is less than or equal to the error threshold, the result is acceptable, that is, the initial accuracy level of the prediction is received, and the fusion accumulation operation is performed. If the upper bound of the error is greater than the error threshold, the error is fed back to the accuracy control module, which sends an accuracy level upgrade signal. The accuracy control module upgrades the accuracy level and triggers the entire calculation to be recalculated from the beginning until the result meets the standard.

[0091] As the decision center of the computing device, the precision control module decides to input the multiplication result to the fusion accumulation module if the error upper bound module verifies the result; if the error upper bound module fails the verification, the precision control module decides to upgrade the precision level and recalculate.

[0092] In some embodiments of this application, the adaptive precision floating-point multiplication and accumulation device further includes: a special value detection module, used to detect whether the received floating-point number to be operated on is a special value; if the received floating-point number to be operated on is detected as a special value, then the special value is specially processed or the result is returned in advance; if the received floating-point number to be operated on is detected as a non-special value, then an unpacking operation is performed. By designing a special value detection module, special cases can be quickly identified, unnecessary complex calculations can be avoided, and power consumption can be saved.

[0093] For example, the special value detection module checks whether the received floating-point number to be operated on is a special value and classifies it. If the exponent bits are all 1s and the mantissa bits are non-zero, it is detected as NaN (Not a Number); if the exponent bits are all 1s and the mantissa bits are all zeros, it is detected as Inf (Infinity); if the exponent bits are all zeros and the mantissa bits are all zeros, it is detected as Zero (Zero); if the exponent bits are all zeros and the mantissa bits are non-zero, it is detected as Subnormal (Disnormal Number). These four special values ​​are handled specially or the result is returned early, bypassing the main calculation path. Specifically: for NaN, the result is returned directly after short-circuiting to avoid meaningless subsequent calculations. For Inf, the result is returned directly after short-circuiting. For Zero, the multiplication operation is terminated early to save power. For subnormal numbers, in Flush To Zero (FTZ) mode, they are treated as 0 and processed in the Zero processing path mentioned above; or in Denormals Are Zero (DAZ) mode, the input nonnormal numbers are treated as 0, but subnormal numbers may still be generated in the output. That is, by detecting nonnormal numbers in advance, the most appropriate processing strategy is selected.

[0094] In some embodiments of this application, the potential for overflow or underflow in the multiplication result is predicted in advance based on the exponent bits of the unpacked floating-point numbers a and b. If overflow or underflow occurs, a fast path is triggered in advance, and the fast path is still self-verified by the error upper bound module, that is, the error caused by this approximation is ensured to be within an acceptable range by the error upper bound module. The formula for determining the underflow of the multiplication result is:

[0095] ;Formula (5)

[0096] in, It is the exponent value extracted from the floating-point number 'a'; It is the exponent value extracted from the floating-point number b; This is the offset of the exponent, for IEEE-754 single-precision floating-point numbers. It is usually 127; The exponent of the smallest normal number; This represents the safety boundary, used for advance judgment and to allow for margin. If the predicted multiplication result is in the underflow region, the fast path is triggered.

[0097] The formula for determining if a multiplication result is overflowing is as follows:

[0098] ;Formula (6)

[0099] in, It is the exponent value extracted from the floating-point number 'a'; It is the exponent value extracted from the floating-point number b; This is the offset of the exponent, for IEEE-754 single-precision floating-point numbers. It is usually 127; The exponent represents the largest normal number; Indicates the safety boundary.

[0100] For example, the first fast path is Flush To Zero (FTZ), which directly returns 0. The error upper bound module converts the interval upper bound to ULP and compares it with the error threshold. If the threshold is met, the calculation passes. The second fast path uses the minimum subnormal approximation (min-subnormal), outputting the minimum subnormal number or a small multiple thereof, which is also determined by the error upper bound module. If the error upper bound module determines that the error introduced by the fast path is too large, the computing device will not output this approximate result, but will instead fall back to the regular main computing path and recalculate.

[0101] like Figure 4 As shown, the working principle of the adaptive precision floating-point multiplication and accumulation device is further explained as follows: The input floating-point numbers a, b, and acc are decomposed into sign bits, exponent bits, and mantissa bits, and special values ​​(not numbers, infinity, zero, non-normal numbers) of the input values ​​are detected and classified. The detected special values ​​are specially processed or the results are returned in advance. At the same time, the formula (4) is used to predict in advance whether the multiplication result will overflow or underflow. If overflow or underflow occurs, the fast path is triggered. If overflow or underflow does not occur, feature extraction is performed on the unpacked data. Key features including exponent value, mantissa high bits, sticky bits, sign bits, and flag bits are extracted from the unpacked data. These key features, along with the pre-set energy consumption mode and error threshold, are input to the precision level prediction module. The precision level prediction module provides initial level prediction (L0~L3) and outputs the predicted initial precision level to the precision control module. The precision control module generates an effective precision bit control signal based on the initial precision level and transmits it to the multiplication module. During the multiplication module's operation, the error upper bound module calculates the error upper bound and compares it with the error threshold. If the error upper bound is less than or equal to the error threshold, the result passes, and the fusion accumulation operation is performed. If the error upper bound is greater than the error threshold, feedback is sent to the precision control module, which sends a precision level upgrade signal. The precision control module upgrades the precision level and triggers the entire calculation to be recalculated from the beginning until the result meets the standard. The fusion accumulation module accumulates the final multiplication results after normalization and rounding operations and outputs the calculation result.

[0102] In some embodiments of this application, the input / output interface supports the AXI-Stream or decoupledvalid / ready protocol. The following is a list of Control and Status Registers (CSRs) configured for the Adaptive-Precision Fused Multiply-Accumulate (AP-FMA) device:

[0103]

[0104] Table 2 List of configured registers

[0105] Furthermore, the adaptive precision floating-point multiply-accumulate operation device in this embodiment can be integrated as a PE (Processing Element) in the MAC array. When multiple adaptive precision floating-point multiply-accumulate operation devices form a MAC array, the whole can handle large-scale matrix multiplication / convolution. At the array level, the power consumption mode (e_mode) and error threshold (τ_ulp) of different PEs can be configured separately, rather than being uniformly fixed. In this way, it can be dynamically adjusted according to the current chip temperature, power supply status, and bandwidth usage, which is beneficial to the balance of global power consumption and performance.

[0106] In neural networks or scientific computing, some steps are particularly sensitive to numerical precision, such as normalization, residual additions, and gradient accumulation. These numerically sensitive operators are prone to distortion due to accumulated errors caused by low precision. Therefore, the error threshold (τ_ulp) can be increased to reduce the allowable error range; or the L2 / L3 precision level (higher / full precision) can be directly selected to ensure the numerical stability of critical operators, while other insensitive operators can still use low precision to save energy.

[0107] The adaptive precision floating-point multiply-accumulate arithmetic unit will undergo upgrades and recalculations (from L0→L1→L2→L3). If all computation units have to wait for upgrades and recalculations, it will disrupt the pipeline's timing. Therefore, a replay bypass queue is added to the array. Operations that need upgrades enter the queue first, and the array continues to process subsequent inputs without being blocked. The results are then merged after the upgrades are completed. In this way, a small number of upgrades will not affect the overall throughput, ensuring that the array can still maintain a high-efficiency pipeline.

[0108] In DNN (Deep Neural Network) inference or training, some tiles (sub-blocks) have low correlation or sparse data. For these parts, even if there is a slight error in the result, it will not significantly affect the final result. Therefore, for these tiles, it is preferable to select the L0 / L1 low precision level to obtain energy savings, while the numerical accuracy is still within the tolerable range.

[0109] The adaptive precision floating-point multiply-accumulate (ULP) arithmetic device of this application embodiment is formalized and simulated. A step-by-step verification method is adopted, following the IEEE anomaly propagation rules. Random vector statistics are used to compare the actual ULP error with the upper bound of the error to ensure the error remains within acceptable limits. Key performance indicators include upgrade rate (%), average power consumption / throughput, default rate, and level hit distribution. A lower upgrade rate is better, as it is affected by power consumption patterns and data distribution. Average power consumption / throughput represents the energy saving rate and performance loss (or improvement) relative to full-precision FMA. The ULP default rate should be 0 (results should not be submitted before the upper bound of the error is passed). The level hit distribution is used for offline retraining of the micro MLP. These key performance indicators are used to evaluate and optimize performance, ensuring that the arithmetic device can maintain high efficiency and high precision under different precision modes while reducing power consumption.

[0110] The adaptive precision floating-point multiplication and accumulation device in this embodiment selects the initial precision level through a precision level prediction module, and then performs self-verification by an error upper bound module. If the precision requirements are not met, the calculation is upgraded and recalculated, thus minimizing energy consumption under the precision constraint and realizing a closed loop of prediction + self-verification + upgrade and recalculation. By using gated partial product units, the participating partial product columns are dynamically controlled at the hardware level according to p_eff, avoiding invalid flips and reducing power consumption. Without full precision comparison, the error upper bound module calculates the error upper bound through sticky and LZC, ensuring the reliability of the calculation results. When the exponent is extremely small and the result underflows, FTZ / minimum non-normal approximation path is used to further reduce energy consumption. Combined with the energy consumption mode (e_mode), dynamic scheduling of the computing unit's energy consumption is realized. In large-scale MAC arrays, different levels can be allocated according to operator sensitivity and data correlation to improve the overall energy efficiency ratio.

[0111] It should be noted that although the adaptive precision floating-point multiply-accumulate arithmetic device of this application is primarily designed for IEEE-754 single-precision floating-point, it is also applicable to double-precision (FP64), half-precision (FP16 / BF16), and even fixed-point formats.

[0112] Figure 5 This is a flowchart illustrating the adaptive precision floating-point multiplication and accumulation method provided in an embodiment of this application. Figure 5 As shown, the adaptive precision floating-point multiplication and accumulation operation method includes the following steps:

[0113] Step S51: Unpack the received floating-point number to be operated to obtain unpacked data in a unified format, and extract features from the unpacked data to extract key features.

[0114] Step S52: Based on the input key features and the preset energy consumption mode and error threshold, predict the initial accuracy level; the accuracy level is preset to multiple levels.

[0115] Step S53: Receive the initial precision level and generate an effective precision bit control signal based on the initial precision level.

[0116] Step S54: Perform the multiplication operation of the floating-point number to be operated on according to the received effective precision bit control signal, output the final multiplication result, and perform normalization and rounding operations on the final multiplication result.

[0117] Step S55: During the multiplication operation, calculate the upper bound of the error; and compare the calculated upper bound of the error with the error threshold; if the upper bound of the error is greater than the error threshold, then feed back to the precision control module, and the precision control module adjusts the precision level for recalculation.

[0118] Step S56: If the upper bound of the error is less than or equal to the error threshold, the final multiplication result after normalization and rounding is accumulated and the calculation result is output.

[0119] It should be understood that the adaptive precision floating-point multiplication and accumulation operation method of this embodiment can realize the function of the above-mentioned adaptive precision floating-point multiplication and accumulation operation device, and for the sake of simplicity, it will not be described again here.

[0120] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0121] Figure 6 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 6As shown, the electronic terminal 600 includes at least one processor 601, a memory 602, at least one network interface 603, and a user interface 605. The various components in the electronic terminal 600 are coupled together via a bus system 604. It is understood that the bus system 604 is used to implement communication between these components. In addition to a data bus, the bus system 604 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 6 The general will label all buses as bus systems.

[0122] The user interface 605 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0123] It is understood that memory 602 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0124] In this embodiment of the invention, the memory 602 is used to store various types of data to support the operation of the electronic terminal 600. Examples of this data include: any executable program for operation on the electronic terminal 600, such as the operating system 6021 and application programs 6022; the operating system 6021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 6022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The methods provided in this embodiment of the invention can be included in the application program 6022.

[0125] The methods disclosed in the above embodiments of the present invention can be applied to processor 601, or implemented by processor 601. Processor 601 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 601 or by instructions in the form of software. The processor 601 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 601 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 601 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0126] In an exemplary embodiment, the electronic terminal 600 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to perform the aforementioned method.

[0127] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute... Figure 5 The method in the illustrated embodiment.

[0128] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when executed on a computer, causes the computer to perform... Figure 5 The method in the illustrated embodiment.

[0129] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0130] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0131] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0132] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0133] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0134] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0135] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).

[0136] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0137] In summary, addressing the technical problems of existing technologies lacking an adaptive and precision-provable mechanism for each operation, difficulty in providing strict upper bounds on runtime errors, and difficulty in achieving fine-grained collaborative scheduling of energy consumption, precision, and performance, this application provides an adaptive precision floating-point multiplication-accumulation operation device, method, medium, terminal, and program product. By dividing floating-point multiplication precision into multiple precision levels and utilizing a precision level prediction module to select the initial precision level based on the key features of the input and pre-set energy consumption patterns and error thresholds, most calculations can be completed quickly at the low precision level, with recalculation only performed when necessary. This reduces the overall computational load, improves throughput, and enhances overall floating-point operation efficiency. Furthermore, by designing a gated partial product unit in the multiplication module, the operation unit can be activated on demand, avoiding unnecessary power consumption. At the array level, precision levels are dynamically allocated based on task relevance, significantly reducing average energy consumption, extending chip lifespan, and lowering operating costs. This application employs an error upper bound module to self-verify each approximation result, ensuring that the result error does not exceed the set error threshold without relying on full-precision comparison. Furthermore, it enforces higher or stricter error thresholds in numerically sensitive operators (such as normalization, residual accumulation, and gradient aggregation) to ensure stable and reliable computation results. It supports fast path channels (FTZ / minimum non-normal approximation) for small exponential / underflow scenarios, enabling it to cover more boundary cases and guarantee continuous availability of computation results. Through flexible configuration registers (CSR), users can dynamically adjust precision and energy consumption strategies according to application scenarios (high performance / low power / balanced mode), enhancing system adaptability and expanding functional applicability. In scenarios such as deep learning, scientific computing, and graphics rendering, this application can significantly reduce power consumption while maintaining accuracy constraints, improving the overall performance-to-power ratio. It effectively resolves the contradiction between "excessive energy consumption in full-precision computation" and "uncontrolled error in low-precision computation" in existing technologies, thus improving performance. Therefore, this application effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0138] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. An adaptive precision floating-point multiplication and accumulation arithmetic device, characterized in that, include: The unpacking and feature extraction module is used to unpack the received floating-point numbers to be operated on to obtain unpacked data in a unified format, and to extract features from the unpacked data to extract key features. The accuracy level prediction module is used to predict the initial accuracy level based on the input key features and the preset energy consumption mode and error threshold; the accuracy level is preset to multiple levels. The precision control module is used to receive the initial precision level and generate an effective precision bit control signal based on the initial precision level. The multiplication module is used to perform multiplication operations on the floating-point number to be operated on according to the received effective precision bit control signal, output the final multiplication result, and perform normalization and rounding operations on the final multiplication result. The upper bound error module is used to calculate the upper bound error during multiplication operations. The calculated upper bound of the error is compared with the error threshold; if the upper bound of the error is greater than the error threshold, the error is fed back to the precision control module, which adjusts the precision level and recalculates. The fusion accumulation module is used to accumulate the final multiplication result after normalization and rounding operations and output the calculation result when the upper bound of the error is less than or equal to the error threshold.

2. The adaptive precision floating-point multiplication and accumulation arithmetic device according to claim 1, characterized in that, The multiplication module includes: A gated partial product unit is used to generate partial products based on the Booth algorithm and to mask irrelevant partial products corresponding to the least significant bits according to the effective precision bit control signal. A compressed tree unit is used to merge multiple partial products corresponding to the most significant bits based on Wallace trees or CSA trees to obtain intermediate multiplication results with carry retention. A pre-shift unit is used to align and shift the intermediate multiplication results to obtain a normalized final multiplication result.

3. The adaptive precision floating-point multiplication and accumulation arithmetic device according to claim 1, characterized in that, The execution process of the error upper bound module includes: Perform a logical OR operation on the truncated bits in the multiplication module operation to obtain sticky bits; and calculate the number of consecutive zeros starting from the most significant bit in the truncated bits to obtain the number of leading zeros. Based on the obtained viscous bits and the number of leading zeros, the upper bound of the basic error and the upper bound of the dynamic error are calculated in parallel, and the minimum value among the calculated upper bounds of the basic error and the upper bound of the dynamic error is taken as the upper bound of the error. The upper bound of the error is compared with the error threshold. If the upper bound of the error is less than or equal to the error threshold, a fusion accumulation operation is performed. If the upper bound of the error is greater than the error threshold, the error is fed back to the precision control module, which adjusts the precision level and recalculates.

4. The adaptive precision floating-point multiplication and accumulation arithmetic device according to claim 1, characterized in that, The energy consumption modes include economic mode, balance mode and performance mode.

5. The adaptive precision floating-point multiplication and accumulation arithmetic device according to claim 1, characterized in that, The key features include the exponent value, the mantissa high-order bits, the sticky bit, the sign bit, and the flag bit.

6. The adaptive precision floating-point multiplication and accumulation arithmetic device according to claim 1, characterized in that, Also includes: The special value detection module is used to detect whether the received floating-point number to be calculated is a special value; If the received floating-point number to be operated on is a special value, then the special value is handled specially or the result is returned in advance; If the received floating-point number to be processed is not a special value, then an unpacking operation is performed.

7. An adaptive precision floating-point multiplication and accumulation operation method, characterized in that, include: The received floating-point numbers to be processed are unpacked to obtain unpacked data in a unified format, and feature extraction is performed on the unpacked data to extract key features. Based on the input key features and the preset energy consumption mode and error threshold, an initial accuracy level is predicted; multiple accuracy levels are preset. Receive the initial precision setting and generate an effective precision bit control signal based on the initial precision setting; The floating-point number to be operated on is multiplied according to the received effective precision bit control signal, the final multiplication result is output, and the final multiplication result is normalized and rounded. During multiplication, calculate the upper bound of the error; The calculated upper bound of the error is compared with the error threshold; if the upper bound of the error is greater than the error threshold, a precision level upgrade signal is issued to adjust the precision level for recalculation. If the upper bound of the error is less than or equal to the error threshold, the final multiplication result after normalization and rounding is accumulated and the calculation result is output.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 7.

9. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the computer to implement the method as described in claim 7.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method as described in claim 7.

Images