Microstrip network layout optimization method based on Fourier series

Abstract

The invention relates to a microstrip network layout optimization method based on Fourier series, and belongs to the technical field of radio frequency circuit design. The method aims at solving the problems of topology dependence, boundary discontinuity and low efficiency caused by sharp increase of optimization parameters along with the area in a traditional rectangular spliced microstrip network. The core of the technical scheme is that a microstrip network boundary is modeled into a plane closed curve, the curve is represented through Fourier series decomposition, and a Fourier coefficient is optimized by taking circuit performance as a target drive, so that a microstrip layout with any shape and a continuous and smooth boundary is generated. According to the method, automatic design rule checking and port adding processes are integrated, and finally electromagnetic simulation iteration is carried out until a design target is met. The method can break through the limitation of the traditional topology, effectively improves the electromagnetic performance and design efficiency, and is widely applied to the microstrip network design of broadband matching, multi-band matching, harmonic control and the like.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency circuit design technology, and relates to a microstrip network layout optimization method based on Fourier series. Background Technology

[0002] With the deepening commercialization of 5G mobile communication technology and the accelerated development of 6G mobile communication technology, modern communication systems are placing unprecedentedly high demands on the performance indicators of core RF front-end equipment. As the core implementation carrier for RF front-end equipment such as matching networks, power dividers, and filters, the rationality of the layout design of microstrip networks directly determines the upper limit of the overall performance of the RF front-end.

[0003] Traditional microstrip network design has long relied on rectangular cell splicing, a method with significant limitations. Firstly, the rigid geometry of rectangles restricts the flexibility of electromagnetic field distribution at microstrip boundaries, limiting performance optimization. Secondly, while computer-aided design (CAD) and intelligent optimization algorithms have driven automated microstrip network design, traditional rectangular network optimization suffers from topology-dependent bottlenecks. Designers must manually define the microstrip topology beforehand, including the number and arrangement of rectangular cells, and then optimize parameters such as the length and width of the rectangles. This approach not only heavily relies on the designer's personal experience but also risks missing out on better irregular shape solutions due to the pre-defined topology.

[0004] In recent years, research has proposed a QR code-shaped microstrip network optimization approach. This method discretizes the microstrip region into a pixelated array of cells and constructs the boundary by optimizing the retention or removal state of each cell, thus enabling the exploration of more flexible microstrip shapes without the need for a predefined fixed topology. However, this approach has two inherent drawbacks. First, the pixelated boundary suffers from stepped discontinuities, which can easily introduce additional electromagnetic losses. Second, under the necessary constraint of fixed individual cell size to ensure modeling accuracy, the number of optimization parameters increases dramatically with the expansion of the optimization area, significantly increasing the burden on computational resources and leading to low design efficiency.

[0005] In summary, existing microstrip network layout optimization methods struggle to simultaneously achieve flexibility in shape, continuity of boundaries, and efficiency in the optimization process. Therefore, there is an urgent need in this field for a microstrip network layout optimization technique capable of generating arbitrary shapes, possessing continuous and smooth boundaries, and having a fixed number of optimization parameters, in order to overcome current design bottlenecks. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a microstrip network layout optimization method based on Fourier series.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A microstrip network layout optimization method based on Fourier series includes the following steps: Step 1: Establish the initial microstrip network layout; Step 2: Perform Fourier series decomposition on the outline of the initial microstrip network layout to obtain Fourier coefficients; Step 3: Optimize the Fourier coefficients using an optimization algorithm to generate the optimized microstrip network layout outline; Step 4: Perform Design Rule Check (DRC) and automatically add ports on the optimized microstrip network layout outline; Step 5: Perform performance simulation on the microstrip network layout after adding ports, and determine whether the design goals are met based on the simulation results. If they are met, output the microstrip network layout; otherwise, return to step 3 for iterative optimization.

[0008] Furthermore, the Fourier series decomposition includes representing the microstrip profile as a complex periodic function. And perform a complex Fourier series expansion, where ,in, For time variables, It is an integer. These are the Fourier coefficients.

[0009] Furthermore, the maximum order used in the complex Fourier series expansion is The Fourier coefficients include to ,common Each coefficient.

[0010] Furthermore, the aforementioned It is 20.

[0011] Furthermore, the optimization algorithm is the Covariance Matrix Adaptation Evolution Strategy (CMA-ES) algorithm.

[0012] Furthermore, the CMA-ES algorithm employs a variable initial step size strategy, including setting a larger initial step size in the early stages of optimization, and then adjusting the step size accordingly if continuous... N If there is no performance improvement in the next iteration, the initial step size is reduced.

[0013] Furthermore, the design rule check DRC includes minimum spacing constraints and self-intersection constraints, wherein the minimum spacing constraints ensure that the spacing between microstrip profile points is not less than a preset value, and the self-intersection constraints set a penalty term for the self-intersection of closed curves.

[0014] Furthermore, the port is automatically added with key points that identify the microstrip layout boundary, and a rectangle and electromagnetic simulation port are added centered on the key points.

[0015] Furthermore, the performance simulation is an electromagnetic (EM) simulation, and the error function is calculated using the circuit parameters obtained from the simulation.

[0016] Furthermore, the microstrip network layout is used for broadband matching, multi-band matching, or harmonic control matching networks.

[0017] The beneficial effects of this invention are as follows: (1) This invention completely breaks free from the pre-imposed limitations of traditional rectangular splicing patterns on microstrip network topology. By adjusting the Fourier coefficients, it is possible to flexibly generate continuous and smooth microstrip boundaries of arbitrary shapes, thereby overcoming the rigid constraints of rectangular geometry. This method allows the design space to no longer be limited to regular rectangular arrangements, enabling the exploration and realization of more irregular and high-performance microstrip structures, providing unprecedented possibilities for the ultimate optimization of RF front-end performance.

[0018] (2) Unlike the pixelated stepped boundaries generated by existing QR code-shaped methods, the microstrip boundaries generated by this invention are naturally continuous smooth curves. This continuity fundamentally eliminates the additional electromagnetic losses and parasitic effects introduced by boundary discontinuities, making the electromagnetic field distribution more ideal and significantly improving the final performance indicators of the microstrip network, such as improving insertion loss and return loss.

[0019] (3) This invention uses Fourier series to represent the boundary, and the optimization parameters are only a fixed set of Fourier coefficients, the number of which will not increase with the expansion of the physical size of the microstrip network. This feature greatly reduces the computational complexity of the optimization algorithm, avoids the curse of dimensionality that may occur during the optimization process, thereby significantly reducing the consumption of computing resources, significantly shortening the design cycle, and improving the overall optimization efficiency.

[0020] (4) This method embeds the design rule check and port addition process into the optimization loop. The system can automatically verify the electrical rules of the generated layout to ensure that it meets physical constraints such as minimum spacing, and automatically identify key locations to add simulation ports. This not only reduces manual intervention and avoids human error, but also ensures the practicality and manufacturability of the final design result, and accelerates the transformation process from design to product.

[0021] (5) The method proposed in this invention has universality, and its optimization objective can be flexibly defined by circuit performance indicators. Therefore, this method can be easily applied to a variety of complex microstrip network design scenarios, including but not limited to broadband matching, multi-band matching, and power amplifier design that requires precise control of harmonic impedance, demonstrating strong versatility and practical value.

[0022] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 A flowchart for microstrip network layout optimization based on Fourier series; Figure 2 This is a diagram showing the transformation between the microstrip network profile and the coefficients of the Fourier series. Figure 3 Microstrip profiles synthesized using Fourier series of different orders; Figure 4 The diagram shows the designed broadband matched microstrip network and its dimensions. Figure 5 S11 is designed to match broadband microstrip networks; Figure 6 The resulting multi-band matched microstrip network and its dimensions are shown in the diagram. Figure 7 S11 is a multi-band matched microstrip network; Figure 8 The diagram shows the harmonic control matching microstrip network and its dimensions. Figure 9 The input impedance of the 1-port microstrip network is matched for harmonic control. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0026] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0027] The core of this invention lies in providing a microstrip network layout optimization method based on Fourier series. The core idea of ​​this method is as follows: Figure 1 As shown, its optimization process mainly includes the following steps: establishing an initial layout, performing Fourier decomposition, optimizing Fourier coefficients, performing design rule checks and port additions, and performance simulation and iterative judgment.

[0028] Example 1: Design of a Broadband-Matched Microstrip Network This embodiment takes the design of a broadband matching network operating in the 1.5GHz to 2.5GHz frequency band as an example to demonstrate the basic workflow of the present invention.

[0029] Step 1: Establish initial layout. Based on the specific application scenario of the microstrip circuit to be optimized (such as broadband matching, multi-band matching), establish an initial layout as the initial value for the optimization algorithm; the initial layout can be designed from the schematic model or directly generated according to the required microstrip shape and structure.

[0030] Step 2: Perform Fourier decomposition on the initial microstrip layout outline. Figure 2 A flowchart illustrating the transformation between the microstrip network profile and the coefficients of the Fourier series is presented. The set of coordinates of the microstrip layout profile can be viewed as a periodic coordinate function, represented using the real part of the imaginary number. x Coordinates, the imaginary part of the imaginary number y Using coordinates, the microstrip layout outline can be represented as a complex periodic function. ,in Let the variable be time. Expanding it using a complex Fourier series yields:

[0031] in, It is an integer. These are the Fourier coefficients (complex numbers). Represented as:

[0032] The maximum order of the Fourier series used is defined as follows: Then the series contains coefficients .

[0033] Figure 3 The comparison between microstrip profiles synthesized using Fourier series of different orders and the initial profile is shown. It can be observed that as... As the number of microstrips increases, the detail of the synthesized microstrip profile also gradually increases. Extensive experimental verification shows that when… At this time, it can achieve a sufficiently clear approximation of most microstrip profiles; and the scaling of the microstrip profile only corresponds to the scaling of the Fourier coefficients, without increasing the number of coefficients, thus avoiding the problem of a surge in optimization parameters for large-size microstrip networks. It should be noted that the DC component a0 only affects the position of the microstrip profile (not its shape), therefore it does not need to be adjusted during the optimization process. ;when At that time, only 40 complex coefficients need to be optimized.

[0034] Step 3: Optimize the Fourier coefficients using an optimization algorithm. Set the error based on the desired circuit performance and select a suitable optimization algorithm to optimize the Fourier series. The optimization algorithm generates new Fourier coefficients for iteration.

[0035] Step 4: Design Rule Check (DRC) and Automatic Port Addition.

[0036] DRC Check: The newly generated Fourier coefficients are redrawn as a microstrip network, and a DRC check is performed. The check may include: Minimum Spacing Constraint: The microstrip profile is approximated as a series of polylines (connecting a series of profile points). The spacing between all profile points is measured, skipping several adjacent points during calculation (to avoid misjudging the spacing between adjacent points) and ignoring the spacing between the start and end points, ensuring the spacing is not less than a preset value (e.g., 0.5mm); Self-Intersection Constraint: A penalty term is set for the number of self-intersections of closed curves. If self-intersections exist, a large penalty value is returned to the optimization algorithm to guide the algorithm to generate a profile without self-intersections (to avoid circuit malfunctions, such as DC power supply branch failures). Layouts that fail DRC do not require further simulation; the penalty value is directly returned to the optimization algorithm to enter the next iteration. Layouts that pass DRC proceed to the port addition step.

[0037] Automatic port addition: This feature allows for the automatic configuration of multiple ports by recording specific locations such as the leftmost, rightmost, and topmost points of the microstrip layout boundary (adjusting the number of points according to port requirements); adding small rectangles centered on each boundary point (facilitating external interface connections); and adding electromagnetic (EM) simulation ports along the edges of the small rectangles.

[0038] Step 5: Performance Simulation and Iteration Termination Judgment. Perform EM simulation (e.g., using Keysight Advanced Design System, ADS) on the microstrip layout that has passed DRC and added ports; convert the circuit parameters (e.g., S-parameters, input impedance) obtained from the simulation into an error function. If the error function meets the design objective (e.g., the error function returns to zero), the optimization terminates and a qualified microstrip layout is output; if it does not meet the objective, the error value is returned to the optimization algorithm in Step 3, and the next iteration begins.

[0039] Figure 4 An optimized broadband matched microstrip network is presented. The design rules used in the optimization process specify a minimum spacing of 0.5 mm. The optimization objective of the broadband matched microstrip network is set as follows: to achieve performance within the 1.5–2.5 GHz frequency band. ~ The impedance is matched, and the return loss (S11) at port 1 is less than -25dB.

[0040] The network is a two-port network, with electromagnetic simulation ports added at the leftmost and rightmost endpoints of the microstrip layout. Figure 4 The optimized microstrip layout and its dimensions are presented. The layout is 59 mm long and 18 mm wide. It can be seen that the shape of the microstrip is different from that of traditional microstrip networks and exceeds the description scope of conventional rectangular spliced ​​microstrip networks. This further proves that the proposed microstrip network optimization method can provide richer contour solutions. Figure 5 The optimized return loss curve of port 1 of the microstrip network is shown. In the 1.5~2.5GHz frequency band, the return loss is always below -25dB.

[0041] Example 2: Design of a multi-band matching microstrip network with DC branch This embodiment demonstrates how the present invention can be used to design a more complex three-port microstrip network. Figure 6 An example of optimized design of a multi-band matched microstrip network with a DC-fed branch is presented, which can be used to power active devices. This microstrip network is a three-port network; the electromagnetic simulation ports are added at the leftmost, rightmost, and topmost points of the microstrip profile, respectively; during S-parameter simulation, port 3 (the connection point of the DC branch) is grounded. The optimization objective is set to achieve [optimization / optimization] at three frequency points: 0.7 GHz, 1.8 GHz, and 2.4 GHz. ~ The impedance matching and optimization process parameters are consistent with those in the broadband matching network design case. Figure 7 The optimized microstrip network layout and its dimensions are shown, with a length of 108 mm and a width of 34 mm. Figure 7 The return loss curve of port 1 of the optimized microstrip network is given. As can be seen from the figure, the return loss is less than -25 dB at the three frequency points of 0.7 GHz, 1.8 GHz and 2.4 GHz.

[0042] Example 3: Design of a Harmonic Controlled Matching Microstrip Network with DC Branch This embodiment demonstrates the effectiveness of the invention in the high-order application of harmonic control, for designing the output matching network of a power amplifier.

[0043] The workflow is similar to the previous two embodiments, but the core of performance simulation and error calculation is the input impedance Zin of port 1. The design target requires that within the fundamental frequency range of 1.5GHz to 1.7GHz, the real part of the input impedance be between 29 ohms and 31 ohms, and the imaginary part meet the capacitive or inductive requirements within a specific sub-frequency band; at the same time, within the third harmonic frequency range of 3.0GHz to 3.4GHz, the real part must be less than 1 ohm, and the imaginary part must also meet the corresponding requirements.

[0044] Figure 8 A harmonic-controlled matching microstrip network with a DC branch is presented. This network can be used as the output matching network for power amplifiers (PAs) requiring harmonic control. The design goal of this microstrip network is to achieve impedance matching between the fundamental and harmonic frequencies for a continuous Class-BJ power amplifier with a fundamental frequency range of 1.5–1.7 GHz. Specifically, within the 1.5–1.7 GHz range, the real part of the input impedance Zin1 at port 1 must be within the range of 1.5–1.7 GHz. Between 1.5 and 1.6 GHz; within the range of 1.5 to 1.6 GHz, the imaginary part of Zin1 needs to be within... Between 1.6 and 1.7 GHz; within the range of 1.6 to 1.7 GHz, the imaginary part of Zin1 needs to be within... Between. For the harmonic frequency range of 3~3.4GHz, the real part of Zin1 is required to be less than. Within the 3~3.2GHz range, the imaginary part of Zin1 needs to be in the range of 3~3.2GHz. Between 3.2 and 3.4 GHz; within the range of 3.2 to 3.4 GHz, the imaginary part of Zin1 needs to be in the range of 3.2 to 3.4 GHz. between. Figure 9 The optimized microstrip network layout and its dimensions are shown, with a length of 53 mm and a width of 30 mm. Figure 9 by Using the reference impedance, the input impedance of port 1 of the optimized microstrip network is presented on the Smith chart. As can be seen from the figure, the network meets the harmonic control requirements.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A microstrip network layout optimization method based on Fourier series, characterized in that: Includes the following steps: Step 1: Establish the initial microstrip network layout; Step 2: Perform Fourier series decomposition on the outline of the initial microstrip network layout to obtain Fourier coefficients; Step 3: Optimize the Fourier coefficients using an optimization algorithm to generate the optimized microstrip network layout outline; Step four: Perform design rule checks (DRC) and automatic port addition on the optimized microstrip network layout outline; Step 5: Perform performance simulation on the microstrip network layout after adding ports, and determine whether the design goals are met based on the simulation results. If they are met, output the microstrip network layout; otherwise, return to step 3 for iterative optimization.

2. The microstrip network layout optimization method based on Fourier series according to claim 1, characterized in that: The Fourier series decomposition includes representing the microstrip profile as a complex periodic function. And perform a complex Fourier series expansion, where ,in, For time variables, It is an integer. These are the Fourier coefficients.

3. The microstrip network layout optimization method based on Fourier series according to claim 2, characterized in that: The maximum order used in the complex Fourier series expansion is The Fourier coefficients include to ,common Each coefficient.

4. The microstrip network layout optimization method based on Fourier series according to claim 3, characterized in that: The It is 20.

5. The microstrip network layout optimization method based on Fourier series according to claim 1, characterized in that: The optimization algorithm is the Covariance Matrix Adaptive Evolution Strategy (CMA-ES) algorithm.

6. The microstrip network layout optimization method based on Fourier series according to claim 5, characterized in that: The CMA-ES algorithm employs a variable initial step size strategy, including setting a large initial step size in the early stages of optimization, and then adjusting the step size accordingly if continuous... N If there is no performance improvement in the next iteration, the initial step size is reduced.

7. The microstrip network layout optimization method based on Fourier series according to claim 1, characterized in that: The design rule check DRC includes minimum spacing constraints and self-intersection constraints. The minimum spacing constraints ensure that the spacing between microstrip profile points is not less than a preset value, and the self-intersection constraints set a penalty term for the self-intersection of closed curves.

8. The microstrip network layout optimization method based on Fourier series according to claim 1, characterized in that: The port is automatically added by identifying key points of the microstrip layout boundary and adding a rectangle and electromagnetic simulation port centered on the key points.

9. The microstrip network layout optimization method based on Fourier series according to claim 1, characterized in that: The performance simulation is an electromagnetic EM simulation, and the error function is calculated using the circuit parameters obtained from the simulation.

10. The microstrip network layout optimization method based on Fourier series according to claim 1, characterized in that: The microstrip network layout is used for broadband matching, multi-band matching, or harmonic control matching networks.

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