Trimming circuit, electronic equipment and storage medium
By designing the fuse module and readout module, and utilizing the chip's original pins to receive control signals, fuse adjustment was achieved without a communication interface and internal clock, solving the problem in existing technologies where adjustment could not be performed during the final testing stage.
Patent Information
- Application Number
- CN202511374985.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-24
- Publication Date
- 2026-02-13
Smart Images
Figure CN121531996A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics, and more particularly to a tuning circuit, electronic device, and storage medium. Background Technology
[0002] Fuse trimming circuits have the advantage of not increasing wafer manufacturing costs. Therefore, fuse trimming circuits are often used in integrated circuits. They can also be used to calibrate analog circuits, configure digital circuits, replace defective memory cells, and select chip functions and chip types.
[0003] Existing fuse trimming circuits typically include polysilicon fuse trimming circuits and electronic fuse trimming circuits. However, since existing polysilicon fuse trimming circuits usually require a large current to melt the polysilicon fuse, they need to use a high-voltage generation circuit and incorporate trimming pads in their structure. This allows the polysilicon fuse circuit to trim the fuse via probes during the wafer testing stage (before chip packaging). Furthermore, electronic fuse trimming circuits require external testing equipment and a programming enable signal via an integrated circuit's communication interface to trigger the fuse trimming operation. Additionally, the integrated circuit needs an internal clock signal to synchronize the programming timing. Therefore, electronic fuse trimming circuits require a communication interface and an internal clock interface to perform fuse trimming during the final testing stage (after chip packaging).
[0004] Therefore, how to solve the technical problem of not being able to make adjustments during the final testing phase without a communication interface and internal clock has become an urgent technical problem to be solved in the industry. Summary of the Invention
[0005] This invention provides a tuning circuit, electronic device, and storage medium that enables tuning during the final testing phase without a communication interface or internal clock.
[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a trimming circuit, comprising: The first multiplexed chip pin is used to receive a first control signal, which is either a high level or a low level. A fuse module, wherein the input terminal of the fuse module is coupled to the pin of the first multiplexing chip, and, based on the first control signal, the output terminal of the fuse module outputs a first fuse status signal, the first fuse status signal being used to characterize whether the first fuse in the fuse module has blown; The first reading module has its sampling terminal coupled to the output terminal of the fuse module, and outputs an output signal based on the first fuse status signal.
[0007] Optionally, the fuse module includes: The first NMOS transistor has its drain terminal as the input terminal of the fuse module. The control terminal of the first NMOS transistor is used to receive a third control signal. The source terminal of the first NMOS transistor is coupled to the sampling terminal of the first readout module and the first terminal of the first fuse. The first NMOS transistor is used to turn on or off based on the third control signal, which is a high level or a low level. The first fuse has its second end grounded.
[0008] Optional, also includes: The second multiplexed chip pin is used to receive a second control signal, which is either a high level or a low level. The termination fuse module has its sampling terminal coupled to the pin of the second multiplexing chip, and based on the second control signal, the output terminal of the termination fuse module outputs a second fuse status signal, which is used to characterize whether the second fuse in the termination fuse module has blown. The second reading module receives the second fuse status signal at its sampling terminal and outputs a third control signal based on the second fuse status signal. The first output terminal of the second reading module is coupled to the control terminal of the first NMOS transistor, and the second output terminal of the second reading module is coupled to the second input terminal of the termination fuse module.
[0009] Optionally, the termination fuse module includes: The second NMOS transistor has its drain terminal receiving the second control signal and its control terminal receiving the third control signal. The source terminal of the second NMOS transistor is coupled to the first terminal of the second fuse and the sampling terminal of the second readout module. The second NMOS transistor is turned on or off based on the third control signal, which is either high or low. The second fuse, with its second end grounded.
[0010] Optionally, the number of fuse modules is one, and the number of pins of the first multiplexed chip is one.
[0011] Optionally, the number of fuse modules is two or more, and the number of first multiplexed pins is two or more, wherein each first multiplexed pin is coupled to an input terminal of a corresponding fuse module.
[0012] According to a second aspect of the present invention, an electronic device is provided, comprising the tuning circuit described in the first aspect above.
[0013] According to a third aspect of the present invention, a storage medium is provided, including the adjustment circuit described in the first aspect above.
[0014] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: This invention provides a tuning circuit, electronic device, and storage medium. Since a first multiplexed chip pin is used to receive a first control signal (high or low level), the chip's circuitry operates based on a second signal. The input terminal of the fuse module is coupled to the first multiplexed chip pin, and based on the first control signal, the output terminal of the fuse module outputs a first fuse status signal, which characterizes whether the first fuse in the fuse module has blown. Therefore, this invention receives the first control signal through the original first multiplexed chip pin and controls the first fuse status signal output by the fuse module, allowing the invention to change the resistance in the fuse module without an external communication interface or clock signal. Furthermore, since the sampling terminal of the first reading module is coupled to the output terminal of the fuse module, and based on the first fuse status signal, the output terminal of the first reading module outputs an output signal. Thus, the tuning circuit of this invention enables tuning during the final testing phase without a communication interface or internal clock. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of the adjustment circuit in the first embodiment of the present invention. Figure 1 ; Figure 2 This is a schematic diagram of the adjustment circuit in the first embodiment of the present invention. Figure 2 ; Figure 3 This is a schematic diagram of the adjustment circuit in the third embodiment of the present invention. Figure 1 ; Figure 4 This is a schematic diagram of the adjustment circuit in the third embodiment of the present invention. Figure 2 . Detailed Implementation
[0017] As described in the background section, how to solve the technical problem of not being able to make adjustments during the final testing phase when there is no communication interface and internal clock has become an urgent technical problem to be solved in the industry.
[0018] In view of this, the present invention proposes a tuning circuit, comprising: a first multiplexed chip pin for receiving a first control signal, wherein the first control signal is a high level or a low level, and the chip circuit operates based on a second signal; a fuse module, wherein the input terminal of the fuse module is coupled to the first multiplexed chip pin, and the output terminal of the fuse module outputs a first fuse status signal based on the first control signal, wherein the first fuse status signal is used to characterize whether the first fuse in the fuse module has blown; and a first reading module, wherein the sampling terminal of the first reading module is coupled to the output terminal of the fuse module, and the output terminal of the first reading module outputs an output signal based on the first fuse status signal. Thus, the present invention enables tuning during the final testing phase without a communication interface and an internal clock.
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0020] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0021] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0022] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0023] [First Embodiment] Please refer to Figure 1 This invention provides a trimming circuit, comprising: Pin 100 of the first multiplexed chip is used to receive a first control signal, which is either high or low. The chip's circuitry operates based on a second signal. The fuse module 200 has its input terminal coupled to the first multiplexing chip pin 100, and, based on the first control signal, the output terminal of the fuse module 200 outputs a first fuse status signal, which is used to characterize whether the first fuse fuse1 in the fuse module 200 has blown. The first reading module 300 has its sampling terminal coupled to the output terminal of the fuse module 200, and outputs an output signal based on the first fuse status signal.
[0024] As one specific embodiment, please refer to Figure 2 The fuse module 200 includes: The first NMOS transistor MN1 has its drain terminal as the input terminal of the fuse module 200. The control terminal of the first NMOS transistor MN1 is used to receive a third control signal. The source terminal of the first NMOS transistor MN1 is coupled to the sampling terminal of the first reading module 300 and the first terminal of the first fuse 1. The first NMOS transistor MN1 is used to turn on or off based on the third control signal, which is either high or low level. The first fuse (fuse1) is grounded at its second end.
[0025] In this embodiment, at the start of adjustment, the first control signal is set to a high level, and the third control signal is also set to a high level by default. At this time, the first NMOS transistor MN1 is turned on, and the source of the first NMOS transistor MN1 outputs a high level, the first fuse 1 blows, and the resistance value of the path of the fuse module 200 represented by the first fuse status signal collected by the sampling terminal of the first reading module 300 is greater than 1000Ω. The output signal output by the first reading module 300 represents the adjusted signal or the function-selected signal. When no adjustment is required, the first control signal is low, the third control signal is high by default, the first fuse 1 will not blow, the resistance value of the path of the fuse module 200 represented by the first fuse status signal collected by the sampling terminal of the first reading module 300 is less than 100Ω, and the output signal output by the first reading module 300 is a default high level, representing the default and unadjusted signal, or the default function signal.
[0026] In this embodiment, there is one fuse module 200 and one first multiplexed chip pin 100.
[0027] In the above embodiments, since the first multiplexing chip pin 100 is used to receive the first control signal, which is either high or low level; the input terminal of the fuse module 200 is coupled to the first multiplexing chip pin 100, and based on the first control signal, the output terminal of the fuse module 200 outputs a first fuse status signal, which is used to characterize whether the first fuse (fuse1) in the fuse module 200 has blown; therefore, the present invention receives the first control signal through the original first multiplexing chip pin 100 of the multiplexing chip, and controls the first fuse status signal output by the fuse module 200 through the first control signal, so that the present invention can change the resistance in the fuse module 200 without an external communication interface and clock signal. Furthermore, since the sampling terminal of the first reading module 300 is coupled to the output terminal of the fuse module 200, and based on the first fuse status signal, the output terminal of the first reading module 300 outputs an output signal. Thus, the adjustment circuit of the present invention enables adjustment during the final testing stage without a communication interface and internal clock.
[0028] [Second Embodiment] As a variation of the first embodiment, the number of fuse modules 200 is two or more (not shown), and the number of first multiplexed pins is two or more, wherein each first multiplexed pin is coupled to an input terminal of a corresponding fuse module 200.
[0029] [Third Embodiment] This embodiment is a modified version of the first embodiment; please refer to [the original text]. Figure 3 The adjustment circuit also includes: The second multiplexing chip pin 400 is used to receive the second control signal as high or low level. The termination fuse module 500 is connected to the sampling terminal of the second multiplexing chip pin 400. Based on the second control signal, the output terminal of the termination fuse module 500 outputs a second fuse status signal, which is used to characterize whether the second fuse fuse2 in the termination fuse module 500 has blown. The second reading module 600 receives the second fuse status signal at its sampling terminal and outputs a third control signal based on the second fuse status signal. The first output terminal of the second reading module 600 is coupled to the control terminal of the first NMOS transistor MN1, and the second output terminal of the second reading module 600 is coupled to the second input terminal of the termination fuse module 500.
[0030] As one specific embodiment, please refer to Figure 4 The termination fuse module 500 includes: The second NMOS transistor MN2 has a drain terminal that receives a second control signal and a control terminal that receives a third control signal. The source terminal of the second NMOS transistor MN2 is coupled to the first terminal of the second fuse 2 and the sampling terminal of the second read module 600. The second NMOS transistor is turned on or off based on the third control signal, which is either high or low level. The second fuse, fuse2, has its second terminal grounded.
[0031] Specifically, at the start of the adjustment, the second control signal is set to low level, and the third control signal is high voltage by default. At this time, the second NMOS transistor MN2 is turned on. However, since the second control signal is low level, the second fuse 2 will not be blown. The resistance value of the circuit of the end fuse module 500 represented by the second fuse status signal is less than 100Ω. At this time, the third control signal output by the output terminal of the second reading module 600 is high level.
[0032] After the adjustment is completed, or when it is desired that the fuse module 200 does not need to be blown, the second control signal is set to a high level. At this time, the second NMOS transistor MN2 is turned on, the second fuse 2 is blown, and the second fuse 2 signal read by the sampling terminal of the second reading module 600 indicates that the resistance value of the path of the second fuse module 200 is greater than 1000Ω. At this time, the third control signal output by the second reading module 600 is a low level, the first NMOS transistor MN1 is turned off, the second NMOS transistor MN2 is turned off, thus avoiding the second rewriting of the first fuse 1 and the second fuse 2 in the fuse module 200 and the termination fuse module 500.
[0033] In addition, the present invention also provides an electronic device including the above-described adjustment circuit.
[0034] Accordingly, the present invention also provides a storage medium including the above-described adjustment circuit.
[0035] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A tuning circuit, characterized in that, include: The first multiplexed chip pin is used to receive a first control signal, which is either a high level or a low level. A fuse module, wherein the input terminal of the fuse module is coupled to the pin of the first multiplexing chip, and, based on the first control signal, the output terminal of the fuse module outputs a first fuse status signal, the first fuse status signal being used to characterize whether the first fuse in the fuse module has blown; The first reading module has its sampling terminal coupled to the output terminal of the fuse module, and outputs an output signal based on the first fuse status signal.
2. The adjustment circuit as described in claim 1, characterized in that, The fuse module includes: The first NMOS transistor has its drain terminal as the input terminal of the fuse module. The control terminal of the first NMOS transistor is used to receive a third control signal. The source terminal of the first NMOS transistor is coupled to the sampling terminal of the first readout module and the first terminal of the first fuse. The first NMOS transistor is used to turn on or off based on the third control signal, which is a high level or a low level. The first fuse has its second end grounded.
3. The adjustment circuit as described in claim 2, characterized in that, Also includes: The second multiplexed chip pin is used to receive a second control signal, which is either a high level or a low level. The termination fuse module has its sampling terminal coupled to the pin of the second multiplexing chip, and based on the second control signal, the output terminal of the termination fuse module outputs a second fuse status signal, which is used to characterize whether the second fuse in the termination fuse module has blown. The second reading module receives the second fuse status signal at its sampling terminal and outputs a third control signal based on the second fuse status signal. The first output terminal of the second reading module is coupled to the control terminal of the first NMOS transistor, and the second output terminal of the second reading module is coupled to the second input terminal of the termination fuse module.
4. The adjustment circuit as described in claim 3, characterized in that, The termination fuse module includes: The second NMOS transistor has its drain terminal receiving the second control signal and its control terminal receiving the third control signal. The source terminal of the second NMOS transistor is coupled to the first terminal of the second fuse and the sampling terminal of the second readout module. The second NMOS transistor is turned on or off based on the third control signal, which is either high or low. The second fuse, with its second end grounded.
5. The adjustment circuit as described in claim 1, characterized in that, The number of fuse modules is one, and the number of pins of the first multiplexed chip is one.
6. The adjustment circuit as described in claim 1, characterized in that, The number of fuse modules is two or more, and the number of first multiplexed pins is two or more, wherein each first multiplexed pin is coupled to an input terminal of a corresponding fuse module.
7. An electronic device, characterized in that, Includes the adjustment circuit as described in any one of claims 1-6.
8. A storage medium, characterized in that, Includes the adjustment circuit as described in any one of claims 1-6.