Dynamic competition perception workflow scheduling method for heterogeneous computing system

Abstract

A dynamic competition perception workflow scheduling method for a heterogeneous computing system comprises the following steps: constructing a scheduling problem model based on a scheduling object set and bus resources of an obtained system; constructing a dynamic competition perception simulator according to the scheduling problem model, wherein the method comprises the following steps of: decomposing a time-varying behavior of cross-domain bus data transmission into a time-invariant meta-process; each meta-process is mapped into a timeout event carrying a specific timestamp; the completion event indicates that all the timeout events to which the same scheduling object belongs are completed, so that the end of the task or cross-domain bus data transmission is marked; according to an event-driven mechanism, a completion event is arranged on the premise that the preorder constraint of a scheduling object is met, and total completion time estimation is generated while integration of multiple scheduling strategies is supported; according to the total completion time estimation, generating an approximate optimal scheduling solution by using a hybrid earliest completion time genetic algorithm; and optimizing the approximate optimal scheduling solution by adopting a quota weighted ant colony algorithm to generate a final scheduling solution.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a dynamic competition-aware workflow scheduling method for heterogeneous computing system. BACKGROUND

[0002] With the wide application of programmable logic devices in general computing, CPU-FPGA heterogeneous computing system (CFHCS) has become an important architecture form for processing compute-intensive and data-intensive workflows. Such a system is usually composed of CPU domain and FPGA domain, and the two domains perform data transmission through shared bus (such as on-chip AXI cross switch, board / backplane bus or off-chip high-speed interconnection). When facing multi-task workflows, the data movement across domain edges is coupled with the mapping, queuing and execution of tasks on heterogeneous processing units, which directly affects the total completion time and resource utilization of the system.

[0003] In the prior art, the communication delay is often treated as a constant proportional to the edge data volume, or the "average bandwidth / fixed link occupancy" is approximated, thereby decoupling between the computing domain and the communication domain. This processing ignores the dynamic competition between multiple concurrent data transmissions under the shared bus, and cannot reflect the influence of instantaneous load fluctuations on effective bandwidth, resulting in deviation of the scheduling result when deployed. In addition, the workflow scheduling in such CPU-FPGA heterogeneous computing system involves task ordering, processing unit selection and shared bus allocation, which are strongly coupled and discrete combination characteristics. SUMMARY

[0004] In view of the above defects of the prior art, the present application provides a dynamic competition-aware workflow scheduling method for heterogeneous computing system, which uniformly models full-duplex, directional bandwidth and concurrent capacity at the system level, can dynamically evaluate effective bandwidth and transmission completion conditions over time, has high-precision and fast-reusable evaluation capability to support search of large-scale candidate solutions, and applies an efficient solution search algorithm, thereby effectively shortening the total completion time of the workflow and improving resource utilization under the premise of ensuring feasibility.

[0005] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0006] A dynamic competition-aware workflow scheduling method for heterogeneous computing system, comprising the following steps:

[0007] S1, based on the scheduling object set and bus resources of the acquired system, a scheduling problem model is constructed;

[0008] S2, a dynamic competition-aware simulator is constructed according to the scheduling problem model, comprising:

[0009] Decompose time-varying behavior of cross-domain bus data transmission into time-invariant meta-processes; each meta-process is mapped to an over-time event carrying a specific timestamp; a completion event is used to indicate that all the over-time events belonging to the same schedule object have been completed, thereby marking the end of a task or cross-domain bus data transmission; according to an event-driven mechanism, the completion event is scheduled under the premise of meeting the schedule object's precedence constraints, thereby generating an overall completion time estimate while supporting integration of multiple scheduling strategies;

[0010] S3, according to the overall completion time estimate, generate an approximately optimal scheduling solution using a hybrid earliest completion time genetic algorithm; and optimize the approximately optimal scheduling solution using a quota-weighted ant colony algorithm to generate a final scheduling solution.

[0011] Preferably, S1 comprises:

[0012] S1.1, construct a workflow directed graph; and extract the set of schedule objects including tasks and bus data transmissions according to the workflow directed graph;

[0013] S1.2, abstract the bus resources of the system, and construct a dynamic bus communication competition model according to the bus communication bandwidth scaling caused by the budget-based arbitration mechanism;

[0014] S1.3, construct a scheduling problem model according to the dependency relationship in the workflow directed graph, the dynamic bus communication competition model, and the system resource constraints.

[0015] Preferably, S1.2 comprises:

[0016] Define the set of processing units P = P CPU ∪ P FPGA = {p1, p2, …, p n} of the CPU domain and the FPGA domain, and the set of full-duplex shared buses B = {b1, b2, …, b n} for cross-domain data communication.

[0017] For a shared bus b k and a direction d ∈ {CPU→FPGA, FPGA→CPU}, define: the maximum bandwidth of the direction and the maximum number of allocatable BDTs

[0018] At time τ, define the set of active BDTs in the same direction The total request bandwidth of the active BDTs is The request bandwidth of all active BDTs in the active set is

[0019] ​​​

[0020] As a preferred option, the budget-based arbitration mechanism includes: when the sum of the requested bandwidths of active BDTs on the same bus and in the same direction does not exceed the maximum bandwidth in that direction, service is provided according to their requested bandwidth; when the requested bandwidth exceeds the maximum bandwidth in that direction, the available effective bandwidth is scaled proportionally for all active BDTs based on their requested bandwidth percentage; the bandwidth scaling factor α(τ) at time τ is defined as:

[0021]

[0022] At time τ, each activity Actual effective bandwidth for:

[0023]

[0024] Preferably, in S1.3, the objective function of the scheduling problem model is to minimize the completion time of the workflow task; the completion time of the workflow task is calculated by integrating the actual effective bandwidth of the activity BDT; from the start time of the BDT, when the integral covers its data volume threshold, it is considered complete.

[0025] Preferably, the dynamic competition-aware simulator includes:

[0026] The simulation core is used to generate and manage completion events;

[0027] A static input generator is used to initialize the simulation and receive inputs including the directed graph of the workflow, system resource configuration, and candidate scheduling solutions. The static input generator dynamically updates the preorder constraints of each scheduling object in the directed graph of the workflow based on completion events. When all dependencies are satisfied, the scheduling object enters the scheduling phase and is handed over to the runtime scheduler.

[0028] The runtime scheduler is used to make scheduling decisions for scheduling objects entering the scheduling phase based on built-in strategies or user-specified strategies.

[0029] The resource manager is used to abstract the underlying hardware based on system resource configuration and generate the timeout and completion events at runtime.

[0030] Preferably, the resource manager includes a PU manager and a bus manager, both of which are initialized by system resource configuration;

[0031] The PU manager maintains tasks by queuing them into the PU queue. In each simulation cycle, the PU manager dequeues at most one task from each PU and transfers the timeout event carrying the execution time timestamp of the task and its corresponding completion event to the simulation core.

[0032] The bus manager maintains a set of active cross-domain bus data transfers on each bus and generates timeout events during runtime to dynamically scale bandwidth. In each simulation cycle, when a new cross-domain bus data transfer arrives, the bus manager generates a completion event, adds the cross-domain bus data transfer to the active set of its assigned bus, and transfers it to the simulation core. Based on the cycle interval and the effective bandwidth obtained in the previous cycle, the remaining data volume of each active cross-domain bus data transfer is updated. If the remaining data volume of a cross-domain bus data transfer drops to zero, it is removed from the set. Then, for the next cycle, the effective bandwidth of the remaining cross-domain bus data transfers is recalculated, the earliest completed cross-domain bus data transfer is identified, and a corresponding timeout event with the completion time as a timestamp is generated and transferred to the simulation core.

[0033] Preferably, the candidate scheduling solution includes a task scheduling sequence, a task-PU mapping sequence, and a BDT-bus allocation sequence; S3 includes:

[0034] S31. The dynamic contention-aware simulator generates a task-PU mapping sequence and a BDT-bus allocation sequence based on the task scheduling sequence using a hybrid earliest completion time scheduler; it optimizes the task scheduling sequence using a hybrid earliest completion time genetic algorithm; and it generates the approximate optimal scheduling solution by using the reciprocal of the total completion time estimate obtained by the simulation of the candidate scheduling solution by the dynamic contention-aware simulator as the fitness.

[0035] S32. The quota-weighted ant colony algorithm is used to optimize the BDT-bus allocation sequence in the near-optimal scheduling solution; the optimized BDT-bus allocation sequence is combined with its corresponding task scheduling sequence and task-PU mapping sequence to form a complete scheduling solution. The reciprocal of the total completion time estimate obtained by the dynamic competition-aware simulator is used as the fitness to generate the final scheduling solution.

[0036] Compared with the prior art, the beneficial effects of the present invention are reflected in:

[0037] 1. Unlike traditional technologies that ignore communication contention or convert dynamic communication contention into static serialized communication, this invention models dynamic communication contention, resulting in a better scheduling solution.

[0038] 2. Unlike traditional technologies that focus on scheduling tasks in an idealized scheduling environment, this invention considers communication-bus scheduling in heterogeneous computing systems based on a shared bus, so that the obtained scheduling solution can be practically applied to real heterogeneous computing systems. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the method architecture of Embodiment 1 of the present invention;

[0040] Figure 2 This is a schematic diagram of the dynamic competition sensing simulator according to Embodiment 1 of the present invention;

[0041] Figure 3 This is a flowchart illustrating the two-stage optimization algorithm based on MP-DCA in Embodiment 1 of the present invention. Detailed Implementation

[0042] To make the technical means, inventive features, objectives, and effects of the invention readily understandable, the invention is further described below with reference to specific illustrations. However, the invention is not limited to the embodiments described below.

[0043] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0044] Example 1:

[0045] like Figure 1 The method for dynamic contention-aware workflow scheduling in a heterogeneous computing system, as shown, includes the following steps:

[0046] S1. After obtaining the system's set of scheduling objects and bus resources, perform dynamic bus communication contention modeling to construct a scheduling problem model;

[0047] S1.1. By extracting scheduling objects from the task workflow, a set of scheduling objects containing task and bus data transmission is obtained.

[0048] The workflow is a directed graph G = (T, E, μ) representing tasks and dependencies, containing a task set T = {t1, t2, ..., t}. n}, representing the set of directed edges E = {e ij |t i ,t j ∈T,i≠j} and computational unit μ; task-computational unit mapping function: μ:T→{CPU,FPGA}. When μ(t i )≠μ(t j When there exists edge e) ij This edge corresponds to a cross-domain bus data transfer (BDT). Therefore, two sets of objects to be scheduled are extracted. in

[0049] S1.2 By abstracting the bus resources in CFHCS based on the shared bus and scaling the bus communication bandwidth due to the budgeted arbitration mechanism, dynamic bus communication contention modeling is achieved.

[0050] A CPU-FPGA heterogeneous computing system (CFHCS) based on a shared bus comprises a set of processing units (PUs) P = PCPU and FPGAs, representing two computing unit domains. CPU ∪P FPGA ={p1,p2,…,p n}, the set of full-duplex shared buses B = {b1, b2, ..., b} used for data communication between CPU and FPGA computing units. n}

[0051] For shared bus b k And the direction d∈{CPU→FPGA,FPGA→CPU}, defined as:

[0052] Maximum bandwidth in direction With the maximum number of allocatable BDTs

[0053] At time τ, define the set of activities in the same direction (BDT). Its total requested bandwidth It can be calculated as all those within the activity set. Activities Requested bandwidth The sum is:

[0054]

[0055] Based on the bus communication bandwidth scaling caused by the budgeted arbitration mechanism, a dynamic bus communication contention model is constructed:

[0056] The bus arbitrator employs a budget-based mechanism for BDT arbitration: when the sum of requested bandwidths of active BDTs on the same bus in the same direction does not exceed the maximum bandwidth for that direction, each BDT serves according to its requested bandwidth; when the total requested bandwidth exceeds the maximum bandwidth, the available effective bandwidth for all active BDTs is scaled proportionally based on their respective requested bandwidth proportions. Therefore, the bandwidth scaling factor α(τ) at time τ is defined as:

[0057]

[0058] Then at time τ, each activity Actual effective bandwidth for:

[0059]

[0060] S1.3. Based on the dependencies between scheduling objects and the objective function of minimizing the completion time of workflow tasks, and combined with the resource constraints in CHCS, construct a scheduling problem model.

[0061] To construct a model of the scheduling problem, feasibility and resource constraints need to be defined. The following decision variables are defined: x ik Used to represent task t i Map to Pup k ;z ik Indicates BDTdelta i Is it assigned to bus b? k Let bus b be an example. k The maximum BDT capacity in the direction d∈{CPU→FPGA,FPGA→CPU} is: Since each task is mapped to exactly one processing unit, each BDT is assigned to exactly one shared bus, and each bus has a BDT capacity limit, the following scheduling constraints apply:

[0062]

[0063] To construct the objective function, let the activity be denoted as . The source task is Its data transmission volume is Its starting moment For the source task The completion time of its completion time Defined as: from its start time The earliest time when the integral of the effective bandwidth with respect to time reaches the data volume threshold of this BDT.

[0064]

[0065] Let task t i In processing unit p m The execution time is Then its start time st(t) i ) and completion time ft(t) i ) is represented as:

[0066]

[0067] Where DPS(t) i ) for t i The set of direct predecessors, avail(t) i ,p m ) represents p m Can execute t i The earliest start time.

[0068] The goal of the optimization problem is to minimize the overall completion time of the workflow, i.e.:

[0069]

[0070] S2. Construct a dynamic contention-aware simulator (MP-DCA) based on the aforementioned scheduling problem model, including:

[0071] The time-varying behavior of cross-domain bus data transmission is decomposed into time-invariant meta-processes; each meta-process is mapped to a timeout event carrying a specific timestamp; the completion event indicates that all timeout events belonging to the same scheduling object have been completed, thereby marking the end of the task or cross-domain bus data transmission; according to the event-driven mechanism, the completion events are orchestrated under the premise of satisfying the pre-order constraints of the scheduling object, and a total completion time estimate is generated while supporting the integration of multiple scheduling strategies.

[0072] like Figure 2 As shown, the core idea of ​​MP-DCA is to decompose the time-varying behavior of each BDT into a set of time-invariant meta-processes. Given that the execution time of each task is assumed to be constant, it can be abstracted into a single meta-process. Each meta-process is mapped to a timeout event (TOE) carrying a specific timestamp. Furthermore, a completion event (CE) is introduced to indicate that all TOEs belonging to the same scheduling object have been completed, thus marking the end of the task or the BDT. By orchestrating these events while satisfying the pre-order constraints of the scheduling object, MP-DCA can simulate the execution process of workflow tasks, characterize dynamic communication contention, and provide an accurate total completion time estimate while supporting the integration of multiple scheduling strategies.

[0073] In MP-DCA, the Static Input Generator (SIG) is used to initialize the simulation and manage various types of inputs. The SIG receives three types of artifacts as inputs: the directed workflow graph G, the CFBCS configuration, and so on. And optional scheduling solutions. The input scheduling solution must contain the scheduling scheme for each scheduling object in the directed workflow graph G, consisting of three parts: task scheduling sequence, task-PU mapping sequence, and BDT-bus allocation sequence. Users can generate these themselves based on the directed workflow graph G. During simulation, the SIG dynamically updates the preorder constraints of each scheduling object in the directed workflow graph G based on CE information to track the state of these scheduling objects. Whenever a CE is triggered, the SIG updates the preorder constraints of the corresponding object; when all its dependencies are satisfied, the object enters the scheduling phase and is handed over to the runtime scheduler (RS), thereby reproducing the runtime scheduling decision. If the input contains a scheduling solution, the SIG forwards the scheduling decision of that object to the RS.

[0074] When a scheduled object enters the scheduling phase, the RS queries the status of all resources maintained by the Resource Manager (RM) and makes a scheduling decision based on built-in policies or user-specified policies. It should be noted that the RS can be skipped by predetermined scheduling decisions forwarded by the SIG, thus allowing specific scheduling solutions to be injected into the simulation.

[0075] Provided CFHCS configuration The RM is used to instantiate the underlying hardware, abstracting the TOE and CE at runtime. Through modular separation, MP-DCA supports various types of computing systems. The RM generates the TOE and registers the corresponding CE, and it includes two configurable submodules: the PU Manager and the Bus Manager. These submodules are all configured by CFHCS from the SIG. Initialization is performed. The PU manager maintains tasks by queuing them into the PU queue to which they are scheduled; within each simulation cycle, it dequeues at most one task from each PU (if any tasks are available) and transfers the TOE (Time of Execution) carrying the task's execution time timestamp and its corresponding CE to the simulation core. The bus manager maintains the set of active BDTs on each bus and generates TOEs at runtime to achieve dynamic bandwidth scaling. Specifically, in each simulation cycle: when a new BDT arrives, the bus manager generates its CE, adds the BDT to the active set of its assigned bus, and transfers it to the simulation core; subsequently, based on the cycle interval and the effective bandwidth B obtained in the previous cycle, the simulation core is initialized. eff Update the remaining data amount for each activity BDT; if the remaining data amount of a BDT drops to zero, remove it from the set; then, recalculate the B of the remaining BDTs for the next period. eff The system identifies the earliest completed BDT, generates the corresponding TOE with that completion time as the timestamp, and transfers it to the simulation core.

[0076] Step 3: The two-stage optimization algorithm based on MP-DCA outputs a scheduling scheme that satisfies the constraints and has the shortest completion time. In the first stage, a hybrid earliest completion time genetic algorithm is used, along with an improved fitness evaluation method, to generate and evaluate the scheduling solution, obtaining an approximate optimal scheduling solution. In the second stage, a quota-weighted ant colony algorithm is used, along with the aforementioned MP-DCA, to evaluate the solution's fitness and optimize the approximate optimal scheduling solution, obtaining the final scheduling solution.

[0077] A scheduling solution consists of three parts: a task scheduling sequence (TSS), a task mapping sequence (TMS), and a BDT-bus assignment sequence (BAS).

[0078] S31, such as Figure 3 As shown, the first stage employs a hybrid earliest completion time genetic algorithm (CEGA) to evolve only the earliest completion time scheduler (TSS). For each TSS, a hybrid earliest completion time scheduler (C-EFT) generates a total completion time scheduler (TMS) and a basic completion time scheduler (BAS) in MP-DCA, thus obtaining a complete scheduling solution. The fitness is then determined by the reciprocal of the total completion time estimate obtained from MP-DCA simulation of this scheduling solution. The algorithm yields a set of approximately optimal scheduling solutions.

[0079] Specifically, the population initialization of CEGA in the first phase is as follows: First, each individual TSS is required to be a topologically valid sequence of the given workflow directed graph. To balance computation and communication factors, three metrics are calculated for each task: the first is the task level, i.e., the depth accumulated backward from the source node; the second is forward sorting, which is based on the predecessor link, combining the average execution time of the predecessor task and the static communication time connected to it (zero for tasks within the same domain, and estimated for cross-domain tasks by dividing the edge data volume by the requested bandwidth of that edge); the third is backward sorting, which is based on the successor link, combining the average execution time of this task and the static communication time between successors. The average execution time is determined as follows: if the task is in the CPU domain, the average execution time on all available CPUs is taken; if it is in the FPGA domain, the execution time of the task core it is bound to is taken. Subsequently, the task indexes are sorted in ascending order by task level, ascending order by forward sorting, and descending order by backward sorting; when there are ties within a certain level / metric, random sorting is performed to increase diversity without violating dependencies. Finally, based on the above sorting and random shuffling, a topologically valid initial TSS set of 50 is generated as a population for subsequent evolutionary search.

[0080] Evolution of TSS employs one or more types of crossover and mutation operators. The crossover operator reassembles prefix or suffix segments between two parent sequences and fills in missing tasks according to their relative order in the other parent, thereby generating two child sequences. The mutation operator adjusts the local order of the sequences by exchanging or inserting task positions without violating predecessor / successor constraints. The crossover and mutation methods are executed randomly.

[0081] The C-EFT scheduler is integrated into MP-DCA as a runtime RS, instantiating the task sequence TSS obtained from evolutionary search into a complete scheduling solution for simulation evaluation, realizing fitness evaluation and solution generation. Each time C-EFT is invoked, it receives a batch of objects to be scheduled (tasks and BDTs) and makes incremental scheduling decisions based on the current system state; the incremental results from multiple invocations are finally aggregated into a complete SS for MP-DCA to evaluate workflow completion time. After receiving a batch of objects to be scheduled, the C-EFT scheduler first sorts them into two categories: tasks and BDTs. Then, tasks are inserted into the global ready queue Q in the order indicated by the current TSS; BDTs enter the candidate pool in their corresponding direction, waiting for bus allocation. For each task in the ready queue Q, the PU manager is queried to obtain the set of idle processing units P within the attribute domain of that task. idle If P idle If not empty, then for each candidate PUp m Calculate the execution time of this task. Choose to The smallest processing unit completes the mapping and determines the corresponding start / end time; if P idle If empty, its current position in Q is maintained until the next round of calls. In some embodiments, when there are candidates with equal optimality, a parallel resolution strategy of "earliest available time first" or "lowest load first" can be adopted. For any direction d, BDTδ i RS queries the direction concurrency count maintained by the bus manager to construct a candidate bus set. For each candidate bus b k Perform the following steps:

[0082] 1. δ i The activity set in this bus direction is added as a "provisional activity transfer";

[0083] 2. While keeping the current activity set unchanged, proceed iteratively at the time slice level based on the aforementioned dynamic competition model:

[0084] At each time slice, the effective bandwidth of each activity's BDT is calculated based on the activity set;

[0085] The remaining data amount of each BDT is deducted from the bandwidth to identify the first completed BDT, and then the local clock is advanced to that completion time.

[0086] Repeat the above process until all BDTs are completed, and record their BFTs on the candidate bus.

[0087] After enumerating all candidate buses in the CB, the bus with the smallest BFT is selected as the final assignment, and the "assigned count" for that bus direction is incremented by one.

[0088] The CEGA process in one iteration is as follows:

[0089] Step 1: Randomly select two parent sequences from the previous generation population using a tournament selection strategy, and apply the crossover and mutation operators. Repeat until a new generation population is generated.

[0090] Step 2: For each individual in the next generation, invoke the C-EFT scheduler in MP-DCA to instantiate a complete scheduling solution. Simulate the scheduling solution using MP-DCA to obtain the total completion time estimate, and use its reciprocal as the fitness value for the sequence.

[0091] Step 3: Merge the previous generation population with the new generation population and sort them in descending order of fitness. When there are ties, strategies such as "historical best, solution diversity, and earliest discovery time" can be used to resolve the ties.

[0092] Step 4: Repeat steps S1–S4 until the preset maximum number of iterations (50) is reached or the convergence criterion is met (e.g., the optimal fitness has not improved for several consecutive generations). At termination, output a set of near-optimal complete scheduling solutions.

[0093] S32. In the second stage of the algorithm, the Quota-Weighted Ant Colony Algorithm (QWACO) is used to optimize the BAS in each scheduling solution obtained in the first stage. In QWACO, a BAS is regarded as an ant; its fitness is defined as the reciprocal of the total completion time estimate obtained by MP-DCA simulation after combining the BAS with the corresponding TSS and TMS to form a complete scheduling solution. The core of QWACO includes three parts: ant colony initialization, pheromone representation (elite profile), and quota-weighted ant construction. To ensure the feasibility of BAS, the algorithm uses the BDT capacity constraint as a hard constraint, maintains the remaining quota of "direction-bus" in real time during the sampling process, and only performs weighted sampling on candidates with a quota greater than zero, thereby ensuring that the generated BAS naturally meets the capacity limit.

[0094] The second phase first constructs an initial ant colony of size 25: the BAS from the complete scheduling solution obtained in the first phase is directly incorporated into the ant colony as a "seed" individual, and the remaining 24 ants are generated in two ways:

[0095] (1) Seed-based multi-point mutation: Randomly select several positions in the seed sequence, assign the corresponding BDT to other buses in the same direction that have not yet reached their capacity limit, and synchronously update the counter maintained in the "direction-bus" dimension; repeat this process until a new feasible BAS is formed. This method will be repeated many times until 12 ants are generated.

[0096] (2) Balanced random sampling: Initialize the "direction-bus" counter to zero, process the BDTs of the buses to be allocated one by one, and select the candidate buses with the smallest current count first and draw them with medium probability, under the premise of meeting the capacity limit, so as to maintain balance among the buses and directions as much as possible, until a feasible BAS is generated. This method will be repeated many times until 12 ants are generated.

[0097] Instead of using a traditional matrix, pheromones are represented by a fixed-size elite archive. This archive continuously stores five best-fit BAS (Body Assemblies) and replaces them with newly generated superior individuals after each iteration, ensuring the archive size remains constant while maintaining overall quality superior to the current ant colony. Individuals within the archive are sorted from best to worst fitness and assigned decreasing influence weights based on their ranking, allowing higher-ranked individuals to play a stronger guiding role in subsequent sampling. These weighting rules can be implemented using a monotonically decreasing function, which is not limited in this invention.

[0098] The new ant colony is constructed based on the elite archive, involving two steps: First, a weight set is formed to guide sampling. This set comprehensively considers "the frequency of a position being assigned to a bus in the archive and its corresponding weight" and "the reward given to non-occurring values ​​to improve diversity," aiming to balance "using excellent patterns" and "exploring new combinations." Second, quota-weighted sampling is performed to embed capacity constraints: a set of "remaining quotas" is maintained for each direction. When selecting a bus for each position in the sequence, sampling is only performed on candidates with remaining quotas, normalized according to the aforementioned weights. After each assignment, the corresponding quota is deducted immediately. This process is executed sequentially for all positions to obtain a new feasible sequence. This is repeated to generate the next generation of ant colonies according to the target size, and is carried out in a loop with simulation evaluation and elite archive updates until the maximum number of iterations (50) is reached or the convergence condition is met (e.g., the optimal fitness has not improved for several consecutive generations). The optimal scheduling solution is output upon termination.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dynamic competition-aware workflow scheduling method for heterogeneous computing systems, characterized in that, Includes the following steps: S1. Based on the set of scheduling objects and bus resources of the system, construct a scheduling problem model; S2. Construct a dynamic contention-aware simulator based on the aforementioned scheduling problem model, including: The time-varying behavior of cross-domain bus data transmission is decomposed into time-invariant meta-processes; each meta-process is mapped to a timeout event carrying a specific timestamp; the completion event indicates that all timeout events belonging to the same scheduling object have been completed, thereby marking the end of the task or cross-domain bus data transmission; according to the event-driven mechanism, the completion events are orchestrated under the premise of satisfying the pre-order constraints of the scheduling object, and a total completion time estimate is generated while supporting the integration of multiple scheduling strategies. S3. Based on the estimated total completion time, a near-optimal scheduling solution is generated using a hybrid earliest completion time genetic algorithm; the near-optimal scheduling solution is optimized using a quota-weighted ant colony algorithm to generate the final scheduling solution.

2. The method for dynamic competition-aware workflow scheduling in a heterogeneous computing system according to claim 1, characterized in that, S1 includes: S1.1 Construct a directed workflow graph; Extract the set of scheduling objects containing task and bus data transmission from the directed workflow graph; S1.

2. Abstract the bus resources of the system and construct a dynamic bus communication contention model based on the bus communication bandwidth scaling caused by the budget arbitration mechanism. S1.

3. Based on the dependencies in the directed workflow graph and the dynamic bus communication contention model, and combined with system resource constraints, construct a scheduling problem model.

3. The method for dynamic contention-aware workflow scheduling in a heterogeneous computing system according to claim 2, characterized in that, S1.2 includes: Define the set of processing units P = P in the CPU domain and FPGA domain. CPU ∪P FPGA ={p1,p2,…,p n A set of full-duplex shared buses for cross-domain data communication, B = {b1, b2, ..., b} n }; For shared bus b k And the direction d∈[CPU→FPGA,FPGA→CPU}, defined as: maximum bandwidth of the direction. With the maximum number of allocatable BDTs At time τ, define the set of activities in the same direction (BDT). Its total requested bandwidth For all in the activity set Activities Requested bandwidth sum:

4. The method for dynamic contention-aware workflow scheduling in a heterogeneous computing system according to claim 3, characterized in that, The budget-based arbitration mechanism includes: when the sum of the requested bandwidth of active BDTs on the same bus and in the same direction does not exceed the maximum bandwidth in that direction, service is provided according to their requested bandwidth; when the requested bandwidth exceeds the maximum bandwidth in that direction, the available effective bandwidth is scaled proportionally for all active BDTs based on their requested bandwidth percentage; the bandwidth scaling factor α(τ) at time τ is defined as: At time τ, each activity Actual effective bandwidth for:

5. A dynamic contention-aware workflow scheduling method for heterogeneous computing systems according to claim 2, characterized in that, In S1.3, the objective function of the scheduling problem model is to minimize the completion time of the workflow task; the completion time of the workflow task is calculated by integrating the actual effective bandwidth of the activity BDT; from the start time of the BDT, when the integral covers its data volume threshold, it is considered complete.

6. The method for dynamic contention-aware workflow scheduling in a heterogeneous computing system according to claim 1, characterized in that, The dynamic competition-aware simulator includes: The simulation core is used to generate and manage completion events; A static input generator is used to initialize the simulation and receive inputs including the directed graph of the workflow, system resource configuration, and candidate scheduling solutions. The static input generator dynamically updates the preorder constraints of each scheduling object in the directed graph of the workflow based on completion events. When all dependencies are satisfied, the scheduling object enters the scheduling phase and is handed over to the runtime scheduler. The runtime scheduler is used to make scheduling decisions for scheduling objects entering the scheduling phase based on built-in strategies or user-specified strategies. The resource manager is used to abstract the underlying hardware based on system resource configuration and generate the timeout and completion events at runtime.

7. A dynamic contention-aware workflow scheduling method for heterogeneous computing systems according to claim 6, characterized in that, The resource manager includes the PU manager and the bus manager, both of which are initialized by system resource configuration; The PU manager maintains tasks by queuing them into the PU queue. In each simulation cycle, the PU manager dequeues at most one task from each PU and transfers the timeout event carrying the execution time timestamp of the task and its corresponding completion event to the simulation core. The bus manager maintains a set of active cross-domain bus data transfers on each bus and generates timeout events at runtime to enable dynamic scaling of bandwidth. In each simulation cycle, when a new cross-domain bus data transfer arrives, the bus manager generates a completion event, adds the cross-domain bus data transfer to the active set of its assigned bus, and hands it over to the simulation core. Based on the cycle interval and the effective bandwidth obtained in the previous cycle, the remaining data volume of each active cross-domain bus data transfer is updated. If the remaining data volume of a cross-domain bus data transfer drops to zero, it is removed from the set. Then, for the next cycle, the effective bandwidth of the remaining cross-domain bus data transfers is recalculated, the earliest completed cross-domain bus data transfer is identified, and a corresponding timeout event with the completion time as the timestamp is generated and handed over to the simulation core.

8. The method for dynamic contention-aware workflow scheduling in a heterogeneous computing system according to claim 1, characterized in that, The candidate scheduling solutions include a task scheduling sequence, a task-PU mapping sequence, and a BDT-bus allocation sequence; S3 includes: S31. The dynamic contention-aware simulator generates a task-PU mapping sequence and a BDT-bus allocation sequence based on the task scheduling sequence using a hybrid earliest completion time scheduler; it optimizes the task scheduling sequence using a hybrid earliest completion time genetic algorithm; and it generates the approximate optimal scheduling solution by using the reciprocal of the total completion time estimate obtained by the simulation of the candidate scheduling solution by the dynamic contention-aware simulator as the fitness. S32. The quota-weighted ant colony algorithm is used to optimize the BDT-bus allocation sequence in the near-optimal scheduling solution; the optimized BDT-bus allocation sequence is combined with its corresponding task scheduling sequence and task-PU mapping sequence to form a complete scheduling solution. The reciprocal of the total completion time estimate obtained by the dynamic competition-aware simulator is used as the fitness to generate the final scheduling solution.

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