Ultrasonic fingerprint pixel circuit and construction method thereof

Abstract

The invention provides an ultrasonic fingerprint pixel circuit and a construction method of the ultrasonic fingerprint pixel circuit. The method comprises the following steps: firstly, determining an auxiliary metal layer from a plurality of metal layers of a circuit layer, and connecting the auxiliary metal layer with a connecting metal layer of a lower pole plate serving as a sensing layer; a middle metal layer wrapped by the connecting metal layer and the auxiliary metal layer is determined from the metal layers between the auxiliary metal layer and the connecting metal layer, and the middle metal layer is connected with the input end of the operational amplifier; therefore, an auxiliary capacitor inserted between the sensing layer and the operational amplifier can be formed by the middle metal layer and the connecting metal layer and the auxiliary metal layer which are connected with the middle metal layer, interference and influence of parasitic capacitance at the input end of the operational amplifier can be effectively reduced, and fingerprint data with high quality and small errors can be obtained.

Description

Technical Field

[0001] This manual pertains to the field of fingerprint chip technology, and particularly relates to ultrasonic fingerprint pixel circuits and methods for constructing ultrasonic fingerprint pixel circuits. Background Technology

[0002] With the development and promotion of ultrasonic fingerprint recognition technology, more and more fingerprint products are adopting ultrasonic fingerprint-based chip circuits for fingerprint acquisition. However, in existing ultrasonic fingerprint chip circuits, the lower electrode of the piezoelectric transducer structure of the ultrasonic fingerprint pixel forms a large parasitic capacitance relative to the circuit below. This parasitic capacitance often causes significant interference and influence on the operational amplifier in the fingerprint chip circuit, and may even drown out the valid fingerprint information in the echo signal, resulting in the inability to obtain a clear and accurate fingerprint image.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This specification provides an ultrasonic fingerprint pixel circuit and a method for constructing such a circuit, which can effectively reduce the interference and influence of parasitic capacitance at the input of the operational amplifier, and obtain fingerprint data with high quality and small error.

[0005] This specification provides an ultrasonic fingerprint pixel circuit, comprising at least: a sensing layer and a circuit layer; wherein, the circuit layer includes multiple metal layers, the number of which is greater than or equal to 3; the circuit layer also includes an operational amplifier;

[0006] The sensing layer is electrically connected to the connecting metal layer in the circuit layer; wherein, the connecting metal layer is the metal layer disposed on the top layer of the circuit layer among the plurality of metal layers; the sensing layer is used to receive echo signals about the fingerprint of the target object;

[0007] The connecting metal layer is connected to an auxiliary metal layer among the plurality of metal layers; wherein at least one of the plurality of metal layers exists between the connecting metal layer and the auxiliary metal layer;

[0008] The input terminal of the operational amplifier is connected to an intermediate metal layer; wherein, the intermediate metal layer is a metal layer located between the connecting metal layer and the auxiliary metal layer among a plurality of metal layers; an auxiliary capacitor is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

[0009] In one embodiment, the connecting metal layer and the auxiliary metal layer are connected by a via structure.

[0010] In one embodiment, the sensing layer includes a piezoelectric transducer layer.

[0011] In one embodiment, the intermediate metal layer is also connected to a connecting metal layer among the plurality of metal layers; the intermediate metal layer is connected to the input terminal of the operational amplifier through the connecting metal layer.

[0012] In one embodiment, the area of ​​the auxiliary capacitor is greater than a preset area threshold; wherein the preset area threshold is determined based on the attenuation constraint parameter of the fingerprint signal.

[0013] In one embodiment, the plurality of metal layers, ordered from largest to smallest distance from the circuit layer substrate, include: a fourth metal layer, a third metal layer, a second metal layer, and a first metal layer.

[0014] In one embodiment, the connecting metal layer is a fourth metal layer.

[0015] In one embodiment, the auxiliary metal layer is a first metal layer and / or a second metal layer.

[0016] In one embodiment, when the auxiliary metal layer is a first metal layer, the intermediate metal layer is a third metal layer, and the connecting metal layer is a second metal layer.

[0017] In one embodiment, when the auxiliary metal layer is a second metal layer, the intermediate metal layer is a third metal layer, and the connecting metal layer is a first metal layer.

[0018] This specification also provides a method for constructing an ultrasonic fingerprint pixel circuit, including:

[0019] The top metal layer of the circuit layer is designated as the connection metal layer; and this connection metal layer is electrically connected to the sensing layer; wherein, the circuit layer contains multiple metal layers, and the number of the multiple metal layers is greater than or equal to 3; the circuit layer is also provided with an operational amplifier;

[0020] An auxiliary metal layer is determined from a plurality of metal layers; and the auxiliary metal layer is connected to the connecting metal layer; wherein at least one of the plurality of metal layers exists between the connecting metal layer and the auxiliary metal layer;

[0021] The input terminal of the operational amplifier is connected to an intermediate metal layer; wherein, the intermediate metal layer is a metal layer located between the connecting metal layer and the auxiliary metal layer among a plurality of metal layers; an auxiliary capacitor is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

[0022] In one embodiment, when the number of the plurality of metal layers is greater than 3, connecting the input terminal of the operational amplifier to the intermediate metal layer includes:

[0023] The connecting metal layer is determined from the remaining metal layers among the plurality of metal layers;

[0024] The connecting metal layer is electrically connected to the input terminal of the operational amplifier; and the connecting metal layer is connected to the intermediate metal layer.

[0025] This specification also provides an ultrasonic fingerprint chip, which includes at least the ultrasonic fingerprint pixel circuit described above.

[0026] This specification also provides an electronic device, which includes at least the ultrasonic fingerprint chip.

[0027] Based on the ultrasonic fingerprint pixel circuit and its construction method provided in this specification, the ultrasonic fingerprint pixel circuit includes at least: a sensing layer and a circuit layer; wherein the circuit layer comprises multiple metal layers, and the number of the multiple metal layers is greater than or equal to 3; the circuit layer also includes an operational amplifier; the sensing layer is electrically connected to a connecting metal layer in the circuit layer; wherein the connecting metal layer is the metal layer disposed on the top layer of the multiple metal layers; the sensing layer is used to receive echo signals about the fingerprint of a target object; the connecting metal layer is connected to an auxiliary metal layer among the multiple metal layers; wherein at least one of the multiple metal layers exists between the connecting metal layer and the auxiliary metal layer; the input terminal of the operational amplifier is connected to an intermediate metal layer; wherein the intermediate metal layer is the metal layer located between the connecting metal layer and the auxiliary metal layer among the multiple metal layers; an auxiliary capacitor for insertion between the sensing layer and the operational amplifier is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer. First, an auxiliary metal layer is identified from among the multiple metal layers of the circuit layer, and this auxiliary metal layer is connected to the connecting metal layer, which serves as the lower electrode of the sensing layer. Then, an intermediate metal layer, in which most or even all of the area is wrapped by the connecting metal layer and the auxiliary metal layer, is identified from the metal layers between the auxiliary metal layer and the connecting metal layer, and this intermediate metal layer is connected to the input terminal of the operational amplifier. This intermediate metal layer, along with the connected connecting metal layer and the auxiliary metal layer, forms an auxiliary capacitor for insertion between the sensing layer and the operational amplifier. This transforms the parasitic capacitance at the input terminal of the operational amplifier from the parasitic capacitance formed by the lower electrode of the sensing layer relative to the lower circuitry into a parasitic capacitance formed by the lower electrode of the auxiliary capacitor relative to the lower circuitry. This effectively reduces the interference and influence of parasitic capacitance at the input terminal of the operational amplifier, resulting in the acquisition of high-quality fingerprint data with minimal error. Attached Figure Description

[0028] To more clearly illustrate the embodiments of this specification, the accompanying drawings used in the embodiments will be briefly introduced below. The drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of an existing ultrasonic fingerprint pixel circuit;

[0030] Figure 2 This is a schematic diagram of the equivalent circuit of an existing ultrasonic fingerprint pixel circuit;

[0031] Figure 3 This is a signal timing diagram of acquiring fingerprint data using an ultrasonic fingerprint pixel circuit in a scenario example;

[0032] Figure 4 This is a schematic diagram of the structural composition of an ultrasonic fingerprint pixel circuit provided in one embodiment of this specification;

[0033] Figure 5 This is an equivalent circuit diagram of an ultrasonic fingerprint pixel circuit provided in one embodiment of this specification;

[0034] Figure 6 This is a schematic diagram of one embodiment of the ultrasonic fingerprint pixel circuit provided in the embodiments of this specification, applied in a scenario example.

[0035] Figure 7 This is a schematic diagram of one embodiment of the ultrasonic fingerprint pixel circuit provided in the embodiments of this specification, applied in a scenario example.

[0036] Figure 8 This is a schematic diagram of one embodiment of the ultrasonic fingerprint pixel circuit provided in the embodiments of this specification, applied in a scenario example.

[0037] Figure 9 This is a schematic diagram of one embodiment of the ultrasonic fingerprint pixel circuit provided in the embodiments of this specification, applied in a scenario example.

[0038] Figure 10 This is a schematic flowchart illustrating a method for constructing an ultrasonic fingerprint pixel circuit according to an embodiment of this specification.

[0039] Figure 11 This is a schematic diagram of the structural composition of an electronic device provided in one embodiment of this specification;

[0040] Figure 12 This is a schematic diagram of the structural composition of an ultrasonic fingerprint pixel circuit construction device provided in one embodiment of this specification. Detailed Implementation

[0041] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0042] It should be noted that the information and data related to users involved in the embodiments of this specification are all information and data authorized by the user or fully authorized by the relevant parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of the relevant data all comply with relevant laws, regulations, and standards, and necessary confidentiality measures have been taken. They do not violate public order and good morals, and corresponding operation entry points are provided for users or relevant parties to choose to authorize or refuse.

[0043] It should also be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0044] Considering the ultrasonic fingerprint pixel circuit based on the existing structure, see [reference] Figure 1 As shown, when a user presses their finger against the fingerprint acquisition module, such as pressing it on the upper plate of the piezoelectric transducer layer (e.g., a piezoelectric thin-film sensor, PVDF sensor, which can be abbreviated as PVDF, or piezoelectric transducer structure), an ultrasonic signal is automatically emitted to the user's finger. The reflected echo signal (e.g., VIN) is received by the piezoelectric transducer layer. This echo signal carries fingerprint information such as ridges and valleys in the fingerprint. The operational amplifier (e.g., PXL_OP) then processes the echo signal through sampling and integration to obtain the corresponding output (Vout), which serves as the required fingerprint data (e.g., fingerprint image).

[0045] For specific implementation, please refer to Figure 1 and Figure 2As shown, in existing ultrasonic fingerprint pixel circuits, the lower plate of the piezoelectric transducer layer is usually directly connected to the input of the operational amplifier. Since the lower plate of the piezoelectric transducer layer forms distributed parasitic capacitance with the metal traces of the multiple metal layers below, a large parasitic capacitance (e.g., cpar) is formed at the input of the operational amplifier. This capacitance value is usually on the order of 100fF, which will interfere with and affect the processing of the echo signal, causing offset, or even drowning out the fingerprint information in the echo signal. This results in poor consistency and low accuracy of the final output fingerprint data, and mismatch problems are likely to occur.

[0046] Specifically, for existing ultrasonic fingerprint pixel circuit structures, please refer to... Figure 2 and Figure 3 As shown, during the specific operation of acquiring fingerprint data, assuming the offset of the bias voltage vcm is vos1 and the offset of the operating voltage vrst is vos2, during the reset phase, when sampling the pixel output using the first signal cds_sp1, the corresponding output voltage can be obtained as vcm + vos1. And when the echo signal arrives, refer to... Figure 2 As shown, the second switch sw2 is periodically turned on to integrate the echo signal. However, when the second switch sw2 is closed, the third switch sw3 needs to be turned on to reset the net_rst node to the rst voltage. Without this reset operation, net_rst would be pulled off balance by the echo signal coupling. When the second switch sw2 is closed again, this pulled-off voltage would cause abnormal output. Therefore, after the third switch sw3 is closed, the voltage of the net_rst node will be reset to vrst + vos2. After multiple integrations, the signal sampled using the second signal cds_sp2 is: vcm + vos1 + vs + N*(vos2 - vos1)*cpar / cfb, where N is the number of integrations, vs is the pure ultrasonic electrical signal obtained by N integrations, cfb is the feedback capacitor, cpar is the parasitic capacitance of the lower plate of the piezoelectric transducer layer (PVDF) to the circuit below it, sw3 is the third switch, and net_rst is the reset node. Since the capacitance value of cpar is a large capacitor on the order of 100fF, the final sampled input signal of the operational amplifier is: vs + N*(vos2-vos1)*cpar / cfb. Here, N*(vos2-vos1)*cpar / cfb can be represented as the interference factor caused by parasitic capacitance.

[0047] To address the aforementioned problems in existing ultrasonic fingerprint pixel circuits, and considering the root causes of these problems, this specification proposes selecting a suitable metal layer from the circuit layer as an auxiliary metal layer, and electrically connecting this auxiliary metal layer to the lower electrode of the sensing layer (e.g., a piezoelectric transducer structure). Specifically, at least one intermediate metal layer, enclosed by the lower electrode of the sensing layer and the auxiliary metal layer, is required to exist within the longitudinal space between the auxiliary metal layer and the lower electrode of the sensing layer. This intermediate metal layer is then connected directly or indirectly to the input terminal of an operational amplifier. This intermediate metal layer and the auxiliary metal layer can then form an auxiliary capacitor (e.g., denoted as CCO) for insertion between the sensing layer and the operational amplifier. For details, please refer to [reference needed]. Figure 4 and Figure 5 The content shown is as follows. Due to the presence of the auxiliary capacitor CCO, the actual parasitic capacitance at the operational amplifier input changes from the parasitic capacitance cpar of the lower electrode of the sensing layer to the circuit below it, to the parasitic capacitance cpar1 of the lower electrode of the auxiliary capacitor to the circuit below it. The parasitic capacitance cpar1 can be adjusted by modifying the design (e.g., layout optimization) of the lower electrode of the auxiliary capacitor so that the value of cpar1 is much smaller than cpar; for example, cpar1 can be adjusted to only 3fF. This makes the actual parasitic capacitance at the operational amplifier input relatively small, and consequently, the interference factor N*(vos2-vos1)*cpar / cfb caused by the parasitic capacitance is also relatively small. This effectively reduces the interference and influence of the parasitic capacitance at the operational amplifier input, resulting in high-quality fingerprint data with smaller errors.

[0048] Based on the above ideas, see Figure 4 As shown in the figure, this specification provides an ultrasonic fingerprint pixel circuit, which may include at least: a sensing layer, a circuit layer, etc.; wherein, the circuit layer includes multiple metal layers, and the number of the multiple metal layers is greater than or equal to 3; the circuit layer is also provided with an operational amplifier;

[0049] The sensing layer is electrically connected to the connecting metal layer in the circuit layer; wherein, the connecting metal layer is the metal layer disposed on the top layer of the circuit layer (e.g., the top metal layer); the sensing layer is used to receive echo signals about the fingerprint of the target object;

[0050] The connecting metal layer is connected to an auxiliary metal layer among the plurality of metal layers; wherein at least one of the plurality of metal layers exists between the connecting metal layer and the auxiliary metal layer;

[0051] The input terminal of the operational amplifier is connected to the intermediate metal layer; wherein, the intermediate metal layer is a metal layer located between the connecting metal layer and the auxiliary metal layer among a plurality of metal layers; an auxiliary capacitor is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

[0052] Specifically, the aforementioned ultrasonic fingerprint pixel circuit can be applied to a fingerprint acquisition module. This fingerprint acquisition module can be used to acquire fingerprint data of a user's target object. This target object can specifically be the user's finger. In some cases, the target object can also be the user's palm, toes, etc.; correspondingly, the fingerprint acquisition module can also be used to acquire palmprint data of the user's palm, fingerprint data of the toes, etc.

[0053] The fingerprint acquisition module described above can be applied to various electronic devices such as electronic door locks, mobile phone fingerprint locks, and safe fingerprint locks. It should be noted that the various electronic devices listed above are only illustrative. In actual implementation, depending on the specific circumstances and processing requirements, the fingerprint acquisition module can also be applied to other types of electronic devices. This specification does not limit its application in this regard.

[0054] Specifically, the aforementioned fingerprint acquisition module can be a fingerprint acquisition module based on ultrasonic fingerprint recognition. The aforementioned ultrasonic fingerprint pixel circuit can correspond to at least one pixel unit in the fingerprint acquisition module.

[0055] Specifically, the fingerprint acquisition module described above can be equipped with an active area (AA). Multiple fingerprint pixel units can be arranged within this active area. For example, see [reference needed]. Figure 6 As shown, the aforementioned recognition area may contain a fingerprint pixel unit array consisting of N*M fingerprint pixel units. Each fingerprint pixel unit may be connected to a corresponding ultrasonic fingerprint pixel circuit. Each pixel unit can be understood as corresponding to a fingerprint pixel size.

[0056] In practice, when a user presses a target object (e.g., a finger) onto the aforementioned recognition area, different fingerprint regions of the target object correspond to different fingerprint pixel units. Based on these different fingerprint pixel units, echo signals (e.g., VIN) corresponding to different fingerprint regions can be received by emitting ultrasonic signals. Because of differences in valleys and ridges in different fingerprint regions, the sound wave transmission and reflection processes also differ, resulting in corresponding differences in the received echo signals. Accordingly, multiple echo signals corresponding to multiple different fingerprint regions can be received through the aforementioned multiple fingerprint pixel units; these multiple echo signals can then be processed using structures such as operational amplifiers to obtain multiple fingerprint signals corresponding to multiple different fingerprint regions; based on these multiple fingerprint signals, fingerprint data (e.g., a fingerprint image) for the user's target object can be acquired. The fingerprint signal obtained based on a single fingerprint pixel unit can be understood as a fingerprint pixel corresponding to one fingerprint region.

[0057] The following explanation will focus on the circuit of any one of the multiple fingerprint pixel units.

[0058] For details, please refer to Figure 4 As shown, the ultrasonic fingerprint pixel circuit described above may include at least the following structures: a sensing layer, a circuit layer, etc.

[0059] Specifically, the aforementioned sensing layer may include a piezoelectric transducer structure (or piezoelectric transducer layer). This piezoelectric transducer structure may include a piezoelectric transducer layer with a piezoelectric material and upper and lower electrodes. Specifically, the piezoelectric transducer structure may include a sensor based on a PVDF piezoelectric thin film, or a sensor based on AlN, PZT, etc. The aforementioned piezoelectric thin film sensor (PVDF sensor, abbreviated as pvdf) can be understood as a sensing layer capable of converting received echo signals into corresponding electrical signals using the piezoelectric effect.

[0060] The aforementioned sensing layer can be integrated onto the circuit layer. Specifically, an operational amplifier can also be integrated onto the aforementioned circuit layer.

[0061] The aforementioned circuit layer (IC) may include multiple metal layers. Depending on the manufacturing process, the circuit layer may contain varying numbers of metal layers. The number of these multiple metal layers is greater than or equal to three. This ensures that at least one connection metal layer, one auxiliary metal layer, and one intermediate metal layer enclosed by the connection metal layer and the auxiliary metal layer can be identified based on the circuit layer.

[0062] Specifically, for example, in a circuit layer based on 1p4m technology, there can be four different metal layers, ordered from smallest to largest distance from the substrate: M1, M2, M3, M4, etc. See reference [link to relevant documentation]. Figure 1 As shown.

[0063] The 1p4m process can be understood as a chip manufacturing process. Specifically, 1p indicates the use of a single layer of polysilicon in the chip manufacturing process. This polysilicon layer is mainly used to form the gate of the transistor and is an important component of the transistor. 4m indicates the use of four metal layers in the chip design. These metal layers are mainly used to realize the interconnection within the chip, connecting different transistors to form complex circuits.

[0064] Of course, it should be noted that the 1p4m process listed above is only an illustrative example. In specific implementations, depending on the specific circumstances and processing requirements, the solutions provided in this application can also be extended to circuit layers manufactured using processes other than 1p4m. This specification does not limit this application.

[0065] Specifically, the metal layer that is furthest from the substrate (e.g., P-type substrate, psub) among the multiple metal layers of the circuit layer (e.g., M4 in a circuit layer based on 1p4m process), i.e. the outermost metal layer of the circuit layer, can be used as the lower electrode plate connecting the metal layer and the sensing layer for electrical connection, or directly as the lower electrode plate of the sensing layer.

[0066] Simultaneously, based on the location information of the connecting metal layer and the distribution information of multiple metal layers in the circuit layer, among the remaining metal layers in the circuit layer excluding the connecting metal layer, a metal layer that ensures at least one more metal layer exists in the vertical space between it and the connecting metal layer is identified as an auxiliary metal layer. This auxiliary metal layer is then electrically connected to the connecting metal to jointly serve as the lower electrode of the sensing layer. Determining the auxiliary metal layer in this way ensures that at least one metal layer enclosed by both the connecting metal layer and the auxiliary metal layer can be found as an intermediate metal layer in the subsequent vertical space between the auxiliary metal layer and the connecting metal.

[0067] Accordingly, at least one metal layer can be identified from the metal layers connecting the connecting metal layer and the auxiliary metal layer as an intermediate metal layer; and this intermediate metal layer can be connected to the input terminal (e.g., the negative input terminal) of the operational amplifier in a direct or indirect manner.

[0068] In this way, by utilizing the aforementioned intermediate metal layer and the connected connecting metal layer and auxiliary metal layer, a capacitor can be formed that can be inserted between the sensing layer and the operational amplifier, serving as an auxiliary capacitor cco. By inserting this auxiliary capacitor cco, the actual parasitic capacitance at the input terminal of the operational amplifier can be converted into the parasitic capacitance cpar1 of the lower plate of the auxiliary capacitor (or the connection point between the input terminal of the operational amplifier and the intermediate metal layer) to the circuit below. This transforms the originally large parasitic capacitance cpar at the input terminal of the operational amplifier into a smaller parasitic capacitance cpar1, thereby reducing the interference and impact caused by parasitic capacitance.

[0069] In practical implementation, both the area constraint parameters and attenuation constraint parameters of the circuit layer can be considered to construct an auxiliary capacitor with a suitable area and capacitance value. Generally, the larger the area of ​​an auxiliary capacitor, the larger its capacitance value, and the smaller the attenuation caused by the auxiliary capacitor. However, considering the specific scenario requirements, as well as the actual size and layout of the circuit layer, the area of ​​the auxiliary capacitor must not be too large. Therefore, in practical implementation, both attenuation constraint parameters (e.g., attenuation coefficient less than 2%) and area constraint parameters (e.g., the ratio of the capacitor area to the area of ​​the corresponding pixel unit less than 5%) can be combined to determine a preset area threshold for the auxiliary capacitor; then, based on this preset area threshold, an auxiliary capacitor with a corresponding area and capacitance value can be designed and constructed. This results in an auxiliary capacitor that can simultaneously consider multiple factors and achieve better performance. For example, preferably, the capacitance value of the aforementioned auxiliary capacitor can fall within the range of 1.5pF to 3pF.

[0070] Furthermore, when constructing auxiliary capacitors, the position and layout information of the metal layers in the circuit layer can be fully utilized. By using capacitor stack-up traces and connecting methods such as vias, the capacitance value of the auxiliary capacitor can be increased within a relatively limited area to obtain an auxiliary capacitor that meets the requirements.

[0071] The aforementioned operational amplifier (OP) can be understood as a multi-stage direct-coupled amplifier circuit unit with high gain characteristics. Its core structure includes a differential input stage, a voltage amplification intermediate stage, and a low-impedance output stage, achieving the two fundamental principles of virtual short (equal input potential) and virtual open (input current approaches zero) through deep negative feedback.

[0072] The aforementioned operational amplifier (e.g., it can be denoted as PXL_OP) may specifically include a differential amplifier. For details, see [link to relevant documentation]. Figure 4As shown, the input terminals of the aforementioned operational amplifier may include a positive input terminal and a negative input terminal. Specifically, the negative input terminal may be connected to the aforementioned auxiliary capacitor. The positive input terminal may be used to connect to a preset bias power supply. This preset bias power supply is used to provide the preset bias voltage (e.g., denoted as Vcm) required for acquiring the fingerprint signal.

[0073] For details, please refer to Figure 5 As shown in the equivalent circuit diagram, the negative input terminal of the operational amplifier is equivalent to having the actual parasitic capacitance cpar1 connected in series; simultaneously, an auxiliary capacitor cco is also connected in series through the second switch sw2. Furthermore, the first switch sw1 and the feedback capacitor cfb are connected in parallel between the negative input and output terminals of the operational amplifier.

[0074] In specific implementation, the aforementioned ultrasonic fingerprint pixel circuit, during operation, is based on Figure 5 The equivalent circuit is shown. The operational amplifier can acquire and process the echo signal received by the sensing layer to obtain and output the corresponding fingerprint data. By using the aforementioned intermediate metal layer, the connected metal layer, and the auxiliary metal layer to form an auxiliary capacitor for insertion between the sensing layer and the operational amplifier, the actual parasitic capacitance at the input of the operational amplifier is changed from the original large parasitic capacitance cpar of the lower electrode of the sensing layer to the circuit below it, to the smaller parasitic capacitance cpar1 of the lower electrode of the auxiliary capacitor to the circuit below it. In this way, during the processing of the echo signal, since the actual parasitic capacitance cpar1 is relatively very small, the interference and influence of the parasitic capacitance at the input of the operational amplifier can be effectively reduced, so that the fingerprint data directly processed by the operational amplifier has better consistency and higher quality, thereby effectively solving the fingerprint data mismatch problem caused by parasitic capacitance.

[0075] In some embodiments, the connecting metal layer and the auxiliary metal layer are connected by a via structure.

[0076] Specifically, the aforementioned vias can refer to vertical hole structures within a semiconductor chip that connect different metal layers to establish electrical connections between them.

[0077] Based on the above embodiments, by using a via structure to connect the auxiliary metal layer and the connecting metal layer, the stacked structure of multiple metal layers in the circuit layer can be fully utilized to connect the relatively far-away auxiliary metal layer and the connecting metal layer to form an auxiliary capacitor with a relatively large capacitance value, which helps to reduce the related structural size.

[0078] In some embodiments, the sensing layer may specifically include a piezoelectric transducer layer. Specifically, a piezoelectric layer or other structures capable of similar function may be used instead of the aforementioned sensing layer.

[0079] In some embodiments, the intermediate metal layer is further connected to a connecting metal layer among the plurality of metal layers; the intermediate metal layer is connected to the input terminal of the operational amplifier through the connecting metal layer.

[0080] For details, please refer to [link / reference]. Figure 7 As shown, the connecting layer (e.g., M1) can be directly connected to the input terminal of the operational amplifier. The intermediate layer (e.g., M3) can be connected to the connecting layer via a via or other structure; and then indirectly connected to the input terminal of the operational amplifier through the connecting layer. In this case, the parasitic capacitance of the input terminal of the operational amplifier can specifically be the parasitic capacitance formed by the connecting layer on the circuit below it.

[0081] Of course, in some cases, depending on specific needs, the aforementioned intermediate layer can also be directly connected to the input terminal of the operational amplifier. In this case, the parasitic capacitance of the operational amplifier's input terminal can be specifically determined by the parasitic capacitance of the connecting layer to the capacitor below it.

[0082] In some embodiments, the area of ​​the auxiliary capacitor may be larger than a preset area threshold; wherein the preset area threshold is determined based on the attenuation constraint parameter of the fingerprint signal.

[0083] In practical implementation, a preset area threshold can be determined based on the attenuation constraint parameters, serving as the lower limit of the auxiliary capacitor's area. Simultaneously, based on scenario requirements and the structural parameters of the circuit layer, a matching area constraint parameter can be determined. And based on this area constraint parameter, the upper limit of the auxiliary capacitor's area can be determined. Then, an auxiliary capacitor meeting the requirements can be designed and constructed using the connected connecting metal layer and the auxiliary metal layer; wherein the area of ​​the compliant auxiliary capacitor is greater than the lower limit and less than the upper limit.

[0084] Based on the above embodiments, a compatible and compliant auxiliary capacitor can be accurately constructed using the interconnected connecting metal layer and auxiliary metal layer.

[0085] In some embodiments, the circuit layer may specifically include a circuit layer fabricated based on a 1p4m process.

[0086] In some embodiments, the plurality of metal layers, ordered from largest to smallest distance from the circuit layer substrate, include: a fourth metal layer (e.g., M4), a third metal layer (e.g., M3), a second metal layer (e.g., M2), and a first metal layer (e.g., M1). The fourth metal layer is the outermost metal layer furthest from the substrate. The first metal layer is the innermost metal layer closest to the substrate. The second and third metal layers are located between the first and second metal layers.

[0087] In some embodiments, the connecting metal layer may specifically be a fourth metal layer. This fourth metal layer can also be understood as the top metal layer of a circuit layer.

[0088] In practice, the connecting metal layer can be electrically connected to the lower electrode of the sensing layer, or the connecting metal layer can be directly used as the lower electrode of the sensing layer.

[0089] In some embodiments, the auxiliary metal layer may specifically be a first metal layer and / or a second metal layer.

[0090] Specifically, when the first metal layer is used as the auxiliary metal layer, there are two more metal layers, a second metal layer and a third metal layer, between the auxiliary metal layer and the connecting metal layer.

[0091] When a second metal layer is used as an auxiliary metal layer, at least a third metal layer exists between the auxiliary metal layer and the connecting metal layer.

[0092] Furthermore, the aforementioned auxiliary metal layer can also be a first metal layer and a second metal layer. For example, the connecting metal layer and the intermediate metal layer can be simultaneously layered on the third metal layer (M3). In this case, the fourth metal layer (M4) can be connected to both the second metal layer (M2) and the first metal layer (M1), thus obtaining an auxiliary metal layer that simultaneously includes both the first and second metal layers. In this case, the design of the second and first metal layers can be made more flexible, and they can jointly shield the parasitic capacitance of the third metal layer to the lower circuit.

[0093] In some embodiments, specific implementations may refer to Figure 7 As shown, when the auxiliary metal layer is the second metal layer, the intermediate metal layer is the third metal layer, and the connecting metal layer is the first metal layer.

[0094] The auxiliary metal layer and the connecting metal layer can be connected through vias, together serving as the lower electrode of the sensing layer; at the same time, the auxiliary metal layer and the connecting metal layer can also enclose the intermediate metal layer.

[0095] The aforementioned intermediate metal layer and connecting metal layer can be connected through vias; and the connecting metal layer is directly connected to the input terminal of the operational amplifier. Thus, the intermediate metal layer can be connected to the input terminal of the operational amplifier through the connecting metal layer.

[0096] For details, please refer to Figure 7 As shown, the connecting metal layer and the intermediate metal layer can respectively form a first sub-auxiliary capacitor (e.g., cco1) and a second sub-auxiliary capacitor (e.g., cco2) with the intermediate metal layer, thereby forming a total auxiliary capacitor cco between the intermediate metal layer and the connected auxiliary metal layer and the connecting metal layer.

[0097] Meanwhile, the connecting intermediate metal layer and the connecting metal layer can be understood as the lower plate of the auxiliary capacitor, and are connected to the input terminal of the operational amplifier. Since the intermediate metal layer is enveloped by the connecting metal layer and the auxiliary metal layer up to the input terminal of the operational amplifier, only the connecting layer, which is directly connected to the operational amplifier, forms parasitic capacitance to the circuit below it in the lower plate of the auxiliary capacitor. The intermediate metal layer, however, does not form parasitic capacitance to the circuit below it. Thus, through layout optimization (e.g., layout optimization), the area of ​​the connecting metal layer relative to the circuit below it can be minimized, thereby minimizing the parasitic capacitance formed by the connecting layer to the circuit below it.

[0098] This reduces the interference and impact of parasitic capacitance, making it less sensitive to the offset of the operational amplifier in each pixel unit. Consequently, the mismatch in the final output pixel data between different pixel units is reduced, directly reflecting the difference in DC quantity. Without needing to subtract background mismatch, a more uniform and consistent fingerprint image of higher quality can be obtained.

[0099] In some embodiments, specific implementations may refer to Figure 8 As shown, when the auxiliary metal layer is the first metal layer, the intermediate metal layer is the third metal layer, and the connecting metal layer is the second metal layer.

[0100] For details, please refer to Figure 8 As shown, the connecting metal layer and the intermediate metal layer can respectively form a first sub-auxiliary capacitor (e.g., cco1) and a second sub-auxiliary capacitor (e.g., cco2) with the intermediate metal layer, thereby forming a total auxiliary capacitor cco between the intermediate metal layer and the connected auxiliary metal layer and the connecting metal layer.

[0101] Meanwhile, the connecting intermediate metal layer and the connecting metal layer can be understood as the lower plate of the auxiliary capacitor, and are connected to the input terminal of the operational amplifier. Since the intermediate metal layer is enveloped by the connecting metal layer and the auxiliary metal layer up to the input terminal of the operational amplifier, only the connecting layer, which is directly connected to the operational amplifier, forms parasitic capacitance to the circuit below it in the lower plate of the auxiliary capacitor. The intermediate metal layer, however, does not form parasitic capacitance to the circuit below it. Thus, through layout optimization (e.g., layout optimization), the area of ​​the connecting metal layer relative to the circuit below it can be minimized, thereby minimizing the parasitic capacitance formed by the connecting layer to the circuit below it.

[0102] Similarly, when the auxiliary metal layer is the first metal layer, the intermediate metal layer can also be the second metal layer, and correspondingly, the connecting metal layer is the third metal layer.

[0103] Based on the above embodiments, the layout structure of multiple metal layers in the circuit layer fabricated using 1p4m technology can be effectively utilized. By using capacitor stacking and routing, a relatively large auxiliary capacitor that meets the requirements and is inserted between the sensing layer and the operational amplifier can be constructed while minimizing area consumption. Furthermore, the smaller parasitic capacitance formed by the lower plate of this auxiliary capacitor relative to the circuit below can replace the parasitic capacitance formed directly between the lower plate of the sensing layer and the circuit below, serving as the actual parasitic capacitance at the input of the operational amplifier. This effectively reduces the interference and impact caused by parasitic capacitance.

[0104] In some embodiments, see Figure 9 As shown, the plurality of metal layers may include three metal layers. Among them, the third metal layer (M3) is the metal layer farthest from the substrate, the first metal layer (M1) is the metal layer closest to the substrate, and the second metal layer (M2) is the metal layer located between the first metal layer and the third metal layer.

[0105] In practice, a third metal layer can be used as a connecting metal layer, a first metal layer as an auxiliary metal layer, and a second metal layer as an intermediate metal layer. The first and third metal layers are then connected through vias and then connected to the sensing layer. At the same time, the second metal layer is connected to the input terminal of the operational amplifier.

[0106] In this way, the first and third metal layers can be used to form a first sub-auxiliary capacitor (e.g., cco1) and a second sub-auxiliary capacitor (e.g., cco2) with the second metal layer, respectively, thereby forming the total auxiliary capacitance cco between the intermediate metal layer and the connected auxiliary and connecting metal layers. Simultaneously, a small portion of the second metal layer not covered by the first and third metal layers can be used to form the actual parasitic capacitance at the input of the operational amplifier relative to the circuit below. This allows for better adaptation to applications involving three metal layers, effectively reducing interference and impact caused by parasitic capacitance.

[0107] Of course, for applications where the circuit layer includes five or more metal layers, the above embodiments can be consulted to select connecting metal layers, auxiliary metal layers, and intermediate metal layers to construct compatible auxiliary capacitors and parasitic capacitors. This specification does not limit this aspect.

[0108] As can be seen from the above, the ultrasonic fingerprint pixel circuit provided in the embodiments of this specification includes at least: a sensing layer and a circuit layer; wherein, the circuit layer includes multiple metal layers, and the number of multiple metal layers is greater than or equal to 3; the circuit layer is also provided with an operational amplifier; the sensing layer is electrically connected to a connecting metal layer in the circuit layer; wherein, the connecting metal layer is the metal layer disposed on the top layer of the multiple metal layers; the sensing layer is used to receive echo signals about the fingerprint of a target object; the connecting metal layer is connected to an auxiliary metal layer among the multiple metal layers; wherein, at least one of the multiple metal layers exists between the connecting metal layer and the auxiliary metal layer; the input terminal of the operational amplifier is connected to an intermediate metal layer; wherein, the intermediate metal layer is the metal layer located between the connecting metal layer and the auxiliary metal layer among the multiple metal layers; an auxiliary capacitor for insertion between the sensing layer and the operational amplifier is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer. By first identifying an auxiliary metal layer from among the multiple metal layers of the circuit layer and connecting it to the connecting metal layer, which serves as the lower electrode of the sensing layer; then identifying an intermediate metal layer from the metal layers between the auxiliary and connecting metal layers, where most or even all of the area is enclosed by the connecting and auxiliary metal layers, and connecting this intermediate metal layer to the input terminal of the operational amplifier, an auxiliary capacitor can be formed using the intermediate metal layer, the connected metal layer, and the auxiliary metal layer for insertion between the sensing layer and the operational amplifier. This transforms the parasitic capacitance at the input terminal of the operational amplifier from the parasitic capacitance formed by the lower electrode of the sensing layer relative to the circuit below to the parasitic capacitance formed by the lower electrode of the auxiliary capacitor relative to the circuit below, thereby effectively reducing the interference and influence of parasitic capacitance at the input terminal of the operational amplifier and acquiring fingerprint data with high quality and low error.

[0109] See Figure 10 As shown in the embodiments of this specification, a method for constructing an ultrasonic fingerprint pixel circuit is also provided. Specifically, this method may include the following:

[0110] S1001: The top metal layer of the circuit layer is designated as a connection metal layer; and the connection metal layer is electrically connected to the sensing layer; wherein, the circuit layer contains multiple metal layers, and the number of the multiple metal layers is greater than or equal to 3; the circuit layer is also provided with an operational amplifier;

[0111] S1002: Determine an auxiliary metal layer from a plurality of metal layers; and connect the auxiliary metal layer to the connecting metal layer; wherein at least one of the plurality of metal layers exists between the connecting metal layer and the auxiliary metal layer;

[0112] S1003: Connect the input terminal of the operational amplifier to the intermediate metal layer; wherein, the intermediate metal layer is a metal layer located between the connecting metal layer and the auxiliary metal layer among a plurality of metal layers; an auxiliary capacitor is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

[0113] In practice, after determining the connecting metal layer, the auxiliary metal layer can be determined from the remaining metal layers based on the structural layout characteristics of multiple metal layers in the circuit layer and the position information of the connecting metal layer, ensuring that there is at least one more metal layer in the vertical space between it and the connecting metal layer.

[0114] In practice, the connecting metal layer and the auxiliary metal layer can also be connected by vias.

[0115] In practice, the areas of the connecting metal layer, auxiliary metal layer, and intermediate metal layer can be determined and adjusted by optimization based on the attenuation constraint parameters of the fingerprint signal and / or the area constraint parameters of the circuit layer. This ensures that the capacitance value of the auxiliary capacitor formed between the intermediate metal layer and the connected connecting metal layer and auxiliary metal layer for insertion between the sensing layer and the operational amplifier is relatively large, thereby reducing the attenuation effect of the auxiliary capacitor and minimizing the area consumption of the circuit layer.

[0116] In some embodiments, when the number of the plurality of metal layers is equal to 3, the above-mentioned connection of the input terminal of the operational amplifier to the intermediate metal layer may, in specific implementation, include: connecting the intermediate metal layers to the input terminal of the operational amplifier. Accordingly, the parasitic capacitance formed by a small portion of the intermediate metal layer not covered by the first and third metal layers relative to the underlying circuit can be used as the actual parasitic capacitance of the input terminal of the operational amplifier.

[0117] In some embodiments, when the number of the plurality of metal layers is greater than 3, the connection of the input terminal of the operational amplifier to the intermediate metal layer can, in specific implementation, include:

[0118] S1: Determine the connecting metal layer from the remaining metal layers among the plurality of metal layers;

[0119] S2: Electrically connect the connecting metal layer to the input terminal of the operational amplifier; and connect the connecting metal layer to the intermediate metal layer.

[0120] In practice, the connecting metal layer and the intermediate metal layer can be connected by vias.

[0121] Accordingly, the parasitic capacitance formed by the connecting metal layer relative to the circuit below can be used as the actual parasitic capacitance of the operational amplifier's input terminal.

[0122] Furthermore, when the number of the plurality of metal layers is greater than three, the above-mentioned connection of the input terminal of the operational amplifier to the intermediate metal layer may, in a specific implementation, include: directly connecting the intermediate metal layer to the input terminal of the operational amplifier; and minimizing the traces of other metal layers below the intermediate metal layer. Correspondingly, the parasitic capacitance formed by a small portion of the intermediate metal layer not covered by the first and third metal layers relative to the circuit below can be used as the actual parasitic capacitance of the input terminal of the operational amplifier.

[0123] As can be seen from the above, the method for constructing the ultrasonic fingerprint pixel circuit based on the embodiments of this specification first determines an auxiliary metal layer from among the multiple metal layers of the circuit layer and connects the auxiliary metal layer to the connecting metal layer, which serves as the lower electrode of the sensing layer; then, it determines an intermediate metal layer from the metal layers between the auxiliary metal layer and the connecting metal layer, where most or even all of the area is wrapped by the connecting metal layer and the auxiliary metal layer, and connects the intermediate metal layer to the input terminal of the operational amplifier. This intermediate metal layer, along with the connected connecting metal layer and the auxiliary metal layer, forms an auxiliary capacitor for insertion between the sensing layer and the operational amplifier. Consequently, the actual parasitic capacitance at the input terminal of the operational amplifier is transformed from the parasitic capacitance formed by the lower electrode of the sensing layer relative to the lower circuit to a parasitic capacitance formed by the lower electrode of the auxiliary capacitor relative to the lower circuit. This effectively reduces the interference and influence of the parasitic capacitance at the input terminal of the operational amplifier, enabling the acquisition of fingerprint data with higher quality and smaller errors.

[0124] This specification provides an ultrasonic fingerprint chip, including at least the ultrasonic fingerprint pixel circuit. The ultrasonic fingerprint pixel circuit includes at least a sensing layer and a circuit layer; wherein the circuit layer comprises multiple metal layers, the number of which is greater than or equal to three; the circuit layer also includes an operational amplifier; the sensing layer is electrically connected to a connecting metal layer in the circuit layer; wherein the connecting metal layer is the metal layer disposed on the top layer of the circuit layer; the sensing layer is used to receive echo signals about the fingerprint of a target object; the connecting metal layer is connected to an auxiliary metal layer among the multiple metal layers; wherein at least one of the multiple metal layers exists between the connecting metal layer and the auxiliary metal layer; the input terminal of the operational amplifier is connected to an intermediate metal layer; wherein the intermediate metal layer is the metal layer located between the connecting metal layer and the auxiliary metal layer; an auxiliary capacitor is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer, the auxiliary capacitor being located between the sensing layer and the operational amplifier.

[0125] This specification also provides an electronic device (e.g., an ultrasonic fingerprint sensing device) that includes at least an ultrasonic fingerprint chip. The ultrasonic fingerprint chip includes at least the ultrasonic fingerprint pixel circuit.

[0126] This specification provides an electronic device through its embodiments. (See attached document.) Figure 11 As shown. The electronic device includes a network communication port 1101, a processor 1102, and a memory 1103. These structures are connected by internal cables so that they can perform specific data interaction.

[0127] Specifically, the network communication port 1101 can be used to receive construction instructions.

[0128] The processor 1102 can specifically be used to respond to a build instruction to determine an outer metal layer of the circuit layer as a connection metal layer; and electrically connect the connection metal layer to the sensing layer; wherein the circuit layer includes multiple metal layers, the number of which is greater than or equal to 3; the circuit layer also includes an operational amplifier; an auxiliary metal layer is determined from the multiple metal layers; and the auxiliary metal layer is connected to the connection metal layer; wherein at least one of the multiple metal layers exists between the connection metal layer and the auxiliary metal layer; the input terminal of the operational amplifier is connected to an intermediate metal layer; wherein the intermediate metal layer is a metal layer located between the connection metal layer and the auxiliary metal layer; an auxiliary capacitor is formed between the intermediate metal layer and the connected connection metal layer and the auxiliary metal layer, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

[0129] The memory 1103 can be used to store the corresponding instruction program and related intermediate data.

[0130] Based on the above method, the relevant structural performance of electronic devices can be effectively utilized to improve the data processing speed of electronic devices and efficiently realize the data processing of the construction of ultrasonic fingerprint pixel circuit.

[0131] In this embodiment, the network communication port 1101 can be a virtual port bound to different communication protocols, thereby enabling the sending or receiving of different data. For example, the network communication port can be a port responsible for web data communication, a port responsible for FTP data communication, or a port responsible for email data communication. Furthermore, the network communication port can also be a physical communication interface or communication chip. For example, it can be a wireless mobile network communication chip, such as GSM or CDMA; it can also be a Wi-Fi chip; or it can be a Bluetooth chip.

[0132] In this embodiment, the processor 1102 can be implemented in any suitable manner. For example, the processor can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers, etc. This specification is not limiting.

[0133] In this embodiment, the memory 1103 may include multiple layers. In a digital system, anything that can store binary data can be a memory. In an integrated circuit, a circuit with storage function but no physical form is also called a memory, such as RAM, FIFO, etc. In a system, a storage device with a physical form is also called a memory, such as a memory stick, TF card, etc.

[0134] This specification also provides a computer-readable storage medium based on the above-described method for constructing an ultrasonic fingerprint pixel circuit. The computer-readable storage medium stores computer program instructions that, when executed, implement: determining an outer metal layer of the circuit layer as a connection metal layer; and electrically connecting the connection metal layer to a sensing layer; wherein the circuit layer comprises multiple metal layers, the number of which is greater than or equal to 3; the circuit layer further includes an operational amplifier; determining an auxiliary metal layer from the multiple metal layers; and connecting the auxiliary metal layer to the connection metal layer; wherein at least one of the multiple metal layers exists between the connection metal layer and the auxiliary metal layer; connecting the input terminal of the operational amplifier to an intermediate metal layer; wherein the intermediate metal layer is a metal layer located between the connection metal layer and the auxiliary metal layer; and forming an auxiliary capacitor between the intermediate metal layer and the connected connection metal layer and auxiliary metal layer, the auxiliary capacitor being located between the sensing layer and the operational amplifier.

[0135] In this embodiment, the storage medium includes, but is not limited to, Random Access Memory (RAM), Read-Only Memory (ROM), Cache, Hard Disk Drive (HDD), or Memory Card. The memory can be used to store computer program instructions. The network communication unit can be an interface configured according to standards specified in the communication protocol for network connection communication.

[0136] In this embodiment, the specific functions and effects implemented by the program instructions stored in the computer-readable storage medium can be explained in comparison with other embodiments, and will not be repeated here.

[0137] This specification also provides a computer program product, comprising at least a computer program, which, when executed by a processor, implements the following method steps: determining an outer metal layer of a circuit layer as a connection metal layer; and electrically connecting the connection metal layer to a sensing layer; wherein the circuit layer comprises a plurality of metal layers, the number of which is greater than or equal to 3; the circuit layer further comprises an operational amplifier; determining an auxiliary metal layer from the plurality of metal layers; and connecting the auxiliary metal layer to the connection metal layer; wherein at least one of the plurality of metal layers exists between the connection metal layer and the auxiliary metal layer; connecting the input terminal of the operational amplifier to an intermediate metal layer; wherein the intermediate metal layer is a metal layer located between the connection metal layer and the auxiliary metal layer; and forming an auxiliary capacitor between the intermediate metal layer and the connected connection metal layer and the auxiliary metal layer, the auxiliary capacitor being located between the sensing layer and the operational amplifier.

[0138] See Figure 12 As shown in the embodiments of this specification, an apparatus for constructing an ultrasonic fingerprint pixel circuit is also provided. This apparatus may specifically include the following structural modules:

[0139] The first connection module 1201 is specifically used to determine the top metal layer of the circuit layer as the connection metal layer; and to electrically connect the connection metal layer to the sensing layer; wherein, the circuit layer includes multiple metal layers, and the number of the multiple metal layers is greater than or equal to 3; the circuit layer is also provided with an operational amplifier;

[0140] The second connection module 1202 is specifically used to determine an auxiliary metal layer from a plurality of metal layers; and connect the auxiliary metal layer to the connection metal layer; wherein at least one of the plurality of metal layers exists between the connection metal layer and the auxiliary metal layer;

[0141] The third connection module 1203 is specifically used to connect the input terminal of the operational amplifier to the intermediate metal layer; wherein, the intermediate metal layer is a metal layer located between the connecting metal layer and the auxiliary metal layer among a plurality of metal layers; an auxiliary capacitor is formed between the intermediate metal layer and the connected connecting metal layer and the auxiliary metal layer, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

[0142] In some embodiments, when the number of the plurality of metal layers is greater than 3, the third connection module 1203 described above can be implemented in such a way as follows: the input terminal of the operational amplifier is connected to the intermediate metal layer from the remaining metal layers among the plurality of metal layers; the connecting metal layer is electrically connected to the input terminal of the operational amplifier; and the connecting metal layer is connected to the intermediate metal layer.

[0143] It should be noted that the units, devices, or modules described in the above embodiments can be implemented by a computer circuit layer or physical entity, or by a product with a certain function. For ease of description, the above devices are described by dividing them into various modules according to their functions. Of course, in implementing this specification, the functions of each module can be implemented in one or more software and / or hardware, or a module that implements the same function can be implemented by a combination of multiple sub-modules or sub-units, etc. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection between the shown or discussed mutuals can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0144] As can be seen from the above, the construction apparatus for the ultrasonic fingerprint pixel circuit provided in the embodiments of this specification first determines an auxiliary metal layer from among the multiple metal layers of the circuit layer and connects the auxiliary metal layer to the connecting metal layer, which serves as the lower electrode of the sensing layer; then, it determines an intermediate metal layer from the metal layer between the auxiliary metal layer and the connecting metal layer, in which most or even all of the area is wrapped by the connecting metal layer and the auxiliary metal layer, and connects the intermediate metal layer to the input terminal of the operational amplifier. This intermediate metal layer, along with the connected connecting metal layer and the auxiliary metal layer, forms an auxiliary capacitor for insertion between the sensing layer and the operational amplifier. Consequently, the actual parasitic capacitance at the input terminal of the operational amplifier is transformed from the parasitic capacitance formed by the lower electrode of the sensing layer relative to the lower circuit to a parasitic capacitance formed by the lower electrode of the auxiliary capacitor relative to the lower circuit, thereby effectively reducing the interference and influence of the parasitic capacitance at the input terminal of the operational amplifier and enabling the acquisition of fingerprint data with high quality and low error.

[0145] While this specification provides the steps of operation for the methods described in the embodiments or flowcharts, more or fewer steps may be included based on conventional or non-inventive means. The order of steps listed in the embodiments is merely one possible order of execution among many steps and does not represent the only possible order. In actual device or client product execution, the methods shown in the embodiments or drawings may be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment, or even a distributed data processing environment). The terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, product, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, product, or apparatus. Without further limitations, the presence of other identical or equivalent elements in a process, method, product, or apparatus that includes said elements is not excluded. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

[0146] Those skilled in the art will also know that, besides implementing the controller using purely computer-readable program code, the same functions can be achieved by logically programming the method steps, making the controller function as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers (PLCs), and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the devices within it used to implement various functions can also be considered structures within that hardware component. Alternatively, the devices used to implement various functions can be considered as both software modules implementing the method and structures within a hardware component.

[0147] This specification can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, classes, etc., that perform a specific task or implement a specific abstract data type. This specification can also be practiced in distributed computing environments, where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer-readable storage media, including storage devices.

[0148] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this specification can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions of this specification can essentially be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments of this specification.

[0149] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. This specification can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0150] Although this specification has been described by way of examples, those skilled in the art will recognize that many variations and modifications are possible without departing from the spirit of this specification, and it is intended that the appended claims cover such variations and modifications without departing from the spirit of this specification.

Claims

1. An ultrasonic fingerprint pixel circuit, characterized by, At least comprising: a sensing layer, a circuit layer; wherein the circuit layer contains a plurality of metal layers, the number of the plurality of metal layers is greater than or equal to 3; the circuit layer is further provided with an operational amplifier; the sensing layer and the connecting metal layer in the circuit layer are electrically connected; wherein the connecting metal layer is a metal layer in the plurality of metal layers which is arranged on the top layer of the circuit layer; the sensing layer is used to receive echo signals about the fingerprint of a target object; the connecting metal layer is connected with an auxiliary metal layer in the plurality of metal layers; wherein there is at least one metal layer in the plurality of metal layers between the connecting metal layer and the auxiliary metal layer; the input end of the operational amplifier is connected with an intermediate metal layer; wherein the intermediate metal layer is a metal layer in the plurality of metal layers which is located between the connecting metal layer and the auxiliary metal layer; the intermediate metal layer forms an auxiliary capacitor between the connecting metal layer and the auxiliary metal layer which is connected, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

2. The ultrasonic fingerprint pixel circuit of claim 1, wherein, The connecting metal layer and the auxiliary metal layer are connected through a via structure.

3. The ultrasonic fingerprint pixel circuit of claim 1, wherein, The sensing layer includes a piezoelectric transduction layer.

4. The ultrasonic fingerprint pixel circuit of claim 1, wherein, The intermediate metal layer is also connected with a linking metal layer in the plurality of metal layers; the intermediate metal layer is connected with the input end of the operational amplifier through the linking metal layer.

5. The ultrasonic fingerprint pixel circuit of claim 1, wherein, The area of the auxiliary capacitor is greater than a preset area threshold; wherein the preset area threshold is determined according to a decay constraint parameter of the fingerprint signal.

6. The ultrasonic fingerprint pixel circuit of claim 4, wherein, According to the distance from the circuit layer substrate in descending order, the plurality of metal layers include: a fourth metal layer, a third metal layer, a second metal layer, and a first metal layer.

7. The ultrasonic fingerprint pixel circuit of claim 6, wherein, The connecting metal layer is the fourth metal layer.

8. The ultrasonic fingerprint pixel circuit of claim 7, wherein, The auxiliary metal layer is the first metal layer and / or the second metal layer.

9. The ultrasonic fingerprint pixel circuit of claim 8, wherein, When the auxiliary metal layer is the first metal layer, the intermediate metal layer is the third metal layer, and the linking metal layer is the second metal layer.

10. The ultrasonic fingerprint pixel circuit of claim 8, wherein, When the auxiliary metal layer is the second metal layer, the intermediate metal layer is the third metal layer, and the linking metal layer is the first metal layer.

11. A method of constructing an ultrasonic fingerprint pixel circuit, comprising: Including: determining the top layer metal layer of the circuit layer as the connecting metal layer; and electrically connecting the connecting metal layer with the sensing layer; wherein the circuit layer contains a plurality of metal layers, the number of the plurality of metal layers is greater than or equal to 3; the circuit layer is further provided with an operational amplifier; from the plurality of metal layers, determining an auxiliary metal layer; and connecting the auxiliary metal layer with the connecting metal layer; wherein there is at least one metal layer in the plurality of metal layers between the connecting metal layer and the auxiliary metal layer; connecting the input end of the operational amplifier with an intermediate metal layer; wherein the intermediate metal layer is a metal layer in the plurality of metal layers which is located between the connecting metal layer and the auxiliary metal layer; the intermediate metal layer forms an auxiliary capacitor between the connecting metal layer and the auxiliary metal layer which is connected, and the auxiliary capacitor is located between the sensing layer and the operational amplifier.

12. The method of claim 11, wherein, When the number of the plurality of metal layers is greater than 3, connecting the input end of the operational amplifier with the intermediate metal layer includes: determining a connection metal layer from the rest of the plurality of metal layers; electrically connecting the connection metal layer with an input terminal of an operational amplifier, and connecting the connection metal layer with the intermediate metal layer.

13. An ultrasonic fingerprint chip, comprising at least the ultrasonic fingerprint pixel circuit according to any one of claims 1 to 10.

14. An electronic device, comprising: at least the ultrasonic fingerprint chip according to claim 13.

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