High-voltage gate drive circuit

Abstract

The application relates to the technical field of integrated circuits, and particularly discloses a high-voltage gate drive circuit which comprises a signal input unit, a level shift unit, a signal latch unit, a low-bridge output unit and a high-bridge output unit; the signal input unit is used for filtering and processing an input signal; the low-bridge output unit is used for low-bridge drive enhancement of the filtered and processed signal; the level shift unit is used for transmitting the filtered and processed signal based on a step-by-step conduction function; the signal latch unit is used for voltage hysteresis processing of a high-bridge filtered and processed signal; the high-bridge output unit is used for high-bridge drive enhancement of the high-bridge filtered and processed signal after voltage hysteresis, and high-bridge output signals are obtained; the high-bridge output signals and the low-bridge output signals are opposite in phase. The high-voltage gate drive circuit can avoid large current of a sharp pulse at the moment when a high-voltage transmission tube is opened and can also eliminate the influence of high-speed voltage conversion interference noise caused by a floating island.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-voltage gate drive circuit. Background Technology

[0002] High-voltage gate drive circuits are a core supporting technology for power electronic systems. Their development is deeply intertwined with the evolution of power electronic technology, the upgrading of power semiconductor devices, the iteration of downstream application demands, and the improvement of industry standards. Their core mission is to provide safe, accurate, and efficient gate control signals for high-voltage power switching devices, supporting the conversion and transmission of power in high-power and high-voltage scenarios.

[0003] The schematic diagram of the high-voltage gate drive circuit in the prior art is as follows: Figure 1 As shown, in this circuit, the low-bridge input signal is transmitted to the input of inverter INV1 through the low-bridge pre-amplifier module, then to the gate of high-voltage transfer transistor Q1 through inverter INV6, and then to the high-bridge channel through pull-up resistor R. After being filtered by the high-bridge filter module, it finally drives the external switching device at the high-bridge output port HO after passing through inverters INV8 and INV9. At the same time, the input signal from the low-bridge input is input to inverters INV2 and INV3, then filtered by the low-bridge filter module, and then drives the external switching device at the low-bridge output port LO after passing through inverters INV4 and INV5. Figure 1 The high-voltage gate drive circuit shown has a simple structure and can transmit the input signal of the low bridge to the high / low bridge output to drive external switching devices. However, the circuit turns on the high-voltage transmission transistor all at once during signal transmission without staged conduction. This can easily lead to a spike pulse current at the moment the high-voltage transmission transistor turns on, which affects the SOA (Safe Operating Area) performance of the high-voltage transmission transistor and reduces its reliability. In addition, the signal of this circuit is easily affected by the high-speed voltage transformation interference noise from the VS of the floating island terminal during high-bridge transmission, which can cause the high-bridge output to turn on / off incorrectly.

[0004] Therefore, how to avoid the spike pulse current at the moment the high-voltage transmission tube is turned on to improve the reliability of the high-voltage transmission tube, while also eliminating the interference noise caused by the high-speed voltage transformation at the floating island end, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This invention provides a high-voltage gate drive circuit that solves the problems in related technologies, such as the unavoidable spike pulse current at the moment the high-voltage transmission tube is turned on and the interference noise at the floating island end.

[0006] As one aspect of the present invention, a high-voltage gate driving circuit is provided, comprising: a signal input unit, a level shifting unit, a signal latching unit, a low-bridge output unit, and a high-bridge output unit, wherein the signal input unit is connected to the level shifting unit and the low-bridge output unit respectively, the signal latching unit is connected to the level shifting unit, and the high-bridge output unit is connected to the signal latching unit;

[0007] The signal input unit is used to filter the input signal to obtain the filtered signal.

[0008] The low-bridge output unit is used to enhance the filtered signal with low-bridge drive to obtain a low-bridge output signal, and the low-bridge output signal is used to drive the switching action of the low-bridge external switching device.

[0009] The level shifting unit is used to transmit the filtered signal based on the step-by-step conduction function to obtain the high-bridge filtered signal. The step-by-step conduction function is that the two shifting modules in the level shifting unit are turned on at different times to realize the step-by-step transmission of the filtered signal.

[0010] The signal latching unit is used to perform voltage hysteresis processing on the high-bridge filtered signal to obtain the high-bridge filtered signal after voltage hysteresis.

[0011] The high-bridge output unit is used to enhance the high-bridge filtered signal after voltage hysteresis to obtain a high-bridge output signal, and the high-bridge output signal is used to drive the switching action of the external high-bridge switching device.

[0012] The high-bridge output signal and the low-bridge output signal are out of phase.

[0013] Furthermore, the level shifting unit includes a first shift module and a second shift module, wherein the first shift module is connected to the second shift module.

[0014] The first shift module is used to turn on at a first moment to transmit the filtered signal to the second shift module;

[0015] The second shift module is used to turn on at a second time to transmit the filtered signal and obtain the high-bridge filtered signal, wherein there is a time difference between the second time and the first time, and the second time is later than the first time.

[0016] Furthermore, the first shift module includes: a first constant current source, a second constant current source, a seventeenth transistor, an eighteenth transistor, a twentieth transistor, and a twenty-first transistor.

[0017] One end of the first constant current source is connected to signal ground, and the other end of the first constant current source is connected to the source terminal of the 21st transistor. The drain terminal of the 21st transistor is connected to the source terminal of the 20th transistor. The gate terminal of the 21st transistor is the second input terminal of the level shifting unit and is connected to the signal input unit. The drain terminal of the 20th transistor is connected to the signal latching unit. The gate terminal of the 20th transistor is connected to the gate terminal of the 17th transistor. The drain terminal of the 17th transistor is connected to the signal latching unit. The source terminal of the 17th transistor is connected to the drain terminal of the 18th transistor. The source terminal of the 18th transistor is connected to one end of the second constant current source. The other end of the second constant current source is connected to signal ground. The gate terminal of the 18th transistor is the first input terminal of the level shifting unit and is connected to the signal input unit.

[0018] The second shift module includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a nineteenth transistor, and a twenty-second transistor.

[0019] The source terminal of the eleventh transistor is connected to the high-bridge power supply voltage terminal, the drain terminal of the eleventh transistor is connected to the drain terminal of the thirteenth transistor, and the gate terminal of the eleventh transistor is connected to the signal latch unit. The source terminal of the twelfth transistor is connected to the high-bridge power supply voltage terminal, the drain terminal of the twelfth transistor is connected to the drain terminal of the fourteenth transistor, and the gate terminal of the twelfth transistor is connected to the signal latch unit. The gate terminal of the thirteenth transistor is connected to the gate terminal of the twentieth transistor, and the gate terminal of the thirteenth transistor is the input terminal of the level shift unit. The source terminal of the thirteenth transistor is connected to the gate terminal of the twentieth transistor, the gate terminal of the fourteenth transistor is connected to the gate terminal of the thirteenth transistor, the source terminal of the fourteenth transistor is connected to the gate terminal of the nineteenth transistor, the drain terminal of the nineteenth transistor is connected to one end of the second constant current source, and the source terminal of the nineteenth transistor is connected to signal ground. The drain terminal of the twenty-second transistor is connected to the other end of the first constant current source, and the source terminal of the twenty-second transistor is connected to signal ground.

[0020] Furthermore, the signal latching unit includes: a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a twenty-sixth transistor.

[0021] The drain terminal of the 23rd transistor is connected to both the level shifting unit and the gate terminal of the 24th transistor. The source terminal of the 23rd transistor is connected to the high-bridge power supply voltage terminal, and the gate terminal of the 23rd transistor is connected to the drain terminal of the 24th transistor.

[0022] The source terminal of the 24th transistor is connected to the high-bridge power supply voltage terminal, and the drain terminal of the 24th transistor is connected to the level shifting unit.

[0023] The drain terminal of the 25th transistor is connected to the drain terminal of the 23rd transistor, the source terminal of the 25th transistor is connected to the floating island terminal of the high-bridge output unit, and the gate terminal of the 25th transistor is connected to the drain terminal of the 26th transistor.

[0024] The gate of the 26th transistor is connected to the drain of the 25th transistor, the drain of the 26th transistor is connected to the drain of the 24th transistor, and the source of the 26th transistor is connected to the floating island of the high-bridge output unit.

[0025] Furthermore, the high-voltage gate drive circuit also includes a delay matching unit, the input terminal of which is connected to the output terminal of the signal input unit, and the output terminal of which is connected to the input terminal of the low-bridge output unit;

[0026] The delay matching unit is used to adjust the dead time of the high-bridge output signal and the low-bridge output signal.

[0027] Furthermore, the delay matching unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a second resistor, a third resistor, and a second capacitor;

[0028] The gate terminal of the seventh transistor is connected to the gate terminal of the eighth transistor, and both are connected to the output terminal of the signal input unit.

[0029] The source terminal of the seventh transistor is connected to the low-bridge power supply voltage terminal, the drain terminal of the seventh transistor is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the third resistor, the other end of the third resistor is connected to the drain terminal of the eighth transistor, and the source terminal of the eighth transistor is connected to signal ground.

[0030] One end of the second capacitor is connected to the other end of the second resistor, and the other end of the second capacitor is connected to signal ground;

[0031] The gate terminal of the ninth transistor is connected to the gate terminal of the tenth transistor, and both are connected to one end of the second capacitor. The source terminal of the ninth transistor is connected to the low-bridge power supply voltage terminal, and the drain terminal of the ninth transistor is connected to the drain terminal of the tenth transistor, and both are connected to the input terminal of the low-bridge output unit. The source terminal of the tenth transistor is connected to signal ground.

[0032] Furthermore, the high-voltage gate drive circuit also includes a voltage clamping unit, which is connected to the level shifting unit. The voltage clamping unit is used to convert the high voltage in the high-bridge filtered signal of the level shifting unit into a low voltage.

[0033] Furthermore, the voltage clamping unit includes a fourth resistor and a Zener diode. One end of the fourth resistor is connected to the high-bridge power supply voltage terminal, and the other end of the fourth resistor is connected to the cathode of the Zener diode. The anode of the Zener diode is connected to signal ground.

[0034] Furthermore, the signal input unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, and a first capacitor.

[0035] The gate terminal of the first transistor is connected to the gate terminal of the second transistor, and both are input terminals of the signal input unit; the source terminal of the first transistor is connected to the low bridge power supply voltage terminal; the drain terminal of the first transistor is connected to the drain terminal of the second transistor, and both are connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to signal ground; the source terminal of the second transistor is connected to signal ground.

[0036] The gate of the third transistor is connected to the gate of the fourth transistor, and both are connected to the other end of the first resistor; the source of the third transistor is connected to the low bridge power supply voltage terminal; the drain of the third transistor is connected to the drain of the fourth transistor, and both are connected to the first input terminal of the level shifting unit; the source of the fourth transistor is connected to signal ground.

[0037] The gate terminal of the fifth transistor is connected to the gate terminal of the sixth transistor, and both are connected to the first input terminal of the level shifting unit; the source terminal of the fifth transistor is connected to the low bridge power supply voltage terminal; the drain terminal of the fifth transistor is connected to the drain terminal of the sixth transistor, both of which are output terminals of the signal input unit, and both are connected to the second input terminal of the level shifting unit; the source terminal of the sixth transistor is connected to signal ground.

[0038] Furthermore, the low-bridge output unit includes: a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, and a thirty-fourth transistor.

[0039] The gate terminal of the thirty-first transistor is connected to the gate terminal of the thirty-second transistor, and both are input terminals of the low-bridge output unit. The source terminal of the thirty-first transistor is connected to the low-bridge power supply voltage terminal, the drain terminal of the thirty-first transistor is connected to the drain terminal of the thirty-second transistor, and the source terminal of the thirty-second transistor is connected to signal ground.

[0040] The gate terminal of the thirty-third transistor is connected to the gate terminal of the thirty-fourth transistor, and both are connected to the drain terminals of the thirty-first transistor and the thirty-second transistor; the source terminal of the thirty-third transistor is connected to the low-bridge power supply voltage terminal; the drain terminal of the thirty-third transistor is connected to the drain terminal of the thirty-fourth transistor, and both are output terminals of the low-bridge output unit; the source terminal of the thirty-fourth transistor is connected to signal ground.

[0041] The high-bridge output unit includes: the twenty-seventh transistor, the twenty-eighth transistor, the twenty-ninth transistor, and the thirtieth transistor.

[0042] The gate terminal of the 27th transistor is connected to the gate terminal of the 28th transistor, and both are input terminals of the high-bridge output unit; the source terminal of the 27th transistor is connected to the high-bridge power supply voltage terminal; the drain terminal of the 27th transistor is connected to the drain terminal of the 28th transistor; the source terminal of the 28th transistor is connected to the floating island terminal of the high-bridge output unit.

[0043] The gate terminal of the 29th transistor is connected to the gate terminal of the 30th transistor, and both are connected to the drain terminals of the 27th transistor and the 28th transistor; the source terminal of the 29th transistor is connected to the high-bridge power supply voltage terminal; the drain terminal of the 29th transistor is connected to the drain terminal of the 30th transistor, and both are output terminals of the high-bridge output unit; the source terminal of the 30th transistor is connected to the floating island terminal of the high-bridge output unit.

[0044] The high-voltage gate drive circuit provided by this invention automatically filters the input signal in the signal input unit, then accurately transmits the signal to the high-bridge output unit via a level shifting unit and a signal latching unit. Finally, the high-bridge output unit enhances its driving capability to drive the external high-bridge switching device. Simultaneously, the filtered signal is transmitted to the low-bridge output unit, which also enhances its driving capability to drive the external low-bridge switching device. Furthermore, the output signals at the high-bridge and low-bridge outputs are out of phase. This high-voltage gate drive circuit not only effectively transmits the signal from the low-bridge input to the high / low-bridge outputs to drive external switching devices, but also eliminates dv / dt interference noise from the floating island through the voltage hysteresis function of the signal latching unit. Additionally, the step-by-step conduction function of the level shifting unit effectively avoids the spike pulse current that occurs when the high-voltage transmission tube turns on during the transmission of the input signal from the low-bridge to the high-bridge, thereby improving transmission reliability. Therefore, the high-voltage gate drive circuit provided by this invention not only has the functions of accurate transmission of input signals and strong anti-interference, but also has the characteristics of simple structure, low cost and high reliability. Attached Figure Description

[0045] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.

[0046] Figure 1 This is a circuit schematic of a high-voltage gate drive circuit in the prior art.

[0047] Figure 2 The structural block diagram of the high-voltage gate drive circuit provided by the present invention.

[0048] Figure 3 This is a structural block diagram of a specific embodiment of the high-voltage gate drive circuit provided by the present invention.

[0049] Figure 4 The circuit diagram of the high-voltage gate drive circuit provided by the present invention.

[0050] Figure 5 This is a structural block diagram of another specific embodiment of the high-voltage gate drive circuit provided by the present invention.

[0051] Figure 6 The schematic diagram of the application circuit of the high-voltage gate drive circuit provided by the present invention.

[0052] Figure 7 Waveform diagram of the high-voltage gate drive circuit provided by the present invention. Detailed Implementation

[0053] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] This embodiment provides a high-voltage gate drive circuit. Figure 2 This is a structural block diagram of the high-voltage gate drive circuit 100 provided according to an embodiment of the present invention, as shown below. Figure 2 As shown, it includes: a signal input unit 110, a level shifting unit 120, a signal latching unit 130, a low-bridge output unit 140, and a high-bridge output unit 150. The signal input unit 110 is connected to the level shifting unit 120 and the low-bridge output unit 140, the signal latching unit 130 is connected to the level shifting unit 120, and the high-bridge output unit 150 is connected to the signal latching unit 130.

[0057] The signal input unit 110 is used to filter the input signal to obtain a filtered signal.

[0058] The low-bridge output unit 140 is used to enhance the filtered signal with low-bridge drive to obtain a low-bridge output signal, and the low-bridge output signal is used to drive the switching action of the low-bridge external switching device.

[0059] The level shifting unit 120 is used to transmit the filtered signal based on the step-by-step conduction function to obtain the high-bridge filtered signal. The step-by-step conduction function is that the two shifting modules in the level shifting unit are turned on at different times to realize the step-by-step transmission of the filtered signal.

[0060] The signal latch unit 130 is used to perform voltage hysteresis processing on the high-bridge filtered signal to obtain the high-bridge filtered signal after voltage hysteresis.

[0061] The high-bridge output unit 150 is used to enhance the high-bridge filtered signal after voltage hysteresis to obtain a high-bridge output signal, and the high-bridge output signal is used to drive the switching action of the high-bridge external switching device.

[0062] The high-bridge output signal and the low-bridge output signal are out of phase.

[0063] In this embodiment of the invention, the signal input unit 110 can filter the input signal to remove high-frequency interference noise. It should be understood that the input signal here is specifically a low-bridge input signal, i.e., a low-voltage signal. This input signal is enhanced by the low-bridge output unit 140 to obtain a low-bridge output signal, which drives the external switching devices of the low-bridge. The input signal can also be passed through the step-by-step conduction function of the level shift unit 120 to progressively transmit sound pressure to obtain a high-bridge filtered signal. This high-bridge filtered signal undergoes voltage hysteresis processing by the signal latch unit 130 for effective latching, thereby effectively avoiding the influence of interference noise. The high-bridge filtered signal, after being processed by the signal latch unit 130 and then hysteresis-processed, is enhanced by the high-bridge output unit 150 to obtain a high-bridge output signal, which can drive the external switching devices of the high-bridge.

[0064] Therefore, the high-voltage gate drive circuit provided by this invention automatically filters the input signal in the signal input unit, then accurately transmits the signal to the high-bridge output unit via a level shifting unit and a signal latching unit. Finally, the high-bridge output unit enhances its driving capability to drive the external high-bridge switching device. Simultaneously, the filtered signal is transmitted to the low-bridge output unit, which also enhances its driving capability to drive the external low-bridge switching device. Furthermore, the output signal at the high-bridge output terminal is out of phase with the output signal at the low-bridge output terminal. This high-voltage gate drive circuit not only effectively transmits the signal from the low-bridge input terminal to the high / low-bridge output terminals to drive the external switching device, but also eliminates the dv / dt interference noise from the floating island terminal through the voltage hysteresis function of the signal latching unit. Simultaneously, the step-by-step conduction function of the level shifting unit effectively avoids the spike pulse current that occurs when the high-voltage transmission tube turns on during the transmission of the input signal from the low-bridge to the high-bridge, thereby improving transmission reliability. Therefore, the high-voltage gate drive circuit provided by this invention not only has the functions of accurate transmission of input signals and strong anti-interference, but also has the characteristics of simple structure, low cost and high reliability.

[0065] In this embodiment of the invention, in order to achieve the step-by-step conduction function of the high-voltage transmission tube, such as... Figure 3 As shown, the level shifting unit 120 includes a first shift module 121 and a second shift module 122, wherein the first shift module 121 is connected to the second shift module 122.

[0066] The first shift module 121 is used to turn on at a first moment to transmit the filtered signal to the second shift module 122;

[0067] The second shift module 122 is used to be turned on at the second time to transmit the filtered signal and obtain the high-bridge filtered signal, wherein there is a time difference between the second time and the first time, and the second time is later than the first time.

[0068] It should be understood that by turning on the first shift module 121 and the second shift module 122 in sequence, the input signal is transmitted in a time-division manner through the high-voltage transmission tube, thereby effectively avoiding the spike pulse current at the moment the high-voltage transmission tube is turned on.

[0069] Specifically, such as Figure 4 As shown, the first shift module 121 includes: a first constant current source I1, a second constant current source I2, a seventeenth transistor Q17, an eighteenth transistor Q18, a twentieth transistor Q20, and a twenty-first transistor Q21.

[0070] One end of the first constant current source I1 is connected to signal ground, and the other end of the first constant current source I1 is connected to the source terminal of the 21st transistor Q21. The drain terminal of the 21st transistor Q21 is connected to the source terminal of the 20th transistor Q20. The gate terminal of the 21st transistor Q21 is the second input terminal of the level shifting unit and is connected to the signal input unit. The drain terminal of the 20th transistor Q20 is connected to the signal latching unit 130. The gate terminal of the 20th transistor Q20 is connected to the gate terminal of the 17th transistor Q17. The drain terminal of the 17th transistor Q17 is connected to the signal latching unit 130. The source terminal of the 17th transistor Q17 is connected to the drain terminal of the 18th transistor Q18. The source terminal of the 18th transistor Q18 is connected to one end of the second constant current source I2. The other end of the second constant current source I2 is connected to signal ground. The gate terminal of the 18th transistor Q18 is the first input terminal of the level shifting unit 120 and is connected to the signal input unit 110.

[0071] The second shift module 122 includes: an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a nineteenth transistor Q19, and a twenty-second transistor Q22.

[0072] The source terminal of the eleventh transistor Q11 is connected to the high-bridge power supply voltage terminal VBB, the drain terminal of the eleventh transistor Q11 is connected to the drain terminal of the thirteenth transistor Q13, and the gate terminal of the eleventh transistor Q11 is connected to the signal latch unit 130. The source terminal of the twelfth transistor Q12 is connected to the high-bridge power supply voltage terminal VBB, the drain terminal of the twelfth transistor Q12 is connected to the drain terminal of the fourteenth transistor Q14, and the gate terminal of the twelfth transistor Q12 is connected to the signal latch unit 130. The gate terminal of the thirteenth transistor Q13 is connected to the gate terminal of the twentieth transistor Q20, and the thirteenth transistor Q11... The gate terminal of transistor 3 is the input terminal of the level shifting unit 120. The source terminal of the thirteenth transistor Q13 is connected to the gate terminal of the twentieth transistor Q22. The gate terminal of the fourteenth transistor Q14 is connected to the gate terminal of the thirteenth transistor Q13. The source terminal of the fourteenth transistor Q14 is connected to the gate terminal of the nineteenth transistor Q19. The drain terminal of the nineteenth transistor Q19 is connected to one end of the second constant current source I2. The source terminal of the nineteenth transistor Q19 is connected to signal ground. The drain terminal of the twenty-second transistor Q22 is connected to the other end of the first constant current source I1. The source terminal of the twenty-second transistor Q22 is connected to signal ground.

[0073] Specifically, when a high-level input signal arrives, the seventeenth transistor Q17 and the eighteenth transistor Q18 in the first shift module 121 are turned on, while the twentieth transistor Q20 and the twenty-first transistor Q21 are turned off. When the seventeenth transistor Q17 and the eighteenth transistor Q18 are turned on, the second constant current source I2 is turned on, completing the first stage of conduction. Then, the drain voltage of the seventeenth transistor Q17 gradually decreases, turning on the twelfth transistor Q12, the fourteenth transistor Q14, and the nineteenth transistor Q19 in the second shift module 122. The nineteenth transistor Q19 is turned on, completing the second stage of conduction. This realizes the step-by-step conduction function of the first shift module 121 and the second shift module 122.

[0074] Similarly, when a low-level input signal arrives, the twentieth transistor Q20 and the twenty-first transistor Q21 in the first shift module 121 are turned on, while the seventeenth transistor Q17 and the eighteenth transistor Q18 are turned off. When the twentieth transistor Q20 and the twenty-first transistor Q21 are turned on, the first constant current source I1 is turned on, completing the first stage of conduction. Then, the drain voltage of the twentieth transistor Q20 gradually decreases, turning on the eleventh transistor Q11, the thirteenth transistor Q13, and the twenty-second transistor Q22 in the second shift module 122. The twenty-second transistor Q22 is turned on, completing the second stage of conduction. This achieves the step-by-step conduction function of the first shift module 121 and the second shift module 122. Therefore, the level shifting unit can achieve the function of distributed step-by-step conduction when a switch signal is input.

[0075] In this embodiment of the invention, in order to transmit the high-bridge filtered signal after voltage hysteresis to the high-bridge output unit, the level shifting unit 120 further includes a fifth resistor R5. One end of the fifth resistor R5 is connected to the high-bridge power supply voltage terminal VBB, and the other end of the fifth resistor R5 is connected to the gate terminal of the twelfth transistor Q12 and the drain terminal of the seventeenth transistor Q17.

[0076] Specifically, when a high-level input signal arrives, a current flows through the fifth resistor R5 in the level shift unit 120, generating a voltage drop. When the voltage drop across the fifth resistor R5 gradually increases to the turn-on voltage of the twelfth transistor Q12 and the twenty-fourth transistor Q24, the twelfth transistor Q12 and the twenty-fourth transistor Q24 are turned on, transmitting the high-level signal to the high-bridge output unit. Similarly, when a low-level input signal arrives, the voltage drop across the fifth resistor R5 in the level shift unit 120 decreases. When the voltage drop across the fifth resistor R5 is less than the turn-on voltage of the twelfth transistor Q12 and the twenty-fourth transistor Q24, the twelfth transistor Q12 and the twenty-fourth transistor Q24 are turned off, transmitting the low-level signal to the high-bridge output unit.

[0077] In addition, to accelerate the switching speed of the nineteenth transistor Q19 and the twenty-second transistor Q22, the level shifting unit 120 further includes a fifteenth transistor Q15 and a sixteenth transistor Q16. The gate of the fifteenth transistor Q15 is connected to the drain of the sixteenth transistor Q16, the source of the fifteenth transistor Q15 is connected to signal ground, the drain of the fifteenth transistor Q15 is connected to the source of the thirteenth transistor Q13 and the gate of the twenty-second transistor Q22, the gate of the sixteenth transistor Q16 is connected to the drain of the fifteenth transistor Q15, the source of the sixteenth transistor Q16 is connected to signal ground, and the drain of the sixteenth transistor Q16 is connected to the source of the fourteenth transistor Q14 and the gate of the nineteenth transistor Q19.

[0078] Specifically, when a high-level input signal arrives, the drain potential of the sixteenth transistor Q16 is raised, and the gate potential of the fifteenth transistor Q15 is also raised simultaneously, turning it on. The turning on of the fifteenth transistor Q15 then pulls down its own drain potential, thereby simultaneously pulling down the gate potential of the sixteenth transistor Q16, further turning it off. Therefore, the drain potential of the sixteenth transistor Q16 is further raised, creating a positive feedback effect, thus accelerating the switching function. Similarly, when a low-level input signal arrives, the drain potential of the fifteenth transistor Q15 is raised, and the gate potential of the sixteenth transistor Q16 is also raised simultaneously, turning it on. The turning on of the sixteenth transistor Q16 then pulls down its own drain potential, thereby simultaneously pulling down the gate potential of the fifteenth transistor Q15, further turning it off. Therefore, the drain potential of the fifteenth transistor Q15 is further raised, also creating a positive feedback effect, thus accelerating the switching function.

[0079] It should be noted that, in the embodiments of the present invention, the eleventh transistor Q11 and the twelfth transistor Q12 can specifically be P-type MOS transistors, and the thirteenth transistor Q13 to the twenty-second transistor Q22 can specifically be N-type MOS transistors.

[0080] In embodiments of the present invention, such as Figure 4 As shown, the signal latch unit 130 includes: a twenty-third transistor Q23, a twenty-fourth transistor Q24, a twenty-fifth transistor Q25, and a twenty-sixth transistor Q26.

[0081] The drain terminal of the 23rd transistor Q23 is connected to both the level shifting unit 120 and the gate terminal of the 24th transistor Q24. The source terminal of the 23rd transistor Q23 is connected to the high-bridge power supply voltage terminal VBB. The gate terminal of the 23rd transistor Q23 is connected to the drain terminal of the 24th transistor Q24.

[0082] The source terminal of the 24th transistor Q24 is connected to the high-bridge power supply voltage terminal VBB, and the drain terminal of the 24th transistor Q24 is connected to the level shifting unit 120.

[0083] The drain terminal of the 25th transistor Q25 is connected to the drain terminal of the 23rd transistor Q23, the source terminal of the 25th transistor Q25 is connected to the floating island terminal VS of the high-bridge output unit 150, and the gate terminal of the 25th transistor Q25 is connected to the drain terminal of the 26th transistor Q26.

[0084] The gate of the 26th transistor Q26 is connected to the drain of the 25th transistor Q25, the drain of the 26th transistor Q26 is connected to the drain of the 24th transistor Q24, and the source of the 26th transistor Q26 is connected to the floating island terminal VS of the high-bridge output unit 150.

[0085] It should be understood that the 23rd transistor Q23 to the 26th transistor Q26 together form a positive feedback latch structure, which has the effects of voltage hysteresis and accelerated level switching. This prevents the dv / dt interference noise of the floating island terminal VS from interrupting the current transmission signal state, thus better eliminating the influence of dv / dt interference noise brought by the floating island terminal.

[0086] It should be noted that, in the embodiments of the present invention, the twenty-third transistor Q23 and the twenty-fourth transistor Q24 can be P-type MOS transistors, and the twenty-fifth transistor Q25 and the twenty-sixth transistor Q26 can be N-type MOS transistors.

[0087] In this embodiment of the invention, in order to prevent damage to the devices caused by the simultaneous on / off state of the high-bridge external switching device and the low-bridge external switching device, such as... Figure 5 As shown, the high-voltage gate drive circuit 100 further includes a delay matching unit 160. The input terminal of the delay matching unit 160 is connected to the output terminal of the signal input unit 110, and the output terminal of the delay matching unit 160 is connected to the input terminal of the low-bridge output unit 140.

[0088] The delay matching unit 160 is used to adjust the dead time of the high bridge output signal and the low bridge output signal.

[0089] Specifically, such as Figure 4 As shown, the delay matching unit 160 includes: a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, a second resistor R2, a third resistor R3, and a second capacitor C2.

[0090] The gate terminal of the seventh transistor Q7 is connected to the gate terminal of the eighth transistor Q8, and both are connected to the output terminal of the signal input unit 110.

[0091] The source terminal of the seventh transistor Q7 is connected to the low-bridge power supply voltage terminal VCC. The drain terminal of the seventh transistor Q7 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the drain terminal of the eighth transistor Q8. The source terminal of the eighth transistor Q8 is connected to signal ground.

[0092] One end of the second capacitor C2 is connected to the other end of the second resistor R2, and the other end of the second capacitor C2 is connected to signal ground;

[0093] The gate of the ninth transistor Q9 is connected to the gate of the tenth transistor Q10, and both are connected to one end of the second capacitor C2. The source of the ninth transistor Q9 is connected to the low-bridge power supply voltage terminal, and the drain of the ninth transistor Q9 is connected to the drain of the tenth transistor Q10, and both are connected to the input of the low-bridge output unit 140. The source of the tenth transistor Q10 is connected to signal ground.

[0094] Specifically, in the delay matching unit 160, the seventh transistor Q7 and the eighth transistor Q8 function as a switch, while the ninth transistor Q9 and the tenth transistor Q10 form a digital inverter with a switching level of 0.5*VCC, equivalent to a simple voltage comparator. When a high-level input signal arrives, the eighth transistor Q8 is turned off, and the seventh transistor Q7 is turned on. The low-bridge power supply VCC charges the second capacitor C2 through the second resistor R2. When the voltage on the upper plate of the second capacitor C2 rises from 0 to above 0.5*VCC, the digital inverter formed by the ninth transistor Q9 and the tenth transistor Q10 outputs a low level. When a low-level input signal arrives, the seventh transistor Q7 is turned off, and the eighth transistor Q8 is turned on, discharging the second capacitor C2 through the third resistor R3. When the voltage on the upper plate of the second capacitor C2 drops from VCC to below VCC, the voltage on the second capacitor C2 discharges. At 0.5*VCC, the digital inverter composed of the ninth transistor Q9 and the tenth transistor Q10 outputs a high level. Therefore, the charging / discharging speed of the second capacitor C2 can be controlled by adjusting the resistance values ​​of the second resistor R2 and the third resistor R3, thereby adjusting the charging / discharging time. The charging / discharging time is positively correlated with the dead time. Therefore, the larger the resistance values ​​of the second resistor R2 and the third resistor R3, the longer the charging / discharging time and the longer the dead time. Similarly, the smaller the resistance values ​​of the second resistor R2 and the third resistor R3, the shorter the charging / discharging time and the shorter the dead time.

[0095] Therefore, in this embodiment of the invention, the dead time of the high / low bridge output terminals HO / LO is adjusted by the resistance values ​​of the second resistor R2 and the third resistor R3. Increasing the resistance values ​​of the second resistor R2 and the third resistor R3 lengthens the dead time of the high / low bridge output terminals HO / LO, while decreasing the resistance values ​​of the second resistor R2 and the third resistor R3 shortens the dead time of the high / low bridge output terminals HO / LO. Based on this adjustment method, the dead time can be adjusted to prevent damage to external switching devices.

[0096] It should be noted that, in the embodiments of the present invention, the seventh transistor Q7 and the ninth transistor Q9 can be P-type MOS transistors, and the eighth transistor Q8 and the tenth transistor Q10 can be N-type MOS transistors.

[0097] In this embodiment of the invention, in order to reduce the production cost of the device, such as Figure 5As shown, the high-voltage gate drive circuit 100 further includes a voltage clamping unit 170, which is connected to the level shifting unit 120. The voltage clamping unit 170 is used to convert the high voltage in the high-bridge filtered signal in the level shifting unit 120 into a low voltage.

[0098] Specifically, such as Figure 4 As shown, the voltage clamping unit 170 includes a fourth resistor R4 and a Zener diode Vz. One end of the fourth resistor R4 is connected to the high-bridge power supply voltage terminal VBB, and the other end of the fourth resistor R4 is connected to the cathode of the Zener diode Vz. The anode of the Zener diode Vz is connected to signal ground.

[0099] It should be understood that the voltage clamping unit 170 can convert the high voltage in the high-bridge filter signal in the level shifting unit 120 into a low voltage, thereby achieving a voltage reduction clamping effect, which can replace the high-voltage device connected to it with a low-voltage device, thereby reducing the device production cost.

[0100] In embodiments of the present invention, such as Figure 4 As shown, the signal input unit 110 includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a first resistor R1, and a first capacitor C1.

[0101] The gate of the first transistor Q1 is connected to the gate of the second transistor Q2, and both are input terminals of the signal input unit 110; the source terminal of the first transistor Q1 is connected to the low bridge power supply voltage terminal VCC; the drain terminal of the first transistor Q1 is connected to the drain terminal of the second transistor Q2, and both are connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to signal ground; the source terminal of the second transistor Q2 is connected to signal ground.

[0102] The gate of the third transistor Q3 is connected to the gate of the fourth transistor Q4, and both are connected to the other end of the first resistor R1; the source of the third transistor Q3 is connected to the low bridge power supply voltage terminal VCC; the drain of the third transistor Q3 is connected to the drain of the fourth transistor Q4, and both are connected to the first input terminal of the level shifting unit 120; the source of the fourth transistor Q4 is connected to signal ground.

[0103] The gate of the fifth transistor Q5 is connected to the gate of the sixth transistor Q6, and both are connected to the first input terminal of the level shifting unit 120; the source terminal of the fifth transistor Q5 is connected to the low bridge power supply voltage terminal VCC; the drain terminal of the fifth transistor Q5 is connected to the drain terminal of the sixth transistor Q6, both of which are output terminals of the signal input unit 110, and both are connected to the second input terminal of the level shifting unit 120; the source terminal of the sixth transistor Q6 is connected to signal ground.

[0104] In this embodiment of the invention, the first input terminal of the level shifting unit 120 can specifically be the gate terminal of the eighteenth transistor Q18, and the second input terminal of the level shifting unit 120 can specifically be the gate terminal of the twenty-first transistor Q21.

[0105] In this embodiment of the invention, the first resistor R1 and the first capacitor C1 together constitute a low-pass filter, which can effectively filter out high-frequency interference noise in the input signal.

[0106] It should be understood that the structures of the first transistor Q1 and the second transistor Q2, the third transistor Q3 and the fourth transistor Q4, and the fifth transistor Q5 and the sixth transistor Q6 all serve to invert the signal in the signal input unit, that is, they all constitute the inverter of the signal input unit.

[0107] It should be noted that, in the embodiments of the present invention, the first transistor Q1, the third transistor Q3 and the fifth transistor Q5 can be P-type MOS transistors, and the second transistor Q2, the fourth transistor Q4 and the sixth transistor Q6 can be N-type MOS transistors.

[0108] In embodiments of the present invention, such as Figure 4 As shown, the low-bridge output unit 140 includes: a thirty-first transistor Q31, a thirty-second transistor Q32, a thirty-third transistor Q33, and a thirty-fourth transistor Q34.

[0109] The gate terminal of the thirty-first transistor Q31 is connected to the gate terminal of the thirty-second transistor Q32, and both are input terminals of the low-bridge output unit 140. The source terminal of the thirty-first transistor Q31 is connected to the low-bridge power supply voltage terminal VCC, the drain terminal of the thirty-first transistor Q31 is connected to the drain terminal of the thirty-second transistor Q32, and the source terminal of the thirty-second transistor Q32 is connected to signal ground.

[0110] The gate of the thirty-third transistor Q33 is connected to the gate of the thirty-fourth transistor Q34, and both are connected to the drain of the thirty-first transistor Q31 and the drain of the thirty-second transistor Q32; the source of the thirty-third transistor Q33 is connected to the low-bridge power supply voltage terminal VCC; the drain of the thirty-third transistor Q33 is connected to the drain of the thirty-fourth transistor Q34, and both are output terminals of the low-bridge output unit 140; the source of the thirty-fourth transistor Q34 is connected to signal ground.

[0111] The high-bridge output unit 150 includes: the twenty-seventh transistor Q27, the twenty-eighth transistor Q28, the twenty-ninth transistor Q29, and the thirtieth transistor Q30.

[0112] The gate of the 27th transistor Q27 is connected to the gate of the 28th transistor Q28, and both are input terminals of the high-bridge output unit 150; the source terminal of the 27th transistor Q27 is connected to the high-bridge power supply voltage terminal VBB; the drain terminal of the 27th transistor Q27 is connected to the drain terminal of the 28th transistor Q28; the source terminal of the 28th transistor Q28 is connected to the floating island terminal VS of the high-bridge output unit 150.

[0113] The gate of the 29th transistor Q29 is connected to the gate of the 30th transistor Q30, and both are connected to the drain of the 27th transistor Q27 and the drain of the 28th transistor Q28; the source of the 29th transistor Q29 is connected to the high-bridge power supply voltage terminal VBB; the drain of the 29th transistor Q29 is connected to the drain of the 30th transistor Q30, and both are output terminals of the high-bridge output unit 150; the source of the 30th transistor Q30 is connected to the floating island terminal VS of the high-bridge output unit 150.

[0114] It should be understood that, in the embodiments of the present invention, the four transistors, from the thirty-first transistor Q31 to the thirty-fourth transistor Q34, together constitute a digital buffer structure, which enhances the driving capability of the low-bridge output port; and the four transistors, from the twenty-seventh transistor Q27 to the thirtieth transistor Q30, together constitute a digital buffer structure, which enhances the driving capability of the high-bridge output port.

[0115] It should be noted that, in the embodiments of the present invention, the 27th transistor Q27, the 29th transistor Q29, the 31st transistor Q31 and the 33rd transistor Q33 can specifically be P-type MOS transistors, and the 28th transistor Q28, the 30th transistor Q30, the 32nd transistor Q32 and the 34th transistor Q34 can specifically be N-type MOS transistors.

[0116] The following is combined Figure 6 The specific application embodiments shown illustrate the working principle of the high-voltage gate drive circuit of the present invention in detail. For example... Figure 6 As shown, this is a high-voltage drive device that uses a high-voltage gate drive circuit. Its purpose is to transmit the signal from the low-bridge input terminal to the high / low-bridge output terminal to drive the external high-voltage switching device.

[0117] In this embodiment of the invention, the input signal of the low-bridge input terminal IN is a square wave signal, and the low-bridge power supply voltage terminal VCC = 5V. Simultaneously, the VCC terminal is connected to the high-bridge power supply voltage terminal VBB through diode D1. The output terminal HO of the high-bridge output unit 150 is connected to the gate terminal of the external switching device NM1, and the output terminal LO of the low-bridge output unit 140 is connected to the gate terminal of the external switching device NM2. The upper plate of the bootstrap capacitor Cbs is connected to the high-bridge power supply voltage terminal VBB, and the lower plate is connected to the floating island terminal VS of the high-bridge output unit 150. The drain terminal of the switching device NM1 is connected to the external high-voltage power supply terminal HV, where HV = 50V, and its source terminal is connected to the drain terminal of the switching device NM2. The source terminal of the switching device NM2 is connected to signal ground. The output terminal OUT of the high-voltage drive device is coupled to the common connection terminal of NM1 and NM2.

[0118] In this embodiment, when the input signal at the low-bridge input terminal IN is high, the output terminal HO of the high-bridge output unit 150 outputs a high level, which is in phase with the input signal, and the output terminal LO of the low-bridge output unit 140 outputs a low level, which is out of phase with the input signal. At this time, the output terminal OUT of the high-voltage drive device outputs a high level, and its high-level voltage is 50V. Similarly, when the input signal at the low-bridge input terminal IN is low, the output terminal HO of the high-bridge output unit 150 outputs a low level, and the output terminal LO of the low-bridge output unit 140 outputs a high level. At this time, the output terminal OUT of the high-voltage drive device outputs a low level, and its low-level voltage is 0V.

[0119] In this embodiment, when a square wave signal is input to the low-bridge input terminal IN, its waveform is as follows: Figure 7As shown, when the input signal at the low-bridge input terminal IN is low, the output terminal HO of the high-bridge output unit 150 outputs a low level, and the output terminal LO of the low-bridge output unit 140 outputs a high level. At this time, its high-level voltage is 5V. External switching devices NM1 are closed, NM2 is open, the output terminal OUT of the high-voltage drive device outputs a low level, and the bootstrap capacitor Cbs is charged to 5V through the low-bridge power supply voltage terminal VCC and diode D1. When the input signal at the low-bridge input terminal IN is high, the output terminal HO of the high-bridge output unit 150 outputs a high level, and the output terminal LO of the low-bridge output unit 140 outputs a low level. Normally, at this time, its external switching device NM1 is open and NM2 is closed. The output terminal OUT of the high-voltage drive device outputs a high level, and its high-level voltage is 50V. The voltage of the bootstrap capacitor Cbs cannot change abruptly and remains at 5V. The voltage of the high-bridge power supply voltage terminal VBB is the sum of the voltage of the floating island terminal VS and the voltage on the bootstrap capacitor Cbs. Since the floating island terminal VS of the high-voltage drive device is connected to the output terminal OUT of the high-voltage drive device, their voltages are the same. Therefore, the voltage of the high-bridge power supply voltage terminal VBB is 55V at this time. So the high-level voltage output by the output terminal HO of the high-bridge output unit 150 is also 55V.

[0120] In this embodiment of the invention, the dead time of the output terminals HO / LO of the high / low bridge is adjusted by setting the resistance values ​​of the second resistor R2 and the third resistor R3. Increasing the resistance values ​​of the second resistor R2 and the third resistor R3 can lengthen the dead time of the output terminals HO / LO of the high / low bridge, while decreasing the resistance values ​​of the second resistor R2 and the third resistor R3 can shorten the dead time of the output terminals HO / LO of the high / low bridge.

[0121] In this embodiment of the invention, the first constant current source I1 and the second constant current source I2 are turned on before the twenty-second transistor Q22 and the nineteenth transistor Q19, forming a step-by-step turn-on, reducing the instantaneous large current surge of the transistors, improving the SOA performance of the transistors, and enhancing the reliability of the device. Simultaneously, due to the function of the signal latch unit, the dv / dt interference noise of the floating island terminal VS cannot interrupt the current transmission signal state, thus better eliminating the influence of dv / dt interference noise from the floating island terminal.

[0122] In this embodiment of the invention, due to the voltage clamping effect of the voltage clamping unit, the high voltage is converted into a low voltage, so the high voltage device connected to it can be replaced with a low voltage device, thereby reducing the device production cost.

[0123] In this embodiment of the invention, both the high-bridge output unit and the low-bridge output unit adopt a digital buffer structure, which enhances the driving capability of the high / low bridge output ports and can better drive external switching devices.

[0124] Therefore, by simply connecting an external signal source to the signal input port of this invention, the signal input unit in the high-voltage gate drive circuit provided by this invention will automatically filter the input signal, and then transmit the signal accurately to the high-bridge output unit after passing through the level shifting unit and the signal latching unit. Finally, the high-bridge output unit enhances its driving capability to drive the high-bridge external switching device. At the same time, the filtered signal is first input to the delay matching unit, and then transmitted to the low-bridge output unit. Finally, the low-bridge output unit enhances its driving capability to drive the low-bridge external switching device. The output signal of the high-bridge output terminal is out of phase with the output signal of the low-bridge output terminal, and its dead time is adjusted by the delay matching unit, which can prevent the external switching device from being damaged by switching.

[0125] In summary, the high-voltage gate drive circuit provided by this invention can not only effectively transmit the signal from the low-bridge input terminal to the high / low-bridge output terminal to drive the external switching device, but also eliminate the dv / dt interference noise caused by the floating island terminal. At the same time, the circuit cleverly uses a voltage clamping unit to replace some high-voltage devices with low-voltage devices, reducing costs. Therefore, the high-voltage gate drive circuit provided by this invention not only has accurate transmission of input signals and strong anti-interference function, but also has the characteristics of simple structure, low cost, and high reliability.

[0126] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A high voltage gate drive circuit, characterized by, include: The system includes a signal input unit, a level shifting unit, a signal latching unit, a low-bridge output unit, and a high-bridge output unit. The signal input unit is connected to the level shifting unit and the low-bridge output unit, the signal latching unit is connected to the level shifting unit, and the high-bridge output unit is connected to the signal latching unit. The signal input unit is used to filter the input signal to obtain a filtered signal. The low-bridge output unit is used to enhance the filtered signal with low-bridge drive to obtain a low-bridge output signal, and the low-bridge output signal is used to drive the switching action of the low-bridge external switching device. The level shifting unit is used to transmit the filtered signal based on the step-by-step conduction function to obtain the high-bridge filtered signal. The step-by-step conduction function is that the two shifting modules in the level shifting unit are turned on at different times to realize the step-by-step transmission of the filtered signal. The signal latching unit is used to perform voltage hysteresis processing on the high-bridge filtered signal to obtain the high-bridge filtered signal after voltage hysteresis. The high-bridge output unit is used to enhance the high-bridge filtered signal after voltage hysteresis to obtain a high-bridge output signal, and the high-bridge output signal is used to drive the switching action of the external high-bridge switching device. The high-bridge output signal and the low-bridge output signal are out of phase. The level shifting unit includes a first shift module and a second shift module, wherein the first shift module is connected to the second shift module. The first shift module is used to turn on at a first moment to transmit the filtered signal to the second shift module; The second shift module is used to be turned on at a second time to transmit the filtered signal and obtain the high-bridge filtered signal, wherein there is a time difference between the second time and the first time, and the second time is later than the first time; The first shift module includes: a first constant current source, a second constant current source, a seventeenth transistor, an eighteenth transistor, a twentieth transistor, and a twenty-first transistor. One end of the first constant current source is connected to signal ground, and the other end of the first constant current source is connected to the source terminal of the 21st transistor. The drain terminal of the 21st transistor is connected to the source terminal of the 20th transistor. The gate terminal of the 21st transistor is the second input terminal of the level shifting unit and is connected to the signal input unit. The drain terminal of the 20th transistor is connected to the signal latching unit. The gate terminal of the 20th transistor is connected to the gate terminal of the 17th transistor. The drain terminal of the 17th transistor is connected to the signal latching unit. The source terminal of the 17th transistor is connected to the drain terminal of the 18th transistor. The source terminal of the 18th transistor is connected to one end of the second constant current source. The other end of the second constant current source is connected to signal ground. The gate terminal of the 18th transistor is the first input terminal of the level shifting unit and is connected to the signal input unit. The second shift module includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a nineteenth transistor, and a twenty-second transistor. The source terminal of the eleventh transistor is connected to the high-bridge power supply voltage terminal, the drain terminal of the eleventh transistor is connected to the drain terminal of the thirteenth transistor, and the gate terminal of the eleventh transistor is connected to the signal latch unit. The source terminal of the twelfth transistor is connected to the high-bridge power supply voltage terminal, the drain terminal of the twelfth transistor is connected to the drain terminal of the fourteenth transistor, and the gate terminal of the twelfth transistor is connected to the signal latch unit. The gate terminal of the thirteenth transistor is connected to the gate terminal of the twentieth transistor, and the gate terminal of the thirteenth transistor is the input terminal of the level shift unit. The source terminal of the thirteenth transistor is connected to the gate terminal of the twentieth transistor, the gate terminal of the fourteenth transistor is connected to the gate terminal of the thirteenth transistor, the source terminal of the fourteenth transistor is connected to the gate terminal of the nineteenth transistor, the drain terminal of the nineteenth transistor is connected to one end of the second constant current source, and the source terminal of the nineteenth transistor is connected to signal ground. The drain terminal of the twenty-second transistor is connected to the other end of the first constant current source, and the source terminal of the twenty-second transistor is connected to signal ground.

2. The high voltage gate drive circuit of claim 1, wherein, The signal latch unit includes: a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a twenty-sixth transistor. The drain terminal of the 23rd transistor is connected to both the level shifting unit and the gate terminal of the 24th transistor. The source terminal of the 23rd transistor is connected to the high-bridge power supply voltage terminal, and the gate terminal of the 23rd transistor is connected to the drain terminal of the 24th transistor. The source terminal of the 24th transistor is connected to the high-bridge power supply voltage terminal, and the drain terminal of the 24th transistor is connected to the level shifting unit. The drain terminal of the 25th transistor is connected to the drain terminal of the 23rd transistor, the source terminal of the 25th transistor is connected to the floating island terminal of the high-bridge output unit, and the gate terminal of the 25th transistor is connected to the drain terminal of the 26th transistor. The gate of the 26th transistor is connected to the drain of the 25th transistor, the drain of the 26th transistor is connected to the drain of the 24th transistor, and the source of the 26th transistor is connected to the floating island of the high-bridge output unit.

3. The high voltage gate drive circuit of claim 1, wherein, The high-voltage gate drive circuit further includes a delay matching unit, the input terminal of which is connected to the output terminal of the signal input unit, and the output terminal of which is connected to the input terminal of the low-bridge output unit. The delay matching unit is used to adjust the dead time of the high-bridge output signal and the low-bridge output signal.

4. The high voltage gate drive circuit of claim 3, wherein, The delay matching unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a second resistor, a third resistor, and a second capacitor; The gate terminal of the seventh transistor is connected to the gate terminal of the eighth transistor, and both are connected to the output terminal of the signal input unit. The source terminal of the seventh transistor is connected to the low-bridge power supply voltage terminal, the drain terminal of the seventh transistor is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the third resistor, the other end of the third resistor is connected to the drain terminal of the eighth transistor, and the source terminal of the eighth transistor is connected to signal ground. One end of the second capacitor is connected to the other end of the second resistor, and the other end of the second capacitor is connected to signal ground; The gate terminal of the ninth transistor is connected to the gate terminal of the tenth transistor, and both are connected to one end of the second capacitor. The source terminal of the ninth transistor is connected to the low-bridge power supply voltage terminal, and the drain terminal of the ninth transistor is connected to the drain terminal of the tenth transistor, and both are connected to the input terminal of the low-bridge output unit. The source terminal of the tenth transistor is connected to signal ground.

5. The high voltage gate drive circuit of claim 1, wherein, The high-voltage gate drive circuit further includes a voltage clamping unit, which is connected to the level shifting unit. The voltage clamping unit is used to convert the high voltage in the high-bridge filtered signal of the level shifting unit into a low voltage.

6. The high voltage gate drive circuit of claim 5, wherein, The voltage clamping unit includes a fourth resistor and a Zener diode. One end of the fourth resistor is connected to the high-bridge power supply voltage terminal, and the other end of the fourth resistor is connected to the cathode of the Zener diode. The anode of the Zener diode is connected to signal ground.

7. The high voltage gate drive circuit of claim 1, wherein, The signal input unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, and a first capacitor. The gate terminal of the first transistor is connected to the gate terminal of the second transistor, and both are input terminals of the signal input unit; the source terminal of the first transistor is connected to the low bridge power supply voltage terminal; the drain terminal of the first transistor is connected to the drain terminal of the second transistor, and both are connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to signal ground; the source terminal of the second transistor is connected to signal ground. The gate of the third transistor is connected to the gate of the fourth transistor, and both are connected to the other end of the first resistor; the source of the third transistor is connected to the low bridge power supply voltage terminal; the drain of the third transistor is connected to the drain of the fourth transistor, and both are connected to the first input terminal of the level shifting unit; the source of the fourth transistor is connected to signal ground. The gate terminal of the fifth transistor is connected to the gate terminal of the sixth transistor, and both are connected to the first input terminal of the level shifting unit; the source terminal of the fifth transistor is connected to the low bridge power supply voltage terminal; the drain terminal of the fifth transistor is connected to the drain terminal of the sixth transistor, both of which are output terminals of the signal input unit, and both are connected to the second input terminal of the level shifting unit; the source terminal of the sixth transistor is connected to signal ground.

8. The high voltage gate drive circuit of claim 1, wherein, The low-bridge output unit includes: transistors 31, 32, 33, and 34. The gate terminal of the thirty-first transistor is connected to the gate terminal of the thirty-second transistor, and both are input terminals of the low-bridge output unit. The source terminal of the thirty-first transistor is connected to the low-bridge power supply voltage terminal, the drain terminal of the thirty-first transistor is connected to the drain terminal of the thirty-second transistor, and the source terminal of the thirty-second transistor is connected to signal ground. The gate terminal of the thirty-third transistor is connected to the gate terminal of the thirty-fourth transistor, and both are connected to the drain terminals of the thirty-first transistor and the thirty-second transistor; the source terminal of the thirty-third transistor is connected to the low-bridge power supply voltage terminal; the drain terminal of the thirty-third transistor is connected to the drain terminal of the thirty-fourth transistor, and both are output terminals of the low-bridge output unit; the source terminal of the thirty-fourth transistor is connected to signal ground. The high-bridge output unit includes: the twenty-seventh transistor, the twenty-eighth transistor, the twenty-ninth transistor, and the thirtieth transistor. The gate terminal of the 27th transistor is connected to the gate terminal of the 28th transistor, and both are input terminals of the high-bridge output unit; the source terminal of the 27th transistor is connected to the high-bridge power supply voltage terminal; the drain terminal of the 27th transistor is connected to the drain terminal of the 28th transistor; the source terminal of the 28th transistor is connected to the floating island terminal of the high-bridge output unit. The gate terminal of the 29th transistor is connected to the gate terminal of the 30th transistor, and both are connected to the drain terminals of the 27th transistor and the 28th transistor; the source terminal of the 29th transistor is connected to the high-bridge power supply voltage terminal; the drain terminal of the 29th transistor is connected to the drain terminal of the 30th transistor, and both are output terminals of the high-bridge output unit; the source terminal of the 30th transistor is connected to the floating island terminal of the high-bridge output unit.

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