1T-2B code conversion circuit based on memristor

Abstract

The invention discloses a 1T-2B code conversion circuit based on a memristor, and belongs to the technical field of memristors. Comprising memristors, excitation voltage sources V, a transistor and a direct-current voltage source, the memristors are a three-value input memristor Min and a two-value output memristor Mout, and the number of the excitation voltage sources is six, namely V0, V1, V2, V3, V4 and V5; the memristors are respectively M0, M1, M2, M3, M4 and M5; the transistors are respectively T0, T1, T2, T3, T4 and T5; the direct current voltage sources are Vdd0, Vdd1, Vdd2, Vdd3, Vdd4 and Vdd5 respectively; the invention designs a 1T-2B code conversion circuit based on a memristor. The design shows remarkable advantages in a memristor storage and communication system: multiplication of storage density, improvement of data transmission rate and enhancement of anti-interference capability are realized, and key technical support is provided for a next-generation high-efficiency computing and communication system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memristor, and particularly relates to a 1T-2B encoding conversion circuit based on a memristor. BACKGROUND

[0002] With the rapid development of big data and artificial intelligence technology, the demand for data storage density and operation efficiency is growing exponentially, and the traditional binary logic system is facing the bottleneck of waste of storage resources and limited data transmission rate. Multi-value logic technology has become a key direction to break through the bottleneck because a single cell can carry more information, and three-value logic has great potential in high-density storage and high-speed communication fields due to its advantages of balancing information density and circuit complexity. However, the current three-value logic system is incompatible with the mainstream binary processing architecture, and data interaction needs to be realized through encoding conversion. Existing conversion schemes mostly rely on traditional CMOS circuits, which have defects such as high power consumption, low integration, and weak anti-interference ability. At the same time, the traditional von Neumann architecture separates storage and operation, which increases the data transfer delay and further restricts the performance improvement of the system. As a new type of non-volatile memory device, the memristor has characteristics such as adjustable resistance state, low power consumption, and high integration, and can realize the integration of storage and operation, providing a new path for multi-value-binary conversion. However, existing memristor-based conversion circuits mostly focus on simple logic operations, lack of special circuit design for 1T-2B encoding, and have problems such as complex conversion process and insufficient stability, which are difficult to meet the actual needs of high-performance computing and communication systems. Therefore, it is an urgent need to develop a new type of 1T-2B encoding conversion circuit based on a memristor to realize the multiplication of storage density, the improvement of transmission rate, and the enhancement of anti-interference ability, and to promote the development of the next generation of computing and communication technology. SUMMARY

[0003] The purpose of the present application is to realize efficient conversion of three-value input signals to binary output signals, to achieve the goals of multiplying storage density, improving data transmission rate, and enhancing anti-interference ability under the premise of ensuring the accuracy of conversion logic, and to meet the core needs of high-performance computing and communication systems for encoding conversion. Another purpose of the present application is to ensure that the circuit can stably reproduce the logic relationship corresponding to the truth table, and has compatibility with existing memristor manufacturing processes, providing a practical technical solution for the practical application of the circuit in the fields of multi-value digital logic operation, artificial intelligence acceleration computing, high-density data storage, and high-speed communication.

[0004] Technical scheme: A 1T-2B encoding conversion circuit based on a memristor, comprising a memristor, an excitation voltage source V, a transistor, and a direct current voltage source, wherein the memristor is a three-value input memristor M in and a binary output memristor M out, the number of the excitation voltage sources is six, which are V0, V1, V2, V3, V4, V5 respectively; the memristors are M0, M1, M2, M3, M4, M5 respectively; the transistors are T0, T1, T2, T3, T4, T5 respectively; the direct current voltage sources are V dd0 , V dd1 , V dd2 , V dd3 , V dd4 , V dd5 .

[0005] Further, the initial resistance state of the output binary memristor of the three-value to binary circuit is R H , and the working process of the circuit is divided into two stages, which is driven by the excitation voltage source V, the first stage is the initial stage (0-10 ms), V outputs a smaller initial voltage V Init =0.5V to obtain the initial resistance state of the memristor.

[0006] Further, the second stage is the running stage (10-20 ms), V outputs a larger running voltage V Run =1.5V, the high and low resistance values R H and R L of the input three-value memristor are converted into the high and low resistance values R H and R L of the output binary memristor, that is, when the resistance value of the input three-value memristor is R H , the resistance value of the output binary memristor is converted into R H , when the resistance value of the input three-value memristor is R L , the resistance value of the output binary memristor is converted into R L , and the logic operation is completed.

[0007] Further, at 0-1 ms, V0=V1=V2=V3=V4=V5=0.5V is set, the gate output of T0, T1, T2, T3, T4 and T5 outputs a conductive voltage V DD， , so that all transistors are turned on, and the initial state of all memristors in the array is detected. At 1-2 ms, V0=V1=2.15V is set, the gate output of T0, T1 and T2 outputs a conductive voltage V DD， , so that the corresponding transistors are turned on, and the result of the negative three-value non-operation of M0 is stored in M2.

[0008] Further, at 2-3 ms, V0=V1=1.8V is set, the gate output of T0, T1 and T3 outputs a conductive voltage V DD， , so that the corresponding transistors are turned on, and the result of the positive three-value non-operation of M0 is stored in M3.

[0009] Further, at 3-4 ms, V4=1.5V is set, the gate output of T2 and T4 is set to turn on the voltage V DD， The corresponding transistor is turned on, and the result of the ternary-to-binary operation of M2 is stored in M4, that is, the output B0. At 4-5 ms, V5=1.5V is set, and the gate output of T3 and T5 is set to turn on the voltage V DD， The corresponding transistor is turned on, and the result of the ternary-to-binary operation of M3 is stored in M5, that is, the output B1. Thus, the logic operation of 1T-2B encoding conversion is realized.

[0010] Beneficial effects: The application designs a 1T-2B encoding conversion circuit based on a memristor. The design has significant advantages in a memristor storage and communication system: the storage density is doubled, the data transmission rate is improved, and the anti-interference ability is enhanced, which provides key technical support for the next generation of high-efficiency computing and communication systems. With the continuous maturity of the manufacturing process of the memristor, the circuit model is expected to be widely used in multi-value digital logic operation, artificial intelligence acceleration calculation, high-density data storage, high-speed communication and other frontier fields, and has important research value and broad application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a ternary-to-binary circuit of the application; Figure 2 is a 1T-2B encoding conversion circuit of the application; Figure 3 is a LTSpice simulation result graph of the circuit when the input is "0"; Figure 4 is a LTSpice simulation result graph of the circuit when the input is "1"; Figure 5 is a LTSpice simulation result graph of the circuit when the input is "2". DETAILED DESCRIPTION

[0012] In order to make the technical scheme of the application clearer, the application will be further described in detail below in combination with the drawings and specific embodiments.

[0013] EMBODIMENT In order to make the technical scheme of the application clearer, the application will be further described in detail below in combination with the drawings and specific embodiments.

[0014] The binary memristor used in the application is a voltage-controlled threshold type binary memristor, and its two threshold voltages are v th1 =-0.8V and v th2 =1.3V, and the high and low resistances R H and R L1000kΩ and 10kΩ respectively. The resistance switching conditions of the binary memristor are as follows: (1) R L Switching and maintaining conditions: when the initial state of the memristor is R H , if the voltage applied to the two ends of the memristor is v>1.3V, the resistance of the memristor will switch to R L . When the initial state of the memristor is R L , as long as the voltage v> -0.8V is ensured at the two ends of the memristor, R L remains unchanged.

[0015] (2) R H Switching and maintaining conditions: when the initial state of the memristor is R L , if the voltage applied to the two ends of the memristor is v<-0.8V, the resistance of the memristor will switch to R H . When the initial state of the memristor is R H , as long as the voltage v<1.3V is ensured at the two ends of the memristor, R H remains unchanged.

[0016] The three-value memristor used in the present application is a voltage-controlled threshold type three-value memristor, and the two threshold voltages thereof are v th1 =1.1V and v th2 =1.3V, and the three resistance values R L , R M and R H of the three-value memristor are 10kΩ, 100kΩ and 1000kΩ respectively. The resistance switching conditions of the three-value memristor are as follows: (1) R L Switching and maintaining conditions: when the initial state of the memristor is R H or R M , if the applied voltage v>1.3V, the resistance value will switch to R L . If the initial state of the memristor is R L , as long as v>-1.1V is ensured, R L remains unchanged.

[0017] (2) R M Switching and maintaining conditions: when the memristor switches from R H to R M , the applied voltage needs to satisfy 1.1V<v<1.3V; and when the memristor switches from R L to R M , the corresponding voltage range is -1.3V≤v≤-1.1V. If the initial state of the memristor is R M , as long as the applied voltage is in the interval -1.3V≤v≤1.3V, R MThe state can remain unchanged.

[0018] (3)R H Switching and holding conditions: If the memristor needs to switch from R M Or R L Switch to R H Then the applied voltage should satisfy v < -1.3V. When the memristor's initial state is R H At that time, it is sufficient to maintain R by keeping v ≤ 1.1V. H The state remains unchanged.

[0019] The binary logic described in this invention has two different logic states. The corresponding memristor states are R... H and R L , where R H Represents logic "0"; R L This represents logic "1". Ternary logic has three different logic states. The corresponding memristor states are R... H R M and R L , where R H Represents logic "0"; R M Represents logic "1"; R L It represents the logical "2".

[0020] like Figure 1 As shown, a ternary-to-binary circuit is used. The input is a ternary memristor M. in The negative terminal and the output binary memristor M out The negative terminal is connected, and the output is a binary memristor M. out The positive terminal of the circuit is connected to the positive terminal of the excitation voltage source V, and the negative terminal of the excitation voltage source V is connected to the input three-valued memristor M. in The positive terminal is connected to the ground.

[0021] like Figure 2 As shown, a 1T-2B encoding conversion circuit based on memristors is illustrated. The positive terminals of ternary memristors M0, M1, M2, and M3 are connected to the positive terminals of excitation voltage sources V0, V1, V2, and V3, respectively, while the negative terminals of excitation voltage sources V0, V1, V2, and V3 are grounded. The positive terminals of binary memristors M4 and M5 are connected to the positive terminals of excitation voltage sources V4 and V5, respectively, while the negative terminals of excitation voltage sources V4 and V5 are grounded. The negative terminals of memristors M0, M1, M2, M3, M4, and M5 are connected to the drains of transistors T0, T1, T2, T3, T4, and T5. The sources and substrates of transistors T0, T1, T2, T3, T4, and T5 are all connected together. The gates of transistors T0, T1, T2, T3, T4, and T5 are connected to a DC voltage source V0, T1, T2, T3, T4, and T5, respectively. dd0 V dd1 V dd2 V dd3 Vdd4 , V dd5 , V dd0 , V dd1 , V dd2 , V dd3 , V dd4 , V dd5 , V

[0022] Table 1 1T—2B encoding truth table T [B0] <B1> 0 1 1 1 0 1 2 0 0 The 1T—2B encoding conversion circuit truth table based on the memristor is shown in Table 1, where T represents a three-value input signal, B0 and B1 represent a two-value output signal.

[0023] In the 1T—2B encoding conversion circuit, M0 is an input three-value memristor, M1 is an auxiliary memristor, which assists M0 to perform negative three-value NOT gate operation and positive three-value NOT gate operation, and the initial resistance value is R L , which will not change during operation. M2 is the result of M0 performing negative three-value NOT gate operation, and the initial resistance value is R L . M3 is the result of M0 performing positive three-value NOT gate operation, and the initial resistance value is R L . M4 is the result of M2 performing three-value to two-value operation, and the initial resistance value is R H . M5 is the result of M3 performing three-value to two-value operation, and the initial resistance value is R H At 0-1 ms, set V0=V1=V2=V3=V4=V5=0.5V, and the gate output voltage V DD， of T0, T1, T2, T3, T4 and T5 is set to turn on the corresponding transistor, so that all transistors are turned on, and the initial state of all memristors in the array is detected. According to different inputs, it can be divided into the following three cases: (1) When the input is “0”, that is, the memristor M0=1000kΩ, at 1-2 ms, set V0=V1=2.15V, and the gate output voltage V DD， of T0, T1 and T2 is set to turn on the corresponding transistor, so that M0 performs negative three-value NOT gate operation, and the operation result is R L , that is, logic “2”, which is stored in M2; at 2-3 ms, set V0=V1=1.8V, and the gate output voltage V DD， of T0, T1 and T3 is set to turn on the corresponding transistor, so that M0 performs positive three-value NOT gate operation, and the operation result is R L , that is, logic “2”, which is stored in M3; at 3-4 ms, set V4=1.5V, and the gate output voltage V DD， of T2 and T4 is set to turn on the corresponding transistor, so that M2 performs three-value to two-value operation, and the operation result is R L, stored in M4, i.e. output B0, logic state is "1". At 4-5 ms, set V5=1.5V, the gate output of T3 and T5 is turned on, V DD， , so that the corresponding transistor is turned on, M3 performs a ternary to binary operation, and the operation result is R L , stored in M5, i.e. output B1, logic state is "1".

[0024] (2) When the input is "1", i.e. the memristor M0=100kΩ, at 1-2 ms, set V0=V1=2.15V, the gate output of T0, T1 and T2 is turned on, V DD， , so that the corresponding transistor is turned on, M0 performs a negative ternary NOT gate operation, and the operation result is R H , i.e. logic "0", stored in M2; at 2-3 ms, set V0=V1=1.8V, the gate output of T0, T1 and T3 is turned on, V DD， , so that the corresponding transistor is turned on, M0 performs a positive ternary NOT gate operation, and the operation result is R L , i.e. logic "2", stored in M3; at 3-4 ms, set V4=1.5V, the gate output of T2 and T4 is turned on, V DD， , so that the corresponding transistor is turned on, M2 performs a ternary to binary operation, and the operation result is R H , stored in M4, i.e. output B0, logic state is "0". At 4-5 ms, set V5=1.5V, the gate output of T3 and T5 is turned on, V DD， , so that the corresponding transistor is turned on, M3 performs a ternary to binary operation, and the operation result is R L , stored in M5, i.e. output B1, logic state is "1".

[0025] (3) When the input is "2", i.e. the memristor M0=10kΩ, at 1-2 ms, set V0=V1=2.15V, the gate output of T0, T1 and T2 is turned on, V DD， , so that the corresponding transistor is turned on, M0 performs a negative ternary NOT gate operation, and the operation result is R H , i.e. logic "0", stored in M2; at 2-3 ms, set V0=V1=1.8V, the gate output of T0, T1 and T3 is turned on, V DD， , so that the corresponding transistor is turned on, M0 performs a positive ternary NOT gate operation, and the operation result is R H , i.e. logic "0", stored in M3; at 3-4 ms, set V4=1.5V, the gate output of T2 and T4 is turned on, V DD， , so that the corresponding transistor is turned on, M2 performs a ternary to binary operation, and the operation result is R HThis is stored in M4, i.e., output B0, with a logic state of "0". During 4-5ms, V5 is set to 1.5V, and the gate output turn-on voltage V of T3 and T5 is... DD， This turns on the corresponding transistor, and M3 performs a ternary-to-binary conversion, the result of which is R. H It is stored in M5, i.e., output B1, with a logical state of "0".

[0026] Build in LTSpice Figure 2 The 1T-2B encoding conversion circuit is shown, and the circuit in the array is simulated according to different stages. When the input is "0", that is, M0=1000kΩ, the result is... Figure 3 The simulation results shown show that when the input is "1", i.e., M0 = 100kΩ, the following results are obtained: Figure 4 The simulation results shown, when the input is "2", i.e., M0 = 10kΩ, yield the following results: Figure 5 The simulation results shown are consistent with the theoretical values, which fully verifies the feasibility and effectiveness of the 1T-2B encoding conversion circuit.

[0027] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A 1T-2B encoding conversion circuit based on memristor, comprising a memristor, an excitation voltage source V, a transistor and a direct current voltage source, characterized in that: The memristors are three-value input memristors M in and two-value output memristors M out , the number of the excitation voltage sources is six, which are V0, V1, V2, V3, V4 and V5 respectively; the memristors are M0, M1, M2, M3, M4 and M5 respectively; the transistors are T0, T1, T2, T3, T4 and T5 respectively; the direct current voltage sources are V dd0 , V dd1 , V dd2 , V dd3 , V dd4 and V dd5 .

2. The 1T-2B encoding conversion circuit based on memristor according to claim 1, characterized in that: The initial resistance state of the output binary memristor is R H The working process of the circuit is divided into two stages, and is driven by an excitation voltage source V. The first stage is an initial stage (0-10 ms), and a small initial voltage V Init =0.5V is output by V to obtain the initial resistance state of the memristor.

3. The 1T-2B encoding conversion circuit based on memristor according to claim 1, characterized in that: The second stage is the running stage (10-20 ms), Voutput is a large running voltage V Run =1.5V, the high and low resistance R H and R L of the input ternary memristor are converted into the high and low resistance R H and R L of the output binary memristor, that is, when the resistance of the input ternary memristor is R H , the resistance of the output binary memristor is converted into R H , when the resistance of the input ternary memristor is R L , the resistance of the output binary memristor is converted into R L , and the logic operation is completed.

4. The 1T-2B encoding conversion circuit based on memristor according to claim 1, characterized in that: At 0-1 ms, set V0=V1=V2=V3=V4=V5=0.5V, the gate output voltage V of TO, T1, T2, T3, T4 and T5 is turned on DD， Make all the transistors turn on, detect the initial state of all the memristors in the array. At 1-2 ms, set V0=V1=2.15V, the gate output voltage V of TO, T1 and T2 is turned on DD， Make the corresponding transistor turn on, the result of the negative ternary non-operation of M0 is stored in M2.

5. The memristor-based 1T-2B encoding conversion circuit according to claim 4, characterized in that: At 2-3 ms, set V0=V1=1.8V, the gate output voltage V of T0, T1 and T3 is turned on DD， The corresponding transistor is turned on, and the result of the positive ternary non-operation of M0 is stored in M3.

6. The memristor-based 1T-2B encoding conversion circuit according to claim 4, characterized in that: At 3-4 ms, set V4=1.5V, the gate output of T2 and T4 is set to turn on voltage V DD， The corresponding transistor is turned on, and the result of the ternary-to-binary operation of M2 is stored in M4, i.e. output B0. At 4-5 ms, set V5=1.5V, the gate output of T3 and T5 is set to turn on voltage V DD， The corresponding transistor is turned on, and the result of the ternary-to-binary operation of M3 is stored in M5, i.e. output B1. Thus, the logic operation of 1T-2B encoding conversion is realized.

Images