Simple clock error detection method and device under flexible oversampling factor, equipment, storage medium and product

Abstract

This application discloses a simplified clock error detection method, apparatus, device, storage medium, and product under a flexible oversampling factor, relating to the field of clock error detection technology. The method includes: performing complex sign-deduction processing on the received signal to obtain a sign result; and querying a preset clock error mapping table based on the sign result to obtain the clock error. Since this application performs complex sign-deduction processing on the received signal to obtain a sign result, and then queries a preset clock error mapping table based on the sign result to obtain the clock error, compared to existing digital timing error detectors with excessively high computational complexity, the above method of this application can eliminate multiplication operations in existing clock error detection, reducing power consumption and computational resources.

Description

Technical Field

[0001] This application relates to the field of clock error detection technology, and in particular to a simplified clock error detection method, apparatus, device, storage medium and product under flexible oversampling factors. Background Technology

[0002] High-speed fiber optic communication transceivers widely employ Digital Signal Processing (DSP) technology to compensate for various impairments during signal transmission. As baud rates continue to increase, DSPs need to evolve towards lower power consumption per bit and lower computational complexity. Furthermore, the power consumption of a DSP chip directly depends on the sampling rate of the analog-to-digital converter (ADC) and the computational complexity of the DSP. In the receiver-side DSP program, Timing Recovery (TR) is a critical component placed in the DSP front-end, and its performance directly affects the normal operation of subsequent DSP algorithm modules. Within TR, a simple and efficient Timing Error Detector (TED) is crucial because it estimates timing errors and inputs them into the TR loop to correct time-varying sampling clock frequency and phase errors. Traditional digital timing error detectors (TEDs), such as Gardner, Godard, and Lee TEDs, require two sampling points per symbol (SPS) operation, leading to higher ADC sampling rate requirements and consequently higher cost and power consumption. TEDs that require minimal resources to meet the demands of higher-speed signal transmission can operate at 1 SPS, such as the classic MM clock error detector (Mueller-Müller (MM) TED). However, this requires a sign decision value, which is difficult to implement in practical systems due to the complex TR loop design. To address this issue, a simplified sign-MM TED was proposed. This method uses simple logic operations to replace complex decision circuits, thereby reducing complexity and computational feedback delay. While reducing implementation complexity, the timing jitter performance of sign-MM TED still needs further improvement. Furthermore, TEDs operating at 1 SPS inevitably introduce a performance penalty because the original signal does not satisfy the Nyquist sampling theorem, resulting in the loss of some effective spectral information. This is unacceptable for impairment-sensitive high-speed optical communication systems.

[0003] To address this issue, scholars have proposed improved MG schemes (Godard TED) and improved Lee TED. These schemes satisfy the Nyquist sampling theorem, ensuring no loss of effective spectral components, while extracting the clock signal at a sampling rate of less than 2 SPS, reducing the requirements on the ADC sampling rate. However, since each clock phase error estimation requires hundreds of real multiplications, the computational complexity of these TED schemes is excessively high, introducing significant computational delays and reducing the clock phase tracking speed, thus degrading the performance of the clock phase-locked loop. Currently, a real-time clock recovery scheme based on a simplified improved SMG scheme (Godard TED) has emerged, achieving real-time clock recovery. However, this traditional scheme fails when processing Nyquist signals with small roll-off factors, and due to the complex Fourier / Inverse Fourier Transform (FFT / IFFT) required for frequency domain processing, the overall complexity remains high, leading to increased cost and power consumption of the DSP chip. Summary of the Invention

[0004] The main purpose of this application is to provide a simplified clock error detection method, device, equipment, storage medium and product with flexible oversampling factor, which aims to solve the technical problem that existing clock error detection requires a large number of multiplication operations and has high computational complexity.

[0005] To achieve the above objectives, this application proposes a simplified clock error detection method under a flexible oversampling factor, which includes:

[0006] The received signal is subjected to complex sign decomposition to obtain the sign result;

[0007] Based on the symbol result, a preset clock error mapping table is queried to obtain the clock error.

[0008] Optionally, the step of performing complex sign-decomposition processing on the received signal to obtain the sign result includes:

[0009] The received signal is sampled to obtain a first sampled signal and a second sampled signal;

[0010] The first sampled signal and / or the second sampled signal are subjected to complex sign-determination processing to obtain the sign result.

[0011] Optionally, the oversampling factor for sampling the received signal is a non-integer, and the oversampling factor is the ratio of the sampling frequency to the baud rate.

[0012] Optionally, before querying a preset clock error mapping table based on the symbol result to obtain the clock error, the method further includes:

[0013] The target clock error corresponding to the preset symbol result is determined based on a preset clock error algorithm;

[0014] A preset clock error mapping table is constructed based on the preset symbol result and the target clock error.

[0015] Optionally, the preset clock error algorithm is:

[0016]

[0017] in, Used to characterize clock error, n is used to characterize the time index value of the sampled signal, x n β is used to characterize the received signal, β is used to characterize the oversampling rate, Im is used to characterize the imaginary part of the operand, and N is the length of the signal block used to calculate one clock error. The conjugate operation is represented by `csgn()`, which is the complex number sign-reversal function. Used to characterize a fixed phase shift.

[0018] Optionally, the preset clock error algorithm is:

[0019]

[0020] in, Used to characterize clock error, n is used to characterize the time index value of the sampled signal, x n β is used to characterize the received signal, β is used to characterize the oversampling rate, Im is used to characterize the imaginary part of the operand, and N is the length of the signal block used to calculate one clock error. The conjugate operation is represented by arg(), which represents the complex phase angle function. Used to characterize a fixed phase shift.

[0021] Furthermore, to achieve the above objectives, this application also proposes a simplified clock error detection device under a flexible oversampling factor, the simplified clock error detection device under a flexible oversampling factor comprising:

[0022] The complex sign-decoding module is used to perform complex sign-decoding on the received signal to obtain the sign result;

[0023] The query module is used to query a preset clock error mapping table based on the symbol result to obtain the clock error.

[0024] Furthermore, to achieve the above objectives, this application also proposes a simplified clock error detection device under a flexible oversampling factor, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the simplified clock error detection method under a flexible oversampling factor as described above.

[0025] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the simplified clock error detection method under the flexible oversampling factor described above.

[0026] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the simplified clock error detection method under the flexible oversampling factor described above.

[0027] This application performs complex sign-decoding on the received signal to obtain a sign result; based on the sign result, it queries a preset clock error mapping table to obtain the clock error. Since this application performs complex sign-decoding on the received signal to obtain a sign result, and then queries a preset clock error mapping table based on the sign result to obtain the clock error, compared to existing digital timing error detectors with excessively high computational complexity, the above method of this application can eliminate the multiplication operations in existing clock error detection, thereby reducing power consumption and computational resources. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating an embodiment of the simplified clock error detection method under the flexible oversampling factor of this application.

[0031] Figure 2 This is a flowchart illustrating Embodiment 2 of the simplified clock error detection method under the flexible oversampling factor of this application;

[0032] Figure 3 This is a schematic diagram of the time-domain TED structure based on LUT provided in Embodiment 2 of the simplified clock error detection method under flexible oversampling factor of this application;

[0033] Figure 4 This is a schematic diagram illustrating the design concept of the TED calculation LUT provided in Embodiment 2 of the simplified clock error detection method under flexible oversampling factor in this application;

[0034] Figure 5 This is a schematic diagram of the effect curve provided in Embodiment 2 of the simplified clock error detection method under the flexible oversampling factor of this application;

[0035] Figure 6 This is a schematic diagram of the module structure of the simplified clock error detection device under the flexible oversampling factor in the embodiments of this application;

[0036] Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the simplified clock error detection method under the flexible oversampling factor in the embodiments of this application.

[0037] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0038] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0039] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0040] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device capable of performing the above functions, or a simplified clock error detection device with flexible oversampling factors, etc. The following description uses a clock error detection device as an example to illustrate this embodiment and the subsequent embodiments.

[0041] Based on this, embodiments of this application provide a simplified clock error detection method with a flexible oversampling factor, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the simplified clock error detection method under the flexible oversampling factor of this application.

[0042] In this embodiment, the simplified clock error detection method under flexible oversampling factor includes the following steps:

[0043] Step S10: Perform complex sign decomposition on the received signal to obtain the sign result;

[0044] It should be noted that the received signal can be the original signal containing the clock information to be recovered, obtained by the communication receiver from the channel. Complex sign extraction processing can involve applying a csgn() (Complex Sign Function) operation to the sampled signal in the received signal, preserving its phase direction, discarding amplitude information, and outputting a discrete complex sign, such as ±1±j. The sign result can be the output after complex sign extraction processing, which is a finite number of discrete values ​​(usually 4), used for subsequent clock error detection.

[0045] Step S20: Based on the symbol result, query the preset clock error mapping table to obtain the clock error.

[0046] It should be noted that the preset clock error mapping table (LUT) can be a lookup table that stores the correspondence between symbol results and clock errors. It can be constructed through mathematical modeling or simulation, enumerating all possible combinations of symbol results (such as the current symbol s(n), adjacent symbols s(n+1), phase rotation terms, etc.), and calculating the clock error value corresponding to each combination according to the clock error detection formula, then storing it in the LUT. The clock error detection formula can be a formula used to calculate clock errors.

[0047] Furthermore, in order to reduce the efficiency of clock error detection, before step S20, the following may be included: determining the target clock error corresponding to the preset symbol result based on a preset clock error algorithm;

[0048] A preset clock error mapping table is constructed based on the preset symbol result and the target clock error.

[0049] It should be noted that the preset clock error algorithm can be an algorithm that determines the clock error based on the symbol result. The preset symbol result can be a pre-listed list of possible symbol results. The target clock error can be the clock error corresponding to the preset symbol result calculated based on the preset clock error algorithm.

[0050] The preset clock error algorithm can be the following formula (1):

[0051] (1)

[0052] in, Used to characterize clock error, n is used to characterize the time index value of the sampled signal, x n β is used to characterize the received signal, β is used to characterize the oversampling rate, Im is used to characterize the imaginary part of the operand, and N is the length of the signal block used to calculate one clock error. The conjugate operation is represented by `csgn()`, which is the complex number sign function. `csgn(.) = sgn[Re(.)] + j·sgn[Im(.)]` represents the complex number sign operation. =π(1 / β-0.5) represents a fixed phase shift given an OSF.

[0053] In this embodiment, the imaginary part Im(.) operation in formula (1) can be replaced with the complex phase angle arg(.) operation. This is similar to formula (1) above, as the sign operation eliminates the need for multiplication. Therefore, the preset clock error algorithm can also be the following formula (2):

[0054] (2)

[0055] in, Used to characterize clock error, n is used to characterize the time index value of the sampled signal, x n β is used to characterize the received signal, β is used to characterize the oversampling rate, Im is used to characterize the imaginary part of the operand, and N is the length of the signal block used to calculate one clock error. The conjugate operation is represented by arg(), which represents the complex phase angle function. Used to characterize a fixed phase shift.

[0056] This embodiment performs complex sign-decoding on the received signal to obtain a sign result; based on the sign result, it queries a preset clock error mapping table to obtain the clock error. Since this embodiment performs complex sign-decoding on the received signal to obtain a sign result, and then queries a preset clock error mapping table based on the sign result to obtain the clock error, compared to existing digital timing error detectors with excessively high computational complexity, the above method in this embodiment can eliminate the multiplication operations in existing clock error detection, thereby reducing power consumption and computational resources.

[0057] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 , Figure 2 This is a flowchart illustrating Embodiment 2 of the simplified clock error detection method under the flexible oversampling factor of this application. Step S10 further includes the following steps:

[0058] Step S101: Sample the received signal to obtain a first sampled signal and a second sampled signal;

[0059] It should be noted that sampling the received signal to obtain the first sampled signal and the second sampled signal can be achieved by discretizing the received signal using an ADC at a certain sampling rate to obtain a digital sampling sequence. The first sampled signal and the second sampled signal can be sampling results at different times or with different phase offsets. The first / second sampled signal can be non-integer multiples of sampling points within adjacent symbol periods, that is, the oversampling factor of sampling the received signal is non-integer, and the oversampling factor is the ratio of the sampling frequency to the baud rate.

[0060] Step S102: Perform complex sign processing on the first sampled signal and / or the second sampled signal to obtain the sign result.

[0061] It should be noted that this embodiment can perform complex sign processing on both the first sampled signal and the second sampled signal simultaneously, or it can perform complex sign processing on only one of the sampled signals.

[0062] Since this embodiment can perform a sign-taking operation on only one of the sampled signals, in the scenario where only one of the sampled signals is subjected to a sign-taking operation, the preset clock error algorithms used to determine the preset clock error mapping table are as follows: Formula (3) and Formula (4):

[0063] Formula (3)

[0064] Formula (4)

[0065] in, and This is used to characterize the clock error obtained from the calculation. Due to the addition of the sign operation, the multiplication operation can still be eliminated, and it is guaranteed to work at non-integer multiples of the baud rate, thus reducing computational complexity and power consumption. Compared to the above formula (1), the disadvantage of the modified scheme shown in formula (3-4) is that because the sign operation is only performed on one side, more bits are retained in the result, resulting in a relatively higher demand for addition resources. However, in systems that consume a lot of computation, these differences in addition resources are small, and this method can achieve similar results to formula (1).

[0066] Similarly, in the scenario where only one of the sampled signals undergoes complex sign-determination processing, the modified formulas corresponding to formula (2) can be found in formulas (5) and (6) below:

[0067] Formula (5)

[0068] Formula (6)

[0069] in, and This is used to characterize the calculated clock error. By replacing the imaginary part operation with an angle calculation operation, the clock component can also be calculated, and the sign of the calculation result can still characterize the advance / delay of the sampling time. Similar to the above embodiment, if this type of modified scheme is adopted, it is only necessary to redesign the LUT according to the angle calculation, and the TED calculation result can be obtained through similar addressing operations.

[0070] Whether in direct modulation-direct detection (IM / DD) or coherent optical communication systems, there is a pressing need for a time-domain fractional-time error detector (TED) that can operate at non-integer sampling rates below twice the baud rate, with lower complexity and stronger robustness, while satisfying the Nyquist sampling theorem and without losing any frequency information. This TED algorithm, which maintains TR performance while reducing ADC sampling rate and TR complexity, is crucial for improving the capacity upgrade and power consumption reduction of optical communication systems. Therefore, addressing the drawbacks of existing TED schemes requiring high sampling rates and computational complexity, this embodiment proposes for the first time a time-domain improved multiplication-free clock error detector operating at non-integer baud rate sampling, namely, a TED operating at a 1.x SPS sampling rate. Effective clock information is extracted through a nonlinear operation such as sign-taking of the sampling points, while simultaneously eliminating multiplication operations to reduce power consumption and computational resource requirements. Then, for real-time implementation, a multiplication-free simplified computation based on lookup table (LUT) addressing operations is proposed. For details, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the time-domain TED structure based on LUT provided in Embodiment 2 of the simplified clock error detection method under the flexible oversampling factor of this application.

[0071] This embodiment proposes a low-complexity time-domain TED scheme for sampling scenarios with non-integer multiples of baud rate, thereby avoiding FFT / IFFT operations, such as... Figure 3 As shown. Its calculation output is given by the above formula (1). With the help of the csgn function, the TED proposed in this embodiment eliminates the multiplication requirement because it only includes multiplication between (±1±j)*(±1±j) and its phase rotation term Given an OSF, which is also a constant sequence that changes periodically with the time index value n, all calculations can be performed using a very simple lookup table (LUT) (the input combination includes ±1±j and a phase rotation term, with the corresponding TED output clock error value). Compared to the sign function, the csgn function can handle not only real signals but also complex signals, thus it is applicable to both IM / DD and coherent systems, further enhancing the versatility of the proposed scheme in this embodiment.

[0072] Secondly, the LUT designed in this embodiment is as follows: Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the design concept of the TED calculation LUT provided in Embodiment 2 of the simplified clock error detection method under the flexible oversampling factor of this application. The result of multiplying the received signal after symbol extraction, csgn(x(n))·csgn(x*(n+1)), has only two possibilities: ±2 and ±2j. Therefore, LUT1 can further simplify the output to ±1 and ±j by judging the symbol of the received signal, because 2, as a constant amplification factor, does not affect the symbol and optimal sampling point judgment of TED phase discrimination. In this embodiment, if the system is an IM / DD system, the output of LUT1 only has two possibilities: ±1. In this case, this embodiment is further simplified. The output of LUT1 in a coherent system has four possibilities: ±1 and ±j.

[0073] The reason why another input to LUT2 is the time index n is because the last term in formula (1), the phase shift term, is a fixed cyclic phase shift with a period of M (M is the period length of the phase rotation term, in units of the number of sampling points). By taking the remainder of M, the required phase shift can be found directly, avoiding the need to continuously increase n and repeatedly calculate the phase value, effectively reducing the complexity and implementation difficulty of this embodiment. Therefore, the output of LUT1 needs to be rotated in a fixed phase according to the time index value n. M and L are integers, which are the smallest integer ratio between 1 and 2 that makes M / L between 1 and 2. The larger the value of M / L, the closer the sampling rate is to 2, and the theoretical performance may be better, but the complexity of the scheme is also higher. The smaller the value of M / L, the performance of the scheme may be degraded, but the complexity is also lower. Therefore, different M / L represent different sampling rate situations, which can be flexibly adjusted to meet the actual application requirements, reflecting the universality of this embodiment under different parameter configurations. For ease of explanation, OSF=M / L=4 / 3 is used as an example here. For other cases, M and L are integers greater than zero and M>L means that OSF is a non-integer between 1 and 2. At this point, the phase shift term in formula (1) can be expressed as the following formula (7):

[0074] Formula (7)

[0075] Therefore, when the time index value n takes the values ​​0, 1, 2, 3, 4, 5, ..., N -2, N When -1, the phase shift term shown in formula (7) can be expressed as: , , , , , …, its cycle of change is M =4. Therefore, above Figure 4 Another input to LUT2 is the time index value.n right M The result of taking the remainder is mod( n, M As can be seen from formula (1), the output of TED in this embodiment is the imaginary part of the complex number calculation result. Therefore, it is only necessary to determine whether the output result of LUT1 is ±1 or ±j, and extract the real part (cos term) or imaginary part (sin term) of the phase shift term in formula (7) to obtain the TED output. When the system OSF=M / L is configured to other values, the corresponding LUT2 can be generated by analogy according to the above principle.

[0076] The superior performance of this embodiment is confirmed by simulations in a 61 Gbaud dual-polarization QPSK system. See also... Figure 5 , Figure 5 The diagram shows the effect curves of the simplified clock error detection method under the flexible oversampling factor in this application (including the relationship curves between the TED output value and the preset clock error value obtained by using the SMG scheme (a) and the scheme (b) of this embodiment respectively; (c): the relationship curve between different TED timing jitter and roll-off factor; (d): the relationship curve between different TED timing jitter and oversampling factor). Figure 5 In the figure, (a) and (b) represent the S-curves (the relationship curve between the TED output value and the preset clock error value) obtained by using SMG and the TED scheme of this embodiment when ROF is 0.01 and OSF is 1.25, respectively. The timing jitter is defined as 20log. 10 (Δ t ), where Δ t It represents the standard deviation of the S-curve at the zero point (optimal sampling point). Figure 5 Figures (c) and (d) show the timing jitter curves of different TED schemes as a function of ROF or OSF, respectively, with a fixed OSF or ROF. It can be seen that when the ROF decreases to below 0.01, the performance of the MG and SMG schemes deteriorates sharply; timing jitter greater than -20dB directly leads to the failure of the clock recovery loop. However, the TED scheme in this embodiment, due to the use of the csgn function to broaden the signal spectrum, maintains jitter around -30dB under different ROFs, thus supporting a stable clock recovery loop. Figure 5 As shown in (d), the timing jitter of the proposed scheme gradually decreases with increasing OSF and is consistently superior to the MG and SMG schemes. When the OSF is 1.6, the timing jitter of the proposed scheme is reduced by approximately 7dB and 11.5dB compared to the MG and SMG schemes, respectively. These results indicate that the proposed scheme not only effectively reduces computational complexity but also maintains stable operation under different roll-off factors and oversampling ratios, demonstrating good robustness.

[0077] This embodiment of the non-multiplication-based TED operates at non-integer multiple baud rate sampling, effectively supporting all subsequent DSP operations at non-integer multiple oversampling rates. This significantly reduces the ADC sampling rate and the area and power consumption of the DSP chip. Furthermore, this embodiment of the TED offers good scalability and flexibility. For signals with sampling rates between 1 and 2 SPS and different roll-off factors (ROF), the calculation formula can be flexibly adjusted based on the given non-integer oversampling rate (OSF) and ROF, thereby improving its applicability. Moreover, through lookup table (LUT) addressing operations, it achieves the most computationally efficient hardware implementation of time-domain TED operating at 1.X SPS.

[0078] This embodiment samples the received signal to obtain a first sampled signal and a second sampled signal; it then performs complex sign-decomposition processing on the first sampled signal and / or the second sampled signal to obtain a sign result. This embodiment extracts the sampling clock error through complex sign-decomposition operations, effectively reducing the hardware complexity of the algorithm.

[0079] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the simplified clock error detection method under the flexible oversampling factor of this application. Any simple transformations based on this technical concept are within the protection scope of this application.

[0080] This application also provides a simplified clock error detection device with a flexible oversampling factor; please refer to [reference needed]. Figure 6 The simplified clock error detection device under the flexible oversampling factor includes:

[0081] The complex number sign-taking processing module 10 is used to perform complex number sign-taking processing on the received signal to obtain the sign result;

[0082] The query module 20 is used to query a preset clock error mapping table based on the symbol result to obtain the clock error.

[0083] This embodiment performs complex sign-decoding on the received signal to obtain a sign result; based on the sign result, it queries a preset clock error mapping table to obtain the clock error. Since this embodiment performs complex sign-decoding on the received signal to obtain a sign result, and then queries a preset clock error mapping table based on the sign result to obtain the clock error, compared to existing digital timing error detectors with excessively high computational complexity, the above method in this embodiment can eliminate the multiplication operations in existing simplified clock error detection under flexible oversampling factors, thereby reducing power consumption and computational resources.

[0084] The simplified clock error detection device under flexible oversampling factors provided in this application employs the simplified clock error detection method under flexible oversampling factors described in the above embodiments. This solves the technical problem that existing simplified clock error detection methods under flexible oversampling factors require a large number of multiplication operations, resulting in high computational complexity. Compared with the prior art, the beneficial effects of the simplified clock error detection device under flexible oversampling factors provided in this application are the same as those of the simplified clock error detection method under flexible oversampling factors provided in the above embodiments. Furthermore, other technical features of the simplified clock error detection device under flexible oversampling factors are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0085] This application provides a simplified clock error detection device under a flexible oversampling factor. The simplified clock error detection device under a flexible oversampling factor includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the simplified clock error detection method under a flexible oversampling factor in the above embodiment 1.

[0086] The following is for reference. Figure 7 This document illustrates a structural schematic diagram of a simplified clock error detection device suitable for implementing the embodiments of this application under a flexible oversampling factor. The simplified clock error detection device under a flexible oversampling factor in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The simplified clock error detection device with flexible oversampling factor shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0087] like Figure 7As shown, the simplified clock error detection device under flexible oversampling factor may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the simplified clock error detection device under flexible oversampling factor. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via bus 1005. Input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the simplified clock error detection device with flexible oversampling factors to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a simplified clock error detection device with flexible oversampling factors and various systems, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0088] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0089] The simplified clock error detection device under flexible oversampling factors provided in this application employs the simplified clock error detection method under flexible oversampling factors described in the above embodiments. This solves the technical problem that existing simplified clock error detection methods under flexible oversampling factors require a large number of multiplication operations, resulting in high computational complexity. Compared with the prior art, the beneficial effects of the simplified clock error detection device under flexible oversampling factors provided in this application are the same as those of the simplified clock error detection method under flexible oversampling factors provided in the above embodiments. Furthermore, other technical features of this simplified clock error detection device under flexible oversampling factors are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0090] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0092] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the simplified clock error detection method under the flexible oversampling factor in the above embodiments.

[0093] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0094] The aforementioned computer-readable storage medium may be included in a simplified clock error detection device with flexible oversampling factor; or it may exist independently and not assembled into a simplified clock error detection device with flexible oversampling factor.

[0095] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include object-oriented programming languages—such as Python, Java, Smalltalk, and C++—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0096] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0097] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0098] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the simplified clock error detection method under the flexible oversampling factor described above. This solves the technical problem that existing simplified clock error detection methods under flexible oversampling factors require a large number of multiplication operations, resulting in high computational complexity. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the simplified clock error detection method under the flexible oversampling factor provided in the above embodiments, and will not be elaborated upon here.

[0099] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the simplified clock error detection method under the flexible oversampling factor described above.

[0100] The computer program product provided in this application can solve the technical problem that existing simplified clock error detection methods under flexible oversampling factors require a large number of multiplication operations, resulting in high computational complexity. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the simplified clock error detection method under flexible oversampling factors provided in the above embodiments, and will not be repeated here.

[0101] The above description is only a part of the embodiments of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the technical concept of this application and using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included in the scope of protection of this application.

Claims

1. A simplified clock error detection method under a flexible oversampling factor, characterized in that, The simplified clock error detection method under the flexible oversampling factor includes the following steps: The received signal is subjected to complex sign decomposition to obtain the sign result; Based on the symbol result, a preset clock error mapping table is queried to obtain the clock error; Before querying the preset clock error mapping table based on the symbol result to obtain the clock error, the process further includes: The target clock error corresponding to the preset symbol result is determined based on a preset clock error algorithm; Construct a preset clock error mapping table based on the preset symbol result and the target clock error; The preset clock error algorithm is as follows: in, The clock error is represented by n, the time index of the sampled signal is represented by x(n), the received signal is represented by β, the oversampling factor is represented by Im, the imaginary part of the operand is represented by Im, and N is the length of the signal block used to calculate the clock error once. The conjugate operation is represented by `csgn()`, which is the complex number sign-reversal function. Used to characterize a fixed phase shift.

2. The simplified clock error detection method under flexible oversampling factor as described in claim 1, characterized in that, The process of performing complex sign-decomposition on the received signal to obtain the sign result includes: The received signal is sampled to obtain a first sampled signal and a second sampled signal; The first sampled signal and / or the second sampled signal are subjected to complex sign-determination processing to obtain the sign result.

3. The simplified clock error detection method under flexible oversampling factor as described in claim 2, characterized in that, The oversampling factor for sampling the received signal is a non-integer, and the oversampling factor is the ratio of the sampling frequency to the baud rate.

4. The simplified clock error detection method under flexible oversampling factor as described in claim 1, characterized in that, The preset clock error algorithm is as follows: in, The clock error is represented by n, the time index of the sampled signal is represented by β, the received signal is represented by x(n), the oversampling factor is represented by β, and N is the length of the signal block used to calculate one clock error. The conjugate operation is represented by arg(), which represents the complex phase angle function. Used to characterize a fixed phase shift.

5. A simplified clock error detection device with flexible oversampling factor, characterized in that, The simplified clock error detection device with flexible oversampling factor includes: The complex sign-decoding module is used to perform complex sign-decoding on the received signal to obtain the sign result; The query module is used to query a preset clock error mapping table based on the symbol result to obtain the clock error; Before querying the preset clock error mapping table based on the symbol result to obtain the clock error, the process further includes: The target clock error corresponding to the preset symbol result is determined based on a preset clock error algorithm; Construct a preset clock error mapping table based on the preset symbol result and the target clock error; The preset clock error algorithm is as follows: in, The clock error is represented by n, the time index of the sampled signal is represented by x(n), the received signal is represented by β, the oversampling factor is represented by Im, the imaginary part of the operand is represented by Im, and N is the length of the signal block used to calculate the clock error once. The conjugate operation is represented by `csgn()`, which is the complex number sign-reversal function. Used to characterize a fixed phase shift.

6. A simplified clock error detection device with flexible oversampling factor, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the simplified clock error detection method under the flexible oversampling factor as described in any one of claims 1 to 4.

7. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the simplified clock error detection method under the flexible oversampling factor as described in any one of claims 1 to 4.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the simplified clock error detection method under the flexible oversampling factor as described in any one of claims 1 to 4.

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