Voltage detector in data communication interface

Abstract

Aspects relate to a mechanism for detecting a voltage level (414) on a data communication interface (404) between a slave device (402) and a host device. Based on the detected voltage level (414), the slave device (402) may respond to the host device at the detected voltage level on the data communication interface (404). In some examples, a slave device (402) may include circuitry configured to switch between a first voltage level and a second voltage level to provide one of the first voltage level or the second voltage level corresponding to a detected voltage level on a data communication interface (404).

Description

Cross-references to related applications

[0001] This patent application claims priority to pending U.S. Provisional Application No. 63 / 514,071, filed July 17, 2023, and U.S. Non-Provisional Application No. 18 / 498,927, filed October 31, 2023, which have been assigned to the assignee of this application and are hereby incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0002] The technologies discussed below generally relate to data communication interfaces, and more specifically to data communication interfaces used to connect devices in audiovisual or multimedia systems. Background Technology

[0003] Electronic devices, including mobile communication devices, wearable computing devices (such as smartwatches), and tablet computers, support increasing functionality and capabilities. Many electronic devices include internal microphones and speakers and may include connectors that enable the use of audiovisual equipment, including headphones, external speakers, etc. Communication can be provided through digital interfaces defined by one or more standards. In another example, a mobile communication device may employ an interface conforming to the SoundWire standard defined by the Mobile Industry Processor Interface (MIPI) Alliance. The SoundWire standard defines a multi-wire communication bus. In other examples, a mobile communication device may employ a Digital Microphone (DMIC) interface.

[0004] The demand for enhanced audiovisual capabilities continues to grow. For example, mobile communication devices may include cameras and stereo microphones, which can be modified over time to improve performance. In another example, digital processing capabilities allow electronic devices to implement sound decoders that can provide signals to drive more than two speakers. In these and other examples, improved communication capabilities are needed to enable processing circuitry, controllers, decoder-decoder (codec) devices, and other components to transmit audio data to multiple audio devices via a common communication bus. Summary of the Invention

[0005] The following provides an overview of one or more aspects of this disclosure to offer a basic understanding of those aspects. This overview is not a comprehensive summary of all anticipated features of this disclosure, nor is it intended to identify key or essential elements of all aspects of this disclosure, nor to depict the scope of any or all aspects of this disclosure. Its sole purpose is to present some concepts of one or more aspects of this disclosure in one form as a prelude to the more detailed description that follows.

[0006] In one example, an apparatus is provided. The apparatus includes: a clock line voltage detector configured to detect the voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the apparatus and the host device; and circuitry configured to provide an output voltage on the data communication interface. The output voltage is at one of a first voltage level or a second voltage level corresponding to the detected voltage level.

[0007] Another example provides a method capable of operating at a slave device. The method includes: detecting a voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the slave and host devices; and providing an output voltage on the data communication interface. The output voltage is at either a first voltage level or a second voltage level corresponding to the detected voltage level.

[0008] Another example provides a slave device comprising: components for detecting the voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the slave device and the host device; and components for providing an output voltage on the data communication interface. The output voltage is at either a first voltage level or a second voltage level corresponding to the detected voltage level.

[0009] These and other aspects will be more fully understood after reading the following detailed description. Other aspects, features, and examples will be apparent to those skilled in the art after reading the following description of specific exemplary aspects in conjunction with the accompanying drawings. Although the features may be discussed below with respect to certain examples and drawings, all examples may include one or more of the features discussed herein. In other words, although one or more examples may be discussed having certain features, one or more of such features may also be used according to the various examples discussed herein. Similarly, although the examples may be discussed below as examples of devices, systems, or methods, it should be understood that such examples can be implemented in a variety of devices, systems, and methods. Attached Figure Description

[0010] Figure 1 It is a diagram depicting a device that uses a data link between integrated circuit (IC) devices according to some aspects.

[0011] Figure 2 This is a diagram illustrating an example of the architecture of a data communication interface based on some aspects.

[0012] Figure 3 This is a diagram illustrating an example data communication interface based on some aspects.

[0013] Figure 4This is an illustration of an example of a device configured to detect voltage levels on a data communication interface, based on certain aspects.

[0014] Figure 5 This is a diagram illustrating an example of a clock line voltage detector based on some aspects.

[0015] Figure 6 This is a flowchart illustrating an exemplary process for detecting voltage on a data communication interface, based on some aspects.

[0016] Figure 7 This is a diagram illustrating an example of voltage ranges based on certain aspects.

[0017] Figure 8 This is a diagram illustrating another example of a clock line voltage detector based on some aspects.

[0018] Figure 9 This is a flowchart illustrating another exemplary process for detecting voltage on a data communication interface, based on some aspects. Detailed Implementation

[0019] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0020] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, firmware, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0021] While aspects and examples are described herein by way of illustration, those skilled in the art will understand that additional specific implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or uses may arise via integrated chip examples and other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / shopping devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to a use case or application, the applicability of various types of the described innovations is evident. The scope of implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessary include additional components and features for the specific implementation and practice of the described examples. The aim is that the innovations described herein can be implemented in a variety of devices, chip-level components, systems, distributed deployments, end-user devices, etc., with various sizes, shapes, and constructions.

[0022] A host device (e.g., a master device) can be coupled to a slave device (e.g., a sensor, such as a microphone) via a data communication interface (e.g., a bus). The data communication interface can be, for example, a single-ended bus with a clock line, a data line, and ground. The clock line carries a clock signal provided by the host. The data line can be unidirectional (e.g., from the slave device to the host device) or bidirectional. In some examples, the data communication interface can be a Soundwire interface, a DMIC interface, a Serial Peripheral Interface (SPI), or other suitable interfaces with a single-ended structure.

[0023] Data communication interfaces can operate on either a 1.8V or 1.2V supply. As process geometry on the host device decreases, the number of 1.8V input / output (I / O) supplies that can be supported by the host device can decrease. Therefore, data communication interfaces between the host and slave devices can increasingly operate on a 1.2V supply. However, slave devices (such as microphones or other types of sensors) may be pin-limited in terms of the number of I / O supply pins they can support. Additionally, adding extra pins may prevent the slave device from maintaining backward compatibility and may increase package complexity. Furthermore, reducing the supply voltage from 1.8V to 1.2V may impact the performance of the slave device, thus limiting its ability to achieve key performance indicators (KPIs) such as signal-to-noise ratio (SNR), distortion characteristics, and / or maximum signal level. However, using, for example, voltage doublers or switching gaps to generate a higher voltage (e.g., 1.8V) internally within the slave device based on a lower supply voltage (e.g., 1.2V) may increase the cost and size of the slave device.

[0024] Various aspects relate to mechanisms for detecting voltage levels on a data communication interface between a slave device and a host device. Based on the detected voltage level, the slave device can respond to the host device at the detected voltage level on the data communication interface. In some examples, the slave device may include circuitry (such as a low-dropout (LDO) regulator, buck converter, voltage divider, or other suitable circuitry) configured to switch the circuit's output voltage between a first voltage level and a second voltage level to provide an output voltage at the data communication interface at either a first voltage level or a second voltage level corresponding to the detected voltage level. The first voltage level may correspond to 1.8V, and the second voltage level may correspond to 1.2V.

[0025] In some examples, the slave device can be configured to measure the voltage level of a clock signal transmitted on a clock line. For example, the slave device may include a clock line voltage detector configured to measure (detect) the voltage level of a clock signal on a clock line. In one example, the clock line voltage detector may include: a comparator configured to compare the clock line voltage with a threshold voltage to produce a comparator output indicating the detected voltage level; and a level shifter configured to generate a clock level signal based on the comparator output. The clock level signal may be input to circuitry to switch the circuitry's output voltage between a first voltage level and a second voltage level.

[0026] In some examples, the threshold voltage may be set between a first voltage level and a second voltage level. For example, the threshold voltage may be set between 1.3V and 1.4V. In some examples, the slave device may further include a low-pass filter configured to filter the clock signal and provide the filtered clock signal to the comparator. The low-pass filter may be included in the clock line voltage detector or may be external to the clock line voltage detector. In some examples, the low-pass filter may include a cutoff frequency (-3dB point) several times higher than the highest clock rate to avoid false detection by the comparator of the first voltage level (e.g., 1.8V).

[0027] The circuitry (e.g., an LDO regulator) can be coupled to an external power source that provides a supply voltage at a first voltage level (e.g., 1.8V). In an example where the detected voltage level is the first voltage level, the LDO regulator may include a bypass switch to allow the first voltage level from the supply voltage to pass through the LDO regulator and be supplied to the data communication interface. In an example where the detected voltage level is a second voltage level (e.g., 1.2V), the LDO regulator can be configured to downregulate the supply voltage to the second voltage level (e.g., 1.2V) and provide the second voltage level to the data communication interface.

[0028] Figure 1This is a diagram depicting an apparatus employing a data communication interface between integrated circuit (IC) devices according to some aspects. In one example, apparatus 100 may include a radio communication device that communicates with a radio access network (RAN), a core access network, the Internet, and / or another network via a radio frequency (RF) transceiver 118. The transceiver 118 may be embodied in or operatively coupled to processing circuitry 102. Processing circuitry 102 may be implemented using a System-on-Chip (SoC) and / or may include one or more IC devices. In some examples, processing circuitry 102 may include one or more application processors 104, one or more ASICs 108, and one or more peripheral devices 106 (such as codecs, amplifiers, and other audiovisual components). Each ASIC 108 may include one or more processing devices, logic circuitry, storage devices, registers, etc. Application processor 104 may include processor 110 and memory 114, and may be controlled by an operating system 112 loaded from internal or external storage devices as data and instructions executable by processor 110. Processing circuitry 102 may include or access a local database 116 implemented in memory 114, for example, where database 116 may be used to maintain operating parameters and other information for configuring and operating device 100. Local database 116 may be implemented as a set of registers, or may be implemented in a database module, flash memory, magnetic media, non-volatile or persistent storage devices, optical media, magnetic tape, floppy disk, or hard disk, etc. Processing circuitry may also be operatively coupled to internal and / or external devices, such as antenna 120, display 124, operator controls (such as buttons 128, 130, and keypad 126), and other components.

[0029] A data communication interface (e.g., a bus) 122 may be provided to support communication between the application processor 104, the ASIC 108, and / or the peripheral device 106. The data communication interface 122 may operate according to standard protocols defined for interconnecting certain components of the mobile device. For example, various types of interfaces may exist defined for communication between the application processor and the display and camera components of the mobile device, or between a codec provided in the ASIC 108 and an audio driver in one of the peripheral devices in the peripheral device 106. In some examples, the data communication interface 122 may conform to standards defined by the Mobile Industry Processor Interface (MIPI) Alliance. For example, the MIPI Alliance defines the SLIMbus and SoundWire interface standards, which enable mobile device designers to achieve design goals including scalability, reduced power consumption, lower pin counts, ease of integration, and consistency across system designs.

[0030] For example, the SoundWire data communication interface may allow up to eleven peripheral (e.g., slave) devices 106 to connect to a host device (e.g., application processor 104), where data can be driven from both the host and slave devices according to a time-division multiplexing (TDM) scheme. In other examples, the data communication interface 122 may correspond to a digital microphone (DMIC) interface, which can be used to collect pulse density modulation (PDM) audio data from one or two digital microphones via an integrated analog-to-digital converter (ADC). In other examples, the data communication interface 122 may correspond to a serial peripheral interface (SPI) or other suitable interface with a single-ended structure, where the clock signal is driven from the host device.

[0031] Figure 2 An example of a SoundWire system according to some aspects is illustrated. Various devices can be connected to the SoundWire data communication interface (e.g., the SoundWire bus), including audio headsets, codecs, amplifiers, repeaters, switches, bridges, and signal processing devices. A 32kHz system clock can be distributed with minimal commands and control. In the illustrated SoundWire system 200, an application processor 202 (e.g., a host device) or other IC device may include or be configured to operate as a codec and may be configured to communicate via a SoundWire bus manager 204. The SoundWire bus manager 204 may include channel (line) drivers and receivers, SoundWire encoders and decoders, state machines and / or sequencers, and other logic circuitry. In some instances, the SoundWire bus manager 204 may be implemented within a codec. The line drivers and receivers of the SoundWire bus manager 204 can be coupled to the lines of the data communication interface 220 (referred to herein as multi-line bus 220) via designated terminals (pins) of the application processor 202.

[0032] In the illustrated example, application processor 202 communicates with at least four slave devices 212, 214, 216, and 218 associated with audio input / output device 230. First slave device 212 includes an analog-to-digital converter (ADC 222) that digitizes input received from left microphone 232; second slave device 214 includes an ADC 224 that digitizes input received from right microphone 234; third slave device 216 includes a digital-to-analog converter (DAC 226) that provides an output to drive left speaker 236; and fourth slave device 218 includes a DAC 228 that provides an output to drive right speaker 238.

[0033] In the SoundWire system 200, the application processor 202 is coupled to slave devices 212, 214, 216, and 218 via a multi-line bus 220. The multi-line bus 220 can be configured to provide a clock line 206 and one or more data lines 208, 210. In practice, each data line 208, 210 is assigned to one of the physical lines of the multi-line bus 220. The multi-line bus 220 can be configured by a SoundWire bus manager 204. The SoundWire bus manager 204 can control data transmission on up to eleven data lines 208, 210 of the multi-line bus 220.

[0034] Figure 3 This is a diagram illustrating an example data communication interface 306 based on some aspects. Figure 3 The data communication interface 306 shown is a single-ended bus between a host device 302 (e.g., a master device) and a slave device 304 (e.g., a sensor, such as a microphone). In some examples, the data communication interface 306 may be a Soundwire interface, a DMIC interface, a Serial Peripheral Interface (SPI), or other suitable interfaces with a single-ended structure. The data communication interface 306 includes a clock line (Clk) 308, a data line (Data) 310, and a ground (Gnd) 312. The clock line 308 carries a clock signal provided by the host device 302 to the slave device 304. For example, the clock signal may have a 50% duty cycle. The data line 310 may be, for example, a single-ended bus between the host device 302 and the slave device 304. Figure 3 The data line shown is either a bidirectional data line or a unidirectional data line (e.g., from slave device 304 to host device 302).

[0035] Data communication interface 306 can operate on either a 1.8V or 1.2V supply. However, the data communication interface 306 between the host device 302 and the slave device 304 can increasingly operate on a 1.2V supply. In some examples, the slave device 304 (such as a microphone or other type of sensor) may be pin-limited in terms of the number of I / O supply pins it can support. Additionally, adding extra pins may prevent the slave device 304 from maintaining backward compatibility and may increase package complexity. Furthermore, reducing the supply voltage from 1.8V to 1.2V may affect the performance of the slave device 304. However, using, for example, a voltage doubler or switch cap to generate a higher voltage (e.g., 1.8V) internally within the slave device 304 based on a lower supply voltage (e.g., 1.2V) may increase the cost and size of the slave device.

[0036] Therefore, various aspects involve mechanisms for detecting voltage levels on the data communication interface between the slave device and the host device. Based on the detected voltage level, the slave device can respond to the host device at the detected voltage level on the data communication interface.

[0037] Figure 4 This is an illustration of an example of a device 402 configured to detect voltage levels on a data communication interface 404, according to some aspects. Device 402 may correspond to, for example, a slave device. For example, a slave device may include a microphone, a sensor, or other peripheral device. Data communication interface 404 may correspond to, for example... Figure 2 and / or Figure 3 The data communication interface shown may include at least a clock line (Clk) 406 and a data line (Data) 408. Device 402 includes a bus module 410, which may include, for example, line drivers and receivers, encoders and decoders, state machines and / or sequencers, and other logic circuitry. The line drivers and receivers of bus module 410 can be coupled to the lines of data communication interface 404 via pins of device 402.

[0038] The device 402 may further include a clock line voltage detector 414 configured to receive a clock signal 412 provided by a host device on clock line 406. For example, when the host device enables the data communication interface 404 and initiates clock signal 412 on clock line 406, clock signal 412 can be provided to clock line voltage detector 414 to detect the voltage level of clock signal 412. The voltage level may be, for example, 1.2V or 1.8V, depending on the supply voltage provided by the host device. For example, clock line voltage detector 414 is configured to measure (detect) the voltage level of the clock signal on the clock line to determine whether the detected voltage level is at a first voltage level (e.g., 1.8V) or a second voltage level (e.g., 1.2V).

[0039] Clock line voltage detector 414 can be configured to generate a clock level signal 418 indicating the detected voltage level, and input the clock level signal 418 to circuitry 416, such as a buck converter, voltage divider, or low dropout (LDO) regulator (the latter being exemplified). LDO regulator 416 can be configured to switch its output voltage 422 between a first voltage level and a second voltage level. The output voltage 422 can then be provided to bus module 410 for output to data communication interface 404. Therefore, based on the detected voltage level, device 402 can respond to the host device at the detected voltage level on data communication interface 404.

[0040] For example, LDO regulator 416 may be coupled to an external power supply 420 that provides a supply voltage at a first voltage level (e.g., 1.8V). In the example where clock level signal 418 indicates that the detected voltage level is the first voltage level, LDO regulator 416 may include a bypass switch to allow the first voltage level from supply voltage 420 to pass through LDO regulator 416 and be supplied to data communication interface 404 as LDO output voltage 422. In the example where clock level signal 418 indicates that the detected voltage level is a second voltage level (e.g., 1.2V), LDO regulator 416 may be configured to downregulate supply voltage 420 to the second voltage level (e.g., 1.2V) and supply the second voltage level as output voltage 422 to data communication interface 404. Thus, device 402 is able to communicate with a host device on data communication interface 404 without requiring additional pins on the device or a drop to supply voltage 420 on device 402.

[0041] Figure 5 This is a diagram illustrating an example of a clock line voltage detector 500 according to some aspects. The clock line voltage detector 500 includes a comparator 502 configured to compare the clock line voltage (CLK) of the clock line signal 504 with a threshold voltage 506 (V). REF A comparison is made to produce a comparator output 508 indicating the detected voltage level. In some examples, a threshold voltage 506 may be set between a first voltage level (e.g., 1.8V) and a second voltage level (e.g., 1.2V). For example, comparator 502 may be configured to compare the clock line voltage of clock line signal 504 with the threshold voltage 506, and the comparator output may be high if the clock line voltage is greater than the threshold voltage, and low if the clock line voltage is less than the threshold voltage. This application may cover other configurations of the clock line voltage detector 500, and therefore, the clock line voltage detector 500 is not limited to the use of... Figure 5 The comparator 502 and threshold voltage 506 shown are used to detect the voltage level.

[0042] The clock line voltage detector 500 may further optionally include a horizontal shifter 510 configured to generate a clock level signal 512 based on the comparator output 508. For example, the horizontal shifter 510 may be configured to shift the comparator output 508 from V DD Domain conversion to V DDCX (Lower internal voltage) domain. Clock level signal 512 can be input to the LDO regulator to switch the LDO regulator output between a first voltage level and a second voltage level. In some examples, the level shifter may be omitted, and the comparator output 508 may be directly input to the LDO regulator.

[0043] Figure 6 This is a flowchart illustrating an exemplary process for detecting voltage on a data communication interface according to some aspects. As described below, in specific embodiments within the scope of this disclosure, some or all of the illustrated features may be omitted, and some illustrated features may not be necessary for all specific implementations. In some examples, process 600 may be... Figure 4 The process 600 is performed by the device 402 illustrated herein. In some examples, the process 600 may be performed by any suitable device or component for performing the functions or algorithms described below.

[0044] At box 602, the process begins, where the data communication interface between the slave and master devices is not operational (e.g., not in operation). At box 604, the data communication interface clock is enabled at the slave device. For example, the master device may enable the clock line on the data communication interface and begin transmitting clock signals to the slave device.

[0045] At box 606, the slave device measures the voltage level of the clock line. For example, the slave device may measure (detect) the voltage level of a clock signal received on the clock line to determine whether the detected voltage level is at a first voltage level (e.g., 1.8V) or a second voltage level (e.g., 1.2V). At box 608, the detected voltage level may be compared to a threshold (e.g., a voltage threshold). In some examples, the voltage threshold may be set between a first threshold level and a second threshold level (e.g., between 1.2V and 1.8V).

[0046] At box 610, it is determined whether the detected voltage (V) is greater than a threshold (V>Th). If the detected voltage is greater than the threshold (Y branch of box 610), then at box 612, the slave device can respond to the master device at a first voltage level (e.g., 1.8V) on the data communication interface. However, if the detected voltage is less than the threshold (N branch of box 610), then at box 614, the slave device can respond to the master device at a second voltage level (e.g., 1.2V) on the data communication interface.

[0047] Figure 7This is a diagram illustrating examples of voltage ranges based on certain aspects. For both 1.8V and 1.2V supplies, there exist acceptable voltage ranges within, for example, the DMIC and SoundWire specifications. For instance, for a 1.8V clock supply, as seen in the second column, the DMIC and SoundWire specifications allow voltages within 65% of the IO to meet the 1.8V supply standard. Therefore, voltages between 1.1V and 2.15V can meet the 1.8V supply standard. Similarly, for a 1.2V clock supply, as seen in the fourth column, the DMIC and SoundWire specifications allow voltages within 10% of the IO, and therefore, voltages between .75 and 1.45V can meet the 1.2V supply standard. Figure 7 As can be seen, there is overlap between the acceptable voltages of the 1.8V and 1.2V supply. Therefore, it is impossible to identify... Figure 7 The threshold voltage between the 1.8V supply specification and the 1.2V supply specification is shown in the figure.

[0048] Therefore, in various aspects, the 1.8V and 1.2V specifications can be tightened (e.g., to allow for improved control of master and slave device implementations compared to the specifications) to enable the determination of appropriate threshold voltages. For example, as Figure 7 As shown, the 1.8V clock supply specification can be tightened, as indicated in the third column, to allow voltages within 85% of the IO pins to meet the standard. Therefore, a voltage between 1.4V and 2.15V can meet the 1.8V supply standard. Similarly, for a 1.2V clock supply, the specification can be tightened, as indicated in the fifth column, to allow voltages within 5% of the IO pins to meet the standard. Therefore, a voltage between 0.75V and 1.3V can meet the 1.2V supply standard. This leaves a gap between the 1.8V and 1.2V specifications, allowing the selection of a threshold voltage between 1.3V and 1.4V to detect the clock signal voltage level. To further prevent erroneous voltage level detection, the clock signal can be low-pass filtered before the comparator.

[0049] Figure 8 This is a diagram illustrating another example of a clock line voltage detector 800 based on some aspects. Figure 8 In the example shown, the clock line voltage detector 800 may include a low-pass filter 814 configured to low-pass filter a clock line signal 804 (CLK) received on the clock line of a data communication interface and generate a filtered clock signal 816. The clock line voltage detector 800 further includes a comparator 802 configured to compare the clock line voltage of the filtered clock signal 816 with a threshold voltage 806 (V). REFA comparison is made to produce a comparator output 808 indicating the detected voltage level. In some examples, a threshold voltage 806 may be set between a first voltage level (e.g., 1.8V) and a second voltage level (e.g., 1.2V). For example, the threshold voltage 806 may be set between 1.3V and 1.4V. In some examples, a low-pass filter 814 may include a cutoff frequency (-3dB point) several times higher than the highest clock rate to avoid false detection of the first voltage level (e.g., 1.8V) by the comparator 802. In one example, the comparator 802 may be configured to compare the clock line voltage of the filtered clock signal 816 with the threshold voltage 806, and the comparator output may be high if the clock line voltage is greater than the threshold voltage, and low if the clock line voltage is less than the threshold voltage. It should be noted that other configurations of the clock line voltage detector 800 may be used instead. Figure 8 The comparator 802 and threshold voltage 806 are shown in the figure.

[0050] The clock line voltage detector 800 may further optionally include a horizontal shifter 810 configured to generate a clock level signal 812 based on the comparator output 808. For example, the horizontal shifter 810 may be configured to shift the comparator output 808 from V DD Domain conversion to V DDCX (Lower internal voltage) domain. Clock level signal 812 can be input to the LDO regulator to switch the LDO regulator output between a first voltage level and a second voltage level. In some examples, the level shifter may not be included, and the comparator output 808 may be directly input to the LDO regulator.

[0051] In some examples, the low-pass filter 814 may be included in the clock line voltage detector 800, such as Figure 8 As shown. In other examples, the low-pass filter 814 can be external to the clock line voltage detector.

[0052] Figure 9 This is a flowchart illustrating another exemplary process 900 for detecting voltage on a data communication interface according to some aspects. As described below, in specific embodiments within the scope of this disclosure, some or all of the illustrated features may be omitted, and some illustrated features may not be necessary for all specific implementations. In some examples, process 900 may be... Figure 4 The process 900 is performed by the device 402 illustrated herein. In some examples, the process 900 may be performed by any suitable device or component for performing the functions or algorithms described below.

[0053] At box 902, the process begins, where the slave device detects the voltage level of the clock signal transmitted by the host device on the clock line of the data communication interface between the slave and host devices. For example, in conjunction with the above... Figure 4 The clock line voltage detector 414 shown and described provides a component for detecting voltage levels.

[0054] At box 904, the slave device can provide an output voltage on the data communication interface. The output voltage can be at either a first voltage level or a second voltage level corresponding to the detected voltage level. For example, as described above... Figure 4 The LDO regulator 416 (or other suitable circuitry) shown and described provides components for obtaining the output voltage.

[0055] In some examples, the slave device can be configured to compare the clock line voltage of a clock signal with a threshold voltage to produce a comparator output indicating the detected voltage level. In some examples, the first voltage level is 1.8V and the second voltage level is 1.2V. In some examples, the threshold voltage is between the first and second voltage levels. In some examples, the threshold voltage is between 1.3V and 1.4V.

[0056] In some examples, the slave device may be further configured to select either a first voltage level or a second voltage level based on the comparator output. In some examples, the slave device may be configured to generate a clock level signal based on the comparator output and select either a first voltage level or a second voltage level based on the clock level signal. In some examples, the slave device is further configured to low-pass filter the clock signal to generate a filtered clock signal. The slave device may be further configured to detect the voltage level of the filtered clock signal.

[0057] In some examples, the slave device may be further configured to receive a supply voltage at a first voltage level, transmit the supply voltage at the first voltage level as an output voltage in response to the detected voltage level being the first voltage level, and down-regulate the supply voltage to a second voltage level to provide the output voltage at the second voltage level to the data communication interface.

[0058] In one configuration, the slave device includes: components for detecting the voltage level of a clock signal transmitted by the host device on a clock line of a data communication interface between the device and the host device; and components for providing an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to the detected voltage level. In one aspect, the aforementioned components may be... Figure 4The clock line voltage detector and LDO regulator shown are configured to perform the functions described by the foregoing components. Alternatively, the foregoing components may be a circuit or any device configured to perform the functions described by the foregoing components.

[0059] Of course, in the above example, the circuitry included in device 402 is provided merely as an example, and other components for performing the described functions may be included in various aspects of this disclosure, including... Figures 1 to 5 , Figure 7 , and / or Figure 8 The descriptions in any of them, and the use of, for example, this article regarding Figure 6 and / or Figure 9 Any other suitable device or component of the described process and / or algorithm.

[0060] The following provides an overview of the various aspects of this disclosure: Aspect 1: An apparatus comprising: a clock line voltage detector configured to detect a voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the apparatus and the host device; and circuitry configured to provide an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to the detected voltage level.

[0061] Aspect 2: The apparatus according to aspect 1, wherein the first voltage level is 1.8V and the second voltage level is 1.2V.

[0062] Aspect 3: The apparatus according to aspect 1 or 2, wherein the clock line voltage detector includes a comparator configured to compare the clock line voltage of the clock signal with a threshold voltage to generate a comparator output indicating the level of the detected voltage.

[0063] Aspect 4: The apparatus according to aspect 3, wherein the circuit is configured to receive the comparator output and select the first voltage level or the second voltage level based on the comparator output.

[0064] Aspect 5: The apparatus of claim 3, wherein the clock line voltage detector further comprises a horizontal shifter configured to generate a clock level signal based on the comparator output and to provide the clock level signal to the circuit.

[0065] Aspect 6: The apparatus according to any one of Aspects 3, 4 or 5, the apparatus further comprising: a low-pass filter configured to filter the clock signal and provide the filtered clock signal to the comparator.

[0066] Aspect 7: The apparatus according to any one of aspects 3 to 6, wherein the threshold voltage is between the first voltage level and the second voltage level.

[0067] Aspect 8: The apparatus according to aspect 7, wherein the threshold voltage is between 1.3V and 1.4V.

[0068] Aspect 9: The apparatus according to any one of Aspects 1 to 8, wherein the circuitry includes a low-dropout (LDO) regulator.

[0069] Aspect 10: The apparatus according to aspect 9, wherein the LDO regulator is configured to receive a supply voltage at the first voltage level, and in response to the detected voltage level being the first voltage level, to pass the supply voltage at the first voltage level as the output voltage through the LDO regulator, and to down-regulate the supply voltage to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

[0070] Aspect 11: A method operable at a slave device, the method comprising: detecting a voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the slave device and the host device; and providing an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to the detected voltage level.

[0071] Aspect 12: The method according to aspect 11, wherein the first voltage level is 1.8V and the second voltage level is 1.2V.

[0072] Aspect 13: The method according to aspect 11 or 12, the method further comprising: comparing the clock line voltage of the clock signal with a threshold voltage to generate a comparator output indicating the detected voltage level.

[0073] Aspect 14: According to the method of aspect 13, the method further includes: selecting the first voltage level or the second voltage level based on the comparator output.

[0074] Aspect 15: The method according to aspect 13, the method further comprising: generating a clock level signal based on the comparator output; and selecting one of the first voltage level or the second voltage level based on the clock level signal.

[0075] Aspect 16: The method according to any one of Aspects 13, 14 or 15, the method further comprising: filtering the clock signal and generating a filtered clock signal; and detecting the voltage level of the filtered clock signal.

[0076] Aspect 17: The method according to any one of Aspects 13 to 16, wherein the threshold voltage is between the first voltage level and the second voltage level.

[0077] Aspect 18: The method according to aspect 17, wherein the threshold voltage is between 1.3V and 1.4V.

[0078] Aspect 19: The method according to any one of Aspects 11 to 18, the method further comprising: receiving a supply voltage at a first voltage level; transmitting the supply voltage at the first voltage level as the output voltage in response to the detected voltage level being the first voltage level; and adjusting the supply voltage down to a second voltage level to provide the output voltage at the second voltage level to the data communication interface.

[0079] Aspect 20: A slave device comprising: means for detecting a voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the slave device and the host device; and means for providing an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to the detected voltage level.

[0080] Aspect 21: The slave device according to aspect 20, wherein the first voltage level is 1.8V and the second voltage level is 1.2V.

[0081] Aspect 22: The slave device according to aspect 20 or 21, the slave device further includes: a component for comparing the clock line voltage of the clock signal with a threshold voltage to generate a comparator output indicating the detected voltage level.

[0082] Aspect 23: The slave device according to aspect 22 further includes: a component for selecting the first voltage level or the second voltage level based on the comparator output.

[0083] Aspect 24: According to aspect 22, the slave device further includes: means for generating a clock level signal based on the comparator output; and means for selecting one of the first voltage level or the second voltage level based on the clock level signal.

[0084] Aspect 25: The slave device according to aspect 22, 23 or 24, the slave device further comprising: components for filtering the clock signal and generating a filtered clock signal; and components for detecting the voltage level of the filtered clock signal.

[0085] Aspect 26: The slave device according to any one of Aspects 22 to 25, wherein the threshold voltage is between the first voltage level and the second voltage level.

[0086] Aspect 27: The slave device according to aspect 26, wherein the threshold voltage is between 1.3V and 1.4V.

[0087] Aspect 28: The slave device according to any one of Aspects 20 to 27, the slave device further comprising: means for receiving a supply voltage at the first voltage level; means for transmitting the supply voltage at the first voltage level as the output voltage in response to the detected voltage level being the first voltage level; and means for adjusting the supply voltage down to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

[0088] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then object A and object C can still be considered coupled to each other, even if they are not in direct physical contact. For example, a first object can be coupled to a second object, even if the first object never has direct physical contact with the second object. The term "circuit" is used broadly, and it is intended to include both hardware implementations of electronic devices and conductors (where these electronic devices and conductors, when connected and configured, perform the functions described in this disclosure, without limitation on the type of electronic circuit) and software implementations of information and instructions (where these information and instructions, when executed by a processor, perform the functions described in this disclosure).

[0089] Figures 1 to 9 One or more of the components, steps, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, step, feature, or function, or embodied in multiple components, steps, or functions. Additional elements, components, steps, and / or functions may be added without departing from the novel features disclosed herein. Figures 1 to 5 and / or Figure 8 The apparatus, devices, and / or components illustrated herein can be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein can also be efficiently implemented in software and / or embedded in hardware.

[0090] The use of designations such as "first," "second," etc., to refer to elements in this document generally does not limit the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Thus, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0091] It should be understood that the specific order or hierarchy of steps in the disclosed methods is an example of an exemplary process. It should be understood that the specific order or hierarchy of steps in these methods may be rearranged based on design preferences. The appended method claims present the elements of various steps in an exemplary order, but are not intended to limit them to the specific order or hierarchy presented, unless specifically stated herein.

[0092] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the claims, wherein references to elements in the singular form are not intended to mean “one and only one”, but rather “one or more”, unless specifically stated otherwise. Unless otherwise specifically stated, the term “some” refers to one or more. The phrase “at least one of” referring to the list of items means any combination of those items, including individual members. As an example, “at least one of a, b, or c” is intended to cover: a; b; c; a and b; a and c; b and c; and a, b, and c. All structural and functional equivalents of the elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly recited in the claims. No element of any claim shall be construed in accordance with 35 USC §112(f) unless it is expressly stated using the phrase “component for…” or, in the case of a method claim, using the phrase “step for…”.

Claims

1. An apparatus comprising: a clock line voltage detector configured to detect a voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the apparatus and the host device; and circuitry configured to provide an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to the detected voltage level.

2. The apparatus of claim 1, wherein the first voltage level is 1.8V and the second voltage level is 1.2V.

3. The apparatus of claim 1, wherein the clock line voltage detector comprises a comparator configured to compare a clock line voltage of the clock signal to a threshold voltage to produce a comparator output indicative of the detected voltage level.

4. The apparatus of claim 3, wherein the circuitry is configured to receive the comparator output and select the first voltage level or the second voltage level based on the comparator output.

5. The apparatus of claim 3, wherein the clock line voltage detector further comprises a level shifter configured to produce a clock level signal based on the comparator output and provide the clock level signal to the circuitry.

6. The apparatus of claim 3, further comprising: a low pass filter configured to filter the clock signal and provide a filtered clock signal to the comparator.

7. The apparatus of claim 3, wherein the threshold voltage is between the first voltage level and the second voltage level.

8. The apparatus of claim 7, wherein the threshold voltage is between 1.3V and 1.4V.

9. The apparatus of claim 1, wherein the circuitry comprises a low dropout (LDO) regulator.

10. The apparatus of claim 9, wherein the LDO regulator is configured to receive a supply voltage at the first voltage level, pass the supply voltage at the first voltage level through the LDO regulator as the output voltage in response to the detected voltage level being the first voltage level, and step down the supply voltage to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

11. A method operable at a slave device, the method comprising: detecting a voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the slave device and the host device; and providing an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to the detected voltage level.

12. The method of claim 11, wherein the first voltage level is 1.8V and the second voltage level is 1.2V.

13. The method of claim 11, further comprising: a clock line voltage of the clock signal is compared to a threshold voltage to produce a comparator output indicative of the detected voltage level.

14. The method of claim 13, the method further comprising: selecting the first voltage level or the second voltage level based on the comparator output.

15. The method of claim 13, the method further comprising: producing a clock level signal based on the comparator output; and selecting one of the first voltage level or the second voltage level based on the clock level signal.

16. The method of claim 13, the method further comprising: filtering the clock signal and producing a filtered clock signal; and detecting the voltage level of the filtered clock signal.

17. The method of claim 13, wherein the threshold voltage is between the first voltage level and the second voltage level.

18. The method of claim 17, wherein the threshold voltage is between 1.3V and 1.4V.

19. The method of claim 11, the method further comprising: receiving a supply voltage at the first voltage level; passing the supply voltage at the first voltage level as the output voltage in response to the detected voltage level being the first voltage level; and adjusting the supply voltage down to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

20. A slave device, the slave device comprising: means for detecting a voltage level of a clock signal transmitted by a host device on a clock line of a data communication interface between the slave device and the host device; and means for providing an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to the detected voltage level.

21. The slave device of claim 20, wherein the first voltage level is 1.8V and the second voltage level is 1.2V.

22. The slave device of claim 20, the slave device further comprising: means for comparing a clock line voltage of the clock signal to a threshold voltage to produce a comparator output indicative of the detected voltage level.

23. The slave device of claim 22, the slave device further comprising: means for selecting the first voltage level or the second voltage level based on the comparator output.

24. The slave device of claim 22, the slave device further comprising: means for producing a clock level signal based on the comparator output; and means for selecting one of the first voltage level or the second voltage level based on the clock level signal.

25. The slave device of claim 22, the slave device further comprising: means for filtering the clock signal and producing a filtered clock signal; and means for detecting the voltage level of the filtered clock signal.

26. A host device, the host device comprising: means for transmitting a clock signal on a clock line of a data communication interface between the host device and a slave device; and means for receiving an output voltage on the data communication interface, the output voltage being at one of a first voltage level or a second voltage level corresponding to a detected voltage level of the clock signal.

27. The host device of claim 26, wherein the first voltage level is 1.8V and the second voltage level is 1.2V.

28. The host device of claim 26, the host device further comprising: means for comparing a clock line voltage of the clock signal to a threshold voltage to produce a comparator output indicative of the detected voltage level.

29. The host device of claim 28, the host device further comprising: means for selecting the first voltage level or the second voltage level based on the comparator output.

30. The host device of claim 28, the host device further comprising: means for producing a clock level signal based on the comparator output; and means for selecting one of the first voltage level or the second voltage level based on the clock level signal.

31. The host device of claim 28, the host device further comprising: means for filtering the clock signal and producing a filtered clock signal; and means for detecting the voltage level of the filtered clock signal.

26. The slave device of claim 22, wherein the threshold voltage is between the first voltage level and the second voltage level.

27. The slave device of claim 26, wherein the threshold voltage is between 1.3 V and 1.4 V.

28. The slave device of claim 20, the slave device further comprising: means for receiving a supply voltage at the first voltage level; means for passing the supply voltage at the first voltage level as the output voltage in response to the detected voltage level being the first voltage level; and means for stepping down the supply voltage to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

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