Parallel operation power balance correction system and method of electronic load

Abstract

The invention discloses a parallel operation power balance correction system and method of an electronic load. Each device is provided with an analog line interface, a synchronous line interface and a digital communication interface. The analog line interface is used for synchronization of control signals of the system host and all slaves; aD and DA enable is switched according to a master-slave mode, the DA is enabled when the master is connected to an analog line, and the AD is used when the slave is connected to the analog line; and all devices are controlled in real time according to agreement through analog interfaces and analog lines, so that the high-dynamic load switching requirement is met. The synchronous interface is used for switching-on and switching-off synchronization, timing pulse sending and system time synchronization; the digital communication interface corrects current sharing characteristics among different machines in the system. Analog dynamics and digital compensation are fused, and dynamic response, current sharing precision and system expansibility are considered at the same time. The problem that dynamic response, current sharing precision and system expansibility are difficult to consider in a traditional control method is solved.

Description

Technical Field

[0001] This invention relates to an electronic load for power system testing, and more particularly to a parallel power balancing correction system and method for an electronic load. Background Technology

[0002] With the rapid development of new energy power generation, electric vehicles, and high-power industrial equipment, power system testing needs are facing the dual challenges of a leap in power levels (from kW to MW) and increasingly stringent dynamic performance (μs-level transient response). Electronic loads, as core testing equipment for power consumption, are limited by the voltage / current withstand capabilities of semiconductor devices (typically ≤30kW), making it difficult to independently meet the full-condition verification requirements of megawatt-level energy storage converters, high-voltage charging piles, and other equipment. Therefore, parallel operation of multiple electronic loads has become a key path to achieve power expansion.

[0003] Traditional control schemes mainly include the following:

[0004] 1) Master-slave control architecture

[0005] Implementation principle:

[0006] One master is designated to generate a PWM drive signal, which is broadcast to the slave via a communication bus (CAN / UART). The slave has no independent control loop, directly copies the master's drive signal, and is only used as a power extension unit.

[0007] defect:

[0008] (1) Communication delay causes dynamic loss of synchronization: CAN bus delay 1~2ms, multi-machine response time difference >200μs;

[0009] (2) Current distribution depends on hardware consistency: differences in the Vgs threshold of the power transistor directly lead to current error >8%.

[0010] 2) Distributed peer-to-peer architecture (high-end solutions, such as Keysight / Chroma)

[0011] Implementation principle:

[0012] Each unit operates its own control loop and exchanges status data via a high-speed bus (such as EtherCAT); a share-bus is used to transmit the total current error signal, and each unit adjusts its output autonomously.

[0013] defect:

[0014] (1) Dynamic performance is average;

[0015] (2) Uncompensated bias voltage: The current imbalance is still >3% under low temperature conditions.

[0016] 3) Simulation synchronization scheme (low-cost dynamic optimization scheme)

[0017] Implementation principle:

[0018] By using analog signals (such as voltage or current) to directly transmit load commands, the delay of digital communication can be avoided;

[0019] The current output value is transmitted through an analog line to generate a global current sharing signal.

[0020] Advantages:

[0021] Optimal dynamic performance (step response <50μs);

[0022] defect:

[0023] Accuracy is affected by temperature drift: when the temperature coefficient of the resistor network is >100ppm / ℃, the current accuracy deteriorates to ±5%;

[0024] Therefore, traditional parallel operation schemes have significant drawbacks:

[0025] 1. Master-slave architecture response delay: Due to signal transmission delay (>1ms), master-slave control based on digital communication (CAN / UART) causes asynchronous operation of parallel units, which cannot meet the requirements of dynamic load switching.

[0026] 2. Insufficient current balancing accuracy: Differences in bias voltage between power modules cause current distribution imbalance (error > 5%), and local overload will lead to heat accumulation or even burnout of devices;

[0027] 3. Limited system scalability: When the number of parallel units in master-slave mode exceeds 4, signal crosstalk causes system instability and it cannot be compatible with the coordinated control of mixed loads such as resistor boxes.

[0028] In view of this, the present invention is hereby proposed. Summary of the Invention

[0029] The purpose of this invention is to provide a parallel power balancing correction system and method for electronic loads to solve the above-mentioned technical problems existing in the prior art.

[0030] The objective of this invention is achieved through the following technical solution:

[0031] The parallel power balancing correction system for electronic loads of the present invention has an analog line interface, a synchronization line interface and a digital communication interface for each device;

[0032] The analog line interface connects to AD and DA; the analog line interface is equipped with a master / slave mode switching unit, in which DA is connected to the analog line when it is the master and AD is connected to the analog line when it is the slave;

[0033] Both the master and slave devices have their synchronization line interfaces connected to analog lines;

[0034] The digital communication interface connects all devices in the system.

[0035] The above system implements a method for parallel power balancing correction of electronic loads:

[0036] The analog line interface serves as the synchronization point for control signals between the system host and all slave devices;

[0037] Switch between AD and DA enable based on master / slave mode. When the device is master, enable DA and connect DA to the analog line. When the device is slave, use AD and connect AD to the analog line.

[0038] Through the analog interface and analog line, all devices can be controlled in real time according to the same device, meeting the requirements of high dynamic load switching.

[0039] The synchronization interface is used for power-on / off synchronization and for periodically sending pulses for system time synchronization.

[0040] The digital communication interface corrects the current sharing characteristics between different machines within the system.

[0041] Compared with existing technologies, the parallel power equalization correction system and method for electronic loads provided by this invention integrates analog dynamics and digital compensation, while simultaneously considering dynamic response, current sharing accuracy, and system scalability. This solves the problem that traditional control methods struggle to balance dynamic response, current sharing accuracy, and system scalability. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the analog line interface connection between AD and DA in an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of the master-slave connection method in the system of this embodiment of the invention;

[0044] Figure 3 This is a schematic diagram of the synchronization line interface according to an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram of a digital communication interface connection system device according to an embodiment of the present invention. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0047] First, the following explanations are provided for the terms that may be used in this article:

[0048] The terms “including,” “contains,” “comprising,” “having,” or other similar semantic descriptions shall be interpreted as non-exclusive inclusion.

[0049] The contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Where the manufacturers of the reagents or instruments used in the embodiments of this invention are not specified, they are all conventional products that can be purchased commercially.

[0050] The parallel power balancing correction system for electronic loads of the present invention has an analog line interface, a synchronization line interface and a digital communication interface for each device.

[0051] The analog line interface connects to AD and DA; the analog line interface is equipped with a master / slave mode switching unit, in which DA is connected to the analog line when it is the master and AD is connected to the analog line when it is the slave;

[0052] Both the master and slave devices have their synchronization line interfaces connected to analog lines;

[0053] The digital communication interface connects all devices in the system.

[0054] The above system implements a method for parallel power balancing correction of electronic loads:

[0055] The analog line interface serves as the synchronization point for control signals between the system host and all slave devices;

[0056] Switch between AD and DA enable based on master / slave mode. When the device is master, enable DA and connect DA to the analog line. When the device is slave, use AD and connect AD to the analog line.

[0057] Through the analog interface and analog line, all devices can be controlled in real time according to the same device, meeting the requirements of high dynamic load switching.

[0058] The synchronization interface is used for power-on / off synchronization and for periodically sending pulses for system time synchronization.

[0059] The digital communication interface corrects the current sharing characteristics between different machines within the system.

[0060] After the digital communication interface is connected, the system performs current sharing calibration and compensation in the following manner:

[0061] When the master device sends the synchronization pulse at the synchronization interface, it periodically sends the current and power values ​​of the master device to the slave device; when the slave device sends the synchronization pulse at the synchronization interface, it periodically calculates the current and power values ​​of the slave device.

[0062] After receiving the value from the master, the slave device compares it with the current value of the slave device and calculates the difference. The slave device's output status variable is then calibrated in real time using the following formula:

[0063] Y = kx + b

[0064] Where x is the current slave current value, y is the actual output value, k is the proportional coefficient, and b is the zero-point bias coefficient;

[0065] Continuously calculate and observe the k and b values ​​to ensure that all slave devices in the system are consistent with the master device.

[0066] In summary, the parallel power equalization correction system and method for electronic loads in this invention integrates analog dynamics and digital compensation in its parallel operation technology, while simultaneously considering dynamic response, current sharing accuracy, and system scalability. This solves the problem that traditional control methods struggle to balance dynamic response, current sharing accuracy, and system scalability.

[0067] To more clearly demonstrate the technical solution and its effects provided by the present invention, the embodiments of the present invention will be described in detail below with reference to specific examples.

[0068] Example 1

[0069] like Figures 1 to 4 As shown:

[0070] Each device has an analog line interface, a synchronous line interface, and a digital communication interface (such as CAN).

[0071] 1. The analog line interface is used for synchronizing control signals of the system host and all slave devices.

[0072] The analog line interface connects to the AD and DA converters; the structure is shown in Figure 1.

[0073] Switch between AD and DA enable based on master / slave mode. When the device is master, enable DA and connect DA to the analog line. When the device is slave, use AD and connect AD to the analog line.

[0074] The master-slave connection method in the system is as follows: Figure 2 As shown. Through the analog interface and analog cable, all devices can be controlled in real time according to the same device, meeting the requirements of high dynamic load switching.

[0075] 2. The connection between the synchronization line and the analog line is the same, such as... Figure 3 As shown.

[0076] The synchronization interface is used for power-on / off synchronization and for periodically sending pulses for system time synchronization.

[0077] 3. Digital communication interfaces (such as CAN) connect all devices in the system, correcting the current sharing characteristics between different machines within the system; their connections are as follows: Figure 4 As shown.

[0078] The factors that cause uneven current distribution in a system can be categorized as follows: 1. Hardware differences and errors; 2. Wiring impedance and layout; 3. Control strategy and communication; 4. Operating point and environment.

[0079] After the digital communication interface is connected, the system operates in the following manner for current sharing calibration and compensation.

[0080] The master device periodically sends the current and power values ​​of the master device to the slave device when the synchronization pulse of the synchronization interface is emitted, and the slave device periodically calculates the current and power values ​​of the slave device when the synchronization pulse of the synchronization interface is emitted.

[0081] After receiving the value from the master, the slave device compares it with the current value of the slave device and calculates the difference. This difference is used to calibrate the slave device's output status variable in real time. The calibration formula can be used as follows:

[0082] Y = kx + b

[0083] Where x is the current slave current value, y is the actual output value, k is the proportional coefficient, and b is the zero-point bias coefficient;

[0084] Continuously calculate and observe the k and b values ​​to ensure that all slave devices in the system are consistent with the master device.

[0085] This method is not limited by the number of parallel units and has high system scalability.

[0086] This invention solves the problem that traditional control methods struggle to balance dynamic response, flow equalization accuracy, and system scalability.

[0087] Key technical points of this invention:

[0088] In the parallel operation scheme, each device has an analog line interface, a synchronization line interface, and a digital communication interface;

[0089] In the parallel operation scheme, each device has an analog line interface and instructions for use;

[0090] In the parallel operation scheme, each device has a synchronization line interface and instructions for use;

[0091] Each device in the parallel operation scheme has a digital communication interface and usage instructions.

[0092] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A parallel power balancing correction system for electronic loads, characterized in that, Each device has an analog line interface, a synchronous line interface, and a digital communication interface; The analog line interface connects to AD and DA; the analog line interface is equipped with a master / slave mode switching unit, in which DA is connected to the analog line when it is the master and AD is connected to the analog line when it is the slave; Both the master and slave devices have their synchronization line interfaces connected to analog lines; The digital communication interface connects all devices in the system.

2. A method for implementing parallel power balancing correction of electronic loads using the system of claim 1, characterized in that: The analog line interface serves as the synchronization point for control signals between the system host and all slave devices; Switch between AD and DA enable based on master / slave mode. When the device is master, enable DA and connect DA to the analog line. When the device is slave, use AD and connect AD to the analog line. Through the analog interface and analog line, all devices can be controlled in real time according to the same device, meeting the requirements of high dynamic load switching. The synchronization interface is used for power-on / off synchronization and for periodically sending pulses for system time synchronization. The digital communication interface corrects the current sharing characteristics between different machines within the system.

3. The method according to claim 2, characterized in that, After the digital communication interface is connected, the system performs current sharing calibration and compensation in the following manner: When the master device sends the synchronization pulse at the synchronization interface, it periodically sends the current and power values ​​of the master device to the slave device; when the slave device sends the synchronization pulse at the synchronization interface, it periodically calculates the current and power values ​​of the slave device. After receiving the value from the master, the slave device compares it with the current value of the slave device and calculates the difference. The slave device's output status variable is then calibrated in real time using the following formula: Y = kx + b Where x is the current slave current value, y is the actual output value, k is the proportional coefficient, and b is the zero-point bias coefficient; Continuously calculate and observe the k and b values ​​to ensure that all slave devices in the system are consistent with the master device.

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