Method and device for running programmable logic controller program and electronic equipment

Abstract

The invention relates to the technical field of industrial control, and provides an operation method and device of a programmable logic controller program and electronic equipment. According to the method, a syntax tree is generated by analyzing a programmable logic controller program; traversing the syntax tree to generate an intermediate code, constructing a time planning model based on the intermediate code, and optimizing the intermediate code according to the time planning model to obtain a target intermediate code; in the running process of the programmable logic controller program, the target intermediate code is compiled in time, and when the programmable logic controller program runs to the target node corresponding to the target intermediate code, the compiled target intermediate code is executed. Structured analysis, time constraint modeling and deterministic immediate compiling execution of the PLC control program are achieved, constraint optimization of the time planning model is combined, the execution time of each intermediate code snippet can be predicted and controlled, and the program operation efficiency and response speed are improved.

Description

Technical Field

[0001] This application relates to the field of industrial control technology, and in particular to a method, apparatus and electronic device for running a programmable logic controller program. Background Technology

[0002] Programmable Logic Controllers (PLCs) are widely used in industrial automation control to perform tasks such as sequential control, logic operations, data processing, signal acquisition, and actuator driving.

[0003] In a typical PLC system, PLC programs are usually executed through interpretation. That is, when the PLC runs, the interpreter parses and executes the control logic such as ladder diagrams (LD), structured text (ST), or function block diagrams (FBD) line by line in the PLC program.

[0004] This method has the advantages of being simple to implement, having clear logic, and being highly deterministic. However, since each instruction needs to be interpreted and executed, its operating efficiency is low, making it difficult to meet the dual requirements of high real-time performance and high performance for complex industrial control tasks. Summary of the Invention

[0005] In view of this, embodiments of this application provide a method, apparatus, and electronic device for running a programmable logic controller (PLC) program, in order to solve the problem of low running efficiency of PLC programs in the prior art.

[0006] A first aspect of this application provides a method for running a programmable logic controller (PLC) program. The method includes: parsing the PLC program to generate a syntax tree; traversing the syntax tree to generate intermediate code, and constructing a time planning model based on the intermediate code. The time planning model is used to determine the execution time distribution and real-time constraints of each basic block in the intermediate code under different paths / tasks; optimizing the intermediate code according to the time planning model to obtain target intermediate code; and, during the execution of the PLC program, performing just-in-time (JIT) compilation on the target intermediate code, and executing the compiled target intermediate code when the PLC program reaches the target node corresponding to the target intermediate code. A second aspect of this application provides a programmable logic controller (PLC) program execution apparatus, comprising: a parsing module for parsing the PLC program and generating a syntax tree; a construction module for traversing the syntax tree to generate intermediate code and constructing a time planning model based on the intermediate code, the time planning model being used to determine the execution time distribution and real-time constraints of each basic block in the intermediate code under different paths / tasks; an optimization module for optimizing the intermediate code according to the time planning model to obtain target intermediate code; and a compilation module for performing just-in-time compilation of the target intermediate code during the execution of the PLC program and executing the compiled target intermediate code when the PLC program reaches the target node corresponding to the target intermediate code.

[0007] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0008] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0009] The beneficial effects of this application's embodiments compared to existing technologies are as follows: The method of this application parses the programmable logic controller (PLC) program to generate a syntax tree; traverses the syntax tree to generate intermediate code, and constructs a time planning model based on the intermediate code. According to the time planning model, the intermediate code is optimized to obtain the target intermediate code. During the execution of the PLC program, the target intermediate code is compiled on demand (JIT), and when the PLC program reaches the target node corresponding to the target intermediate code, the compiled target intermediate code is executed. Through the above scheme, this application achieves structured analysis, time-constraint modeling, and deterministic JIT compilation and execution of PLC control programs. The system can dynamically compile frequently executed logic segments into machine instructions (target intermediate code) that can be directly run on the processor, while ensuring the real-time performance and determinism of the program. This significantly reduces the runtime overhead of syntax parsing, function scheduling, and context switching caused by interpreted execution. Simultaneously, combined with constraint optimization of the time planning model, the execution time of each intermediate code segment is predictable and controllable, effectively avoiding the execution jitter and latency problems introduced by traditional JIT compilation in PLC real-time control scenarios. Therefore, the solution proposed in this application improves the program running efficiency and response speed without affecting the real-time performance and stability of the PLC system. It realizes the lightweight, deterministic, and efficient execution of PLC control logic in an embedded environment, avoiding the problem of low running efficiency of programmable logic controller programs in the prior art. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a method for running a programmable logic controller program according to an embodiment of this application; Figure 2 This is a flowchart illustrating another method for running a programmable logic controller program provided in an embodiment of this application; Figure 3 This is a flowchart illustrating another method for running a programmable logic controller program provided in this application embodiment; Figure 4 This is a schematic diagram of a programmable logic controller program execution system provided in an embodiment of this application; Figure 5 This is a flowchart illustrating another method for running a programmable logic controller program provided in an embodiment of this application; Figure 6 This is a schematic diagram of a programmable logic controller program execution device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, programmable logic controller program execution means, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0013] The following will describe in detail, with reference to the accompanying drawings, a method for running a programmable logic controller (PLC) program and a device for running a PLC program according to embodiments of this application.

[0014] Figure 1 This application provides a method for running a programmable logic controller program, such as... Figure 1 As shown, the method includes: S101. Parse the programmable logic controller program and generate a syntax tree; S102. Traverse the syntax tree to generate intermediate code, and build a time planning model based on the intermediate code. The time planning model is used to determine the execution time distribution and real-time constraints of each basic block in the intermediate code under different paths / tasks. S103. Optimize the intermediate code according to the time planning model to obtain the target intermediate code; S104. During the execution of the programmable logic controller program, the target intermediate code is compiled in real time, and when the programmable logic controller program runs to the target node corresponding to the target intermediate code, the compiled target intermediate code is executed.

[0015] It is understood that the programmable logic controller (PLC) program execution method provided in this embodiment is applied to a PLC operating system or a soft PLC execution platform. The PLC program can be written in various languages ​​such as ladder diagram (LD), function block diagram (FBD), or structured text (ST). During the program loading stage, the system performs syntax analysis on the PLC program source code, identifies syntactic elements such as variable definitions, logical expressions, loop statements, and control structures, and then generates a syntax tree.

[0016] Specifically, PLC control programs are written in languages ​​such as ladder diagrams (LD), function block diagrams (FBD), or structured text (ST). The system first performs language recognition and structure extraction on the input PLC program to determine the hierarchical relationship of each logical unit (such as main program, subroutines, function blocks, global variable tables, etc.) in the PLC program. For multi-language projects, the system uses the standard IEC 61131-3 language description specification for unified identification and encapsulation to enable cross-language analysis in subsequent stages.

[0017] The system uses a built-in lexical analyzer to convert the PLC program's source code into a series of tokens, each token representing a basic semantic unit such as a keyword, operator, variable, or constant. Subsequently, the parser performs syntactic structure matching on the token sequences according to predefined PLC syntax rules (such as assignment, conditional, and loop structure syntax for ST statements), generating a syntax hierarchy tree. For ladder diagram (LD) or function block diagram (FBD) type programs, the system transforms the graphical logic structure into equivalent statement expressions (e.g., converting parallel contacts into logical "OR" structures and series contacts into logical "AND" structures), and uniformly incorporates them into the syntax analysis process.

[0018] After syntax analysis, the system constructs an Abstract Syntax Tree (AST) using a multi-branch tree data structure. Each node corresponds to a syntactic component, such as an expression, statement block, loop body, or conditional statement; leaf nodes correspond to variables, constants, or I / O signals. The AST represents the syntactic logic of the PLC program in a complete tree structure and provides a unified data model for subsequent intermediate code generation and control flow analysis.

[0019] The system further performs semantic checks on the generated syntax tree, including variable scope verification, data type matching, and I / O channel validity verification. It also annotates each node with its type, execution priority, associated resources, and potential real-time constraints. This annotation information will be used for subsequent time planning modeling and execution path analysis.

[0020] Through the above steps, the PLC program is abstracted into an abstract syntax tree in the form of a multi-branch tree. This syntax tree not only reflects the logical hierarchy and control structure of the program, but also retains the necessary semantic information, thus providing a unified structured foundation for subsequent intermediate code generation, execution time analysis, and lightweight JIT optimization.

[0021] After generating the Abstract Syntax Tree (AST), the system uses a depth-first traversal algorithm to go through each node of the AST and generates corresponding intermediate representations (IRs) based on the node type (expression nodes, conditional nodes, loop nodes, I / O nodes, etc.). The generated IRs are divided into several basic blocks, each corresponding to a continuously executing, branchless code sequence. During IR generation, the system automatically identifies and numbers each basic block, recording its entry and exit conditions, control dependencies, and I / O access relationships, thus forming the basic unit for subsequent execution time analysis.

[0022] After generating intermediate code, the system obtains the structural constraints (including nested loop levels, number of branches, path depth, etc.) and functional constraints (including I / O operation cycles, scheduled tasks, external event responses, communication latency, etc.) corresponding to each basic block in the intermediate code. Then, based on these constraints, the system establishes time parameters for instructions / basic blocks (such as the execution cost of each block and the upper bound of loop iterations), and constructs a path analysis problem accordingly: through static analysis (optionally combined with symbolic execution to prune unreachable / constraint-unsatisfied paths), it traverses the set of reachable paths or uses implicit path enumeration (IPET) to solve the problem, calculating the worst-case execution time (WCET) for each path. Finally, the basic block-level time parameters and path-level WCET results are summarized into an Execution Time Planning Model, which describes the execution time distribution and real-time constraints of the program under different paths / tasks, and serves as the basis for subsequent optimization and scheduling.

[0023] Based on the time planning model, the intermediate code is optimized to obtain the target intermediate code. This ensures that the execution time of each basic block of the target intermediate code meets the real-time constraints in the time planning model, thereby guaranteeing the deterministic and predictable execution of the target intermediate code during runtime. This avoids periodic jitter or task timeouts caused by execution time fluctuations, and enables the programmable logic controller program to run efficiently and stably while meeting real-time requirements.

[0024] In some examples, during the execution of the programmable logic controller (PLC) program, the target intermediate code is compiled using Just-In-Time (JIT) compilation. When the PLC program reaches the target node corresponding to the target intermediate code, the system atomically switches from interpreted execution mode to JIT execution mode and executes the compiled target intermediate code. Because the JIT compilation process occurs in the background and runs in parallel with the main control task, it does not block the PLC main loop or affect the real-time performance of the control cycle. By asynchronously executing JIT compilation in the background, instructions that originally required interpretation can be converted into machine instructions that can be directly executed on the processor, and the execution path of the compiled code is atomically switched when the program reaches the target node. This approach not only ensures the determinism and consistency of the switching process, avoiding runtime state anomalies and cycle delays, but also significantly reduces runtime overhead such as syntax parsing, function calls, and interpretation scheduling.

[0025] Meanwhile, the JIT compiler can perform optimizations such as register allocation, constant folding, strength reduction, and instruction merging during the generation of machine instructions, effectively reducing instruction parsing latency and context switching frequency, and improving CPU execution efficiency and system throughput. Therefore, this method achieves efficient operation and fast response of PLC programs while ensuring program real-time performance and determinism.

[0026] According to the above-mentioned scheme provided in this application, the programmable logic controller (PLC) program is parsed to generate a syntax tree; the syntax tree is traversed to generate intermediate code, and a time planning model is constructed based on the intermediate code. The intermediate code is then optimized according to the time planning model to obtain the target intermediate code. During the execution of the PLC program, the target intermediate code is compiled on demand (JIT), and when the PLC program reaches the target node corresponding to the target intermediate code, the compiled target intermediate code is executed. Through this scheme, this application achieves structured analysis, time-constrained modeling, and deterministic JIT compilation and execution of PLC control programs. The system can dynamically compile frequently executed logic segments into machine instructions (target intermediate code) that can be directly run on the processor, while ensuring the real-time performance and determinism of the program. This significantly reduces the runtime overhead of syntax parsing, function scheduling, and context switching caused by interpreted execution. Simultaneously, combined with constraint optimization of the time planning model, the execution time of each intermediate code segment is predictable and controllable, effectively avoiding the execution jitter and latency problems introduced by traditional JIT compilation in PLC real-time control scenarios. Therefore, the solution proposed in this application improves the program running efficiency and response speed without affecting the real-time performance and stability of the PLC system. It realizes the lightweight, deterministic, and efficient execution of PLC control logic in an embedded environment, avoiding the problem of low running efficiency of programmable logic controller programs in the prior art.

[0027] In some examples, such as Figure 2 As shown, based on the time planning model, the intermediate code is optimized to obtain the target intermediate code, including: S201. Determine the estimated execution time for each basic block in the intermediate code; S202. When the expected execution time of any basic block in the intermediate code exceeds the constraint time in the time planning model, the code segment corresponding to the basic block is decomposed and optimized to generate target intermediate code whose execution time meets the constraints of the time planning model. The optimization process includes at least one of loop unrolling, loop block splitting, or conditional branch splitting.

[0028] Specifically, the system estimates the execution time of each basic block in the intermediate code based on the execution time parameters established in the time planning model, determining its worst-case execution time (WCET). This step is used to identify basic blocks or paths whose execution time may exceed real-time constraints, providing a basis for subsequent optimization.

[0029] When the estimated execution time of any basic block exceeds the time constraint in the time planning model, decomposition and optimization are performed. When it is detected that the estimated execution time of a basic block exceeds the real-time constraint time set by the time planning model, the system decomposes and structurally optimizes the code segment corresponding to that basic block to generate target intermediate code whose execution time meets the constraints of the time planning model. The optimization process may include at least one of the following methods: Loop unrolling: The loop body is copied multiple times to reduce loop control overhead; Loop Tiling / Chunking: Divide the loop body into multiple controllable execution segments according to the time budget, so that the execution time of each segment is within the real-time range; Branch Splitting: This technique splits complex conditional branch structures into multiple independent branch blocks to reduce path complexity and balance the execution time of each path.

[0030] Through the above optimization methods, code segments with excessively long execution times or complex paths can be reorganized into multiple code units with finer granularity and predictable execution times, thereby enabling the optimized target intermediate code as a whole to meet the real-time constraints in the time planning model.

[0031] The above-described solution provided in this application determines the expected execution time of each basic block in the intermediate code. When the expected execution time of any basic block in the intermediate code exceeds the constraint time in the time planning model, the code segment corresponding to that basic block is decomposed and optimized to generate target intermediate code whose execution time meets the constraints of the time planning model. The above solution decomposes code segments with uncertain execution time into controllable target intermediate code through static analysis and structured optimization based on the time planning model, so as to ensure the real-time performance and determinism of the program during runtime.

[0032] In some examples, such as Figure 3 As shown, the code snippet corresponding to the basic block is decomposed and optimized, including: S301. Generate a control flow diagram based on intermediate code. The control flow diagram is used to represent the control flow transfer relationship between each basic block in the intermediate code. S302. Based on the control flow transfer relationship, decompose and optimize the code segment corresponding to the basic block to generate target intermediate code whose execution time meets the constraints of the time planning model.

[0033] Specifically, the system constructs a Control Flow Graph (CFG) based on the logical structure and jump information of the intermediate code. The CFG represents the control flow transfer relationships between the basic blocks in the intermediate code, including structures such as sequential execution, branch jumps, and loop back edges. Through the CFG, the execution paths and dependencies of each logical block in the program can be clearly defined, providing a structured basis for subsequent fragment decomposition and optimization.

[0034] The system performs decomposition and optimization based on the control flow transfer relationships. According to the branch paths, loop levels, and execution order identified in the control flow diagram, the system decomposes and optimizes the code segments corresponding to basic blocks whose execution time exceeds the constraints of the time planning model, generating target intermediate code whose execution time meets the constraints of the time planning model. Optimization processes may include loop unrolling, loop block splitting, conditional branch splitting, or path rearrangement to reduce the time complexity of individual execution segments and ensure that the optimized target intermediate code can execute stably under real-time and deterministic constraints.

[0035] The above-mentioned solution provided in the embodiments of this application generates a control flow relationship diagram based on intermediate code; and decomposes and optimizes the code segment corresponding to the basic block according to the control flow transfer relationship to generate target intermediate code whose execution time meets the constraints of the time planning model, thereby generating target intermediate code whose execution time is controllable and meets the constraints of the time planning model.

[0036] In some examples, when the programmable logic controller (PLC) program reaches the target node corresponding to the target intermediate code, the compiled target intermediate code is executed. This includes monitoring the running status of the PLC program; when the PLC program reaches a safe point (such as the end of a scan cycle) and reaches the target node corresponding to the target intermediate code, the interpreted execution mode is switched to just-in-time (JIT) execution mode to execute the compiled target intermediate code. The system continuously monitors the running status of the PLC program to obtain the current execution progress and cycle information; when it detects that the PLC program has reached a preset safe point and reached the target node corresponding to the target intermediate code, the system atomically switches from interpreted execution mode to JIT execution mode and executes the compiled target intermediate code.

[0037] By performing atomic switching at safe points, the determinism and consistency of the execution mode switching process can be guaranteed, avoiding abnormal operating status, control cycle jitter, or task delays caused by switching at unsafe times. This allows for efficient execution of optimized code while maintaining the real-time performance and stability of the PLC system.

[0038] In some examples, this method further includes: monitoring the actual execution time and resource consumption of the compiled target intermediate code during execution; if the actual execution time of the target intermediate code exceeds the constraint time in the time planning model, or the actual resource consumption of the target intermediate code exceeds a pre-set resource threshold, then switching from just-in-time (JIT) compilation execution mode to interpreted execution mode to rerun the programmable logic controller (PLC) program. Through this monitoring and rollback mechanism, abnormal situations caused by changes in external load, optimization deviations, or insufficient resources can be detected in a timely manner during operation, ensuring that the system automatically recovers to a safe interpreted execution state when real-time deviations occur, thereby continuously guaranteeing the deterministic execution of the PLC program and the stability of the system.

[0039] In some examples, the target intermediate code is compiled just-in-time (JIT) during the execution of the programmable logic controller (PLC) program. This includes: compiling the target intermediate code during idle periods of the PLC program execution, and / or, asynchronously compiling the target intermediate code in a low-priority thread of the PLC. By performing JIT compilation during idle periods or in low-priority threads, the dynamic compilation of the target intermediate code can be completed without interrupting the execution of the main control loop. This avoids the JIT compilation process from blocking or delaying the PLC's periodic tasks, ensuring the system's real-time performance and the determinism of task scheduling.

[0040] Based on the same concept, this application also provides a programmable logic controller (PLC) program execution system, which includes the following modules: (1) Abstract syntax tree and intermediate code generation module Function: Parses multi-language PLC source programs (ladder diagrams, FBD, ST, etc.) into a unified abstract syntax tree, generating platform-independent intermediate code.

[0041] Input: PLC multilingual source program.

[0042] Output: Abstract syntax tree and intermediate code, for subsequent analysis and optimization.

[0043] (2) Control flow analysis and constraint modeling module Functionality: Based on the abstract syntax tree / intermediate code, construct a control flow graph, extract structural and functional constraints, and establish an execution time planning model.

[0044] Input: Abstract syntax tree, intermediate code.

[0045] Outputs: Control flow graph, constraint model, and analysis results, for use by the optimization module.

[0046] (3) Code snippet decomposition and optimization module Function: Decompose code snippets that time out or do not meet constraints (such as loop unrolling, block splitting, and branch splitting), optimize the execution path, and generate optimized intermediate code and configuration.

[0047] Inputs: Control flow analysis results, constraint model.

[0048] Output: Optimized intermediate code and configuration for use by the JIT compiler module.

[0049] Intermediate code typically has the following characteristics: It is structured and platform-independent, which facilitates subsequent optimization and target code generation.

[0050] It clearly reflects information such as each functional block, control flow, data flow, and resource dependencies.

[0051] It supports static analysis (such as execution path and worst-case execution time analysis) and dynamic optimization (such as hotspot code identification and fragment decomposition).

[0052] It facilitates the insertion of metadata such as execution constraints and monitoring points.

[0053] Optimize configuration: This refers to the configuration data generated for JIT optimization parameters, switching strategies, execution time constraints, etc., based on the target PLC platform, real-time / deterministic requirements, resource constraints, etc.

[0054] Mainly includes: Execution time budget, priority, and scheduling strategy for each code segment.

[0055] JIT triggering conditions, optimization granularity, switching safety points, and other parameters.

[0056] Resource dependencies, required external libraries / drivers, and target platform compatibility information.

[0057] Runtime monitoring and adaptive adjustment of thresholds, rollback strategies, etc.

[0058] (4) PLC main control process module Function: Responsible for PLC main loop scheduling, periodic execution of control tasks, and driving interpreter / JIT module.

[0059] Inputs: PLC source program, external I / O signals, runtime status.

[0060] Output: Drives / calls the interpreter and JIT compiler modules, generating control instructions and status feedback.

[0061] (5) Interpreter and JIT Compiler Module Functions: Interpret and execute PLC programs, monitor hot code, receive and optimize intermediate code / configuration, and perform JIT compilation and optimization switching.

[0062] Input: PLC main control flow calls, optimization of intermediate code / configuration.

[0063] Output: Execution results, optimized code, and status information, for use by the main process and monitoring module.

[0064] JIT optimization result switching and execution monitoring module (runtime implementation) Functionality: Monitor code execution at runtime, detect JIT optimization results, safely switch to optimized code atomically, and dynamically adjust JIT strategies.

[0065] Inputs: Execution status of the interpreter / JIT module, optimized code, and monitoring data.

[0066] Output: Execution results, monitoring reports, and feedback information after the switch, for reference by the main process and JIT module.

[0067] To better illustrate the operation method of the programmable logic controller program provided in this application, a more specific example is also provided, such as... Figure 5 As shown, it includes the following steps: 1. Abstract Syntax Tree Construction and Traversal The abstract syntax tree of the PLC program is traversed using a multi-branch tree depth-first search algorithm, transforming it into a compilable intermediate code file and constructing the program's control flow diagram. This process is completed during the configuration software stage, ensuring an accurate structural basis for subsequent analysis and optimization.

[0068] 2. Symbolic execution and abstract interpretation By employing symbolic execution and abstract interpretation techniques, the program's execution logic and path constraints are automatically extracted, and the execution conditions of each branch and loop are analyzed. Through static analysis, all possible execution paths are identified in advance, providing data support for subsequent time modeling and optimization.

[0069] 3. Establishment of a multi-constraint execution time planning model Structural constraints (such as nested loops and branching structures) and functional constraints (such as I / O operations and scheduled tasks) are extracted from the control logic code to establish a multi-constraint execution time planning model. For each basic block, branch, and loop, a mathematical model is established based on the above constraints to analyze the worst-case execution time (WCET) and determine the execution frequency of each basic block. This model provides a theoretical basis for subsequent real-time optimization and scheduling.

[0070] 4. Code snippet decomposition and optimization For code segments that exceeded execution time constraints identified in the analysis, further decomposition was performed using methods such as loop unrolling (copying the loop body multiple times), loop splitting (breaking large loops into multiple smaller loops), and conditional branch splitting (breaking complex branches into simpler branches). By breaking large blocks of code into smaller segments, the execution time of each segment became controllable, facilitating subsequent scheduling, analysis, and JIT optimization, and ensuring that all segments met real-time constraints.

[0071] 5. Deterministic JIT Optimization and Switching The JIT optimization process is executed asynchronously during PLC idle cycles or in low-priority threads, with the main control flow only undergoing atomic switching at safe points such as the end of a scan cycle. This strict switching mechanism ensures that the JIT optimization process does not affect the determinism and consistency of the main flow, enabling smooth integration of the optimized code.

[0072] 6. Execution monitoring and adaptive adjustment The system continuously monitors the actual execution time and resource consumption of each code segment during runtime. If a code segment times out or fails to meet the requirements, the system dynamically adjusts the JIT optimization strategy and optimization granularity, or reverts to interpreted execution, ensuring that the system always meets real-time and deterministic requirements. This mechanism enhances the system's adaptability and robustness.

[0073] This invention, through structured analysis and multi-constraint modeling, can precisely control the impact of the JIT optimization process on the PLC main flow, avoiding execution jitter and uncontrollable delays. By re-decomposing code snippets and employing a deterministic switching mechanism, it ensures that all optimized code snippets meet real-time and deterministic requirements, improving the PLC program's operating efficiency and the system's safety and stability.

[0074] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0075] Based on the same concept, this application also provides a device for running a programmable logic controller program, such as... Figure 6 As shown, the programmable logic controller (PLC) program execution device includes: Parsing module 601 is used to parse programmable logic controller programs and generate syntax trees; Module 602 is used to traverse the syntax tree to generate intermediate code and build a time planning model based on the intermediate code. The time planning model is used to determine the execution time distribution and real-time constraints of each basic block in the intermediate code under different paths / tasks. Optimization module 603 is used to optimize intermediate code according to the time planning model to obtain target intermediate code; The compiler module 604 is used to perform just-in-time compilation of the target intermediate code during the execution of the programmable logic controller program, and to execute the compiled target intermediate code when the programmable logic controller program runs to the target node corresponding to the target intermediate code.

[0076] In some examples, a time planning model is built based on intermediate code, including: obtaining the structural and functional constraints corresponding to each basic block in the intermediate code; and building a time planning model based on the structural and functional constraints corresponding to each basic block.

[0077] In some examples, intermediate code is optimized according to the time planning model to obtain target intermediate code, including: determining the expected execution time of each basic block in the intermediate code; when the expected execution time of any basic block in the intermediate code exceeds the constraint time in the time planning model, the code segment corresponding to the basic block is decomposed and optimized to generate target intermediate code whose execution time meets the constraints of the time planning model. The optimization process includes at least one of loop unrolling, loop block division, or conditional branching.

[0078] In some examples, the code segment corresponding to the basic block is decomposed and optimized, including: generating a control flow diagram based on the intermediate code, which is used to represent the control flow transfer relationship between each basic block in the intermediate code; and decomposing and optimizing the code segment corresponding to the basic block according to the control flow transfer relationship to generate target intermediate code whose execution time meets the constraints of the time planning model.

[0079] In some examples, when the programmable logic controller (PLC) program reaches the target node corresponding to the target intermediate code, the compiled target intermediate code is executed. This includes: monitoring the running status of the PLC program; when the PLC program reaches a safe point and reaches the target node corresponding to the target intermediate code, switching the interpreted execution mode to the just-in-time (JIT) compilation execution mode to execute the compiled target intermediate code.

[0080] In some examples, the device is also used to monitor the actual execution time and actual resource consumption of the target intermediate code during the execution of the compiled target intermediate code; if the actual execution time of the target intermediate code exceeds the constraint time in the time planning model, or the actual resource consumption of the target intermediate code exceeds the preset resource threshold, the just-in-time compilation execution mode is switched to the interpreted execution mode to rerun the programmable logic controller program.

[0081] In some examples, the target intermediate code is compiled just-in-time (JIT) during the execution of the programmable logic controller (PLC) program, including: compiling the target intermediate code just-in-time during idle periods of PLC program execution, and / or compiling the target intermediate code just-in-time asynchronously in a low-priority thread of the PLC.

[0082] According to the solution provided in this application, a syntax tree is generated by parsing the programmable logic controller (PLC) program; intermediate code is generated by traversing the syntax tree; a time planning model is constructed based on the intermediate code; the intermediate code is optimized according to the time planning model to obtain the target intermediate code; during the execution of the PLC program, the target intermediate code is compiled in real-time; and when the PLC program reaches the target node corresponding to the target intermediate code, the compiled target intermediate code is executed. Through the above solution, this application realizes structured analysis, time constraint modeling, and deterministic just-in-time compilation and execution of PLC control programs. The system can dynamically compile frequently executed logic segments into machine instructions (target intermediate code) that can be directly run on the processor, while ensuring the real-time performance and determinism of the program. This significantly reduces the runtime overhead of syntax parsing, function scheduling, and context switching caused by interpreted execution. Simultaneously, combined with constraint optimization of the time planning model, the execution time of each intermediate code segment is predictable and controllable, effectively avoiding the execution jitter and latency problems introduced by traditional JIT compilation in PLC real-time control scenarios. Therefore, the solution proposed in this application improves the program running efficiency and response speed without affecting the real-time performance and stability of the PLC system. It realizes the lightweight, deterministic, and efficient execution of PLC control logic in an embedded environment, avoiding the problem of low running efficiency of programmable logic controller programs in the prior art.

[0083] Figure 7 This is a schematic diagram of the electronic device 7 provided in an embodiment of this application. Figure 7 As shown, the electronic device 7 of this embodiment includes: a processor 701, a memory 702, and a computer program 703 stored in the memory 702 and executable on the processor 701. When the processor 701 executes the computer program 703, it implements the steps in the various method embodiments described above. Alternatively, when the processor 701 executes the computer program 703, it implements the functions of each module / unit in the various programmable logic controller program execution device embodiments described above.

[0084] Electronic device 7 can be a desktop computer, laptop, handheld computer, cloud server, or other electronic device. Electronic device 7 may include, but is not limited to, processor 701 and memory 702. Those skilled in the art will understand that... Figure 7 This is merely an example of electronic device 7 and does not constitute a limitation on electronic device 7. It may include more or fewer components than shown, or different components.

[0085] The processor 701 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0086] The memory 702 can be an internal storage unit of the electronic device 7, such as a hard disk or RAM of the electronic device 7. The memory 702 can also be an external storage device of the electronic device 7, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc., equipped on the electronic device 7. The memory 702 can also include both internal and external storage units of the electronic device 7. The memory 702 is used to store computer programs and other programs and data required by the electronic device.

[0087] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed. That is, the internal structure of the programmable logic controller (PLC) program's execution device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0088] If an integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program may include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium may include: any entity or programmable logic controller program capable of carrying computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in a computer-readable medium can be appropriately added or removed according to regional requirements and patent practice requirements. For example, in some regions, according to regional requirements and patent practice, a computer-readable medium may not include electrical carrier signals and telecommunication signals.

[0089] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for running a programmable logic controller (PLC) program, characterized in that, The method includes: Parse the programmable logic controller program and generate a syntax tree; The syntax tree is traversed to generate intermediate code, and a time planning model is constructed based on the intermediate code. The time planning model is used to determine the execution time distribution and real-time constraints of each basic block in the intermediate code under different paths / tasks. Based on the time planning model, the intermediate code is optimized to obtain the target intermediate code; During the execution of the programmable logic controller program, the target intermediate code is compiled in real time, and when the programmable logic controller program runs to the target node corresponding to the target intermediate code, the compiled target intermediate code is executed.

2. The method according to claim 1, characterized in that, Based on the intermediate code, a time planning model is constructed, including: Obtain the structural and functional constraints corresponding to each basic block in the intermediate code; The time planning model is constructed based on the structural constraints and functional constraints corresponding to each basic block.

3. The method according to claim 1, characterized in that, Based on the time planning model, the intermediate code is optimized to obtain the target intermediate code, including: Determine the estimated execution time for each basic block in the intermediate code; When the expected execution time of any basic block in the intermediate code exceeds the constraint time in the time planning model, the code segment corresponding to the basic block is decomposed and optimized to generate the target intermediate code whose execution time meets the constraints of the time planning model. The optimization process includes at least one of loop unrolling, loop block splitting, or conditional branch splitting.

4. The method according to claim 3, characterized in that, The code snippet corresponding to this basic block is decomposed and optimized, including: A control flow graph is generated based on the intermediate code, and the control flow graph is used to characterize the control flow transfer relationship between each basic block in the intermediate code. Based on the control flow transfer relationship, the code segment corresponding to the basic block is decomposed and optimized to generate the target intermediate code whose execution time satisfies the constraints of the time planning model.

5. The method according to claim 1, characterized in that, When the programmable logic controller program reaches the target node corresponding to the target intermediate code, the compiled target intermediate code is executed, including: The programmable logic controller (PLC) program is monitored. When the PLC program reaches a safe point and the PLC program reaches the target node corresponding to the target intermediate code, the interpreted execution mode is switched to just-in-time (JIT) compilation execution mode to execute the compiled target intermediate code.

6. The method according to claim 1, characterized in that, The method further includes: During the execution of the compiled target intermediate code, the actual execution time and actual resource consumption of the target intermediate code are monitored; If the actual execution time of the target intermediate code exceeds the constraint time in the time planning model, or if the actual resource consumption of the target intermediate code exceeds the preset resource threshold, the just-in-time compilation execution mode will be switched to the interpreted execution mode to rerun the programmable logic controller program.

7. The method according to claim 1, characterized in that, During the execution of the programmable logic controller program, the target intermediate code is compiled on the fly, including: During the idle period of the programmable logic controller program execution, the target intermediate code is compiled on the fly, and / or, In a low-priority thread of the programmable logic controller, the target intermediate code is asynchronously compiled just-in-time.

8. A device for running a programmable logic controller program, characterized in that, The programmable logic controller (PLC) program execution device includes: The parsing module is used to parse programmable logic controller (PLC) programs and generate syntax trees. A construction module is used to traverse the syntax tree to generate intermediate code and build a time planning model based on the intermediate code. The time planning model is used to determine the execution time distribution and real-time constraints of each basic block in the intermediate code under different paths / tasks. An optimization module is used to optimize the intermediate code according to the time planning model to obtain the target intermediate code; The compilation module is used to perform just-in-time compilation of the target intermediate code during the execution of the programmable logic controller program, and to execute the compiled target intermediate code when the programmable logic controller program runs to the target node corresponding to the target intermediate code.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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