Control method and device for improving data access speed of DDR (Double Data Rate) chip

Abstract

The invention relates to the technical field of data access speed control, and discloses a control method and device for improving the data access speed of a DDR chip, and the method comprises the steps: obtaining a memory data fragment, reading, analyzing and generating a visual graph, and obtaining data repeatability and a spatial distribution diagram; calculating the similarity of fields in the graph, and screening out a high-repetition field concentration region; if the continuity of the area field address is lower than a threshold value, rearranging the field to a continuous memory block to form a data layout structure; extracting a target field position of the access request from the layout, judging whether the target field position is in a continuous memory block and planning an access path to obtain a path planning result; clustering and grouping access sequences of related fields in the path, optimizing a skipping and reading sequence, and determining a skipping and reading sequence; if the sequence has a dynamic change, updating the clustering group to obtain an adjusted access sequence; and loading the memory block data according to the sequence, and judging a loading time optimization state to obtain an optimized access response. The method can solve the problem of low access response speed.

Description

Technical Field

[0001] This invention relates to the field of data access speed control technology, and in particular to a control method and apparatus for improving the data access speed of DDR chips. Background Technology

[0002] Currently, in the field of modern information technology, improving memory access speed has a crucial impact on overall system performance. Whether it's everyday personal devices or high-performance computing platforms, the efficiency of data reading and storage in intelligent chips, which are the core carriers of computing power, directly determines user experience and task processing capabilities.

[0003] In one existing technology, memory access optimization techniques are employed, primarily focusing on hardware upgrades, static caching strategies, and fixed-granularity data compression. Priority is given to improving basic memory access performance through hardware iterations. At the software level, the classic LRU caching algorithm is used to manage memory data. To address the issue of data redundancy in memory, a fixed-granularity block-level compression scheme is used to compress memory data into blocks. A hash algorithm is used to calculate the hash value of each data block. A hash index table is established; if duplicate data blocks with the same hash value are detected, only one original data block is retained, and the remaining duplicate blocks are stored as reference pointers. During data access, data is loaded in blocks. If the target data is distributed across multiple blocks, multiple blocks are loaded sequentially to complete data concatenation.

[0004] However, existing technologies separate compression and deduplication from data access into independent processes. Compression only focuses on whether data is duplicated, without considering the spatial distribution of duplicate data; access only focuses on whether data is in the cache, without optimizing the loading path of duplicate data. Ultimately, even if duplicate data is compressed, its physical distribution remains highly discrete, requiring frequent jumps during access, failing to fundamentally reduce latency and energy consumption. In industrial-grade high-load scenarios, the static eviction rule of LRU cannot adjust the cache capacity ratio or the granularity of compression blocks. The system can only passively endure the vicious cycle of "cache miss - main memory access - increased latency," resulting in low resource utilization and a continuous decline in stability as the load increases. In summary, existing technologies suffer from slow access response speeds. Summary of the Invention

[0005] This invention provides a control method and apparatus for improving the data access speed of DDR chips, thereby solving the problem of low resource utilization in the prior art.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a control method for improving the data access speed of a DDR chip, comprising: The system retrieves the location of the target field in the access request and the data fragments stored in memory, performs reading and analysis, generates a visual distribution graph, and obtains a data redundancy and spatial distribution map. Calculate the data repetition and the similarity of fields in the spatial distribution map, and determine the continuous distribution of field addresses based on the similarity to obtain the concentrated area of ​​highly repetitive fields; If the continuity of the mapped addresses of fields in the high-repetition field set area is lower than a preset mapping compactness threshold, then the data layout structure is obtained by rearranging the fields into contiguous memory blocks. Determine whether the target field is located in a contiguous memory block of the data layout structure, plan the access path, and obtain the access path planning result; The access sequences of relevant fields in the access path planning results are clustered and grouped, and the jump and reading order is optimized to obtain the reading order with the minimum jump. If the reading order involves dynamic changes, the clustering grouping of the access sequence is updated to obtain an adjusted access sequence; Based on the adjusted access sequence, the field data in the corresponding memory block is loaded, the time optimization status is determined, and the optimized access response is obtained.

[0007] In a second aspect, the present invention provides a control device for improving the data access speed of a DDR chip, comprising: The data acquisition module is used to acquire the location of the target field in the access request and the data fragments stored in memory, and to read and analyze them to generate a visual distribution graph and obtain a data redundancy and spatial distribution map. The data calculation module is used to calculate the data repetition and the similarity of fields in the spatial distribution map, and to determine the continuous distribution of field addresses based on the similarity to obtain the concentrated area of ​​highly repetitive fields; The data arrangement module is used to rearrange the fields into consecutive memory blocks to obtain a data layout structure if the mapping address continuity of the fields in the high repetition field set area is lower than a preset mapping compactness threshold. The path planning module is used to determine whether the target field is located in a contiguous memory block of the data layout structure, and to plan the access path to obtain the access path planning result. The data optimization module is used to cluster and group the access sequences of relevant fields in the access path planning results, and optimize the jump and reading order to obtain the reading order with the fewest jumps; The data update module is used to update the clustering grouping of the access sequence to obtain an adjusted access sequence if the reading order includes dynamic changes. The data judgment module is used to load field data in the corresponding memory block according to the adjusted access sequence, determine the time optimization status, and obtain the optimized access response.

[0008] Compared with the prior art, the present invention has the following beneficial effects: (1) If the high repetition field concentration area located by this method has a mapping address continuity lower than the threshold, the scattered repetitive / highly similar fields are migrated to continuous memory blocks by adjusting the group boundary, compressing the field interval, and integrating memory blocks. Compared with the existing technology, fixed block-level compression only reduces storage occupation and does not solve the problem of distributed dispersion. It eliminates the core problem of cross-address jump of related data from the physical layout level, reduces the number of access jumps by 60%-70%, and reduces the single field access latency.

[0009] (2) This method collects data access frequency and load distribution status in real time. If the reading order becomes discrete due to load changes, it automatically updates the clustering group and adjusts the access sequence, and migrates high-frequency access fields to low-congestion continuous memory blocks. Compared with the existing technology, the cache hit rate drops sharply and the latency soars under high load. This method maintains a high cache hit rate under high load scenarios, breaks through the adaptation bottleneck of static strategies, ensures system stability under complex dynamic scenarios, and controls the fluctuation range of response speed within a very small range. Attached Figure Description

[0010] Figure 1 This is a schematic flowchart of a control method for improving data access speed of DDR chips provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the control device structure for improving the data access speed of DDR chips provided in the second embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Reference Figure 1 The first embodiment of the present invention provides a control method for improving the data access speed of a DDR chip, comprising the following steps: S11, obtain the location of the target field in the access request and the data fragments stored in memory, and perform reading and analysis to generate a visual distribution graph and obtain a data redundancy and spatial distribution map; S12, calculate the data repetition and the similarity of the fields in the spatial distribution map, and determine the continuous distribution of the field addresses based on the similarity to obtain the concentrated area of ​​highly repetitive fields; S13, if the mapping address continuity of the fields in the high repetition field set area is lower than the preset mapping compactness threshold, then the data layout structure is obtained by rearranging the fields into consecutive memory blocks; S14, determine whether the target field is located in a contiguous memory block of the data layout structure, and plan the access path to obtain the access path planning result; S15, cluster the access sequences of relevant fields in the access path planning result, optimize the jump and reading order, and obtain the reading order with the minimum jump. S16, if the reading order includes dynamic changes, then update the clustering group of the access sequence to obtain an adjusted access sequence; S17, Load the field data in the corresponding memory block according to the adjusted access sequence, determine the time optimization status, and obtain the optimized access response.

[0013] It should be noted that, unless otherwise specified, in this invention, addresses refer to the physical memory addresses of the DDR chip, that is, directly corresponding to the addressing space of the memory controller; mapped addresses specifically refer to the logical addresses converted by the operating system page tables, but the optimization process in this invention is based on physical address operations, and logical addresses are only used for initial request parsing; to avoid confusion, physical address descriptions are used uniformly in the text.

[0014] In step S11, obtaining the target field location in the access request and the data fragment stored in memory, and performing read analysis to generate a visual distribution graph, thereby obtaining a data redundancy and spatial distribution map, includes: From the data segments, extract the byte content and corresponding physical address information of each data segment, compare the data segments with the same byte content, and obtain a preliminary set of repeated fields and corresponding location distribution records; A deep validation is performed on the duplicate fields in the initial set of duplicate fields. If the validation results show that the field content is completely consistent, it is determined to be the final set of duplicate fields, and the physical address of the duplicate fields in memory is recorded to obtain the location distribution data. Generate statistical charts and spatial distribution graphs of data repetition for the final set of repeating fields and the location distribution data, classify and label the distribution characteristics in the statistical charts, and obtain the data repetition and spatial distribution map.

[0015] It should be noted that the target field identification information is parsed from the access request. This target field identification information includes the field ID / field path, the data structure identifier, the field offset, and the field length. The logical location information of the target field is retrieved from the field metadata mapping table based on this identification information. The logical location information is then converted into the physical location information corresponding to the DDR memory based on the address mapping relationship, obtaining the physical page frame number and the starting address and length of the page offset or continuous physical address range. The physical address range is then aligned and divided into blocks according to a preset data block size to obtain the target field location for reading and analysis. A dedicated scanning module developed based on the DDR chip memory controller interface reads the DDR chip memory space block by block at a rate of "64 bytes / data block" (adapting to the smallest data transmission unit of the DDR chip to avoid latency caused by cross-block reading), with a sampling frequency of 10 seconds / time (balancing real-time performance and system resource consumption). The collected content includes the data block byte content, the corresponding physical address, and the sampling timestamp. The data is stored in a structured format of "data block ID-byte content-physical address-timestamp" in the local cache. For all collected data blocks, a byte-by-byte XOR comparison method is used to determine the consistency of the content. If the XOR result of 64 bytes of two data blocks is 0 (i.e., the content of each byte is exactly the same), they are marked as suspected duplicate data blocks. After traversing all data blocks, the suspected duplicate data blocks are classified according to their byte content to form a preliminary set of duplicate fields. At the same time, the physical address list corresponding to each field is recorded to obtain the location distribution record.

[0016] For each field in the initial set of repeating fields, the hash value of its byte content is calculated using the SHA-256 hash algorithm (ensuring a hash collision rate ≤ 10). -18 If all data blocks in the same set have completely identical SHA-256 hash values, they are considered to be completely duplicated. If there are data blocks with inconsistent hash values, further random sampling is used for re-examination (10 non-contiguous bytes are extracted from the data block for byte-by-byte comparison) to eliminate misjudgments caused by scanning errors. Finally, fields with 100% identical content are selected to form the final set of duplicate fields. For each field in the final set of duplicate fields, all its physical addresses in memory (accurate to bytes), the collection timestamp of each address, and the address interval are recorded to form location distribution data.

[0017] The final set of repeating fields and their location distribution data are visualized. In one embodiment, the DDR memory controller or its built-in driver firmware generates the visualized graphical data. The memory controller maps the density matrix to a predefined address-color encoding table (e.g., high density = red code 0xFF0000, medium density = yellow code 0xFFFF00) through its integrated state machine and hardware cache. The system's built-in monitoring interface directly reads this encoding table and coordinate parameters to drive the chip-level micro-display or system-level monitoring terminal to generate a basic heatmap by filling pixels. External software rendering is only an optional supplement during the debugging period and is not a necessary step during runtime. The hardware cache is a dedicated graphics cache area integrated inside the memory controller (usually 4-8KB in size), and its access priority is lower than that of the main data channel to ensure that it does not affect normal memory access performance.

[0018] Specifically, the controller organizes the repetitive statistics results into a structured data table of 'field ID - repetition count - physical address density', and encodes the spatial distribution information into a density matrix binned by physical address range (e.g., 1MB). The rows of this matrix correspond to the address range index, and the columns correspond to the repetitive field count or density value. The density value is mapped to a specific display attribute code (e.g., color intensity, grayscale level) through a pre-built lookup table (LUT) inside the controller, thereby forming a visual graphic data containing coordinate range, data matrix and display parameters.

[0019] The generation of the visualized graphical data relies on the lightweight graphics processing unit (GPU) or fixed-function shader embedded in the memory controller, which converts the data matrix into a display list and outputs it through a standard display interface (such as MIPI DSI). A bar chart is generated with "Field ID" as the horizontal axis and "Number of Repetitions (Physical Address Count)" as the vertical axis, marking the number of repetitions for each field. Different colors are used to distinguish between "high-frequency repetition (≥5 times), medium-frequency repetition (2-4 times), and low-frequency repetition (1 time, i.e., no repetition)," generating a data repetition statistics chart. A heatmap is generated with the DDR chip memory physical address as the horizontal axis (divided into 1MB units) and "Field Repetition Density (Number of Repeating Fields per Unit Address Segment)" as the vertical axis, with red marking "High-Density Repetition Areas" (≥3 repeating fields per unit address segment) and blue marking "Low-Density Areas" (≤1 repeating field per unit address segment), generating a spatial distribution graph.

[0020] In the statistical charts, annotate the "core repetitive scenarios" for each field and mark the repetitive features based on the business attributes of the field's byte content; in the heatmap, select the address range of the "high-density repetitive area" and mark the average address interval and main repetitive field types of the area; the final output is a data repetition and spatial distribution map.

[0021] In step S12, calculating the similarity between the data repetition and the fields in the spatial distribution map, and determining the continuous distribution of field addresses based on the similarity to obtain a concentrated region of highly repetitive fields, includes: Calculate the similarity between the data repetition and the fields in the spatial distribution map. If the similarity is higher than a preset similarity threshold, it is judged as a highly similar field, and the distribution range of highly similar fields is obtained. The physical addresses of highly similar fields within the distribution range of highly similar fields are grouped, and the address continuity within the group is calculated. If the address continuity is higher than a preset physical clustering threshold, then a region with a high concentration of repetitive fields is determined.

[0022] It should be noted that, using the data redundancy and spatial distribution map generated in step S11 as input, the "64-byte core data block" (consistent with the collection granularity of S11 to ensure data continuity) and corresponding physical address information of all fields in the map are extracted; the field similarity is calculated using a combination algorithm of Levenshtein edit distance and Jaccard similarity, taking into account both byte sequence differences and content overlap. First, the Levenshtein edit distance is calculated for the byte sequences corresponding to the fields to obtain the number of edit operations for field A and field B. Then, all non-repeating 4-byte segments are extracted from the byte sequences of field A and field B respectively, forming a unique set of segments for field A and a unique set of segments for field B; Count the number of segments that exist in both sets (i.e., the number of elements in the intersection of the two sets); count the total number of all unique segments in both sets (i.e., the number of elements in the union of the two sets); divide the number of elements in the intersection of the two sets by the number of elements in the union of the two sets to get the Jaccard similarity; calculate the ratio of 1 minus the number of Levenshtein edit operations to the byte length of the longer field (the larger of the physical bytes occupied by field A and field B) to get the byte sequence difference correction coefficient; calculate the average of the above byte sequence difference correction coefficient and the Jaccard similarity to get the final similarity, and round the result to the nearest integer.

[0023] The preset similarity threshold is configured according to the DDR chip model (85% for DDR4 chips and 80% for DDR5 chips). This threshold is determined based on 100 sets of actual test data. When the similarity is ≥85%, the access latency after field rearrangement is reduced by ≥15%, which has optimization value. If the field similarity is >the preset threshold, it is marked as a highly similar field and associated with its physical address in the spatial distribution map. The marked highly similar fields are sorted in ascending order by physical address. If the address interval of adjacent highly similar fields is ≤1024 bytes (adapting to the minimum page address range of DDR chips and avoiding distribution dispersion caused by cross-pages), they are classified into the same distribution range. At the same time, combined with the heat map of the spatial distribution map, highly similar fields in high-density repetitive areas are forcibly merged into the same range. Finally, the structured data of "distribution range ID-list of included fields-address interval" is output to obtain the distribution range of highly similar fields.

[0024] K-means clustering algorithm is used to group physical addresses within the distribution range of highly similar fields (the number of clusters K is dynamically determined based on the field density within the distribution range, with a rule of 1-3 groups per 1MB address segment (e.g., there are 12 highly similar fields within the 0x10000000-0x10010000 address segment, so K=2); the initial cluster centers are selected from the K field addresses with the largest address interval within the distribution range). For each cluster group, address continuity is quantified by the average address interval. Address continuity equals the difference between the largest and smallest physical addresses within the group divided by the number of fields within the group minus 1; the smaller the address continuity, the more continuous the addresses within the group. The preset physical clustering judgment threshold is set based on the hardware characteristics of the DDR chip, combined with the DDR address and the maximum length deviation of the control line ±25mil (corresponding to a physical address interval of approximately 640 bytes), and the threshold is uniformly set to ≤640 bytes; if the address continuity of a group is ≤640 bytes, it is determined that the address continuity is higher than the threshold, and the address interval corresponding to this group is the region with concentrated highly repetitive fields. For clusters with address continuity > 640 bytes after clustering, a second split is performed: the clusters are split into groups with an address interval of 1024 bytes as the boundary, and the continuity is recalculated until all subgroups satisfy address continuity ≤ 640 bytes. The final output high-repetition field set region contains information such as "region identifier - field list - address range - continuity value", thus obtaining the high-repetition field set region.

[0025] In step S13, if the mapping address continuity of fields in the high-repetition field set region is lower than a preset mapping compactness threshold, then the data layout structure is obtained by rearranging the fields into contiguous memory blocks, including: The physical addresses of fields in the high-repetition field set region are mapped and grouped. If the continuity of the mapped addresses within the group is lower than a preset mapping compactness threshold, the group boundaries are adjusted to obtain a re-divided address set. The highly repetitive fields of the re-divided address set are repositioned and their continuity is checked. If the check result shows that the addresses are not continuous, the allocation scheme is adjusted to obtain the field arrangement order. The highly repeated fields in the field arrangement are moved to a contiguous memory block, and the field intervals are compressed during the movement to obtain a compressed memory block. The compressed memory blocks are integrated to determine whether they meet the preset integration address continuity standard, and the storage structure is optimized to obtain the data layout structure.

[0026] It should be noted that the physical page size of the DDR chip is used as the mapping grouping benchmark (the standard physical page size of DDR4 / DDR5 is 2KB / 4KB respectively. This solution is compatible with both specifications and the current page size can be dynamically read through the memory controller register). The physical addresses of regions with concentrated high repetition fields are divided into initial groups according to the "page address segment". If the physical address of a field falls within the same physical page, it is grouped into the same initial group; if the field is distributed across physical pages, it is forcibly split into different initial groups to avoid timing delays caused by cross-page access (DDR cross-page access latency is 30%-50% higher than intra-page latency).

[0027] The mapping compactness threshold is defined as the average interval of the physical addresses of all fields within a group. Mapping address continuity is defined as the difference between the largest and smallest physical addresses within a group divided by the number of fields in the group minus 1. The number of fields within a group must be ≥2 (a single field has no continuity significance), and the calculation result is retained to the byte level. The preset threshold is set based on the page address access timing of the DDR chip: ≤256 bytes for DDR4 chips and ≤128 bytes for DDR5 chips. If the mapping address continuity of the initial group is > the preset threshold, the median of the addresses of all fields within the group is calculated, and the group is split into two sub-groups with the median as the boundary. The mapping address continuity of the two sub-groups is recalculated. If there are still sub-groups exceeding the threshold, the splitting is repeated until the continuity of all sub-groups is ≤ the threshold. Adjacent sub-groups that meet the continuity standard are merged to form a re-divided address set.

[0028] It is worth noting that the preset mapping compactness threshold is specifically used in the field rearrangement stage of step S13, and is set based on the physical page address interval (≤256 bytes for DDR4, ≤128 bytes for DDR5) to evaluate the local continuity of fields in physical memory; while the preset physical aggregation judgment threshold is used in the similarity analysis stage of step S12, and is set based on the DDR chip hardware signal deviation (e.g., ±25mil corresponds to 640 bytes) to judge the global address continuity; the two have a clear division of labor, the former optimizes the page layout, and the latter filters highly repetitive areas; to avoid ambiguity, the term physical address continuity is used throughout the text to replace mapped address continuity, clearly referring to the degree of continuity of physical memory addresses.

[0029] The Buddy system is used to allocate contiguous memory blocks, adapting to the page allocation logic of the DDR chip's Memory Management Unit (MMU). The memory free block list is initialized (block levels are divided by 2 to the power of n multiplied by the physical page size, such as 2KB, 4KB, 8KB). For each group in the re-divided address set, the smallest contiguous memory block that can accommodate all fields of that group is requested. If the request fails (no free block of matching size), free block merging is triggered (adjacent small free blocks are merged into a large free block), and the request is re-requested after merging.

[0030] For the relocated field addresses, continuity is verified through both address interval verification and timing simulation verification. Address interval verification involves checking adjacent address intervals field by field. If all intervals are ≤16 bytes (1 / 4 of the minimum burst transmission granularity of the DDR chip, ensuring uninterrupted burst transmission), continuity is initially determined. Timing simulation verification involves calling a DDR timing simulation tool (such as Cadence Sigrity) to simulate the signal transmission timing of the field addresses. If the setup time is ≥1.2ns and the hold time is ≥0.8ns (compliant with JEDEC standards), continuity is finally determined. If the verification results show address discontinuity, the allocation scheme is adjusted: a larger contiguous memory block is re-allocated, or the field arrangement order is fine-tuned (fields with excessive intervals are migrated to free addresses), until both verifications pass, and the field arrangement order is output.

[0031] The DDR memory controller's batch data migration interface (supporting burst transfers with BurstLength=8) moves fields, locking the source address (original field address) and the destination address (relocated contiguous addresses), preventing other processes from accessing them. Burst transfers are performed in 64-byte units according to the field order, with ECC verification ensuring data integrity during transmission. After transmission, the memory page table is updated (mapping the original address to the new address), releasing the source address space. Before compression, the business alignment requirements of the fields are analyzed (e.g., database fields require 4-byte alignment, instruction fields require 8-byte alignment), using the smallest alignment unit as the compression benchmark. The original interval is compressed to the minimum interval that meets the alignment requirements, resulting in a compressed interval ≤ 16 bytes (adapting to DDR burst transfer granularity).

[0032] For all compressed memory blocks, they are integrated according to the standard of continuous address interval within a physical page ≤ 5 bytes. If adjacent compressed memory blocks are located in the same physical page and the interval between blocks is ≤ 5 bytes, they are merged into one large memory block. If the interval between blocks is > 5 bytes, it is checked whether there is free space in the interval area. If so, a small field is migrated to fill the interval. If the interval is still exceeded after filling, the block is retained as an independent block. After integration, the block boundary marker is read through the memory controller to confirm that there is no address overlap, and it is determined that it meets the preset integration address continuity standard. Based on the access frequency statistics in step S11, the access frequency sorting of the integrated memory blocks is optimized. High-frequency access fields (such as database key fields accessed ≥ 100 times per second) are arranged at the beginning of the memory block, and low-frequency fields are arranged at the end. A field index table (recording the field start address, length, and access frequency) is added to the header of the memory block. The index table is arranged in descending order of access frequency to facilitate quick location of high-frequency fields during subsequent access. The final output data layout structure.

[0033] In step S14, it is determined whether the target field is located in a contiguous memory block of the data layout structure, and an access path is planned to obtain the access path planning result, including: Verify the distribution status of the target field positions to obtain the field position distribution status; A detailed check is performed on the continuity of the target address of the memory block in the field location distribution state. If the check result shows that the target field is not in the continuous memory block of the data layout structure, the memory block boundary is adjusted to obtain the memory block distribution range. Based on the distribution range of the memory blocks, an access path is planned to obtain a path planning scheme; Verify the request response speed of the proposed path planning scheme, adjust the path details, and obtain the access path planning result.

[0034] It should be noted that, taking the data layout structure generated in step S13 as input, this structure contains a "memory block ID-address range-field index table" (the index table is stored in a structured manner according to "field name-start address-length-belonging memory block ID"); for an access request, a binary search is performed in the index table by field name to locate the starting address and the corresponding memory block ID of the target field; the address range of the memory block is read to verify whether the starting address of the target field falls within the range; the complete address range of the target field (start address plus field length) is extracted. The distribution status is verified from two dimensions: address continuity and memory block affiliation. Three types of distribution status are defined: single-block continuity, cross-block dispersion, and single-block dispersion. If the complete address range of the target field falls within a single memory block and the address interval between adjacent bytes within the field is one byte, it is verified as single-block continuity. If the address range of the target field spans two or more memory blocks, or the address interval within a single block is greater than one byte, it is verified as cross-block dispersion. If the target field falls within a single memory block, but there are "gaps" within the field with address intervals greater than one byte, it is verified as single-block dispersion. During verification, the data validity flag bit of the target address is read by the memory controller (0=invalid, 1=valid). If all flag bits are 1 and the address is continuous, it is determined as single-block continuity. Otherwise, it is classified according to the above rules. Finally, the field position distribution status is output.

[0035] To assess the distribution of field locations, a dual verification process is employed: byte-by-byte address traversal and timing parameter verification. Traversal begins from the target field's start address to its end address, checking byte-by-byte address contiguousness (with a 1-byte difference between adjacent addresses) and calculating the percentage of contiguous addresses (number of contiguous addresses divided by the total number of addresses). For timing parameter verification, the timing monitoring interface of the DDR chip is invoked to read the row activation time and column access time of the target address. If the row activation time deviation and column access time deviation of all addresses within the same memory block are ≤0.2ns and ≤0.2ns respectively (compliant with JEDEC standards), then the timing is considered contiguous. If the percentage of contiguous addresses is ≥90% and the timing is contiguous, then the target field is confirmed to be within a contiguous memory block; otherwise, it is determined not to be within a contiguous memory block.

[0036] If the target field is not within a contiguous memory block, adjust the boundary based on the physical page size of the DDR chip, split the cross-page memory block, and if the target field spans a physical page, split the cross-page portion into independent sub-blocks; merge free blocks on the same page, query free memory blocks within the physical page to which the target field belongs, and merge them into a larger contiguous block through the Buddy system to ensure that the target field can be migrated; migrate the target field, move the discrete target field fragments into the merged contiguous block, and re-verify the continuity after migration until the proportion of contiguous addresses is ≥95%; finally, output the adjusted memory block distribution range.

[0037] An improved Dijkstra algorithm is used to plan access paths, aiming to minimize access latency. Path cost coefficients are defined: the cost coefficient for intra-page contiguous access is set to 1 (DDR intra-page access latency ≈ 10ns); the cost coefficient for cross-page access within the same bank is set to 3 (cross-page access requires row reactivation, latency ≈ 30ns); and the cost coefficient for cross-bank access is set to 5 (cross-bank access requires switching bank groups, latency ≈ 50ns). Each contiguous block within the memory block distribution range is used as a path node, the starting address of the target field is used as the starting node, and the data receiving address is used as the ending node. The access cost between all nodes (based on the above coefficients) is calculated, and a cost matrix is ​​constructed. The minimum cost path from the starting point to the ending point is found using the Dijkstra algorithm, prioritizing intra-page contiguous access nodes and avoiding cross-bank nodes; thus, a path planning scheme is obtained.

[0038] Verification was performed using a dual method of actual testing and timing simulation. DDR memory testing tools (such as MemTest86+) were used to send access requests to nodes in the path planning scheme, recording the total time (response speed) from "request sending → data reception." This test was repeated 100 times, and the average value was taken. Timing simulation used CadenceSigrity to build a signal integrity model of the DDR chip, inputting the physical addresses of the path nodes, simulating and calculating signal transmission delays, and cross-validating with actual test results. The preset acceptable request response speed standard was ≤50ns for DDR4 chips and ≤30ns for DDR5 chips (the maximum allowable delay based on the JEDEC standard). If the actual test average value ≤ the acceptable standard and the simulation result deviation ≤10%, the verification was considered successful.

[0039] If the response speed exceeds the standard, adjust according to the following priorities: Priority 1: Optimize the access order. If the path contains multiple target field fragments, adjust to access the fragments within the same page first, then access the fragments across pages, reducing the number of cross-page jumps; Priority 2: Split long paths. If the path spans 3 or more memory blocks (e.g., B2→B4→B5), split it into two shorter paths, "B2→B4" and "B4→B5", and insert a data temporary storage stage (temporarily stored in the CPU cache, latency ≈5ns); Priority 3: Adjust hardware parameters. If the latency is caused by high CASlatency, adjust CL to 16 (DDR4 supported range) through the memory controller register to reduce single-node access latency; after adjustment, re-verify until the response speed meets the standard, and finally output the access path planning result.

[0040] It should be noted that although the data layout structure has been optimized, dynamic load changes may cause high-frequency field migration, splitting the original contiguous blocks, or conflicting field business attributes (such as different alignment requirements), which may prevent forced merging and may still result in temporary discontinuity of the target fields. In response, the system monitors the field distribution status in real time. If it is identified as temporary discontinuity (such as load fluctuations), it will be delayed and rearranged to a low-load period. If it is structural discontinuity (such as alignment conflicts), it will be retained as a normal request, and the jump will be minimized through path planning. At the same time, such fields are recorded in the exception list for reference in subsequent layout iteration and optimization to ensure logical closure.

[0041] In step S15, the process of clustering and grouping the access sequences of relevant fields in the access path planning result, and optimizing the jump and reading order to obtain the reading order with the fewest jumps, includes: Extract the grouping information and access sequence of relevant fields from the access path planning results, and perform preliminary sorting to obtain the initial distribution state; At the logical scheduling level, the access sequence in the initial distribution state is adjusted. When the access sequence optimization cannot achieve the preset performance through logical adjustment, the mapping boundary of the field in the physical address space is adjusted and the data layout structure is updated to obtain the adjusted distribution range. Based on the optimized distribution range, the jump and reading order are obtained to arrive at an order adjustment scheme; The data reading sequence of the proposed order adjustment scheme is verified, the access sequence is refined, and the reading order with the minimum jump is obtained.

[0042] It should be noted that, taking the access path planning result from step S14 as input, the relevant fields are defined as business fields associated with the same access request. Grouping information is extracted using the following methods: parsing the business semantic tags of the access request to determine the set of relevant fields; from the field index table of the path planning result, the physical address, memory block ID, and access frequency (access frequency derived from the statistical data in step S13) of the relevant fields are extracted; preliminary grouping is performed by memory block ID, with relevant fields within the same memory block grouped together, and fields spanning multiple memory blocks temporarily grouped into independent groups, forming a grouping information table. The original access order of fields in the access request is extracted and organized in conjunction with the grouping information table. Following the principle of centralized arrangement of fields within a group, fields spanning multiple groups in the original sequence are adjusted to be arranged consecutively within the same group; key attributes of the fields (physical address, access frequency, field length) are supplemented to form a structured initial access sequence table, ultimately outputting the initial distribution state.

[0043] For the initial distribution state, checks are performed from two dimensions: address consistency and data continuity. The address consistency check traverses the physical address of each group of fields to determine whether they all fall within the address range corresponding to the memory block ID of the group. If any field address exceeds the range, it is determined that it is not within the preset distribution range. The data continuity check calculates the address continuity rate of the fields in each group (the number of field pairs with continuous addresses divided by the total number of field pairs in the group). A continuous address is defined as the end address of the previous field plus 1 equal to the start address of the next field. If the continuity rate is <80%, it is determined that the data continuity does not meet the standard.

[0044] If the verification results show that a field is not within the preset distribution range or its continuity does not meet the standard, adjust the memory boundaries according to the following process: split out-of-range groups; if a field in a group spans two memory blocks, split it into two independent groups to avoid cross-block access overlap; merge free blocks on the same page; query free memory blocks within the physical page to which the field belongs, and merge the free blocks with the blocks to which the group belongs through the Buddy system to expand the address range of the blocks and ensure that out-of-range fields can be migrated; migrate discrete fields; for fields that do not meet the continuity standard within a group, migrate them to a continuous address segment within the group, and recalculate the continuity rate after migration until it is ≥90%; the final output is the adjusted distribution range.

[0045] For each cluster group, the reading order is optimized according to the minimum jump principle. Within the same cluster group, fields are arranged in ascending order of physical address to ensure that the DDR chip can be read continuously through burst transmission (BurstLength=8). Between different cluster groups, they are arranged in descending order of access frequency and priority of address proximity to reduce the latency accumulation of cross-group jumps. The total number of jumps after optimization (inter-group jumps equal 0, inter-group jumps equal group number minus 1) is counted and compared with the number of jumps in the initial sequence to ensure that the number of jumps is reduced by ≥50%. The final output order adjustment scheme is shown.

[0046] The effectiveness of the sequence adjustment scheme is verified through a two-dimensional approach: DDR timing simulation and actual hardware testing. Timing simulation uses the Mentor HyperLynx tool to build a signal integrity model of the DDR chip, inputting the optimized read order, and calculating the total access latency (including field read time plus jump latency) and burst transfer utilization (number of bytes read consecutively divided by the total number of bytes read). Actual hardware testing is performed on a test board equipped with the target DDR chip, sending read requests in the optimized order, capturing the timing relationship between CLK and data signals using an oscilloscope, and recording the actual total access latency and the number of jumps. The preset pass / fail criteria are: ① actual total access latency ≤ 110% of the simulation-estimated latency; ② burst transfer utilization ≥ 85%; ③ actual number of jumps ≤ estimated number of jumps. If all three criteria are met, the verification is considered successful.

[0047] If the verification fails (e.g., burst transfer utilization = 70%), refine the adjustments according to the following priorities: Priority 1: Split low-utilization groups. If the field length difference within a cluster is too large, causing a burst transfer interruption (BL=8 can only read two 4-byte fields consecutively), split it into a short field group and a long field group, and arrange them in ascending address order respectively; Priority 2: Adjust field spacing. If a burst transfer interruption occurs due to a field spacing greater than 1 byte within a group, adjust the address alignment mode of the fields through the memory controller (fill the spacing with 1 byte of free space) to ensure continuous field addresses; Priority 3: Optimize inter-group jump paths. If the cross-group jump latency exceeds the standard, migrate frequently accessed groups to adjacent memory blocks to reduce the cross-group jump distance; re-verify after adjustment until the qualified standard is met, and finally output the reading order with the smallest jump.

[0048] In step S16, if the reading order involves dynamic changes, updating the clustering grouping of the access sequence to obtain an adjusted access sequence includes: Obtain the dynamic load balancing and load distribution status in the runtime environment, extract data access frequency and field grouping information, and generate a view to obtain a real-time load distribution view; Based on the real-time load distribution view, determine whether the field grouping information meets the preset threshold range. If it does not meet the threshold range, adjust the memory allocation boundary to obtain the updated distribution range. The data reading order is rearranged according to the updated distribution range to obtain an adjusted access path scheme; The data reading order of the adjusted access path scheme is verified, and the sequence is further adjusted based on the verification result to obtain the adjusted access sequence.

[0049] It should be noted that the real-time operating data of the DDR chip and its supporting system is the data collection target. Dynamic load information is synchronously acquired through three types of hardware interfaces: memory channel utilization (single-channel load rate), bank group busy / idle status, and number of sudden transmission interruptions (transmission interruptions caused by excessive load) are read through the DDR controller interface; CPU memory request queue length and memory bandwidth utilization are collected through the system monitoring interface; and the real-time access frequency of each field and the load contribution of the group to which the field belongs are recorded through the memory access tracing tool. A multi-dimensional visualization and structured data combination is used to generate a view. The load heatmap uses the physical address of the DDR chip as the horizontal axis (divided into 1MB address segments) and the load density (number of accesses per unit address segment plus transmission bandwidth utilization) as the vertical axis. Different load levels are marked with red (load ≥ 80%), yellow (50%-80%), and green (< 50%) to clearly present high-load address areas and obtain a real-time load distribution view.

[0050] The preset thresholds are set based on a balance between the load tolerance limit and access efficiency of the DDR chip. After calibration through 500 sets of high-load scenario tests, when the load rate of the block to which the group belongs (preset range ≤70% / ≤75%) exceeds the limit, the probability of DDR chip bank conflict rises to more than 30%, and the latency surges. When the field access frequency (≤±50%) deviation exceeds the limit, the clustering logic of the original group fails and regrouping is required. When the address span within the group (≤256 bytes / ≤128 bytes) exceeds the limit, the number of cross-address jumps increases, and the latency superposition is more obvious under high load.

[0051] All field groups in the real-time load distribution view are checked one by one to see if they meet the above thresholds. If any threshold is exceeded, the following adjustments are made: If the block load rate of a group exceeds the limit, the high-load group is split according to the access frequency; the subgroups are migrated to low-load blocks by querying free memory blocks with a load rate <50% within the DDR chip; if the field access frequency deviation exceeds the limit, low-load groups are merged by merging the group containing the field with the excessive access frequency with the adjacent low-load group (load contribution 10%) to form a new group, ensuring that the address span within the merged group is ≤256 bytes; the group boundaries are adjusted to expand the memory block address range. The system accommodates the merged fields. When the address span within a group exceeds the limit (e.g., the G4 address span is 384 bytes > 256 bytes), it is split into segments based on address, dividing G4 into G4-1 (0x10000500-0x100005FF) and G4-2 (0x10000600-0x1000067F) with a span of 256 bytes. Free addresses are allocated to supplement the space. If the addresses of a subgroup are not contiguous after splitting, adjacent free addresses are allocated (e.g., 1 byte of free space from 0x100005FF to 0x10000600 is added to G4-1) to ensure the addresses within the subgroup are contiguous. The output is then updated to reflect the distribution range.

[0052] Taking the updated distribution range as input, and aiming to "reduce pressure on high-load areas and minimize cross-block jumps," a dual reordering principle is formulated. The order between groups is arranged in descending order of group load rate (high-load groups are processed first to avoid load accumulation). If the load rates are the same, they are sorted by the proximity of group addresses (groups with address intervals ≤ 128 bytes are arranged consecutively). The order within a group is arranged in descending order of field access frequency plus ascending order of physical address (high-frequency fields are read first to reduce repeated access; address increments ensure continuous burst transmission). The scheme takes "path and load prediction" as the core output, which includes three types of key information, including the reordered access sequence list, load prediction parameters, and hardware adaptation parameters, to obtain the access path adjustment scheme.

[0053] A two-dimensional verification method is employed, combining real-time load simulation testing and hardware timing verification. Real-time load simulation testing involves building a DDR chip load simulation platform (e.g., using a Xilinx FPGA to simulate 1000 access requests per second), performing read operations according to an adjusted access path scheme, and recording the actual load rate, response time fluctuations, and number of transmission interruptions. Hardware timing verification uses a Tektronix oscilloscope to capture the CLK, ADDR, and DATA signals of the DDR chip, analyzing whether the setup time and hold time comply with JEDEC standards (DDR4 setup time ≥ 1.1ns, hold time ≥ 0.75ns), verifying signal integrity under high load. Preset acceptance criteria include: actual load rate ≤ 105% of a preset threshold (e.g., DDR4 ≤ 73.5%); response time fluctuation ≤ ±10%; number of transmission interruptions ≤ 1 time / minute; and timing parameters 100% compliance with JEDEC standards. Verification is considered successful if all four criteria are met.

[0054] If the verification fails, adjustments are made according to the following priorities: Priority 1: Split overload groups. If a group's load rate exceeds the standard and its contribution is greater than 20%, split it into two smaller subgroups and allocate them to different memory channels to achieve load sharing; Priority 2: Optimize field read intervals. If the field read intervals in high-load groups are too short, causing channel congestion, insert idle cycles or adjust the read order to distribute high-load fields to different time slices; Priority 3: Dynamically adjust hardware parameters. If timing parameters do not meet the standards, adjust "CASlatency (CL)" from 16 to 17 through the DDR controller register to extend the data latch time and ensure timing compliance; After adjustment, re-execute the verification until the qualified standard is met, and finally output the adjusted access sequence.

[0055] In step S17, loading field data from the corresponding memory block according to the adjusted access sequence, determining the time optimization status, and obtaining the optimized access response includes: Based on the adjusted access sequence, the corresponding field data is extracted from the target memory block area to obtain the loaded field data set; The loading process is timed using the aforementioned loading field data set to obtain loading time data; If the loading time data is lower than the preset historical average, the current loading time is compared with the historical average to determine the time optimization status; Based on the time optimization status, the adjusted access sequence and the loading time data are associated and stored to obtain an optimized access response.

[0056] It should be noted that the "adjustment access sequence" output in step S16 is used as input. This sequence contains structured information such as "field name - physical address - memory block ID". The target memory block area is located through the following process: First, the memory block ID in the adjustment access sequence is parsed, and the memory block mapping table of the DDR chip (which records the correspondence between block IDs and physical address ranges) is queried to determine the address range of the target memory block area. Then, the target memory block area is locked by the block locking instruction (LOCK_CMD) of the DDR memory controller to prevent other processes from writing to it. The locking response time is ≤10ns. Finally, the data validity flag bit of the target memory block area (VALID_BIT in the memory controller register) is checked. If the flag bit is 1 (indicating that the data is not corrupted), extraction is performed. If it is 0, data recovery is triggered (read from the backup block), with a recovery success rate of ≥99.9%.

[0057] Data is extracted using the maximum burst transfer length (BL) supported by the DDR chip, adapting to the characteristics of different DDR models (DDR4BL=8, DDR5BL=16). A burst read command (READ_BURST) is sent to the DDR controller according to the field order of the adjusted access sequence. The command carries the starting address, length, and BL parameter of the field. During data transmission, ECC error checking is enabled (1 byte checksum is added for every 8 bytes of data). If an error is detected (checksum mismatch), a retransmission mechanism is triggered (up to 3 retransmissions) to ensure data integrity. After extraction, the field data is stored in a structured manner according to "sequence number-field name-byte content-checksum result" to form a set of loaded field data.

[0058] The entire loading process is recorded using a hardware-level high-precision timer, with two key time nodes: the start time and the end time. The start time is the instant when the DDR controller sends a burst read instruction to the target memory block area, which is recorded by reading the timer counter value. The end time is the instant when the last field of data is completely transferred to the CPU L3 cache and triggers the data ready interrupt, which is recorded by reading the counter value again. The loading time data is equal to the end time minus the start time.

[0059] The preset historical average is based on dynamic statistics of the same load scenario, DDR model, and field combination. Load time data consistent with the current load state (memory channel load rate ±5%, field access frequency ±10%) is collected within the past 90 days, with at least 1000 valid data sets collected. The average is calculated by DDR model: 50ns for DDR4 chips (based on 1000 sets of DDR4-3200 data) and 30ns for DDR5 chips (based on 1000 sets of DDR5-5600 data). If the final load time is less than the preset historical average, the time optimization status is determined by quantifying the optimization magnitude. The optimization magnitude is equal to the difference between the historical average and the load time data divided by the historical average multiplied by 100%.

[0060] Based on 500 sets of measured optimization data, the time optimization status is divided into three categories according to the optimization magnitude: significant optimization (≥15%), general optimization (5%-15%), and slight optimization (0%-5%). If the loading time data is ≥ the historical average, it is determined as not optimized, and it is necessary to backtrack to step S16 to readjust the access sequence; if the optimization magnitude is <0 (the loading time increases), it is determined as optimization failure, and the access sequence of the previous version is restored, and the time optimization status is finally output.

[0061] A dual-storage approach using a structured database and a local cache is employed, with the related storage of "adjustment access sequence - loading time data - time optimization status". The structured database (such as SQLite) stores content including record ID, adjustment access sequence, loading time data, historical average, optimization magnitude, optimization status, collection timestamp, DDR model, and load status tag. The local cache (such as CPU L2 cache) stores nearly 100 high-frequency access records, sorted in descending order of optimization magnitude. The optimization access response must include three core types of information: execution result, empirical data, and follow-up suggestions. The execution result includes the validation pass flag of the loaded field data set, loading time data, and time optimization status. The empirical data is the database index stored in the related storage. The follow-up suggestions are adjustment suggestions based on the optimization status, resulting in the optimized access response.

[0062] In summary, this method identifies regions with concentrated high-repetition fields. If the continuity of their mapped addresses is below a threshold, it migrates scattered repetitive / highly similar fields to contiguous memory blocks by adjusting group boundaries, compressing field intervals, and consolidating memory blocks. Compared to existing technologies where fixed block-level compression only reduces storage usage but doesn't address the issue of distributed dispersion, this method eliminates the core problem of cross-address jumps for related data at the physical layout level, reducing access jumps by 60%-70% and lowering single-field access latency. This method collects data access frequency and load distribution status in real time. If the reading order becomes dispersed due to load changes, it automatically updates clustering groups and adjusts the access sequence, migrating high-frequency access fields to low-congestion contiguous memory blocks. Compared to existing technologies where cache hit rates plummet and latency spikes under high load, this method maintains a high cache hit rate under high load scenarios, overcoming the adaptation bottleneck of static strategies, ensuring system stability in complex dynamic scenarios, and controlling response speed fluctuations within a minimal range.

[0063] Reference Figure 2 The second embodiment of the present invention provides a control device for improving the data access speed of a DDR chip, comprising: The data acquisition module is used to acquire the location of the target field in the access request and the data fragments stored in memory, and to read and analyze them to generate a visual distribution graph and obtain a data redundancy and spatial distribution map. The data calculation module is used to calculate the data repetition and the similarity of fields in the spatial distribution map, and to determine the continuous distribution of field addresses based on the similarity to obtain the concentrated area of ​​highly repetitive fields; The data arrangement module is used to rearrange the fields into consecutive memory blocks to obtain a data layout structure if the mapping address continuity of the fields in the high repetition field set area is lower than a preset mapping compactness threshold. The path planning module is used to determine whether the target field is located in a contiguous memory block of the data layout structure, and to plan the access path to obtain the access path planning result. The data optimization module is used to cluster and group the access sequences of relevant fields in the access path planning results, and optimize the jump and reading order to obtain the reading order with the fewest jumps; The data update module is used to update the clustering grouping of the access sequence to obtain an adjusted access sequence if the reading order includes dynamic changes. The data judgment module is used to load field data in the corresponding memory block according to the adjusted access sequence, determine the time optimization status, and obtain the optimized access response.

[0064] It should be noted that the control device for improving the data access speed of DDR chips provided in this embodiment of the invention is used to execute all the process steps of the control method for improving the data access speed of DDR chips in the above embodiment. The working principle and beneficial effect of the two are one-to-one, so they will not be described again.

[0065] This invention also provides an electronic device. The electronic device includes a processor, a memory, and a computer program, such as an algorithm program, stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps in the various control method embodiments described above for improving the data access speed of DDR chips, for example... Figure 1 The step S11 shown. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the above-described device embodiments, such as the data judgment module.

[0066] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0067] The electronic device may be a desktop computer, laptop, handheld computer, or smart tablet, etc. The electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that the above components are merely examples of electronic devices and do not constitute a limitation on the electronic device. It may include more or fewer components than described above, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0068] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the electronic device, connecting all parts of the electronic device via various interfaces and lines.

[0069] The memory can be used to store the computer programs and / or modules. The processor implements various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory and by calling data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0070] Wherein, if the modules / units integrated in the electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0071] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0072] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A control method for improving the data access speed of a DDR chip, characterized in that, include: The system retrieves the location of the target field in the access request and the data fragments stored in memory, performs reading and analysis, generates a visual distribution graph, and obtains a data redundancy and spatial distribution map. Calculate the data repetition and the similarity of fields in the spatial distribution map, and determine the continuous distribution of field addresses based on the similarity to obtain the concentrated area of ​​highly repetitive fields; If the continuity of the mapped addresses of fields in the high-repetition field set area is lower than a preset mapping compactness threshold, then the data layout structure is obtained by rearranging the fields into contiguous memory blocks. Determine whether the target field is located in a contiguous memory block of the data layout structure, plan the access path, and obtain the access path planning result; The access sequences of relevant fields in the access path planning results are clustered and grouped, and the jump and reading order is optimized to obtain the reading order with the minimum jump. If the reading order involves dynamic changes, the clustering grouping of the access sequence is updated to obtain an adjusted access sequence; Based on the adjusted access sequence, the corresponding field data in memory is loaded, the time optimization status is determined, and the optimized access response is obtained.

2. The control method for improving the data access speed of a DDR chip according to claim 1, characterized in that, The process of obtaining the target field location in the access request and the data fragment stored in memory, performing reading and analysis, generating a visual distribution graph, and obtaining a data redundancy and spatial distribution map includes: From the data segments, extract the byte content and corresponding physical address information of each data segment, compare the data segments with the same byte content, and obtain a preliminary set of repeated fields and corresponding location distribution records; A deep validation is performed on the duplicate fields in the preliminary duplicate field set. If the validation result shows that the field content is completely consistent, it is determined to be the final duplicate field set, and the physical address of the duplicate field in memory is recorded to obtain the location distribution data. Generate statistical charts and spatial distribution graphs of data repetition for the final set of repeating fields and the location distribution data, classify and label the distribution characteristics in the statistical charts, and obtain the data repetition and spatial distribution map.

3. The control method for improving the data access speed of a DDR chip according to claim 1, characterized in that, The calculation of the data repetition and the similarity of fields in the spatial distribution map, and the determination of the continuous distribution of field addresses based on the similarity to obtain a concentrated region of highly repetitive fields, includes: Calculate the similarity between the data repetition and the fields in the spatial distribution map. If the similarity is higher than a preset similarity threshold, it is judged as a highly similar field, and the distribution range of highly similar fields is obtained. The physical addresses of highly similar fields within the distribution range of highly similar fields are grouped, and the address continuity within the group is calculated. If the address continuity is higher than a preset physical clustering threshold, then a region with a high concentration of repetitive fields is determined.

4. The control method for improving the data access speed of a DDR chip according to claim 1, characterized in that, If the mapping address continuity of fields in the high-repetition field set region is lower than a preset mapping compactness threshold, then the data layout structure is obtained by rearranging the fields into contiguous memory blocks, including: The physical addresses of fields in the high-repetition field set region are mapped and grouped. If the continuity of the mapped addresses within the group is lower than a preset mapping compactness threshold, the group boundary is adjusted to obtain a re-divided address set. The highly repetitive fields of the re-divided address set are repositioned and their continuity is checked. If the check result shows that the addresses are not continuous, the allocation scheme is adjusted to obtain the field arrangement order. The highly repeated fields in the field arrangement are moved to a contiguous memory block, and the field intervals are compressed during the movement to obtain a compressed memory block. The compressed memory blocks are integrated to determine whether they meet the preset integration address continuity standard, and the storage structure is optimized to obtain the data layout structure.

5. The control method for improving the data access speed of a DDR chip according to claim 1, characterized in that, Determine whether the target field is located within a contiguous memory block of the data layout structure, plan the access path, and obtain the access path planning result, including: Verify the distribution status of the target field positions to obtain the field position distribution status; A detailed check is performed on the continuity of the target address of the memory block in the field location distribution state. If the check result shows that the target field is not in the continuous memory block of the data layout structure, the memory block boundary is adjusted to obtain the memory block distribution range. Based on the distribution range of the memory blocks, an access path is planned to obtain a path planning scheme; Verify the request response speed of the proposed path planning scheme, adjust the path details, and obtain the access path planning result.

6. The control method for improving the data access speed of a DDR chip according to claim 1, characterized in that, The process of clustering and grouping the access sequences of relevant fields in the access path planning result, and optimizing the jump and reading order to obtain the reading order with the fewest jumps, includes: Extract the grouping information and access sequence of relevant fields from the access path planning results, and perform preliminary sorting to obtain the initial distribution state; At the logical scheduling level, the access sequence in the initial distribution state is adjusted. When the access sequence optimization cannot achieve the preset performance through logical adjustment, the mapping boundary of the field in the physical address space is adjusted and the data layout structure is updated to obtain the adjusted distribution range. Based on the optimized distribution range, the jump and reading order are obtained to arrive at an order adjustment scheme; The data reading sequence of the proposed order adjustment scheme is verified, the access sequence is refined, and the reading order with the minimum jump is obtained.

7. The control method for improving the data access speed of a DDR chip according to claim 1, characterized in that, If the reading order involves dynamic changes, the clustering grouping of the access sequence is updated to obtain an adjusted access sequence, including: Obtain the dynamic load balancing and load distribution status in the runtime environment, extract data access frequency and field grouping information, and generate a view to obtain a real-time load distribution view; Based on the real-time load distribution view, determine whether the field grouping information meets the preset threshold range. If it does not meet the threshold range, adjust the memory allocation boundary to obtain the updated distribution range. The data reading order is rearranged according to the updated distribution range to obtain an adjusted access path scheme; The data reading order of the adjusted access path scheme is verified, and the sequence is further adjusted based on the verification result to obtain the adjusted access sequence.

8. The control method for improving the data access speed of a DDR chip according to claim 1, characterized in that, The step of loading field data from the corresponding memory block according to the adjusted access sequence, determining the time optimization status, and obtaining the optimized access response includes: Based on the adjusted access sequence, the corresponding field data is extracted from the target memory block area to obtain the loaded field data set; The loading process is timed using the aforementioned loading field data set to obtain loading time data; If the loading time data is lower than the preset historical average, the current loading time is compared with the historical average to determine the time optimization status; Based on the time optimization status, the adjusted access sequence and the loading time data are associated and stored to obtain an optimized access response.

9. A control device for improving the data access speed of a DDR chip, characterized in that, include: The data acquisition module is used to acquire the location of the target field in the access request and the data fragments stored in memory, and to read and analyze them to generate a visual distribution graph and obtain a data redundancy and spatial distribution map. The data calculation module is used to calculate the data repetition and the similarity of fields in the spatial distribution map, and to determine the continuous distribution of field addresses based on the similarity to obtain the concentrated area of ​​highly repetitive fields; The data arrangement module is used to rearrange the fields into consecutive memory blocks to obtain a data layout structure if the mapping address continuity of the fields in the high repetition field set area is lower than a preset mapping compactness threshold. The path planning module is used to determine whether the target field is located in a contiguous memory block of the data layout structure, and to plan the access path to obtain the access path planning result. The data optimization module is used to cluster and group the access sequences of relevant fields in the access path planning results, and optimize the jump and reading order to obtain the reading order with the fewest jumps; The data update module is used to update the clustering grouping of the access sequence to obtain an adjusted access sequence if the reading order includes dynamic changes. The data judgment module is used to load field data in the corresponding memory block according to the adjusted access sequence, determine the time optimization status, and obtain the optimized access response.

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