Stability test method, device and equipment of DRAM particle and storage medium

Abstract

The application discloses a stability test method, device, equipment and storage medium of a DRAM particle. The method comprises the following steps: restarting a test system for a preset number of times, executing a preset test strategy in a universal boot loader stage of each test system starting process, the preset test strategy comprising the following steps: enabling a CPU cache, and configuring the CPU to access the DRAM particle in a non-burst transmission mode; based on hardware configuration information of the DRAM particle, allocating at least two test areas in an address space of the DRAM particle; traversing each working frequency supported by the test system, testing the read-write stability of the DRAM particle in direct read-write under each working frequency based on the at least two test areas, and testing the read-write stability of the DRAM particle after the test system enters a sleep mode and wakes up under each working frequency. The application has the technical effect of providing sufficient test pressure by using the CPU cache and avoiding external interference after the system is completely started, and effectively improves the comprehensiveness and accuracy of the DRAM particle stability test.

Description

Technical Field

[0001] This application relates to the field of memory testing technology, specifically to a method, apparatus, device, and storage medium for testing the stability of DRAM chips. Background Technology

[0002] Stability testing of Dynamic Random Access Memory (DRAM) is crucial for ensuring the reliability of electronic devices. As electronic devices place increasing demands on memory performance, existing DRAM stability testing methods struggle to eliminate external interference while ensuring sufficient testing, leading to inaccurate results.

[0003] Currently, two main DRAM testing schemes are used: one is to conduct tests in the early stages of the operating system startup on the test device; the other is to conduct tests after the operating system has fully started. The first scheme cannot enable the CPU cache, resulting in insufficient test pressure, and the address space of the internal static random access memory is limited, making it difficult to perform complete tests and hibernation verification. However, the full startup of the operating system introduces multiple interference factors such as power management, the operation of other subsystems, and system stability, which reduces the address space available for testing, makes hibernation tests difficult to implement, and often leads to misjudgments due to non-DRAM factors.

[0004] Therefore, there is an urgent need for a DRAM stability testing scheme that can make full use of resources and eliminate interference. Summary of the Invention

[0005] In view of the above problems, this application provides a method, apparatus, device and storage medium for testing the stability of DRAM chips to solve the above technical problems.

[0006] In a first aspect, this application provides a stability testing method for DRAM chips, applied to a testing system including a CPU and the DRAM chips, the stability testing method for the DRAM chips comprising:

[0007] The test system will be restarted a preset number of times. During the general bootloader phase of each test system startup, a preset test strategy will be executed. The preset test strategy includes:

[0008] Enable CPU caching and configure the CPU to access the DRAM chips in a deburst transfer mode;

[0009] Based on the hardware configuration information of the DRAM chip, at least two test regions are allocated in the address space of the DRAM chip.

[0010] The test system iterates through each operating frequency supported by the test system, and tests the read and write stability of the DRAM chip when directly read and written at each operating frequency based on at least two test regions, as well as the read and write stability of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up.

[0011] Each time the test system is restarted, the read / write stability of the DRAM chip is tested based on the restart status of the test system during the restart.

[0012] Secondly, this application provides a stability testing device for DRAM chips, applied to a test system including a CPU and the DRAM chips, and executed during the general boot loader phase of the test system startup process. The device includes:

[0013] The testing module is used to restart the test system a preset number of times, and execute a preset testing strategy during the general bootloader phase of each test system startup process. The preset testing strategy includes:

[0014] Enable CPU caching and configure the CPU to access the DRAM chips in a deburst transfer mode;

[0015] Based on the hardware configuration information of the DRAM chip, at least two test regions are allocated in the address space of the DRAM chip.

[0016] The test system iterates through each operating frequency supported by the test system, and tests the read and write stability of the DRAM chip when directly read and written at each operating frequency based on at least two test regions, as well as the read and write stability of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up.

[0017] Each time the test system is restarted, the read / write stability of the DRAM chip is tested based on the restart status of the test system during the restart.

[0018] Thirdly, this application provides an electronic device, including a memory and a processor, wherein:

[0019] The memory is used to store computer programs;

[0020] The processor is used to read the program in the memory and execute the steps of the stability test method for DRAM chips as provided in the first aspect above.

[0021] Fourthly, this application provides a computer-readable storage medium having a readable computer program stored thereon, which, when executed by a processor, implements the steps of the stability testing method for DRAM chips as described in the first aspect above.

[0022] This application provides a method, apparatus, device, and storage medium for testing the stability of DRAM chips. The method executes during the general bootloader stage of the test system startup process. In this stage, CPU cache is enabled, the CPU is configured to access the DRAM chips in a non-burst transfer mode, and at least two test areas are allocated based on hardware configuration information. Read / write stability and post-sleep / wake-up stability tests are performed at each operating frequency supported by the test system. Furthermore, the read / write stability in the restart state is verified through multiple system restarts. This solves the technical problems in existing technologies where either insufficient test pressure and limited address space are caused by the inability to enable CPU cache in the early startup phase, or the test space is reduced and sleep testing is difficult due to power consumption and interference from other subsystems after the system is fully started. The method achieves accurate testing results that fully utilize CPU cache to provide sufficient test pressure while avoiding external interference after the system is fully started, effectively improving the comprehensiveness and accuracy of DRAM chip stability testing. Significant technical progress has been made, especially in verifying the data retention capabilities of DRAM chips at different operating frequencies, in sleep / wake-up states, and during system restarts.

[0023] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This application illustrates a method for testing the stability of DRAM chips according to an embodiment of the present application.

[0026] Figure 2 A flowchart of a preset testing strategy provided in an embodiment of this application is shown.

[0027] Figure 3 A flowchart of S200 of the preset test strategy provided in the embodiments of this application is shown.

[0028] Figure 4 A flowchart of S300 of the preset test strategy provided in the embodiments of this application is shown.

[0029] Figure 5 This paper shows another flowchart of S300 of the preset test strategy provided in the embodiments of this application.

[0030] Figure 6 This paper shows another flowchart of S300 of the preset test strategy provided in the embodiments of this application.

[0031] Figure 7 This paper shows another flowchart of S300 of the preset test strategy provided in the embodiments of this application.

[0032] Figure 8 A schematic diagram of an electronic device provided in an embodiment of this application is shown.

[0033] Figure 9 A schematic diagram of a computer storage medium provided in an embodiment of this application is shown. Detailed Implementation

[0034] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0035] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0036] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0037] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0038] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0039] To understand the stability testing method for DRAM chips provided in this application, it is first necessary to understand the normal boot process of the operating system, which includes: Boot Read-Only Memory stage, Preloader / Secondary ProgramLoader stage, Universal Boot Loader / Little kernel stage, and Kernel stage.

[0040] Specifically, when the operating system boots, it first jumps to the boot code in the boot ROM to execute, loading the preloader into the internal static random-access memory (ISRAM). At this point, the dynamic random-access memory (DRAM) is not yet initialized and cannot be used. Subsequently, in the preloader / SPL loader stage, the system initializes the DRAM controller and loads the universal bootloader (U-Boot / Little kernel) from the flash memory device (including NAND flash or eMMC embedded multimedia card) into the initialized DRAM for execution. After entering the universal bootloader stage (U-Boot / Little kernel), the system decompresses the boot image to generate the initial ramdisk and kernel, loads them into the DRAM, and initializes the device tree binary (dtb) to configure hardware information. Finally, the little kernel (lk) transfers control to the main kernel to perform system initialization, completing the entire operating system boot process.

[0041] Currently, there are two main DRAM stability testing schemes, but both have obvious technical defects:

[0042] The first approach involves testing during the preloader / SPL loader phase. This approach is typically used in the early hardware verification phase, with test code integrated into the preloader / SPL loader, executing after DRAM initialization but before the general bootloader phase (U-Boot / Little kernel) loads. However, because the CPU cache controller is not fully initialized at this stage, the CPU cache cannot be enabled, resulting in insufficient test load. Furthermore, the tests must rely on limited internal SRAM (typically no more than 1MB), making it impossible to implement complex test algorithms, allocate a sufficiently large test area, or perform complete sleep / wake-up tests, severely limiting test coverage.

[0043] The second approach is to conduct testing during the kernel phase. This approach executes after the operating system has fully booted, with the test program running as a system application or kernel module. Although the CPU cache is enabled and resources are sufficient at this point, various subsystems (display, network, audio, etc.) are running after the system has fully booted, introducing interference factors such as power consumption fluctuations, bus contention, and system interrupts. Simultaneously, the operating system kernel, drivers, and services occupy a large amount of DRAM space, resulting in a reduced and discontinuous available test area. Furthermore, hibernation testing requires coordinating all subsystems to enter a low-power state, which is complex to configure and susceptible to interference from system power management policies, leading to low reliability of test results and difficulty in accurately distinguishing between DRAM issues and misjudgments caused by other system factors.

[0044] This application provides a stability testing method for DRAM chips, applied to a test system including a CPU and the DRAM chips. Specifically, the test system is a hardware device with complete computing capabilities, comprising a central processing unit (CPU), DRAM memory modules, storage media (such as NAND flash memory or eMMC embedded multimedia cards), and necessary peripheral interface circuits. During the test, the operating system stored on the test system is in the boot phase. After the test system is powered on, it follows a standard boot procedure: first, the boot code in the Boot ROM is executed to load the Preloader into the internal SRAM; then, the Preloader initializes the DRAM controller and loads the general boot loader stage (U-Boot / Little kernel) from the flash memory device into the DRAM; after entering the general boot loader stage (U-Boot / Little kernel), the system has complete memory management and CPU cache control capabilities, but the complex operating system services have not yet been started.

[0045] This method is particularly suitable for various electronic devices requiring high-reliability memory, such as smartphones, tablets, servers, embedded industrial control equipment, IoT terminals, and various smart hardware products. During the production testing, quality verification, or fault diagnosis of these devices, this test method can be executed during the critical mid-system startup phase to accurately evaluate the stability performance of DRAM chips under various operating conditions, providing reliable assurance for product quality.

[0046] Figure 1 This application illustrates a method for testing the stability of DRAM chips according to an embodiment of the present application, such as... Figure 1As shown, the method includes: restarting the test system a preset number of times, and executing a preset test strategy during the general bootloader phase of each test system startup. Specifically, each time the test system restarts, the read / write stability of the DRAM chips is tested based on the restart status of the test system. Optionally, if the test system can normally enter the general bootloader phase during the restart process and successfully execute the preset test strategy during that phase, it indicates that the read / write stability of the DRAM chips in the restart state is normal; conversely, if the test system fails to start normally during the restart process, fails to enter the test phase, or experiences system crashes or freezes while executing the preset test strategy, it indicates that the read / write stability of the DRAM chips in the restart state is abnormal. This restart test mechanism can effectively detect the data reliability of DRAM chips in real-world usage scenarios such as frequent system power-on / off or abnormal power outages.

[0047] Specifically, Figure 2 A flowchart of the preset testing strategy provided in the embodiments of this application is shown, such as... Figure 2 As shown, the preset test strategies include:

[0048] S100: Enable CPU caching and configure the CPU to access DRAM chips in non-burst transfer mode. Optionally, during the general bootloader phase, the system has already completed the initialization of the CPU cache controller. Enabling CPU caching at this time can significantly improve data transfer efficiency. Simultaneously, configuring the CPU to access DRAM chips in non-burst transfer mode (i.e., non-burst transfer mode) avoids the data continuity advantages of burst transfers, thus allowing for more rigorous read / write stress testing of the DRAM chips and effectively exposing stability issues that might be masked under normal burst transfer mode. This testing method can more realistically simulate DRAM usage under high load and random access scenarios.

[0049] S200: Based on the hardware configuration information of the DRAM chip, at least two test regions are allocated in the address space of the DRAM chip. Optionally, during the general bootloader stage, the system has completed the basic initialization and memory mapping of the DRAM chip. At this time, the hardware configuration information such as the capacity and organizational structure of the DRAM chip can be read, and at least two independent test regions can be reasonably allocated in the available address space of the DRAM according to this information. These two test regions are used to perform the same test. By comparing the test results of the two regions, the read-write consistency of the DRAM chip is verified, avoiding misjudgments caused by single points of failure or accidental interference, and improving the reliability of the test results.

[0050] S300: This test system iterates through each operating frequency supported by the testing system, testing the read / write stability of the DRAM chip during direct read / write operations at each frequency using at least two test areas, and also testing the read / write stability of the DRAM chip after the testing system enters sleep mode and wakes up. Optionally, modern electronic devices typically support multiple DRAM operating frequencies to balance performance and power consumption. This solution comprehensively evaluates the stability performance of DRAM chips at different frequencies by iterating through all operating frequencies supported by the testing system. At each operating frequency, direct read / write tests are first performed using two test areas to verify the data integrity of the DRAM in an active state. Subsequently, the system is configured to enter sleep mode (at which point the DRAM will automatically enter a self-refresh state due to the system entering sleep mode), and the system is woken up after a preset time to re-verify the data integrity in the test areas, thereby evaluating the data retention capability of the DRAM in a low-power state. This multi-dimensional, multi-scenario testing strategy effectively covers the stability requirements of DRAM chips under various real-world usage conditions.

[0051] The DRAM stability testing method provided in this application is executed during the general bootloader stage of the test system startup process. During this stage, CPU cache is enabled, the CPU is configured to access the DRAM in a non-burst transfer mode, and at least two test areas are allocated based on hardware configuration information. Read / write stability and post-sleep / wake-up stability tests are performed at each operating frequency supported by the test system. Furthermore, read / write stability in the restart state is verified through multiple system restarts. This method solves the technical problems in existing technologies where either insufficient test pressure and limited address space are caused by the inability to enable CPU cache in the early startup phase, or the test space is reduced and sleep testing is difficult due to power consumption and interference from other subsystems after the system is fully started. It achieves accurate testing results that fully utilize CPU cache to provide sufficient test pressure while avoiding external interference after the system is fully started, effectively improving the comprehensiveness and accuracy of DRAM stability testing. Significant technical progress has been made, especially in verifying the data retention capabilities of DRAM at different operating frequencies, in sleep / wake-up states, and during system restarts.

[0052] In some embodiments, Figure 3 A flowchart of S200 of the preset testing strategy provided in the embodiments of this application is shown, as follows: Figure 3 As shown, S200: The step of allocating at least two test regions in the address space of the DRAM chip based on the hardware configuration information of the DRAM chip includes:

[0053] The hardware configuration information of the DRAM chip is obtained by reading its mode register, which stores hardware configuration information. Optionally, during the general bootloader stage, the system has already completed the basic initialization of the DRAM chip, at which point the DRAM mode register can be accessed via memory-mapped I / O. The mode register stores key hardware parameters of the DRAM chip, including basic information such as die capacity, number of rank, data bit width, and timing parameters. This information is crucial for determining the size and distribution of available test space. By accurately reading this configuration information, the rationality and effectiveness of subsequent test area allocation can be ensured, avoiding test errors or system crashes caused by hardware parameter mismatches.

[0054] Based on the hardware configuration information, at least two test regions of the same size are allocated from the available address space of the DRAM chip. Optionally, based on the read hardware configuration information, the system can calculate the total amount of available address space in the DRAM chip that is not occupied by the system-reserved area, and then divide this available space equally into at least two consecutive test regions of the same size. These two test regions are physically isolated from each other to avoid mutual interference during the testing process. Allocating test regions of the same size ensures accurate data comparison and verification when the same test algorithm is executed subsequently. When the data in one test region is inconsistent with the corresponding data in the other test region, it can be determined that the DRAM chip has a stability problem in that region. This dual-region comparison testing mechanism can effectively eliminate accidental interference factors during the testing process, improve the accuracy and reliability of the test results, and provide basic data support for subsequent error localization and analysis.

[0055] In one implementation, the hardware configuration information of the DRAM chip is stored in Mode Register 8.

[0056] In some embodiments, Figure 4 A flowchart of S300 of the preset testing strategy provided in the embodiments of this application is shown, as follows: Figure 4 As shown, S300: This involves traversing each operating frequency supported by the test system, testing the read / write stability of the DRAM chip during direct read / write operations at each operating frequency based on at least two test regions, and testing the read / write stability of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up. The steps include:

[0057] Configure the DRAM chip at the nth frequency supported by the test system, execute the same preset read and write test strategy for each test area, and compare the test results of each test area, where 1≤n≤N, n is initially 1, and N is the number of operating frequencies supported by the test system.

[0058] If the comparison results are inconsistent, the configuration increments by one, and the steps are repeated: configure the DRAM chip at the nth frequency supported by the test system, execute at least one identical preset read / write test strategy for each test area, and compare the test results for each test area. Optionally, during the general bootloader stage, if inconsistent read / write test results are detected between two test areas, it indicates that the DRAM chip has read / write stability issues at the current operating frequency. In this case, the system will automatically skip the sleep test at the current frequency, directly adjust the DRAM chip's operating frequency to the next test frequency, and continue the read / write test. This processing mechanism ensures that even if a read / write anomaly occurs at a certain frequency, the entire test process will not be interrupted, thus enabling the complete acquisition of test results at all operating frequencies and providing comprehensive data support for subsequent analysis of frequency-related faults in the DRAM chip.

[0059] If the comparison results are consistent, preset test data is written to at least one test area. The test system is configured to enter sleep mode and wake up after a preset time. The preset test data is read and compared with the preset test data before writing. The configuration n is incremented by one, and the steps are repeated: the DRAM chip is configured to operate at the nth frequency supported by the test system, at least one identical preset read / write test strategy is executed for each test area, and the test results of each test area are compared. Optionally, when the read / write test results of two test areas are consistent, it indicates that the DRAM chip's read / write function is normal at the current operating frequency. At this time, it is necessary to further verify its data retention capability in sleep mode. The system will write the preset test data to the test area and then configure the test system to enter a low-power sleep mode. In this mode, the DRAM chip automatically enters a self-refresh state to retain data. After a preset time (e.g., 30 seconds to 5 minutes), the system is woken up, and the test data is reread for comparison. This sleep-wake test can effectively detect the data retention stability of the DRAM chip in low-power state, simulate the scenario of device waking up after sleep in actual use, and comprehensively evaluate the reliability of the DRAM chip in different operating states.

[0060] As one implementation method, before configuring the test system to enter sleep mode, the configuration states of all registers of the DRAM controller (DRAMCTRL) and physical layer (PHY) are first saved. This is because the contents of these registers will be lost when entering sleep mode later. After saving, the system writes preset test data to the testable area of ​​the DRAM, and then configures the test system to enter sleep mode (standby), causing the DRAM chips to automatically enter self-refresh state. In this state, the DRAM controller and physical layer are completely powered off, resulting in the loss of all register configuration information. When the preset sleep time ends, the system wakes up and performs recovery steps: first, the previously saved register configuration is written back to the DRAM controller and physical layer to restore their working state; then, the communication connection between the DRAM chips and the physical layer is rebuilt through the DFI (DDR PHY Interface) protocol, and a specific command is sent to make the DRAM chips exit the self-refresh state and return to normal working mode. The purpose of these technical steps is to ensure that the DRAM can correctly restore to the state before the test after the sleep-wake process, avoid misjudgments caused by the loss of register configuration, and thus accurately verify the data retention capability of the DRAM chips in the power-off self-refresh state, truly reflecting their reliability performance in actual device sleep-wake scenarios. This precise register saving and restoring mechanism is a key technical aspect in ensuring the accuracy of hibernation test results.

[0061] It is understood that the embodiments of this application do not specifically limit the testing order of the DRAM chip operating frequency. The tests can be performed sequentially from low frequency to high frequency, or from high frequency to low frequency, or any other arbitrary order can be used to traverse all supported operating frequencies according to the specific needs of the test system.

[0062] In some embodiments, the preset read / write test strategy in the stability testing method for DRAM chips provided in this application includes:

[0063] In some embodiments, the preset read / write test strategy in the stability testing method for DRAM chips provided in this application includes:

[0064] Stuck Address Test, Random Value Test, XOR Comparison Test, Subtraction Comparison Test, Multiplication Comparison Test, Division Comparison Test, OR Operation Comparison Test, AND Operation Comparison Test, Sequence Increment Comparison Test, Solid Bits Comparison Test, Checkerboard Comparison Test, Block Sequence Comparison Test, Walking Zeros Comparison Test, Walking Ones Comparison Test, Bit Spread Comparison Test, Bit Flip Comparison Test, 8-bit Wide Random Test The algorithm is at least one of the following: Test, 16-bit Wide RandomTest, March C Algorithm, March G Algorithm, and March Y Algorithm.

[0065] It is understood that the various test algorithms listed above are all standard algorithms widely used in the field of memory testing in the prior art. The inventiveness of the embodiments of this application does not lie in the content or implementation of these algorithms themselves, but in integrating and applying these algorithms to specific test timing, namely the general bootloader stage, specific test architecture (dual test area comparison verification), and specific test process (frequency traversal combined with sleep test), thereby solving the technical problems of insufficient test pressure, severe external interference, and limited test space in the prior art. By executing these existing algorithms in the middle stage of system startup, the embodiments of this application make full use of the advantages of CPU cache availability, minimal system interference, and sufficient address space in this stage, and achieve a comprehensive, accurate, and efficient test evaluation of DRAM chip stability.

[0066] In some embodiments, Figure 5 Another flowchart of S300 of the preset test strategy provided in the embodiments of this application is shown, such as... Figure 5 As shown, if the comparison results are inconsistent, the configuration n is incremented by one, and the steps of configuring the DRAM chip at the nth frequency supported by the test system, performing at least one identical preset read / write test strategy for each test area, and comparing the test results of each test area also include:

[0067] Record the first abnormal information, which includes at least one of the following: the abnormal physical address of the DRAM chip at the current frequency, the abnormal bit, the abnormal preset read / write test algorithm, and the abnormal operating frequency.

[0068] When the value of n is N, the correlation between the first abnormal information and the corresponding operating frequency and / or the preset read and write test strategy is determined based on the read and write stability test results of the DRAM chip at each operating frequency.

[0069] Optionally, during the testing process, when inconsistencies are detected in data from different test areas, detailed information such as the physical address of the abnormal location, the specific bit where the error occurred, the type of test algorithm executed, and the current operating frequency is recorded. Since the read / write function of the DRAM chip at that frequency is now determined to be abnormal, the system will automatically skip the sleep test at that frequency and continue testing the next operating frequency, ensuring complete acquisition of test data across all frequencies. After all operating frequency tests are completed, the collected abnormal information is comprehensively analyzed to determine whether the abnormality is caused by a specific operating frequency, a specific preset read / write test strategy, or both, thereby accurately pinpointing the root cause of the DRAM chip read / write abnormality.

[0070] In some embodiments, Figure 6 Another flowchart of S300 of the preset test strategy provided in the embodiments of this application is shown, such as... Figure 6 As shown, if the comparison results are consistent, the preset test data is written to at least one test area, the test system is configured to enter sleep mode and wake up after a preset time, the preset test data is read and compared with the preset test data before writing, n is incremented by one, and the steps of configuring the DRAM chip to be at the nth frequency supported by the test system, executing at least one identical preset read / write test strategy for each test area, and comparing the test results of each test area are followed by:

[0071] If the comparison result between the read preset test data and the preset test data before writing is inconsistent, then a second abnormal information is recorded. The second abnormal information includes at least one of the following: abnormal physical address, abnormal bit, abnormal preset test data, and abnormal operating frequency.

[0072] When the value of n is N, the correlation between the second abnormal information and the corresponding operating frequency and / or preset test data is determined based on the read and write stability test results of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up.

[0073] Optionally, a sleep test anomaly is a special type of test failure because it only occurs after the DRAM chip has passed the direct read / write test at the current frequency. When the system detects data inconsistency after waking from sleep, it precisely records key information such as the physical address location of the anomaly, the specific bit that flipped, the type of test algorithm executed, and the current operating frequency. Even if a sleep anomaly occurs at a certain frequency, the system will not interrupt the test process but will continue to complete the full test for all remaining operating frequencies. After all frequencies have been traversed, the system analyzes the collected sleep anomaly information to determine whether these anomalies are caused by a specific operating frequency, a specific preset test strategy, or both, thereby accurately identifying the failure mode of the DRAM chip in sleep mode.

[0074] In some embodiments, Figure 7 Another flowchart of S300 of the preset test strategy provided in the embodiments of this application is shown, such as... Figure 7 As shown, the steps for configuring the DRAM chips at the nth frequency supported by the test system, performing the same preset read / write test strategy on each test area, and comparing the test results of each test area include:

[0075] The test information generated by the preset read / write test strategy is written to the CPU cache in a preset order.

[0076] The test information in the CPU cache is written to each test area of ​​the DRAM chip.

[0077] Perform a cache invalidation operation on the CPU cache to invalidate the test information in the CPU cache.

[0078] Read test information from each test area of ​​the DRAM chip.

[0079] Compare the test information read from each test area.

[0080] Optionally, during the general bootloader stage, the CPU cache has already been initialized, allowing its high-speed read / write capabilities to be fully utilized to improve testing efficiency. During testing, the system writes the test sequence generated by the test algorithm to the CPU cache according to a preset write order, leveraging the CPU cache's high-speed characteristics to accelerate data transmission. Subsequently, this test data is written to the test area of ​​the DRAM chip. Crucially, after each write operation, the system immediately performs a cache invalidation operation on the CPU cache, completely clearing the test data from the cache. When a read operation is performed, since the CPU cache has been cleared, the read request directly accesses the DRAM chip itself without going through the cache. This mechanism forces the test operation to interact directly with the DRAM chip, avoiding interference from the CPU cache on the test results. This allows for accurate evaluation of the DRAM chip's true read / write performance and stability, with significant advantages, particularly in detecting particle-level defects and timing issues.

[0081] It is understood that the DRAM chip stability testing method provided in this application is implemented through software code. This code can be integrated into the boot process of the general bootloader stage and executed in the middle stage of system startup. The specific implementation of the code can be varied, such as an independent test module, kernel patch, extended function of the bootloader, or dedicated driver. The programming language can be C, assembly, or other languages ​​suitable for low-level hardware operation. Data structures and algorithm optimizations can also be adjusted according to the specific platform characteristics. In summary, as long as CPU caching is enabled and configured to access DRAM in burst transfer mode during the general bootloader stage, at least two test areas are allocated based on hardware configuration information, read / write and sleep stability tests are performed across the system's supported operating frequencies, and the stability of the system in the restart state is verified through multiple restarts, regardless of changes in the specific code structure, function naming, variable definition, or memory management method, it should fall within the protection scope of this application.

[0082] For example, the stability of LPDDR5 DRAM chips is verified through the stability test of DRAM chips provided in the embodiments of this application. The corresponding test system includes a CPU, 8GB of LPDDR5 DRAM chips and eMMC storage devices, and runs an operating system based on a customized Android system.

[0083] The testing process is as follows:

[0084] First, the number of reboots was set to 5, with the test program executed during the U-Boot phase after each reboot. During the U-Boot phase, the processor's L1 and L2 caches were enabled, and the CPU was configured to access DRAM in non-burst transfer mode. By reading the DRAM's MR8 mode register, it was determined that the DRAM chip was a single-die, dual-rank configuration with a total capacity of 8GB. Based on this information, the system allocated two consecutive 4GB test regions (Region A and Region B) within the DRAM address space range of 0x80000000 to 0xBFFFFFFF.

[0085] Next, the system begins iterating through the test frequencies. Assume the test system supports six operating frequencies: 400MHz, 800MHz, 1600MHz, 2133MHz, 3200MHz, and 4266MHz. Testing begins at the lowest frequency, 400MHz, and the March C algorithm, checkerboard test algorithm, and random value test algorithm are executed on two test regions. At 400MHz, 800MHz, 1600MHz, and 2133MHz, the test results for the two regions are completely consistent; however, at 3200MHz, a 0-to-1 flip error occurs in the 5th bit at address 0x98765432 in region A, while the corresponding address data in region B is normal. The system records the first anomaly information: physical address 0x98765432, bit 5, test algorithm March C, operating frequency 3200MHz, and skips the sleep test at 3200MHz, continuing to test the 4266MHz frequency. At a frequency of 4266MHz, read and write tests in both test areas passed. The system then underwent a sleep test: all DRAM register states were saved, preset test data was written to both test areas, the system was configured to enter standby sleep mode for 30 seconds and then wake up, restoring the register states. The DRAM was then exited from self-refresh mode via the DFI protocol. Upon waking and reading the test data, it was found that the data at address 0xA1234567 in area A was inconsistent with the written value. The system recorded a second anomaly: physical address 0xA1234567, bit 3, random value for the test algorithm, operating frequency 4266MHz.

[0086] After completing all frequency tests, the system analyzed the first anomaly information and determined that the read / write anomaly at 3200MHz was strongly correlated with the test frequency, and the error location was concentrated in a specific address range, indicating that the DRAM chip had insufficient timing tolerance at high frequencies. For the sleep anomaly at 4266MHz, the analysis showed that the anomaly was related to a specific physical address, but not to the test strategy, indicating that there was a defect in the self-refresh circuit.

[0087] Finally, the system underwent a reboot test. During five reboots, it failed to enter the U-Boot stage once, and the system recorded a reboot error. Based on all test results, the DRAM chip was deemed unqualified.

[0088] For example, the stability test of the DRAM chips provided in this application embodiment was performed on a DDR4-3200 DRAM module of an enterprise-grade server. The test system included a CPU, a 64GB DDR4 DRAM module, and a 1TB NVMe SSD, running a Linux system. The test focused on the stability performance of the DRAM under various workloads and frequencies.

[0089] The test configuration involved 10 reboots, each executed during the general bootloader phase. The CPU's L3 cache was enabled, and the memory controller was configured to access DRAM in de-burst transfer mode. By reading the MR8 register, the system identified the DRAM module as containing 8 dies, 4 ranks, and a total capacity of 64GB. Based on this information, the system allocated two 32GB test regions within the physical address range of 0x100000000 to 0x2FFFFFFFF.

[0090] The tests covered six operating frequencies supported by the server: 1066MHz, 1333MHz, 1600MHz, 1866MHz, 2400MHz, and 3200MHz. At each frequency, the system executed 12 test algorithms, including March Y, bit flip test, and 16-bit wide random test. All tests passed within the 1066MHz to 2400MHz frequency range; however, at 3200MHz, inconsistent results occurred in the bit flip test across the two test areas. The system recorded the first anomaly and skipped the sleep test at that frequency.

[0091] After passing the read / write test at 2400MHz, a sleep test was performed. The system saved the states of all registers of the DRAM controller and PHY, wrote the test data, and configured the system to enter S3 sleep mode for 5 minutes before waking up. Upon waking, reading the test data revealed that the data at address 0x2A1B2C3D4 in region B was inconsistent with expectations, and the second anomaly information was recorded.

[0092] After completing all frequency tests, the system analyzed the abnormal data and determined that the read / write anomalies at 3200MHz were linearly correlated with the test frequency, and were particularly evident under bit flip tests, indicating that the DRAM chips were not stable enough at the extreme frequency. The sleep anomalies at 2400MHz were related to a specific physical address region, indicating that the charge retention capability of this region was insufficient in the self-refresh state.

[0093] During the 10 reboot tests, the system failed to load the kernel correctly on the 7th reboot, and a reboot exception was recorded. Comprehensive analysis indicates that this DRAM module does not meet the requirements for enterprise-level applications.

[0094] Based on the above-described DRAM chip stability testing method, this application embodiment also provides a DRAM chip stability testing apparatus, applied to a test system including a CPU and DRAM chips, and executed during the general boot loader stage of the test system startup process. The apparatus includes:

[0095] The testing module is used to restart the test system a preset number of times. During the general bootloader phase of each test system startup, a preset test strategy is executed. The preset test strategy includes:

[0096] Enable CPU caching and configure the CPU to access DRAM chips in a deburst transfer mode.

[0097] Based on the hardware configuration information of the DRAM chip, at least two test regions are allocated in the address space of the DRAM chip.

[0098] The test system iterates through each operating frequency supported by the test system, and tests the read and write stability of the DRAM chip when directly read and written at each operating frequency based on at least two test areas, as well as the read and write stability of the DRAM chip after the test system enters sleep mode and wakes up at each operating frequency.

[0099] Each time the test system is restarted, the read and write stability of the DRAM chips is tested based on the restart status of the test system.

[0100] The DRAM chip stability testing method provided in this application embodiment is adaptable to any platform and chip type, can stably detect defective chips, and effectively improves the comprehensiveness and accuracy of DRAM chip stability testing.

[0101] For further details regarding the implementation of the above technical solution by each module in the stability testing device for DRAM chips, please refer to the description of the stability testing method for DRAM chips provided in the above embodiments of the invention, which will not be repeated here.

[0102] Based on the above-described stability testing method for DRAM chips, this application also provides an electronic device. Figure 8 A schematic diagram of an electronic device provided in an embodiment of this application is shown, such as... Figure 8 As shown, the electronic device 80 provided in this embodiment includes a processor 81 and a memory 82 coupled to the processor 81. The memory 82 stores a computer program, which, when executed by the processor 81, causes the processor 81 to perform the steps of the DRAM chip stability testing method described in the above embodiment.

[0103] For other details regarding the implementation of the above technical solution by the processor 81 in the above electronic device, please refer to the description of the stability test method for DRAM chips provided in the above embodiments of the invention, which will not be repeated here.

[0104] The processor 81 can also be called a CPU (Central Processing Unit). The processor 81 may be an integrated circuit chip with signal processing capabilities. The processor 81 can also be a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or the processor 81 can be any conventional processor.

[0105] Based on the above-described stability testing method for DRAM chips, this application also provides a computer-readable storage medium. Figure 9 A schematic diagram of a computer storage medium provided in an embodiment of this application is shown, such as... Figure 9 As shown, this application embodiment also provides a computer-readable storage medium 90, on which a readable computer program 91 is stored; wherein, the computer program 91 can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: USB flash drive, mobile hard disk, magnetic disk or optical disk, ROM (Read-Only Memory), RAM (Random Access Memory) and other media capable of storing program code, or terminal devices such as computers, servers, mobile phones, tablets and other terminal devices.

[0106] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A method for testing the stability of DRAM chips, characterized in that, A test system applied to include a CPU and the DRAM chips, wherein the stability test method for the DRAM chips includes: The test system will be restarted a preset number of times. During the general bootloader phase of each test system startup, a preset test strategy will be executed. The preset test strategy includes: Enable CPU caching and configure the CPU to access the DRAM chips in a deburst transfer mode; Based on the hardware configuration information of the DRAM chip, at least two test regions are allocated in the address space of the DRAM chip. The test system iterates through each operating frequency supported by the test system, and tests the read and write stability of the DRAM chip when directly read and written at each operating frequency based on at least two test regions, as well as the read and write stability of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up. Each time the test system is restarted, the read / write stability of the DRAM chip is tested according to the restart status of the test system during the restart. The steps of traversing each operating frequency supported by the test system, testing the read / write stability of the DRAM chip during direct read / write operations at each operating frequency based on at least two test regions, and testing the read / write stability of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up, include: Configure the DRAM chip at the nth frequency supported by the test system, execute the same preset read / write test strategy for each test region, and compare the test results for each test region. If the comparison results are inconsistent, then n is incremented by one, and the following steps are repeated: the DRAM chip is configured to be at the nth frequency supported by the test system, the same preset read and write test strategy is executed for each test area, and the test results of each test area are compared. If the comparison results are consistent, the preset test data is written to at least one of the test areas, the test system is configured to enter sleep mode and wake up after a preset time, the preset test data is read and compared with the preset test data before writing, n is incremented by one, and the following steps are re-executed: the DRAM chip is configured to be at the nth frequency supported by the test system, the same preset read and write test strategy is executed for each test area, and the test results of each test area are compared. Wherein, 1≤n≤N, and n is initially 1, and N is the number of operating frequencies supported by the test system.

2. The stability testing method for DRAM chips as described in claim 1, characterized in that, The step of allocating at least two test regions in the address space of the DRAM chip based on the hardware configuration information of the DRAM chip includes: Read the mode register in the DRAM chip used to store the hardware configuration information to obtain the hardware configuration information of the DRAM chip; Based on the hardware configuration information, at least two test regions of the same size are allocated from the available address space of the DRAM chip.

3. The stability testing method for DRAM chips as described in claim 1, characterized in that, The preset read / write test strategy includes: At least one of the following algorithms: fixed address comparison algorithm, random value comparison algorithm, XOR comparison algorithm, subtraction comparison algorithm, multiplication comparison algorithm, division comparison algorithm, OR operation comparison algorithm, AND operation comparison algorithm, sequence increment comparison algorithm, fixed bit comparison algorithm, checkerboard comparison algorithm, block sequence comparison algorithm, bit walk 0 comparison algorithm, bit walk 1 comparison algorithm, bit spread comparison algorithm, bit flip comparison algorithm, 8-bit wide random test algorithm, 16-bit wide random test algorithm, March C algorithm, March G algorithm, and March Y algorithm.

4. The stability testing method for DRAM chips as described in claim 1, characterized in that, If the comparison results are inconsistent, the step of configuring n to increment by one and re-executing the following steps—configuring the DRAM chip at the nth frequency supported by the test system, performing the same preset read / write test strategy on each test region, and comparing the test results of each test region—also includes: Record the first abnormal information, which includes at least one of the following: abnormal physical address, abnormal bit, abnormal preset read / write test algorithm, and abnormal operating frequency when the DRAM chip is at the current frequency; When the value of n is N, the correlation between the first abnormal information and the corresponding operating frequency and / or the preset read / write test strategy is determined based on the read / write stability test results of the DRAM chip under each operating frequency.

5. The stability testing method for DRAM chips as described in claim 1, characterized in that, If the comparison results are consistent, then the preset test data is written to at least one of the test areas, the test system is configured to enter a sleep mode and wake up after a preset time, the preset test data is read and compared with the preset test data before writing, n is incremented by one, and the steps of configuring the DRAM chip to be at the nth frequency supported by the test system, performing the same preset read / write test strategy on each of the test areas, and comparing the test results of each test area are further included: If the comparison result between the read preset test data and the preset test data before writing is inconsistent, then the second abnormal information is recorded. The second abnormal information includes at least one of the following: abnormal physical address, abnormal bit, abnormal preset test data, and abnormal operating frequency. When the value of n is N, the correlation between the second abnormal information and the corresponding operating frequency and / or preset test data is determined based on the read and write stability test results of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up.

6. The stability testing method for DRAM chips as described in claim 1, characterized in that, The steps of configuring the DRAM chip at the nth frequency supported by the test system, performing the same preset read / write test strategy on each test region, and comparing the test results of each test region include: The test information generated by the preset read / write test strategy is written into the CPU cache in a preset order; Write the test information in the CPU cache into each test area of ​​the DRAM chip; Perform a cache invalidation operation on the CPU cache to invalidate the test information in the CPU cache; The test information is read from each test area of ​​the DRAM chip; Compare the test information read from each of the test regions.

7. A stability testing device for DRAM chips, characterized in that, An apparatus for use in a test system including a CPU and the DRAM chips, and executed during the generic bootloader phase of the test system's startup process, the apparatus comprising: The testing module is used to restart the test system a preset number of times, and execute a preset testing strategy during the general bootloader phase of each test system startup process. The preset testing strategy includes: Enable CPU caching and configure the CPU to access the DRAM chips in a deburst transfer mode; Based on the hardware configuration information of the DRAM chip, at least two test regions are allocated in the address space of the DRAM chip. The test system iterates through each operating frequency supported by the test system, and tests the read and write stability of the DRAM chip when directly read and written at each operating frequency based on at least two test regions, as well as the read and write stability of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up. Specifically, each time the test system is restarted, the read / write stability of the DRAM chip is tested based on the restart status of the test system during the restart. The steps of traversing each operating frequency supported by the test system, testing the read / write stability of the DRAM chip during direct read / write operations at each operating frequency based on at least two test regions, and testing the read / write stability of the DRAM chip at each operating frequency after the test system enters sleep mode and wakes up, include: Configure the DRAM chip at the nth frequency supported by the test system, execute the same preset read / write test strategy for each test region, and compare the test results for each test region. If the comparison results are inconsistent, then n is incremented by one, and the following steps are repeated: configure the DRAM chip to be at the nth frequency supported by the test system, perform the same preset read and write test strategy for each test area, and compare the test results of each test area; If the comparison results are consistent, the preset test data is written to at least one of the test areas, the test system is configured to enter sleep mode and wake up after a preset time, the preset test data is read and compared with the preset test data before writing, n is incremented by one, and the following steps are re-executed: the DRAM chip is configured to be at the nth frequency supported by the test system, the same preset read and write test strategy is executed for each test area, and the test results of each test area are compared. Wherein, 1≤n≤N, and n is initially 1, and N is the number of operating frequencies supported by the test system.

8. An electronic device, characterized in that, Includes memory and processor, wherein: The memory is used to store computer programs; The processor is used to read the computer program in the memory and execute the steps of the stability test method for DRAM chips as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, It stores a readable computer program that, when executed by a processor, implements the steps of the stability testing method for DRAM chips as described in any one of claims 1 to 6.

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