Surrounding gate transistor and method of manufacturing the same

Abstract

This application provides a gate-all-around transistor and its fabrication method, belonging to the semiconductor field. The fabrication method includes: providing a substrate and forming a first well region within the substrate; forming an isolation layer on the first well region; patterning the isolation layer to expose a portion of the first well region as a drain fabrication region; forming a drain in the drain fabrication region; forming an oxide layer on the surface of the drain, with a second well region fabrication region connected to the drain surrounding the oxide layer; forming a second well region surrounding the oxide layer in the second well region fabrication region, and the second well region contacting the drain; forming a gate structure on the isolation layer, the gate structure including a gate and a gate insulating layer, the gate insulating layer surrounding the second well region; the gate surrounding the gate insulating layer; forming an insulating layer covering the gate structure and the second well region; and converting the second well region on top of the oxide layer into a source. This fabrication process can produce a transistor with a gate-all-around design, improving the gate's control over the conductive channel.

Description

Technical Field

[0001] This application belongs to the field of semiconductors, and in particular relates to a gate-all-around transistor and its fabrication method. Background Technology

[0002] Metal-oxide-semiconductor (MOS) devices are semiconductor devices that use the electric field effect to control the on and off of current. They are the basic building blocks of all modern digital integrated circuits (such as CPUs and memory chips).

[0003] With technological advancements and ever-increasing demands for computing power, MOS devices are becoming increasingly miniaturized. Existing MOS devices are generally planar, meaning the source, gate, and drain are typically spaced apart on the surface of the well region. This planar MOS device controls the conductive channel between the source and drain through the gate. As the size of MOS devices decreases, the distance between the source and drain becomes closer, the gate size becomes smaller, and the contact area between the gate and the conductive channel becomes smaller, leading to a short-channel effect and weakening the gate's control over the conductive channel. This causes a series of problems, such as drain-induced barrier (…). (Decrease threshold voltage) Problems such as fluctuations, large subthreshold swings, low current density, and high power consumption exist. How to improve the short-channel effect is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of this, this application provides a gate-all-around transistor and its fabrication method. By increasing the contact area between the gate structure and the conductive channel, the gate structure's ability to control the current in the conductive channel is greatly enhanced, thereby significantly suppressing the short-channel effect.

[0005] In a first aspect, this application provides a method for fabricating a gate-all-around transistor, comprising:

[0006] A substrate is provided, and a first well region is formed within the substrate;

[0007] An isolation layer is formed on the first trap region;

[0008] The isolation layer is patterned to expose part of the first well region, which serves as the drain fabrication region; and the drain is formed in the drain fabrication region.

[0009] An oxide layer is formed on the surface of the drain electrode, and a second well region fabrication region connected to the drain electrode is formed around the oxide layer.

[0010] A second well region surrounding the oxide layer is formed in the second well region fabrication region, and the second well region is in contact with the drain electrode;

[0011] A gate structure is formed on an isolation layer, the gate structure including a gate and a gate insulating layer, the gate insulating layer surrounding the second well region; the gate surrounds the gate insulating layer.

[0012] An insulating layer is formed, which covers the gate structure and the second well region;

[0013] The second well region on top of the oxide layer is converted into a source.

[0014] Optionally, the isolation layer is patterned to expose a portion of the first well region, serving as the drain fabrication region; and the step of forming the drain in the drain fabrication region includes:

[0015] A first barrier layer with etched windows is formed on the isolation layer;

[0016] Under the etching blocking effect of the first barrier layer, the isolation layer at the bottom of the etching window is removed, exposing the first well region;

[0017] Ion implantation is performed on the first well region at the bottom of the etching window under the ion blocking effect of the first barrier layer to form the drain.

[0018] Optionally, the step of forming an oxide layer on the drain surface includes:

[0019] Under the blocking effect of the first barrier layer, a silicon material layer is epitaxially obtained on the drain surface using a selective deposition process;

[0020] Wet etching is performed on the silicon material layer to form a second well region fabrication area whose bottom is connected to the drain electrode and surrounds the silicon material layer;

[0021] The interior of the silicon material layer is oxidized to form an oxide layer inside the silicon material layer.

[0022] Optionally, the material used for the first barrier layer is different from the material used for the first well region.

[0023] Optionally, the step of oxidizing the silicon material layer to obtain an oxide layer includes:

[0024] The oxygen injection isolation process involves injecting oxygen into the silicon material layer to oxidize it and obtain an oxide layer.

[0025] Optionally, the step of oxidizing the silicon material layer to obtain an oxide layer further includes:

[0026] Annealing is performed on the oxide layer to release its stress.

[0027] Optionally, the step of forming a second well region surrounding the oxide layer in the second well region fabrication region, and the second well region being in contact with the drain electrode, includes:

[0028] Under the blocking effect of the isolation layer, a second well region is selectively epitaxially formed on the surface of the silicon material layer in the second well region preparation region. The second well region surrounds the oxide layer and is in contact with the drain electrode.

[0029] Optionally, the material used for the isolation layer is different from the material used for the silicon material layer.

[0030] Optionally, the step of forming the gate structure located on the isolation layer includes:

[0031] A gate material layer is deposited, the gate material layer covering the isolation layer and the second well region;

[0032] Remove the gate material layer located on top of the second well region to expose the top of the second well region;

[0033] A second barrier layer is deposited on the surface of the gate material layer and on top of the second well region;

[0034] Wet etching is performed on the second barrier layer to form a gate etching window on the second barrier layer, exposing the top of the gate material layer that is in contact with the second well region;

[0035] Dry etching is used to etch the gate material layer along the gate etching window, removing part of the gate material layer at the junction with the second well region to form the gate insulating layer fabrication region;

[0036] A gate insulating layer is formed in the gate insulating layer preparation region, and after removing the second barrier layer, a gate structure is obtained.

[0037] Optionally, the thickness of the second barrier layer formed on the surface of the gate material layer and the second well region in the planar region is greater than the thickness of the second barrier layer formed on the surface of the gate material layer in the sidewall region.

[0038] Optionally, the step of forming a gate insulating layer in the gate insulating layer fabrication region includes:

[0039] A gate insulating layer is selectively epitaxially formed on the surface of the second well region exposed in the gate insulating layer preparation region.

[0040] Secondly, this application provides a gate-all-around transistor, comprising:

[0041] Substrate, with a first well region formed within the substrate;

[0042] The drain electrode is formed within the first well region;

[0043] An isolation layer is formed on the first well region, and the isolation layer is exposed at the drain electrode;

[0044] An oxide layer is formed on the drain electrode;

[0045] A second well region is formed on the drain electrode and surrounds the oxide layer;

[0046] A gate structure, located on an isolation layer, includes a gate and a gate insulating layer, the gate insulating layer surrounding the second well region, and the gate surrounding the gate insulating layer;

[0047] The source electrode is located on top of the oxide layer and the second well region;

[0048] An insulating layer covers the gate structure and the source.

[0049] Optionally, the thickness of the gate is equal to the depth of the second well region.

[0050] The unexpected technical effects of the technical solution provided in this application are:

[0051] This application provides a method for fabricating a gate-all-around transistor. The method involves fabricating a drain in a first well region, fabricating a second well region and an oxide layer on the drain surface, fabricating a source on the surface of the second well region and the oxide layer, and fabricating a gate structure on the surface of an isolation layer. The unexpected technical effects are: (1) The source and drain are distributed in the height direction, so the length of the channel is limited by the height difference between the source and drain. When the planar size of the MOS device is reduced, a certain length of the conductive channel can still be retained. While the device size is reduced, the length of the conductive channel can still be maintained, thereby reducing the problem of reduced contact area between the gate structure and the conductive channel caused by the reduction of device size. This is beneficial to improving the control capability of the gate structure over the conductive channel and suppressing the short-channel effect. (2) The gate structure surrounds the conductive channel between the source and drain, which is beneficial to further increase the contact area between the gate structure and the conductive channel, further improve the control capability of the gate over the conductive channel, and suppress the short-channel effect. Furthermore, since the gate structure surrounds the conductive channel, the thickness of the gate is equal to the length of the conductive channel. When the device size shrinks to a certain extent, the formation of a planar gate (that is, the planar length or width of the gate is equal to the length of the conductive channel) becomes increasingly difficult (because the planar gate structure requires first depositing the gate material through a deposition process, and then etching the gate material through photolithography and etching processes to form the gate. When the device size shrinks to a certain extent, the length or width of the gate will be extremely small, which will require extremely high precision in the photolithography and / or etching processes, thus making the gate fabrication very difficult). For the gate provided in this application, the gate surrounds the conductive channel, so the contact area between the gate and the conductive channel is directly limited by limiting the thickness of the gate. The thickness of the gate can be controlled by controlling the parameters of the deposition process. Compared with controlling the precision of the photolithography and / or etching processes, when the device size shrinks to a certain extent, it is easier to control the thickness of the gate by controlling the parameters of the deposition process, thus making the fabrication of the gate in this application less difficult. (3) By forming an oxide layer in the second well region, a structure similar to silicon-on-insulator (SOI) is formed, which helps to avoid latch-up effect. More specifically, in traditional MOS devices, the device structure is generally located in bulk silicon (substrate), which forms parasitic transistors with the source / drain and trap ions. Due to the amplification effect of the transistor, a positive feedback loop is formed. Ultimately, this results in a large current that burns out the device. However, the silicon-on-insulator (SOI) structure used in this application isolates the device from the bulk silicon with an oxide layer, thus preventing the formation of parasitic transistors and effectively avoiding latch-up. Generally, latch-up requires certain conditions to occur. Since it is a transistor, and the conduction of a transistor requires the base voltage to be greater than the emitter voltage, and the drain is the emitter in the transistor, latch-up cannot be triggered as long as the drain is connected to a high voltage. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0053] Figure 1 A flowchart illustrating a method for fabricating a gate-all-around transistor according to an embodiment of this application;

[0054] Figure 2 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0055] Figure 3 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0056] Figure 4 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0057] Figure 5 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0058] Figure 6 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0059] Figure 7 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0060] Figure 8 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0061] Figure 9 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0062] Figure 10 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0063] Figure 11 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0064] Figure 12 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0065] Figure 13 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0066] Figure 14 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0067] Figure 15 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0068] Figure 16 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0069] Figure 17 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0070] Figure 18 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0071] Figure 19 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0072] Figure 20 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0073] Figure 21 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0074] Figure 22 A schematic diagram of the fabrication process of a gate-all-around transistor provided in an embodiment of this application;

[0075] Figure 23 This is a schematic diagram of the structure of a gate-all-around transistor provided in an embodiment of this application;

[0076] Figure 24 A flowchart illustrating a method for fabricating a gate-all-around transistor according to another embodiment of this application;

[0077] Figure 25 This is a schematic diagram of the structure of a gate-all-around transistor provided in another embodiment of this application;

[0078] Figure 26 A cross-sectional view along the dashed line BB' of a gate-all-around transistor provided in another embodiment of this application;

[0079] Figure 27 This is a top view of a gate-all-around transistor provided in an embodiment of this application.

[0080] The attached figures are labeled as follows:

[0081] 11: Substrate; 12: First well region; 13: Isolation layer; 14: First barrier layer; 141: Etching window; 15: Drain; 16: Silicon material layer; 17: Second well region fabrication area; 18: Oxide layer; 19: Second well region; 191: Second well region material layer; 20: Gate material layer; 21: Second barrier layer; 22: Gate etching window; 23: Gate; 24: Gate insulating layer fabrication area; 25: Gate insulating layer; 26: Insulating layer; 27: Source; 28: Connection structure; 281: Source connection structure; 282: Gate connection structure; 283: Drain connection structure; 29: Intermetallic dielectric layer. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0083] Figure 1 This is a flowchart illustrating a method for fabricating a gate-all-around transistor according to an embodiment of this application. See also... Figure 1 ,include:

[0084] S101. Provide a substrate 11 and form a first well region 12 in the substrate 11.

[0085] In some examples provided in this application, substrate 11 is formed of silicon material.

[0086] For example, substrate 11 may specifically include any one of a silicon (Si) substrate, silicon-on-insulator (SOI) substrate, etc.

[0087] For example, substrate 11 is a Si substrate.

[0088] Of course, it should be noted that any substrate that can be used to fabricate MOS devices can be used as the substrate 11 in this application, and this application does not impose any restrictions on it.

[0089] See Figure 2 This is a schematic diagram of the structure of the substrate 11 provided in an embodiment of this application.

[0090] See Figure 3This is a schematic diagram of the structure of the first well region 12 prepared in the substrate 11 according to an embodiment of this application.

[0091] S102, An isolation layer 13 is formed on the first well region 12.

[0092] The purpose of step S102, which involves preparing the isolation layer 13, is to isolate the first well region 12 from the subsequently prepared gate structure, preventing the first well region 12 from contacting the gate structure. Furthermore, the isolation layer 13 can limit the growth area of ​​the second well region 19 during subsequent preparation, achieving selective growth.

[0093] In some examples, step S102 includes:

[0094] An isolation layer 13 is deposited on the surface of the first well region 12 using a deposition process.

[0095] In some examples provided in this application, the isolation layer 13 may be an oxide layer, such as a silicon oxide layer.

[0096] In some examples provided in this application, the deposition process can be a chemical vapor deposition (CVD) process.

[0097] More specifically, chemical vapor deposition processes can include any one of the following: atmospheric pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD).

[0098] It should be noted that the isolation layer 13 can also be prepared by thermal oxidation process.

[0099] See Figure 4 This is a schematic diagram of the structure of the isolation layer 13 prepared on the surface of the first well region 12 according to an embodiment of this application.

[0100] S103. Pattern the isolation layer 13 to expose part of the first well region 12 as the drain preparation region; and form the drain in the drain preparation region.

[0101] In some examples, step S103 includes:

[0102] S1031. A first barrier layer 14 with an etched window 141 is formed on the isolation layer.

[0103] In step S1031, the preparation of a first barrier layer 14 with an etch window 141 has the following unexpected technical effects: (1) By utilizing the etch blocking effect of the first barrier layer 14, the isolation layer 13 at the bottom of the etch window 141 is etched through the etch window 141 on the first barrier layer 14, thereby exposing the first well region 12 at the bottom of the etch window 141, which facilitates the subsequent preparation of the drain electrode 15 by ion implantation. (2) When preparing the drain electrode 15 by ion implantation, the ion blocking capability of the first barrier layer 14 is used to implant drain ions into the drain preparation region (i.e., the first well region 12 exposed at the bottom of the etch window 141), thereby forming the drain electrode 15. This can save one photolithography and etching process, which is beneficial to saving process costs and improving preparation efficiency. (3) By utilizing the blocking ability of the first barrier layer 14, the silicon material layer 16 can be grown to the designated area (i.e., the etching window 141) during the growth of the silicon material layer 16. The silicon material layer 16 will be grown directly on the surface of the drain 15, instead of growing on the surface of the first barrier layer 14. This can save a photolithography and etching step, which is beneficial to saving process costs and improving preparation efficiency.

[0104] In some examples, step S1031 includes:

[0105] Step 1: Prepare a first barrier layer 14 on the isolation layer 13.

[0106] In some examples, the first barrier layer 14 includes a silicon nitride layer.

[0107] In some examples, the first barrier layer 14 can be obtained by deposition on the surface of the isolation layer 13 using a deposition process.

[0108] In some examples, the deposition process used for the first barrier layer 14 includes any one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD).

[0109] See Figure 5 This is a schematic diagram of the structure of the first barrier layer 14 prepared according to an embodiment of this application.

[0110] The second step is to perform patterning on the first barrier layer 14 to form an etched window 141 on the first barrier layer 14.

[0111] In some examples, by sequentially performing photolithography (e.g., photolithography to form a photoresist pattern) and etching on the first barrier layer 14, an etched window 141 is formed on the first barrier layer 14, exposing a portion of the isolation layer 13.

[0112] In some examples, the etching process performed on the first barrier layer 14 includes dry etching and / or wet etching.

[0113] See Figure 6 This is a schematic diagram of the structure of an etched window 141 prepared on a first barrier layer 14 according to an embodiment of this application.

[0114] S1032. Under the etching blocking effect of the first barrier layer 14, the isolation layer 13 at the bottom of the etching window 141 is removed, exposing the first well region 12.

[0115] Since the isolation layer 13 covers the surface of the first well region 12, although ions can penetrate the isolation layer 13 (which is an oxide layer) when the drain electrode 15 is fabricated in the first well region 12 via ion implantation, the isolation layer 13 also hinders ion formation to some extent, which is detrimental to the fabrication of the drain electrode 15. Furthermore, since a second well region 19 needs to be fabricated on the surface of the drain electrode 15 subsequently, if the isolation layer 13 covers the surface of the drain electrode 15, it will be detrimental to the fabrication of the second well region 19. Therefore, the purpose of step S1032 is to remove part of the isolation layer 13 to expose the fabrication area of ​​the drain electrode 15.

[0116] In some examples, dry etching and / or wet etching processes can be used to etch the isolation layer 13 to expose a portion of the first well region 12, which serves as the fabrication area for the subsequent drain electrode 15.

[0117] It should be noted that the etching step performed on the isolation layer 13 in step S1032 can be combined with the etching step performed on the first barrier layer 14 in step S1031. That is, when performing the etching step on the first barrier layer 14, the etching time can be appropriately extended to remove the isolation layer 13 at the bottom of the etching window 141 on the first barrier layer 14.

[0118] See Figure 7 This is a schematic diagram of the structure of the isolation layer 13 after etching through the etching window 141 according to an embodiment of this application.

[0119] S1033. Under the ion blocking effect of the first barrier layer 14, ion implantation is performed on the first well region 12 at the bottom of the etching window 141 to form the drain 15.

[0120] Since the first barrier layer 14 has a blocking effect on ions, when the isolation layer 13 is etched through the etching window 141 of the first barrier layer 14 to expose the preparation area of ​​the drain electrode 15, ion implantation can be performed directly. Under the blocking effect of the first barrier layer 14, drain ions are controllably implanted into the preparation area of ​​the drain electrode 15 (that is, the first well region 12 at the bottom of the etching window 141 of the first barrier layer 14), thereby forming the drain electrode 15.

[0121] See Figure 8 This is a schematic diagram of the structure of the drain 15 formed in the first well region 12 by etching window 141 according to an embodiment of this application.

[0122] S104. An oxide layer 18 is formed on the surface of the drain electrode 15, and a second well region preparation region 17 connected to the drain electrode 15 is formed around the oxide layer 18.

[0123] In some examples, step S104 includes:

[0124] S1041. Under the blocking effect of the first barrier layer 14, a silicon material layer 16 is epitaxially obtained on the surface of the drain electrode 15 at the bottom of the etched window 141 using a selective deposition process.

[0125] In some examples, the first barrier layer is made of a different material than the first well region. Thus, because the first barrier layer and the first well region are made of different materials, a silicon material layer can be selectively deposited on the drain surface in subsequent steps.

[0126] In some examples, the silicon material layer 16 comprises a monocrystalline silicon layer.

[0127] In some examples, the silicon material layer 16 can be deposited using a deposition process. After the silicon material layer is deposited, it can be planarized, which can be done by chemical mechanical polishing (CMP).

[0128] In some examples, the silicon material layer 16 is deposited using a selective epitaxial growth (SEG) process.

[0129] Selective epitaxial growth (SEG) is a special type of vapor-phase epitaxy process that achieves selective growth by adding an etchant to the reactive gas. The reactive gas (such as a silicon source gas) decomposes on the heated silicon wafer surface, and silicon atoms use the substrate silicon lattice as a template to grow single crystals.

[0130] More specifically, on the surface of the amorphous first barrier layer 14, silicon atoms cannot find ordered lattice positions and can only randomly form many tiny, weakly bonded polycrystalline or amorphous silicon nuclei. By introducing gaseous etchants into the reaction chamber, these etchants preferentially attack and remove the weakly bonded silicon nuclei. On a monocrystalline silicon surface, the deposition rate is greater than the etching rate, so the net effect is growth. On the surface of the first barrier layer 14, the deposition rate is much smaller than the etching rate, so any silicon nuclei attempting to form are immediately removed, and the surface remains clean. Consequently, the silicon material layer 16 selectively grows on the drain 15 surface at the bottom of the etch window 141 of the first barrier layer 14, without growing monocrystalline silicon on the surface of the first barrier layer 14. This avoids additional planarization processes (such as CMP), saves process costs, and improves fabrication efficiency.

[0131] In some examples, the etchant used in the Selective Epitaxial Growth (SEG) process includes hydrogen chloride. This is merely an illustrative example of the etchant used in this application. It should be noted that the choice of etchant is solely for suppressing the growth of the silicon material layer 16 on the surface of the first barrier layer 14. Other etchants that can suppress the growth of the silicon material layer 16 may also be used, and this application does not limit this choice.

[0132] See Figure 9 This is a schematic diagram of the structure of a silicon material layer 16 selectively grown through an etching window 141 according to an embodiment of this application.

[0133] After the silicon material layer 16 is prepared, the first barrier layer 14 is removed using a wet etching process (e.g., using hot phosphoric acid (H3PO4) as the etching solution). See [link to relevant documentation]. Figure 10 This is a schematic diagram of the structure after removing the first barrier layer 14 according to an embodiment of this application.

[0134] S1042. Perform wet etching on the silicon material layer 16 to form a second well region fabrication region 17 whose bottom is connected to the drain electrode 15 and surrounds the silicon material layer 16.

[0135] The purpose of step S1042 is to etch the silicon material layer 16 using the isotropic characteristics of wet etching, with each area of ​​the surface of the silicon material layer 16 being etched by the wet etching solution. Ultimately, under isotropic etching, the dimensions of the silicon material layer 16 are reduced in all directions. When the horizontal cross-sectional area of ​​the silicon material layer 16 is reduced, a second well region fabrication region 17 is formed around the silicon material layer 16, exposing the drain electrode 15. The second well region fabrication region 17 surrounds the silicon material layer 16, and the bottom of the second well region fabrication region 17 exposes the drain electrode 15.

[0136] For example, the etching of the silicon material layer 16 is performed using a hot alkaline solution. The alkaline solution has a very high etching selectivity for silicon and silicon dioxide, which ensures that the silicon material layer 16 is etched without damaging the isolation layer 13. The etching solution can be tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

[0137] In one embodiment, tetramethylammonium hydroxide (TMAH) is selected as the etching solution, and a 2.5% to 25% aqueous solution is used at a temperature range of 60°C to 90°C. Normally, the etching of single-crystal silicon in alkaline solutions is inherently anisotropic, but within the aforementioned concentration and temperature limits, the etching behavior can be adjusted to be nearly isotropic, thereby achieving a uniform "layer reduction" effect.

[0138] See Figure 11 This is a schematic diagram of the structure of the second well region preparation region 17 formed after wet etching of the silicon material layer 16 according to an embodiment of this application.

[0139] S1043. Oxidize the interior of the silicon material layer 16 to form an oxide layer 18 inside the silicon material layer 16.

[0140] The purpose of step S1043 is to oxidize the silicon material layer 16 into an oxide layer 18. In subsequent process steps, the oxide layer 18 will be surrounded by a second well region 19, which is used to connect the source 27 and the drain 15, i.e., the second well region 19 will subsequently serve as a conductive channel. By forming the oxide layer 18 within the second well region 19, a structure similar to silicon-on-insulator (SOI) is formed, which helps to avoid latch-up effects.

[0141] More specifically, traditional MOS devices are typically located in bulk silicon (substrate), forming parasitic transistors with the source / drain and trap ions. Due to the amplification effect of the transistors, a positive feedback loop is formed, ultimately resulting in a large current that burns out the device. However, the silicon-on-insulator (SOI) structure used in this application isolates the device from the bulk silicon using oxide layer 18, thus preventing the formation of parasitic transistors and effectively avoiding latch-up. Latch-up generally requires certain conditions to occur. Since it is a transistor, and transistor conduction requires a base voltage greater than the emitter voltage, and the drain is the emitter of the transistor, latch-up cannot be triggered as long as the drain is connected to a high voltage.

[0142] In some examples, step S1043 includes:

[0143] S10431. Using the oxygen injection isolation process (SIMOX), oxygen is injected into the silicon material layer 16 to oxidize the interior of the silicon material layer 16, resulting in a vertically isolated oxide layer 18.

[0144] It should be noted that the energy of ion implantation determines the depth to which oxygen ions can penetrate, which in turn determines the depth of oxide layer 18.

[0145] The ion implantation dose determines the number of oxygen atoms implanted per unit area. The dose must be high enough to ensure that stoichiometric silicon dioxide (SiO2) is formed after subsequent annealing, rather than oxygen-deficient silicon oxide.

[0146] In some examples, step S1043 further includes:

[0147] S10432. Perform an annealing process on the oxide layer 18 to release the stress in the oxide layer 18.

[0148] In some examples, after performing step S10431, which oxidizes the silicon material layer 16 into an oxide layer 18, a certain stress will be generated. By performing an annealing process, the stress generated during the oxidation of the silicon material layer 16 can be released.

[0149] It should be noted that when the oxide layer 18 is prepared using the oxygen implantation isolation process, only a certain depth within the silicon material layer 16 is converted into the oxide layer 18. This means that a portion of the silicon material layer 16 will remain on the surface of the final oxide layer 18. This remaining portion of the silicon material layer 16 can then be used as a growth template for the second well region 19 during subsequent preparation. This allows the second well region 19 to selectively grow on the surface of this remaining portion of the silicon material layer 16. This selective growth can help save on photolithography and etching processes, thereby improving preparation efficiency and reducing process costs.

[0150] See Figure 12 This is a schematic diagram of the structure of an oxide layer 18 obtained by oxidizing a silicon material layer 16 according to an embodiment of this application. The interior of the silicon material layer 16 is oxidized to form the oxide layer 18, while the upper surface layer of the silicon material layer 16 is not oxidized and is retained.

[0151] S105, a second well region 19 surrounding the oxide layer 18 is formed in the second well region preparation region, and the second well region 19 is in contact with the drain electrode 15.

[0152] The purpose of step S105 is to form a second well region 19 surrounding the oxide layer 18 on the surface of the drain 15. In the subsequently fabricated MOS device, a source 27 will be fabricated on the second well region 19 and the oxide layer 18, thus the second well region 19 will serve as a conductive channel. By converting the horizontally arranged source 27, drain 15, and the conductive channel between source 27 and drain 15 into a sequential arrangement in the height direction, the length of the conductive channel can still be effectively ensured as the horizontal size of the MOS device decreases. Furthermore, this height-direction arrangement is beneficial for further miniaturization of the MOS device's planar size.

[0153] In some examples, step S105 includes:

[0154] S1051a Under the growth barrier effect of the isolation layer 13, a second well region 19 is selectively epitaxially formed on the surface of the silicon material layer 16 in the second well region preparation region 17. The second well region 19 is covered by the oxide layer 18 and is in contact with the drain electrode 15.

[0155] In some examples, the isolation layer is made of a different material than the silicon material layer. Because the isolation layer and the silicon material layer are made of different materials, a second well region can be formed on the surface of the silicon material layer through selective epitaxy in subsequent steps.

[0156] In step S1051a, by directly using the silicon material layer 16 as a growth template, a second well region 19 doped with well region dopants is selectively epitaxially grown. After the second well region 19 is grown, high-temperature annealing is performed, so that the well region dopants in the second well region 19 will directly diffuse into the silicon material layer 16, assimilating a portion of the silicon material layer 16 remaining on the upper surface of the oxide layer 18 into the second well region 19.

[0157] See Figure 13 When the structural schematic diagram of the second well region 19 obtained by executing step S1051a is executed, at this time, Figure 12 In the second well region preparation region 17, single-crystal silicon containing well region impurities will be grown, and through annealing, the well region dopant elements will diffuse to... Figure 12 In the residual silicon material layer 16, the final result is as follows Figure 13 The second well region 19 is shown.

[0158] In another example, step S105 includes:

[0159] S1051b, Under the blocking effect of the isolation layer 13, a second well region material layer 191 is epitaxially obtained on the second well region preparation region 17.

[0160] In step S1051b, the residual silicon material layer 16 on the surface of the oxide layer 18 is used directly as a growth template to selectively grow the second well region material layer 191 epitaxially. The second well region material layer 191 is a single-crystal silicon layer.

[0161] In step S1051b, selective epitaxy is also used, so that the second well region material layer 191 will only grow on the surface of the silicon material layer 16.

[0162] See Figure 14 According to an embodiment of this application Figure 12 The diagram shows a schematic of the structure of the second well region material layer 191 prepared as shown.

[0163] S1052b, Ion implantation is performed on the second well region material layer 191 to form the second well region 19.

[0164] In step S1052b, well region dopant elements are implanted into the second well region material layer 191 and the residual silicon material layer 16 simultaneously using an ion implantation process, thereby converting the second well region material layer 191 and the residual silicon material layer 16 into the second well region 19.

[0165] See Figure 13 ,right Figure 14 After ion implantation is performed on the structure shown, the second well region material layer 191 and the silicon material layer 16 are transformed into the second well region 19.

[0166] It should be noted that when performing ion implantation on the second well region material layer 191 and the silicon material layer 16, an ion blocking layer may not be prepared. Some of the implanted well region ions may penetrate the isolation layer 13 and enter the first well region 12.

[0167] S106. A gate structure is formed on the isolation layer 13, the gate structure including a gate 23 and a gate insulating layer 25, the gate insulating layer 25 surrounding the second well region 19; the gate 23 surrounding the gate insulating layer 25.

[0168] In some examples, step S106 includes:

[0169] S1061, Deposit a gate material layer 20, the gate material layer 20 covering the isolation layer and the second well region 19.

[0170] In some examples, step S1061 includes

[0171] Polycrystalline silicon is deposited using a deposition process to form the gate material layer 20. After the gate material layer 20 is deposited, dopant elements are implanted into the gate material layer 20 using an ion implantation process.

[0172] In some examples, the deposition process of the gate material layer 20 may include a low-pressure chemical vapor deposition (LPCVD) process.

[0173] In some examples, the elements implanted in the gate material layer 20 are determined according to the type of MOS device.

[0174] In some examples, for NMOS devices, phosphorus or arsenic can be doped into the gate material layer 20, and for PMOS devices, boron can be doped into the gate material layer 20.

[0175] See Figure 15 This is a schematic diagram of the structure of the gate material layer 20 prepared according to an embodiment of this application.

[0176] S1062. Remove the gate material layer 20 located on top of the second well region 19 to expose the top of the second well region 19.

[0177] In subsequent steps, source impurities are implanted into the second well region 19 on top of the oxide layer 18 using an ion implantation process, thereby forming the source 27 in the second well region 19 on top of the oxide layer 18. Therefore, in step S1062, the gate material layer 20 located on top of the second well region 19 is removed first, which can prevent the gate material layer 20 located on top of the second well region 19 from affecting the subsequent fabrication process of the source 27.

[0178] In some examples, step S1062 includes:

[0179] The gate material layer 20 located on top of the second well region 19 is removed by chemical mechanical polishing (CMP) to expose the top of the second well region 19.

[0180] See Figure 16 This is a schematic diagram of the structure of the gate material layer 20 after removing the gate material layer 20 at the top of the second well region 19 according to an embodiment of this application.

[0181] S1063, deposit a second barrier layer 21 on the surface of the gate material layer 20 and on top of the second well region 19.

[0182] The purpose of step S1063, which involves depositing the second barrier layer 21, is to increase the thickness of the sidewall region (i.e., Figure 17 D1 in the figure is less than the thickness of the planar region (i.e. Figure 17 The second barrier layer 21 of D2 is used to facilitate the formation of a gate etching window 22 on the second barrier layer 21 that exposes the gate material layer 20 by utilizing the isotropic etching characteristics of the wet etching process. The gate material layer is then etched through the gate etching window to form the gate 23.

[0183] In some examples, step S1063 includes:

[0184] A second barrier layer 21 is deposited on the surface of the gate material layer 20 and on top of the second well region 19 using a deposition process.

[0185] In some examples, the thickness of the second barrier layer 21 formed on the surface of the gate material layer 20 and the second well region 19 in the planar region is greater than the thickness of the second barrier layer 21 formed on the surface of the gate material layer 20 in the sidewall region.

[0186] In some examples, the second barrier layer 21 includes a silicon nitride layer.

[0187] In some examples, the deposition process includes physical vapor deposition (PVD).

[0188] Physical vapor deposition (PVD) exhibits high directionality; the sputtered atoms fly with a strong directionality, similar to a "spray." Effective deposition is only possible when the atomic flight direction is perpendicular to the surface of the area to be deposited. For the horizontal surfaces of a step (top and bottom), atoms can be incident perpendicularly, resulting in a normal deposition rate. For the vertical sidewalls of a step, atoms are incident almost parallel to the surface, making adsorption difficult. The deposition thickness on the sidewalls can be very thin, even zero, creating a so-called "shadowing effect" or "masking effect." Therefore, when forming a second barrier layer using PVD, it is ensured that the second barrier layer is thinner in the sidewall regions and thicker in the planar regions.

[0189] When the thickness of the sidewalls of the second barrier layer 21 is less than the thickness of the plane, in subsequent steps, when the second barrier layer is etched using the isotropic etching characteristics of wet etching, the sidewalls of the second barrier layer 21 will be quickly etched away, while the thickness of the second barrier layer 21 in the planar region will decrease, but the second barrier layer 21 in the planar region will remain. Thus, in subsequent steps, the second barrier layer 21 in the sidewall region is etched away, exposing the gate material layer 20, while the second barrier layer 21 in the planar region is retained as an etching barrier. When the gate material layer 20 is etched, the gate material layer 20 at the sidewall locations can be precisely etched away by the retaining second barrier layer 21 in the planar region, thereby forming the gate insulating layer fabrication region 24.

[0190] See Figure 17 This is a schematic diagram of the structure of a second barrier layer 21 deposited on the surface of the gate material layer 20 and on top of the second well region 19, according to an embodiment of this application. The thickness of the planar region of the second barrier layer 21 is greater than the thickness of the sidewall region of the second barrier layer 21.

[0191] In some examples, the difference between the thickness of the second barrier layer 21 at the planar location and the thickness at the sidewall needs to be greater than the thickness of the gate material layer 20, so that an isotropic etching process can be used in subsequent processes to remove part of the second barrier layer 21 to form the gate insulating layer fabrication region 24.

[0192] S1064. Perform wet etching on the second barrier layer 21 to form a gate etching window 22 on the second barrier layer 21, exposing the top of the gate material layer 20 that is in contact with the second well region 19.

[0193] In some examples, the isotropic etching characteristics of wet etching processes (such as using hot phosphoric acid (H3PO4) as an etchant) are utilized to etch the second barrier layer 21, thereby forming a gate etching window 22 at the junction of the sidewall region and the planar region of the second barrier layer 21.

[0194] See Figure 18 This is a schematic diagram of the gate etching window 22 obtained after wet etching of the second barrier layer 21 according to an embodiment of this application.

[0195] S1065. Using dry etching, the gate material layer 20 is etched along the gate etching window 22 to remove part of the gate material layer 20 that is connected to the second well region 19, forming the gate insulating layer preparation region 24.

[0196] See Figure 19 This is a schematic diagram of the structure of the gate insulating layer preparation region 24 obtained by etching the gate material layer 20 along the gate etching window using reactive ion etching (RIE) process in an embodiment of this application.

[0197] After the gate material layer 20 is dry etched, the remaining gate material layer 20 is used as the gate 23.

[0198] S1066. A gate insulating layer 25 is formed in the gate insulating layer preparation region 24. After removing the second barrier layer 21, a gate structure is obtained.

[0199] In some examples, step S1066 includes:

[0200] On the surface of the second well region 19 exposed in the gate insulating layer preparation region 24, the gate insulating layer 25 is selectively epitaxially formed.

[0201] In step S1066, a selective epitaxial process is used.

[0202] For example, a silicon oxide layer can be formed by first depositing a monocrystalline silicon layer, then oxidizing the monocrystalline silicon layer, and annealing it, thereby serving as the gate insulating layer 25.

[0203] Under this selective growth process, the single-crystal silicon layer will only grow on the surface of the second well region 19 exposed in the gate insulating layer preparation region 24, and will not grow on the surface of the second barrier layer 21.

[0204] In some other examples, step S1066 includes:

[0205] A gate insulating layer 25 is obtained on the surface of the second well region 19 exposed in the gate insulating layer preparation region 24 by a thermal oxidation process.

[0206] See Figure 20 This is a schematic diagram of a structure in which a gate insulating layer 25 is formed in the gate insulating layer preparation region 24 according to an embodiment of this application. The gate insulating layer 25 and the gate electrode 23 together constitute the gate structure.

[0207] Once the gate insulating layer 25 is prepared, the second barrier layer 21 can be removed.

[0208] In some examples, the second barrier layer 21 can be removed by dry etching and / or wet etching processes.

[0209] See Figure 21 This is a schematic diagram of the structure after the second barrier layer 21 is removed by dry etching and / or wet etching processes according to an embodiment of this application.

[0210] S107, forming an insulating layer 26, which covers the gate structure and the second well region 19.

[0211] In some examples, step S107 includes:

[0212] An insulating layer 26 is formed on the surface of the gate 23 and the second well region 19 by a deposition process.

[0213] In some examples, insulating layer 26 includes a silicon dioxide layer.

[0214] In some examples, the deposition process for preparing the insulating layer 26 includes any one of the following processes: low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc.

[0215] See Figure 22 This is a schematic diagram of the structure of the insulating layer 26 deposited by a deposition process according to an embodiment of this application.

[0216] S108, convert the second well region 19 at the top of the oxide layer 18 into a source 27.

[0217] In some examples, step S108 includes:

[0218] Ion implantation is used to implant source ions into the top of the second well region 19, thereby converting the top of the second well region 19 into a source 27.

[0219] It should be noted that if the MOS device is an NMOS device, the element implanted during the fabrication of source 27 can include either arsenic or phosphorus. If the MOS device is a PMOS device, the element implanted during the fabrication of source 27 can include boron.

[0220] See Figure 23 This is a schematic diagram of the source electrode 27 prepared by ion implantation process in an embodiment of this application.

[0221] See Figure 23 This application provides a gate-all-around transistor, comprising:

[0222] Substrate 11, with a first well region 12 formed within the substrate;

[0223] Drain 15 is formed within the first well region;

[0224] An isolation layer 13 is formed on the first well region, and the isolation layer exposes the drain electrode 15;

[0225] Oxide layer 18 is formed on drain electrode 15;

[0226] A second well region 19 is formed on the drain electrode 15 and surrounds the oxide layer 18;

[0227] A gate structure, located on the isolation layer 13, includes a gate 23 and a gate insulating layer 25, the gate insulating layer 25 surrounding the second well region 19; the gate 23 surrounding the gate insulating layer 25;

[0228] Source 27 is located on top of oxide layer 18 and second well region 19;

[0229] Insulating layer 26 covers the gate structure (i.e., covers gate 23 and gate insulating layer 25) and source 27.

[0230] In some examples, the thickness of the gate is equal to the depth of the second well region. Controlling the depth of the well region by the gate thickness reduces the fabrication difficulty of the gate and well region when manufacturing transistors with small planar dimensions. By controlling the process parameters of the deposition process, and thus the gate thickness and the depth of the second well region, the fabrication difficulty of the gate is lower than that of controlling the gate size through photolithography.

[0231] Figure 24 A flowchart illustrating a method for fabricating a gate-all-around transistor according to another embodiment of this application. See also... Figure 24 ,include:

[0232] S201. Provide a substrate and form a first well region within the substrate.

[0233] See step S101.

[0234] S202, An isolation layer is formed on the first well region.

[0235] See step S102.

[0236] S203. Pattern the isolation layer to expose part of the first well region as the drain preparation region; and form the drain in the drain preparation region.

[0237] See step S103.

[0238] S204. An oxide layer is formed on the surface of the drain electrode, and a second well region preparation region connected to the drain electrode is formed around the oxide layer.

[0239] See step S104.

[0240] S205. A second well region surrounding the oxide layer is formed in the second well region preparation region, and the second well region is in contact with the drain electrode.

[0241] See step S105.

[0242] S206. A gate structure is formed on an isolation layer, the gate structure including a gate and a gate insulating layer, the gate insulating layer surrounding the second well region; the gate surrounding the gate insulating layer.

[0243] See step S106.

[0244] S207. An insulating layer is formed, which covers the gate structure and the second well region.

[0245] See step S107.

[0246] S208, convert the second well region at the top of the oxide layer into a source.

[0247] See step S108.

[0248] S209. Prepare the connection structure by leading out the source, drain, and gate.

[0249] Once the source 27 is fabricated, a connection structure 28 can be fabricated to bring out the gate 23, source 27 and drain 15 using a metal interconnect process (contact process).

[0250] In some examples, step S209 includes:

[0251] S2091. Prepare contact holes.

[0252] Contact holes leading to the source, drain, and gate are precisely etched in the insulating layer covering the transistor.

[0253] In some examples, step S2091 includes:

[0254] Step 1: Deposition of the interlayer medium.

[0255] A thick intermetallic dielectric layer 29 is deposited on the silicon wafer after the transistor front-end process is completed.

[0256] The second step is to perform photolithography on the intermetallic dielectric layer 29.

[0257] Photoresist is applied, and through exposure and development, a patterned etch barrier layer is formed on the surface of the intermetallic dielectric layer, defining the location to be etched.

[0258] The third step is to perform dry etching on the intermetallic dielectric layer 29.

[0259] Using photoresist as a mask, anisotropic etching is used to precisely etch deep holes until the source, drain, and gate surfaces underneath are exposed.

[0260] S2092, forming metal silicides.

[0261] The purpose of step S2092 is to significantly reduce the contact resistance between silicon (or polycrystalline silicon) and the subsequent contact metal.

[0262] In some examples, step S2092 employs a self-aligned silicide process to form metal silicides.

[0263] In some examples, step S2092 includes:

[0264] The first step is to deposit a layer of transition metal (such as nickel or cobalt) on the entire silicon wafer surface before or after etching the contact holes.

[0265] The second step involves rapid thermal annealing, where the metal reacts with the exposed silicon (source / drain region) or polysilicon (gate) to form a low-resistance metal silicide.

[0266] The third step is to remove unreacted metals.

[0267] S2093, Deposition barrier layer / adhesion layer.

[0268] The purpose of step S2093 is to prevent the main filler metal (such as tungsten) in the contact hole from diffusing into the silicon and contaminating the device; at the same time, it enhances the adhesion between the dielectric layer and the metal.

[0269] In some examples, step S2093 typically uses a bilayer structure of titanium and titanium nitride as a barrier / adhesive layer. Ti helps to form good ohmic contacts, while TiN serves as an excellent diffusion barrier layer.

[0270] S2094, depositing the main contact metal to form a connection structure.

[0271] The purpose of step S2094 is to completely fill the contact hole with a low resistivity metal.

[0272] In some examples, chemical vapor deposition is used to give the tungsten film good step coverage, which can fill the high aspect ratio contact holes without pores, and finally obtain the connection structure 28 that leads out the gate, source and drain respectively.

[0273] In some examples, planarization processes, such as chemical mechanical polishing, are used to remove excess tungsten and barrier layers from the surface of the intermetallic dielectric layer, leaving tungsten only inside the contact hole to form a separate "tungsten plug".

[0274] See Figure 25 , is the connection structure 28 prepared according to step S209, wherein Figure 25 The diagram shows the source connection structure 281 that leads out the source 27 and the gate connection structure 282 that leads out the gate 23.

[0275] See Figure 26 , for along Figure 25 The cross-sectional view obtained by the dashed line BB'. Figure 26 The diagram further illustrates a drain connection structure 283 that brings out the drain 15. The area of ​​the drain 15 is larger than the area of ​​the source 27, so that the drain connection structure 283 is connected to the surface of the drain 15 that is not blocked by the source 27, thereby bringing out the drain 15.

[0276] It should be noted that when the drain connection structure 283 is brought out, an intermetallic dielectric layer 29 is required to separate the drain connection structure 283 from the gate 23.

[0277] See Figure 27 This is a top view of a gate-all-around transistor provided in an embodiment of this application. Figure 27 The positional relationship of the source connection structure 281, the gate connection structure 282, and the drain connection structure 283 are shown in the diagram. Furthermore, Figure 27 The accompanying drawings also show the dashed cross-section lines AA' and BB'. In the drawings provided in this application, Figure 26 This is a cross-sectional view taken along the dashed line BB'. Figures 2 to 23 , Figure 25 This is a cross-sectional view obtained along the dashed line AA' of the cross-section.

[0278] The unexpected technical effects of the technical solution provided in this application are:

[0279] This application provides a method for fabricating a gate-all-around transistor. The method involves fabricating a drain in a first well region, fabricating a second well region and an oxide layer on the drain surface, fabricating a source on the surface of the second well region and the oxide layer, and fabricating a gate structure on the surface of an isolation layer. The unexpected technical effects are: (1) The source and drain are distributed in the height direction, so the length of the channel is limited by the height difference between the source and drain. When the planar size of the MOS device is reduced, a certain length of the conductive channel can still be retained. While the device size is reduced, the length of the conductive channel can still be maintained, thereby reducing the problem of reduced contact area between the gate structure and the conductive channel caused by the reduction of device size. This is beneficial to improving the control capability of the gate structure over the conductive channel and suppressing the short-channel effect. (2) The gate structure surrounds the conductive channel between the source and drain, which is beneficial to further increase the contact area between the gate structure and the conductive channel, further improve the control capability of the gate over the conductive channel, and suppress the short-channel effect. Furthermore, since the gate structure surrounds the conductive channel, the thickness of the gate is equal to the length of the conductive channel. When the device size shrinks to a certain extent, the formation of a planar gate (that is, the planar length or width of the gate is equal to the length of the conductive channel) becomes increasingly difficult (because the planar gate structure requires first depositing the gate material through a deposition process, and then etching the gate material through photolithography and etching processes to form the gate. When the device size shrinks to a certain extent, the length or width of the gate will be extremely small, which will require extremely high precision in the photolithography and / or etching processes, thus making the gate fabrication very difficult). For the gate provided in this application, the gate surrounds the conductive channel, so the contact area between the gate and the conductive channel is directly limited by limiting the thickness of the gate. The thickness of the gate can be controlled by controlling the parameters of the deposition process. Compared with controlling the precision of the photolithography and / or etching processes, when the device size shrinks to a certain extent, it is easier to control the thickness of the gate by controlling the parameters of the deposition process, thus making the fabrication of the gate in this application less difficult. (3) By forming an oxide layer in the second well region, a structure similar to silicon-on-insulator (SOI) is formed, which helps to avoid latch-up effect. More specifically, in traditional MOS devices, the device structure is generally located in bulk silicon (substrate), which forms parasitic transistors with the source / drain and trap ions. Due to the amplification effect of the transistor, a positive feedback loop is formed. Ultimately, this results in a large current that burns out the device. However, the silicon-on-insulator (SOI) structure used in this application isolates the device from the bulk silicon with an oxide layer, thus preventing the formation of parasitic transistors and effectively avoiding latch-up. Generally, latch-up requires certain conditions to occur. Since it is a transistor, and the conduction of a transistor requires the base voltage to be greater than the emitter voltage, and the drain is the emitter in the transistor, latch-up cannot be triggered as long as the drain is connected to a high voltage.

[0280] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of fabricating a gate-all-around transistor, comprising: include: A substrate is provided, and a first well region is formed within the substrate; An isolation layer is formed on the first trap region; The isolation layer is patterned to expose part of the first well region, which serves as the drain fabrication region; and the drain is formed in the drain fabrication region. An oxide layer is formed on the surface of the drain electrode, and a second well region fabrication region connected to the drain electrode is formed around the oxide layer. A second well region surrounding the oxide layer is formed in the second well region fabrication region, and the second well region is in contact with the drain electrode; A gate structure is formed on an isolation layer, the gate structure including a gate and a gate insulating layer, the gate insulating layer surrounding the second well region; the gate surrounds the gate insulating layer. An insulating layer is formed, which covers the gate structure and the second well region; Convert the second well region at the top of the oxide layer into a source; The isolation layer is patterned to expose part of the first well region, which serves as the drain electrode fabrication region; The steps for forming the drain in the drain fabrication region include: A first barrier layer with etched windows is formed on the isolation layer; Under the etching blocking effect of the first barrier layer, the isolation layer at the bottom of the etching window is removed, exposing the first well region; Ion implantation is performed on the first well region at the bottom of the etching window under the ion blocking effect of the first barrier layer to form the drain. The steps for forming an oxide layer on the drain surface include: Under the blocking effect of the first barrier layer, a silicon material layer is epitaxially obtained on the drain surface using a selective deposition process; Wet etching is performed on the silicon material layer to form a second well region fabrication area whose bottom is connected to the drain electrode and surrounds the silicon material layer; The interior of the silicon material layer is oxidized to form an oxide layer inside the silicon material layer.

2. The method of claim 1, wherein the method further comprises: The steps for oxidizing a silicon material layer to obtain an oxide layer include: The oxygen injection isolation process involves injecting oxygen into the silicon material layer to oxidize it and obtain an oxide layer.

3. The method for fabricating a gate-all-around transistor according to claim 2, characterized in that, The step of oxidizing the silicon material layer to obtain the oxide layer also includes: Annealing is performed on the oxide layer to release its stress.

4. The method for fabricating a gate-all-around transistor according to claim 1, characterized in that, The step of forming a second well region surrounding an oxide layer in a second well region fabrication region, and having the second well region in contact with a drain electrode, includes: Under the blocking effect of the isolation layer, a second well region is selectively epitaxially formed on the surface of the silicon material layer in the second well region preparation region. The second well region surrounds the oxide layer and is in contact with the drain electrode.

5. The method for fabricating a gate-all-around transistor according to any one of claims 1 to 4, characterized in that, The steps for forming the gate structure located on the isolation layer include: A gate material layer is deposited, the gate material layer covering the isolation layer and the second well region; Remove the gate material layer located on top of the second well region to expose the top of the second well region; A second barrier layer is deposited on the surface of the gate material layer and on top of the second well region; Wet etching is performed on the second barrier layer to form a gate etching window on the second barrier layer, exposing the top of the gate material layer that is in contact with the second well region; Dry etching is used to etch the gate material layer along the gate etching window, removing part of the gate material layer at the junction with the second well region to form the gate insulating layer fabrication region; A gate insulating layer is formed in the gate insulating layer preparation region, and after removing the second barrier layer, a gate structure is obtained.

6. The method for fabricating a gate-all-around transistor according to claim 5, characterized in that, The thickness of the second barrier layer formed on the surface of the gate material layer and the second well region in the planar region is greater than the thickness of the second barrier layer formed on the surface of the gate material layer in the sidewall region.

7. The method for fabricating a gate-all-around transistor according to claim 5, characterized in that, The steps for forming a gate insulating layer in the gate insulating layer fabrication region include: A gate insulating layer is selectively epitaxially formed on the surface of the second well region exposed in the gate insulating layer preparation region.

8. A gate-all-around transistor, characterized in that, include: Substrate, with a first well region formed within the substrate; The drain electrode is formed within the first well region; An isolation layer is formed on the first well region, and the isolation layer is exposed at the drain electrode; An oxide layer is formed on the drain electrode; A second well region is formed on the drain electrode and surrounds the oxide layer; A gate structure, located on an isolation layer, includes a gate and a gate insulating layer, the gate insulating layer surrounding the second well region, and the gate surrounding the gate insulating layer; The source electrode is located on top of the oxide layer and the second well region; An insulating layer covers the gate structure and the source. The isolation layer is patterned to expose part of the first well region, which serves as the drain electrode fabrication region; The steps for forming the drain in the drain fabrication region include: A first barrier layer with etched windows is formed on the isolation layer; Under the etching blocking effect of the first barrier layer, the isolation layer at the bottom of the etching window is removed, exposing the first well region; Ion implantation is performed on the first well region at the bottom of the etching window under the ion blocking effect of the first barrier layer to form the drain. The steps for forming an oxide layer on the drain surface include: Under the blocking effect of the first barrier layer, a silicon material layer is epitaxially obtained on the drain surface using a selective deposition process; Wet etching is performed on the silicon material layer to form a second well region fabrication area whose bottom is connected to the drain electrode and surrounds the silicon material layer; The interior of the silicon material layer is oxidized to form an oxide layer inside the silicon material layer.

9. The all-around gate transistor according to claim 8, characterized in that, The thickness of the gate is equal to the depth of the second well region.

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