A method of manufacturing a mesa-type semiconductor device

Abstract

The application discloses a manufacturing method of a mesa type semiconductor device, and comprises the following steps: S1, double-sided etching and mesa etching; S2, performing thermal oxidation smoothing treatment, so that the angle of the smoothed notch is greater than or equal to 100 degrees; S3, selectively removing the oxidation layer which needs to be removed; and S4, performing subsequent standard processes. The application actively smoothes the sharp corner of the notch into a round corner by using the characteristic that the rate of thermal oxidation is faster at the sharp corner, so that the mechanical collapse edge defects in the subsequent processes are fundamentally eliminated. The impurity segregation effect caused at the same time optimizes the surface doping concentration, the breakdown voltage is improved, the triggering characteristics of the device are optimized, and the silicon controlled rectifier triggering current IGT is reduced by about 20%.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a method for manufacturing a mesa-type semiconductor device. Background Technology

[0002] Tabletop terminal technology is a key technology for achieving high voltage in power semiconductor devices. It is an important manifestation of modern computer industrial design and technology integration. By sacrificing some performance and scalability, it achieves a huge improvement in space efficiency, aesthetics, and deployment convenience.

[0003] The shortcomings of existing technology:

[0004] Currently, in subsequent processes such as glass passivation, the coating tool is prone to collision with sharp grooves, resulting in edge chipping defects. These defects can damage the PN junction, leading to a decrease in breakdown voltage and an increase in leakage current, which is the main reason for low yield. Sharp corners are electric field concentration points, causing devices to break down prematurely and limiting their voltage withstand potential. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a mesa-type semiconductor device to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for manufacturing a mesa-type semiconductor device, the method comprising:

[0007] S1, double-sided etching and mesa etching;

[0008] S2. Perform thermal oxidation smoothing treatment to ensure that the smoothed groove angle is ≥100°;

[0009] S3. Select the oxide layer to be removed;

[0010] S4. Proceed with subsequent standard processes.

[0011] Preferably, step S1 includes:

[0012] a1. Provide a semiconductor substrate with a sharp notch mesa structure;

[0013] a2. Protect the die with photoresist;

[0014] a3. Selective etching with silicon etching solution to form a regular inclined platform with sharp grooves.

[0015] Preferably, step S2 specifically includes:

[0016] b1. Perform dry oxygen treatment for 0.5 hours at a temperature of 1140±5℃ to form an initial oxide layer of 100-150nm.

[0017] b2. Perform wet oxygen treatment for 3~4 hours, with the temperature set at 1140±5℃, wet oxygen temperature at 95±2℃, gas flow rate in L / min, heating rate at 5±0.5℃ / min, and cooling rate at 2±0.3℃ / min, to form an oxide layer of 1.0-1.2μm.

[0018] b3. Perform dry oxygen treatment for 0.5 hours at a temperature of 1140±5℃ to form an oxide layer of 1.1μm-1.4μm.

[0019] Preferably, step S3 specifically includes:

[0020] c1. Pre-baking photoresist coating, temperature set to 100±10℃, time set to 30~40min;

[0021] c2. Use an optimized photomask for exposure, development and hardening; set the development time to 15±5 min, the hardening temperature to 135±5℃, and the time to 45±5 min.

[0022] c3. Use a silicon dioxide etching solution to select the silicon dioxide in the tank that needs to be etched away. After the oxide layer in the protected area is protected by photoresist, remove the photoresist and clean it.

[0023] Preferably, step S4 includes:

[0024] d1. Use RCT175 slotting plate to cut grooves on both sides;

[0025] d2. Terrain corrosion, with trench depth set to 135±5um;

[0026] d3, SIPOS deposition, time set to 160±20 min;

[0027] d4. Use IP760C(REG) + IP760C(RWG) glass powder for glass passivation;

[0028] d5, redeposition, with a thickness of 4000±1000 Å;

[0029] d6. Use RCT175 for front lead wire engraving on the front side and RCT175 for back lead wire engraving on the back side.

[0030] d7. Perform double-sided silver steaming;

[0031] d8. The front side uses RCT175 - front lead reverse engraving, and the back side uses RCT175 - back lead reverse engraving;

[0032] d9. Vacuum alloy, temperature set to 525℃, time set to 25min.

[0033] Preferably, in step a3, the silicon etching solution includes nitric acid, glacial acetic acid, and hydrofluoric acid, with a ratio of 5:4:4. The nitric acid includes two parts fuming nitric acid and one part ordinary nitric acid, and the initial temperature of the silicon etching solution is set to 5°C.

[0034] Preferably, in step S2, the oxidation rate is inversely proportional to the interface radius of curvature, and the diffusion field strength of the oxidant is enhanced. The propulsion speed of the / Si interface is inversely proportional to the radius of curvature, following the formula:

[0035] dx / dt = k / r

[0036] Where k is a temperature-dependent rate constant, and dx represents the oxide layer thickness or The minute displacement change at the Si interface, dt represents the minute change in time, and is the time differential term of the oxidation process. dt and dx together constitute the oxidation rate, used to describe the amount of oxide layer growth per unit time, where r represents... / Si interface radius of curvature.

[0037] Preferably, in step c3, the silica etching solution is prepared in a ratio of NH4F:HF = 5:1, and the etching temperature is set to 35±3℃.

[0038] Compared with the prior art, the beneficial effects of the present invention are:

[0039] 1. This method for manufacturing a mesa-type semiconductor device utilizes the characteristic that thermal oxidation occurs faster at sharp corners to actively smooth the sharp corners of the slot into rounded corners, thereby fundamentally eliminating mechanical edge chipping defects in subsequent processes. Simultaneously, the resulting impurity segregation effect optimizes the surface doping concentration, improving the breakdown voltage while also optimizing the device's triggering characteristics, reducing the thyristor trigger current IGT by approximately 20%.

[0040] 2. The manufacturing method of this mesa-type semiconductor device, by selectively removing the oxide layer, perfectly preserves the original insulation structure of the critical area, ensuring the normal function of the device.

[0041] 3. The manufacturing method of this mesa-type semiconductor device starts with the geometry and is applicable to all mesa-type process devices with similar problems. Attached Figure Description

[0042] Figure 1 This is a top view of the tabletop after etching according to the present invention;

[0043] Figure 2 This is a front side view scanning electron microscope image of the chip of the present invention after mesa etching;

[0044] Figure 3This is a scanning electron microscope image of the chip mesa slot after a single oxidation treatment according to the present invention;

[0045] Figure 4 This is a diagram showing the selective removal of the black oxide layer in the chip after a single oxidation process according to the present invention.

[0046] Figure 5 This is a process curve diagram of the primary oxidation process of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0049] In the description of this patent, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection or setting, a detachable connection or setting, or an integrated connection or setting. Those skilled in the art can understand the specific meaning of the above terms in this patent according to the specific circumstances.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a number" means two or more, unless otherwise explicitly specified.

[0051] Example

[0052] Please see Figure 1-5 As shown, the present invention provides a manufacturing method for a mesa-type semiconductor device: a manufacturing method for a mesa-type semiconductor device, the method comprising:

[0053] S1, double-sided etching and mesa etching;

[0054] a1. Provide a semiconductor substrate with a sharp notch mesa structure;

[0055] a2. Protect the die with photoresist;

[0056] a3. Selective etching with silicon etching solution to form a regular inclined platform with sharp grooves;

[0057] S2. Perform thermal oxidation smoothing treatment to ensure that the smoothed groove angle is ≥100°. During thermal oxidation, significant stress concentration occurs at the sharp corners of the silicon surface. According to the Gibbs-Thomson effect, atoms on high-curvature surfaces have higher chemical potentials. At the sharp corners of the mesa groove, the silicon atomic lattice is in a high-energy state, and the activation energy for the reaction with oxygen atoms is significantly reduced, making the oxidation reaction thermodynamically easier. The oxidation rate is inversely proportional to the interface curvature radius, and the diffusion field strength of the oxidant is enhanced. The propulsion speed of the / Si interface is inversely proportional to the radius of curvature, following the formula:

[0058] dx / dt = k / r

[0059] Here, dx represents the oxide layer thickness or the minute displacement change of the SiO2 / Si interface (usually in nanometers or micrometers). During thermal oxidation, dx corresponds to the differential thickness change as the interface advances during oxide layer growth, reflecting the local progress of the oxidation reaction.

[0060] dt represents a small change in time (usually measured in seconds or minutes) and is the time derivative of the oxidation process. dt and dx together constitute the oxidation rate, used to describe the amount of oxide layer growth per unit time.

[0061] r: Represents the radius of curvature of the SiO2 / Si interface (usually in micrometers), used to quantify the degree of curvature of the sharp corners of the slot. The smaller the r value, the sharper the corner (greater curvature), the stronger the oxidant diffusion field, and the faster the oxidation rate. The document emphasizes that through thermal oxidation treatment, the sharp corners (smaller r) are smoothed, optimizing the slot angle from a sharp state to ≥100°, thereby reducing the risk of electric field concentration and mechanical edge chipping.

[0062] k: is a temperature-dependent rate constant, the value of which is determined by the oxidation temperature (such as 1140±5℃ set in the document), and affects the overall rate of the oxidation reaction.

[0063] This formula, based on the Gibbs-Thomson effect and oxidation kinetics theory, reveals the mechanism by which interfacial curvature regulates the oxidation rate during thermal oxidation:

[0064] The oxidation rate is inversely proportional to the curvature: at the sharp corners of the tabletop groove (where r is small), silicon atoms are in a high-energy state, the activation energy of the oxidation reaction is reduced, leading to an enhanced diffusion field of the oxidant (such as oxygen or water vapor), which significantly increases dx / dt. This is the core principle of the thermal oxidation smoothing process in step S2—utilizing the characteristic that sharp corners oxidize faster to actively smooth the corners into a rounded shape;

[0065] b1. Perform dry oxygen treatment for 0.5 hours at a temperature of 1140±5℃ to form an initial oxide layer of 100-150nm, providing a good interface foundation for subsequent wet oxygen oxidation. 1140℃ is the optimal trade-off between the oxidation rate and the generation of lattice defects. At this temperature, the oxidant... The diffusion coefficient and the interfacial reaction rate are optimally matched, which can ensure the quality of the oxide layer while obtaining an appropriate oxidation rate.

[0066] b2. Perform 3-4 hours of wet oxygen treatment, utilizing water vapor in... To achieve a higher diffusion coefficient and rapid oxide layer growth, the temperature was set at 1140±5℃, the wet oxygen temperature at 95±2℃, the gas flow rate was L / min, the heating rate was 5±0.5℃ / min, and the cooling rate was 2±0.3℃ / min, forming an oxide layer of 1.0-1.2μm.

[0067] b3. Perform dry oxygen treatment for 0.5 h to improve the surface quality of the oxide layer, reduce dangling bonds, and improve interfacial properties. The temperature is set to 1140±5℃ to form an oxide layer of 1.1μm-1.4μm.

[0068] S3. Select the oxide layer to be removed;

[0069] c1. Pre-baking photoresist coating, temperature set to 100±10℃, time set to 30~40min;

[0070] c2. Use an optimized photomask for exposure, development and hardening; set the development time to 15±5 min, the hardening temperature to 135±5℃, and the time to 45±5 min.

[0071] c3. Select the silicon dioxide in the tank that needs to be etched using silicon dioxide etching solution. After the oxide layer in the protected area is protected by photoresist, remove the photoresist and clean it. In step c3, the silicon dioxide etching solution ratio is NH4F:HF=5:1, and the etching temperature is set to 35±3℃.

[0072] S4. Proceed with subsequent standard processes;

[0073] d1. Use RCT175 slotting plate to cut grooves on both sides;

[0074] d2. Terrain corrosion, with trench depth set to 135±5um;

[0075] d3, SIPOS deposition, time set to 160±20 min;

[0076] d4. Use IP760C(REG) + IP760C(RWG) glass powder for glass passivation;

[0077] d5, redeposition, with a thickness of 4000±1000 Å;

[0078] d6. Use RCT175 for front lead wire engraving on the front side and RCT175 for back lead wire engraving on the back side.

[0079] d7. Perform double-sided silver steaming;

[0080] d8. The front side uses RCT175 - front lead reverse engraving, and the back side uses RCT175 - back lead reverse engraving;

[0081] d9. Vacuum alloy, temperature set to 525℃, time set to 25min.

[0082] The improved slot morphology of the chip processed by this method is confirmed by scanning electron microscopy, with an actual angle of approximately 114.3°. Electrical performance tests show that the voltage parameters are normal, the mesa defect problem is completely solved, and the IGT value is significantly reduced by about 20% compared with products processed by traditional methods.

[0083] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a mesa-type semiconductor device, characterized in that: The method includes: S1, double-sided etching and mesa etching; S2. Perform thermal oxidation smoothing treatment to ensure that the smoothed groove angle is ≥100°; S3. Select the oxide layer to be removed; S4. Proceed with subsequent standard processes; Step S1 includes: a1. Provide a semiconductor substrate with a sharp notch mesa structure; a2. Protect the die with photoresist; a3. Selective etching with silicon etching solution to form a regular inclined platform with sharp grooves; Step S2 specifically includes: b1. Perform dry oxygen treatment for 0.5 hours at a temperature of 1140±5℃ to form an initial oxide layer of 100-150nm. b2. Perform wet oxygen treatment for 3~4 hours, with the temperature set at 1140±5℃, wet oxygen temperature at 95±2℃, gas flow rate in L / min, heating rate at 5±0.5℃ / min, and cooling rate at 2±0.3℃ / min, to form an oxide layer of 1.0-1.2μm. b3. Perform dry oxygen treatment for 0.5 hours at a temperature of 1140±5℃ to form an oxide layer of 1.1μm-1.4μm. In step S2, the oxidation rate is inversely proportional to the interface radius of curvature, and the diffusion field strength of the oxidant is enhanced. The interface's advancement speed is inversely proportional to its radius of curvature, following the formula: dx / dt = k / r Where k is a temperature-dependent rate constant, and dx represents the oxide layer thickness or The minute displacement change at the interface, dt represents the minute change in time, and is the time differential term of the oxidation process. dt and dx together constitute the oxidation rate, used to describe the amount of oxide layer growth per unit time, where r represents... The radius of curvature of the interface.

2. The method for manufacturing a mesa-type semiconductor device according to claim 1, characterized in that: Step S3 specifically includes: c1. Pre-baking photoresist coating, temperature set to 100±10℃, time set to 30~40min; c2. Use an optimized photomask for exposure, development and hardening; set the development time to 15±5 min, the hardening temperature to 135±5℃, and the time to 45±5 min. c3. Use a silicon dioxide etching solution to select the silicon dioxide in the tank that needs to be etched away. After the oxide layer in the protected area is protected by photoresist, remove the photoresist and clean it.

3. The method for manufacturing a mesa-type semiconductor device according to claim 1, characterized in that: Step S4 includes: d1. Use RCT175 slotting plate to cut grooves on both sides; d2. Terrain corrosion, with trench depth set to 135±5um; d3, SIPOS deposition, time set to 160±20 min; d4. Use IP760C(REG) + IP760C(RWG) glass powder for glass passivation; d5, redeposition, with a thickness of 4000±1000 Å; d6. Use RCT175 for front lead wire engraving on the front side and RCT175 for back lead wire engraving on the back side. d7. Perform double-sided silver steaming; d8. The front side uses RCT175 - front lead reverse engraving, and the back side uses RCT175 - back lead reverse engraving; d9. Vacuum alloy, temperature set to 525℃, time set to 25min.

4. The method for manufacturing a mesa-type semiconductor device according to claim 1, characterized in that: In step a3, the silicon etching solution includes nitric acid, glacial acetic acid, and hydrofluoric acid, with a ratio of 5:4:

4. The nitric acid consists of two parts fuming nitric acid and one part ordinary nitric acid, and the initial temperature of the silicon etching solution is set to 5°C.

5. The method for manufacturing a mesa-type semiconductor device according to claim 2, characterized in that: In step c3, the silica etching solution is prepared with a ratio of NH4F:HF = 5:1, and the etching temperature is set to 35±3℃.

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