Wafer self-alignment structure and method based on liquid surface tension
By combining mechanical pre-alignment and liquid precision alignment, and utilizing the protrusion and groove structures of low-melting-point materials, nanometer-level precision alignment and thermal stress compensation of wafers are achieved. This solves the precision and thermal stress problems in existing technologies and has high reliability and process compatibility.
Patent Information
- Application Number
- CN202511730878.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-02-24
AI Technical Summary
Existing wafer self-alignment technologies struggle to achieve nanometer-level precision alignment and cannot compensate for alignment misalignment caused by thermal stress during bonding, resulting in mechanical precision limitations and potential contamination risks.
By combining a protruding structure and a groove structure made of low-melting-point material, and through a combination of mechanical pre-alignment and liquid precision alignment, submicron to nanometer-level precision alignment is achieved by utilizing the surface tension of the liquid, and the offset caused by thermal stress is dynamically compensated.
It achieves high-precision and high-reliability wafer bonding, balancing a large capture range with a high alignment success rate, avoiding additional process complexity and potential contamination, and meeting the compatibility requirements of semiconductor manufacturing.
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Figure CN121568596A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor and microelectromechanical system packaging technology, and in particular to a wafer self-alignment structure and method based on liquid surface tension. Background Technology
[0002] In the fields of semiconductor manufacturing and microelectromechanical systems (MEMS) packaging, wafer bonding is a key technology for achieving three-dimensional integration, device packaging, and functional integration. Alignment accuracy during the bonding process is one of the core factors determining the final device performance, interconnect yield, and reliability. With the continued advancement of Moore's Law and the rise of advanced packaging (such as 2.5D / 3D ICs and chip-to-chip integration), the requirements for bonding alignment accuracy have increased from the micrometer level to the submicrometer and even nanometer level.
[0003] Currently, the mainstream wafer alignment methods in the industry mainly rely on high-precision optical alignment systems (such as infrared or visible light imaging) combined with mechanical adjustment mechanisms. Although such methods are widely used, their inherent limitations are also quite obvious: the high-precision optical alignment process is complex and time-consuming; the alignment accuracy is limited to the micrometer level.
[0004] To overcome the aforementioned problems, self-alignment technology has been widely studied as a supplementary or alternative solution. Its core idea is to utilize the inherent properties of materials or special structural designs, leveraging inter-material physical forces (such as capillary force, electrostatic force, and magnetic force) to spontaneously achieve or correct the alignment state during the bonding process, thereby reducing reliance on external high-precision equipment. Existing self-alignment technologies include: Patent CN118231312A (A wafer physical self-alignment process method and wafer bonding structure) proposes to achieve wafer self-alignment through the cooperation of beveled bumps and grooves. This method eliminates the dependence on ultra-high precision (and expensive) optical alignment systems, and can achieve high-precision alignment with only ordinary pick-and-place equipment, which has a significant cost advantage.
[0005] However, this method does not introduce precise alignment techniques based on the self-compensation of the bevel, and therefore cannot further reduce alignment deviations. Its final accuracy is limited by the machining accuracy and surface roughness of the bumps and grooves. Any shape deviation or edge burrs will directly affect the final alignment position, requiring extremely high manufacturing processes, and theoretically, it is difficult to achieve nanometer-level precision. In addition, friction may exist when the bumps and the beveled grooves slide in contact. For microstructures, static friction and adhesion may hinder smooth sliding, leading to incomplete alignment or random errors. This method is a "one-time" static alignment process. Once completed, it cannot compensate for thermal stress displacement caused by the difference in thermal expansion coefficients between the upper and lower wafers during subsequent bonding processes.
[0006] Patent CN116544318A (Magnetic-Assisted Self-Alignment Method for Micro-LED Chip Bonding Process) proposes to deposit Fe3O4 magnetic nanoparticles on the electrodes of a Micro-LED chip and prepare a high-density bonding bump array with Fe3O4 magnetic nanoparticles on a substrate. Under the action of a magnetic field, the high-density bonding bumps generate magnetism, and high-precision self-alignment between the Micro-LED electrodes and the bonding bumps is achieved through the mutual attraction of magnetic forces.
[0007] However, this method requires an additional Fe3O4 magnetic nanoparticle deposition step in the standard semiconductor process flow and necessitates the integration of an electromagnetic field generator, increasing the complexity and cost of the process. Furthermore, the addition of magnetic materials may cause contamination or introduce unnecessary electromagnetic interference. For scenarios requiring integral bonding of two wafers, achieving and controlling a uniform magnetic force distribution is even more challenging.
[0008] In summary, among existing self-alignment technologies, inclined plane self-alignment is limited by mechanical precision and thermal stress, while magnetic self-alignment introduces potential contamination and complex processes, and faces the risk of demagnetization. Therefore, how to achieve high-precision and high-reliability wafer-level bonding has become a pressing problem for those skilled in the art. Summary of the Invention
[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer self-alignment structure and method based on liquid surface tension. While retaining the traditional mechanical positioning structure for initial alignment, it solves the problem of achieving nanometer-level alignment accuracy due to limitations in mechanical processing precision and friction by introducing the phase transition properties of low-melting-point materials. Simultaneously, it addresses the alignment misalignment problem caused by thermal mismatch stress during bonding heating, enabling dynamic real-time correction. Furthermore, it uses conventional low-melting-point metals or alloys used in semiconductor manufacturing, avoiding the introduction of non-standard functional materials and ensuring compatibility with existing semiconductor processes. The invention has a clear structure and feasible process, facilitating high-precision and high-reliability wafer-level bonding.
[0010] To achieve the above and other related objectives, the present invention provides the following technical solutions: A first aspect of the present invention provides a wafer self-alignment method based on liquid surface tension, comprising the following steps: S1. Provide an upper wafer and form a protrusion structure on the bonding surface of the upper wafer; S2. Provide a lower wafer, and form a groove structure on the bonding surface of the lower wafer, wherein the groove structure corresponds to and matches the position of the protrusion structure; S3. A thin film layer for enhancing wetting is formed on the bottom and sidewall surfaces of the groove structure; S4. Perform mechanical pre-alignment between the upper and lower wafers, that is, initially embed the protrusion structure of the upper wafer into the opening of the groove structure of the lower wafer to achieve coarse alignment; S5. Heating and liquid alignment of the upper and lower wafers: The stacked wafers are heated and the temperature exceeds the melting point of the protrusion structure material. The protrusion structure melts and forms a molten liquid, which flows to the bottom of the groove under the action of surface tension. Submicron-level precision alignment is achieved through the self-positioning effect of the liquid material. S6. After the fine alignment is completed, bonding is performed, and then the molten material is cooled to resolidify and form a permanent bond.
[0011] In step S1, the material of the upper wafer is selected from semiconductor wafers made of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, or indium phosphide, or insulating wafers made of sapphire, quartz, or glass. The diameter of the upper wafer can be any size in the range of 2 inches to 12 inches.
[0012] In step S1, the protruding structure is made of a low-melting-point material; the low-melting-point material is selected from any one of low-melting-point metallic materials, low-melting-point glass materials, and thermoplastic polymer materials.
[0013] The low-melting-point metallic materials include, but are not limited to, tin, indium, bismuth and their alloys, preferably SnAgCu, InAg, and BiSn series alloys, and the melting point range of the low-melting-point metallic materials is between 100°C and 400°C. Low-melting-point glass materials include bismuthate glass, phosphate glass, or vanadate glass systems, and the glass transition temperature of low-melting-point glass materials is between 250°C and 500°C. Thermoplastic polymer materials include polyimide, polyamide, benzocyclobutene, or special engineering plastics, and the melting temperature of thermoplastic polymer materials is between 150°C and 350°C.
[0014] In step S1, the shape of the protruding structure is hemispherical, cylindrical, frustum conical, or truncated pyramidal.
[0015] Furthermore, the height of the protrusion structure is 2-20 μm, and its bottom feature dimension is 1-15 μm.
[0016] In step S1, the protrusion structure is formed on the bonding surface of the upper wafer by electroplating, sputtering, screen printing or embossing processes.
[0017] In step S2, the material of the lower wafer may be the same as or different from that of the upper wafer.
[0018] In step S2, the opening size of the groove structure is larger than the size of the protrusion structure to accommodate initial placement deviations. Specifically, the opening size of the groove structure is 10%-50% larger than the bottom size of the protrusion structure.
[0019] Furthermore, the depth of the groove structure is less than or equal to the height of the protrusion structure. The groove structure is an integrated inverted triangular structure, specifically a V-shaped groove or a conical groove.
[0020] In step S2, the groove structure is formed on the bonding surface of the lower wafer by anisotropic wet etching, dry etching, or laser ablation, and corresponds to the position of the protrusion structure. For silicon wafers, anisotropic wet etching is preferably performed using KOH or TMAH solution to form a V-shaped groove or an inverted pyramidal conical groove with a sidewall angle of 54.7°.
[0021] In step S3, the thin film layer is a homogeneous material layer of the same material as the protruding structure but thinner, with a thickness of 10-200 nm; or A dielectric layer made of silicon dioxide, silicon nitride, or silicon oxynitride, with a thickness of 50-500 nm; or A metallic layer of titanium, chromium, copper or their alloys, with a thickness of 5-100 nm.
[0022] In step S3, the thin film layer is formed on the bottom and sidewall surfaces of the groove structure by processes such as thermal oxidation, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0023] In step S4, the protrusion structure of the upper wafer is initially embedded into the groove structure of the lower wafer by a mechanical positioning device to achieve coarse alignment.
[0024] In step S5, the material is heated to the bonding temperature at a rate of 5-20°C / min in a protective atmosphere or vacuum environment; the bonding temperature is set to a temperature exceeding the melting point of the low-melting-point material, and the bonding temperature range is 150-450°C.
[0025] In step S5, after reaching the bonding temperature, the temperature is maintained for 5-60 minutes to melt the protruding structure, which then flows to the bottom of the groove under the action of surface tension.
[0026] In step S6, a bonding pressure of 1-20 kN is applied for bonding and the bonding is carried out for 5-60 minutes.
[0027] In step S6, after bonding is completed, the temperature is controlled by a program and cooled to below 50°C at a rate of 1-5°C / min, so that the molten material can be re-solidified to form a permanent bond.
[0028] A second aspect of the present invention provides a wafer self-alignment structure based on liquid surface tension, comprising an upper wafer and a lower wafer bonded together. At least one protrusion structure is provided on the bonding surface of the upper wafer; the protrusion structure is made of a low melting point material; At least one groove structure is disposed on the bonding surface of the lower wafer, and the groove structure corresponds to and engages with the protrusion structure; the bottom and sidewalls of the groove structure are provided with a thin film layer for enhancing wetting.
[0029] The upper and lower wafer self-alignment structure of this invention, through the combination of protrusion and groove structures, constitutes a composite structure of mechanical pre-alignment and liquid precision alignment. The alignment process is divided into the following two stages: The first stage is mechanical pre-alignment: through the embedded cooperation of solid protrusion structures and groove structures, the initial positioning of the initial deviation between wafers within the micrometer range is achieved at room temperature; The second stage is surface tension precision alignment: During the bonding heating process, when the temperature rises above the melting point of the low melting point material, the protrusion structure melts to form a molten liquid; under the action of the liquid surface tension, the molten liquid spontaneously moves towards the bottom of the groove structure, causing the upper wafer to produce micro-displacement, and finally achieving submicron to nanometer-level precision alignment.
[0030] Furthermore, during the heating and holding stages of the bonding process, the molten liquid remains in a liquid state, and can compensate for any relative displacement caused by the difference in thermal expansion coefficients of the upper and lower wafers in real time through dynamic adjustment of surface tension, thereby achieving dynamic real-time alignment correction.
[0031] Furthermore, the low-melting-point material is selected from any one of low-melting-point metallic materials, low-melting-point glass materials, and thermoplastic polymer materials.
[0032] The low-melting-point metallic materials include, but are not limited to, tin, indium, bismuth and their alloys, preferably SnAgCu, InAg, and BiSn series alloys, and the melting point range of the low-melting-point metallic materials is between 100°C and 400°C. Low-melting-point glass materials include bismuthate glass, phosphate glass, or vanadate glass systems, and the glass transition temperature of low-melting-point glass materials is between 250°C and 500°C. Thermoplastic polymer materials include polyimide, polyamide, benzocyclobutene, or special engineering plastics, and the melting temperature of thermoplastic polymer materials is between 150°C and 350°C.
[0033] Furthermore, the shape of the protruding structure is hemispherical, cylindrical, frustum conical, or truncated pyramidal.
[0034] Furthermore, the height of the protrusion structure is 2-20 μm, and its bottom feature dimension is 1-15 μm.
[0035] Furthermore, the protrusion structure is formed on the bonding surface of the upper wafer by electroplating, sputtering, screen printing or embossing processes.
[0036] Furthermore, the opening size of the groove structure is larger than the size of the protrusion structure to accommodate initial placement deviations. Specifically, the opening size of the groove structure is 10%-50% larger than the bottom size of the protrusion structure.
[0037] Furthermore, the depth of the groove structure is less than or equal to the height of the protrusion structure.
[0038] Furthermore, the groove structure is an integrated inverted triangular structure, specifically a V-shaped groove or a conical groove.
[0039] Furthermore, the groove structure is formed on the bonding surface of the lower wafer by anisotropic wet etching, dry etching, or laser ablation processes, and corresponds to the position of the protrusion structure. For silicon wafers, anisotropic wet etching is preferably performed using KOH or TMAH solution to form a V-shaped groove or an inverted pyramidal conical groove with a sidewall angle of 54.7°.
[0040] Furthermore, the thin film layer is a homogeneous material layer of the same type as the protruding structure material but thinner, with a thickness of 10-200 nm; or A dielectric layer made of silicon dioxide, silicon nitride, or silicon oxynitride, with a thickness of 50-500 nm; or A metallic layer of titanium, chromium, copper or their alloys, with a thickness of 5-100 nm.
[0041] Furthermore, the thin film layer is formed on the bottom and sidewall surfaces of the groove structure through processes such as thermal oxidation, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0042] As described above, the wafer self-alignment structure and method based on liquid surface tension of the present invention have the following beneficial effects: 1. It balances a large capture range with a high alignment success rate: Mechanical pre-alignment is first achieved through the embedded cooperation of solid protrusions and grooves, which limits the initial deviation to the effective capture range of liquid self-alignment. This overcomes the problem that traditional surface tension self-alignment technology is prone to failure due to excessive initial deviation, and improves the robustness and yield of the process.
[0043] 2. Achieved ultra-high precision alignment: Utilizing a self-alignment mechanism driven by the surface tension of molten liquid, the final alignment accuracy is determined by the physical properties of the liquid, breaking through the limitations of mechanical structure processing accuracy and achieving sub-micron to nanometer level alignment accuracy, which is significantly better than traditional mechanical alignment methods.
[0044] 3. It has dynamic thermal error compensation capability: Since the self-alignment process occurs and continues during the bonding heating stage, the molten material can adjust its position in real time through surface tension, automatically compensating for thermal mismatch displacement caused by the difference in thermal expansion coefficients between the upper and lower wafers.
[0045] 4. Maintains excellent process compatibility and reliability: The low-melting-point materials used (such as indium and tin) are all standard bonding materials that have been verified in semiconductor manufacturing. There is no need to introduce non-standard substances such as magnetic nanoparticles, avoiding potential pollution risks and ensuring good compatibility with existing front-end and back-end semiconductor manufacturing processes. The technology transfer threshold is low.
[0046] 5. Improved practicality and economy of the technical solution: While achieving high performance, the solution has an intuitive structural design and does not require expensive external magnetic field generating devices or high-precision mechanical alignment equipment, which helps to control manufacturing costs and meet the needs of large-scale production. Attached Figure Description
[0047] Figure 1 The diagram shows the upper and lower wafer structures disclosed in Embodiment 1 of the present invention.
[0048] Figure 2 The diagram shows the structure of the upper and lower wafers in step S4 of the mechanical coarse alignment process in Embodiment 1 of the present invention.
[0049] Figure 3 The diagram shows the structure of the upper and lower wafers in step S5, during the surface tension fine alignment process, in Embodiment 1 of the present invention.
[0050] Figure 4 The diagram shows the structure of the upper and lower wafers after bonding in step S6 in Embodiment 1 of the present invention.
[0051] Figure 5 The diagram shows the upper and lower wafer structures disclosed in Embodiment 2 of the present invention.
[0052] Figure 6 The diagram shows the upper and lower wafer structures disclosed in Embodiment 3 of the present invention.
[0053] Component designation explanation: 1. Upper wafer; 11. Raised structure; 2. Lower wafer; 21. Groove structure; 22. Thin film layer; 31. Molten liquid; 32. Solidified material. Detailed Implementation
[0054] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
[0055] Example 1 This embodiment proposes a wafer self-alignment structure and method based on liquid surface tension. The alignment structure is as follows: Figure 1 As shown, it includes an upper wafer 1 and a lower wafer 2 bonded together; two or more protrusion structures 11 protrude from the bonding surface of the upper wafer 1; the protrusion structures 11 are made of a low melting point material; two or more groove structures 21 are disposed on the bonding surface of the lower wafer 2, and the groove structures 21 correspond to the protrusion structures 11 one by one; the bottom and sidewalls of the groove structures 21 are provided with thin film layers 22 for enhancing wetting.
[0056] Figures 2-4 A cross-sectional structural diagram corresponding to each step in the alignment method is shown. To enable those skilled in the art to better understand the alignment method of the present invention, the following section combines... Figures 1-4 This invention provides a detailed description of a wafer self-alignment method based on liquid surface tension, the alignment method comprising the following steps: S1. Provide an upper wafer, and form a protrusion structure 11 on the bonding surface of the upper wafer 1: The material of the upper wafer 1 is selected from semiconductor wafers of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium phosphide, or insulating wafers of sapphire, quartz, and glass; the diameter of the upper wafer can be any size in the range of 2 inches to 12 inches.
[0057] The protruding structure 11 is made of a low-melting-point material; the low-melting-point material is selected from any one of low-melting-point metallic materials, low-melting-point glass materials, and thermoplastic polymer materials. The low-melting-point metallic materials include, but are not limited to, tin, indium, bismuth and their alloys, preferably SnAgCu, InAg, and BiSn series alloys, with a melting point range of 100°C to 400°C; the low-melting-point glass materials include bismuthate glass, phosphate glass, or vanadate glass systems, with a glass transition temperature between 250°C and 500°C; the thermoplastic polymer materials include polyimide, polyamide, benzocyclobutene, or special engineering plastics, with a melting temperature between 150°C and 350°C.
[0058] The protrusion structure 11 is formed on the bonding surface of the upper wafer by electroplating, sputtering, screen printing or embossing processes.
[0059] The protrusion structure 11 is hemispherical in shape, with a height of 2-20 μm and a bottom feature dimension of 1-15 μm. Figure 1 As shown.
[0060] S2. Provide a lower wafer 2, and form a groove structure 21 on the bonding surface of the lower wafer 2, wherein the groove structure 21 corresponds to and engages with the protrusion structure 11. The material of the lower wafer 2 may be the same as or different from that of the upper wafer 1.
[0061] The groove structure 21 is an integrated inverted triangular structure, specifically a V-shaped groove, such as... Figure 1 As shown.
[0062] The opening size of the groove structure 21 is 10%-50% larger than the bottom size of the protrusion structure 11. The depth of the groove structure 21 is less than or equal to the height of the protrusion structure 11.
[0063] The groove structure 21 is formed on the bonding surface of the lower wafer by anisotropic wet etching, dry etching, or laser ablation processes, and corresponds to the position of the protrusion structure 11. For silicon wafers, anisotropic wet etching with KOH or TMAH solution is preferred to form a V-shaped groove with a sidewall angle of 54.7°.
[0064] S3. A thin film layer 22 for enhancing wetting is formed on the bottom and sidewall surfaces of the groove structure 21: The thin film layer 22 is a homogeneous material layer of the same material as the protrusion structure 11 but with a thinner thickness, having a thickness of 10-200 nm; or A dielectric layer made of silicon dioxide, silicon nitride, or silicon oxynitride, with a thickness of 50-500 nm; or A metallic layer of titanium, chromium, copper or their alloys, with a thickness of 5-100 nm.
[0065] The thin film layer 22 is formed on the bottom and sidewall surfaces of the groove structure through processes such as thermal oxidation, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0066] S4. Perform mechanical pre-alignment between upper wafer 1 and lower wafer 2: The upper wafer 1 and the lower wafer 2 are initially aligned. A mechanical positioning device is used to initially embed the protrusion structure 11 of the upper wafer 1 into the groove opening 21 of the lower wafer 2, achieving coarse alignment. Figure 2 As shown.
[0067] S5. Perform heating and liquid alignment on upper wafer 1 and lower wafer 2: In a protective atmosphere or vacuum environment, the stacked wafers are heated to the bonding temperature at a rate of 5-20°C / min; the bonding temperature is set to a temperature exceeding the melting point of the indicated protrusion structure material, in the range of 150-450°C.
[0068] After reaching the bonding temperature, hold for 5-60 minutes to melt the raised structure 11 into molten liquid 31. The molten liquid 31 flows towards the bottom of the groove structure 21 under surface tension. Figure 3 As shown, this allows for submicron-level precision alignment through the self-positioning effect of liquid materials.
[0069] S6. After fine alignment, perform bonding and cooling: After the alignment is completed, a bonding pressure of 1-20 kN is applied for bonding for 5-60 minutes.
[0070] Then, a programmed cooling method is used to cool the molten liquid 31 to below 50°C at a rate of 1-5°C / min; this allows the molten liquid 31 to re-solidify into a solidified material 32, forming a permanent bond, such as... Figure 4 As shown.
[0071] Example 2 This embodiment proposes a wafer self-alignment structure and method based on liquid surface tension. Compared with Embodiment 1, the only difference is: The protruding structure 11 shown is cylindrical in shape, and the groove structure 21 shown is an integrated inverted triangular structure, specifically a V-shaped groove, as shown. Figure 5 As shown.
[0072] Example 3 This embodiment proposes a wafer self-alignment structure and method based on liquid surface tension. Compared with Embodiment 1, the only difference is: The protruding structure 11 shown is shaped like a frustum or a truncated pyramid, and the groove structure 21 shown is an integrated inverted triangular structure, specifically a V-shaped groove, such as... Figure 6 As shown.
[0073] In summary, the core technology of this invention lies in employing a composite alignment mechanism of "solid-state pre-positioning - liquid-state fine correction": firstly, coarse alignment is achieved through the mechanical cooperation of the protruding structure and the groove structure; subsequently, during the bonding heating process, the low-melting-point material of the protruding structure melts and automatically flows to the anchor point at the bottom of the groove under the drive of surface tension, completing nanoscale fine alignment and dynamically compensating for offsets caused by thermal stress. This alignment method supports various material systems such as metals, glass, and polymers, and features a large capture range, ultra-high precision, and excellent process compatibility. Furthermore, this invention uses conventional low-melting-point metals or alloys used in semiconductor manufacturing, avoiding the introduction of non-standard functional materials and ensuring compatibility with existing semiconductor processes. The structure of this invention is clear, the process is feasible, and it is conducive to achieving high-precision, high-reliability wafer-level bonding. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.
[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A wafer self-alignment method based on liquid surface tension, characterized in that, Includes the following steps: S1. Provide an upper wafer, and form a protrusion structure on the bonding surface of the upper wafer, the protrusion structure being made of a low melting point material; S2. Provide a lower wafer, and form a groove structure on the bonding surface of the lower wafer, wherein the groove structure corresponds to and matches the position of the protrusion structure; S3. A thin film layer for enhancing wetting is formed on the bottom and sidewall surfaces of the groove structure; S4. Perform mechanical pre-alignment between the upper and lower wafers, that is, initially embed the protrusion structure of the upper wafer into the opening of the groove structure of the lower wafer to achieve coarse alignment; S5. Heating and liquid alignment of the upper and lower wafers: The stacked wafers are heated. When the temperature exceeds the melting point of the protrusion structure material, the protrusion structure melts to form a molten liquid. Under the action of surface tension, it flows to the bottom of the groove and achieves fine alignment through the self-positioning effect of the liquid material. S6. After the fine alignment is completed, bonding is performed, and then the molten liquid is cooled to resolidify and form a permanent bond.
2. The wafer self-alignment method according to claim 1, characterized in that, The low-melting-point material is selected from any one of low-melting-point metallic materials, low-melting-point glass materials, and thermoplastic polymer materials.
3. The wafer self-alignment method according to claim 2, characterized in that, The low-melting-point metallic materials include, but are not limited to, tin, indium, bismuth and their alloys, and the melting point range of the low-melting-point metallic materials is between 100°C and 400°C. The low-melting-point glass system material includes bismuthate glass, phosphate glass or vanadate glass system, and the glass transition temperature of the low-melting-point glass system material is between 250°C and 500°C. The thermoplastic polymer material includes polyimide, polyamide, benzocyclobutene, or special engineering plastics, and the melting temperature of the thermoplastic polymer material is between 150°C and 350°C.
4. The wafer self-alignment method according to claim 1, characterized in that, The protruding structure is hemispherical, cylindrical, frustum conical, or truncated pyramidal in shape; the height of the protruding structure is 2-20 μm, and its bottom feature dimension is 1-15 μm.
5. The wafer self-alignment method according to claim 1, characterized in that, The groove structure is an integrated inverted triangular structure, and the opening size of the groove structure is larger than the size of the protrusion structure.
6. The wafer self-alignment method according to claim 1, characterized in that, The thin film layer is a homogeneous material layer of the same type as the protruding structure material but thinner, with a thickness of 10-200 nm; or The thin film layer is a dielectric layer made of silicon dioxide, silicon nitride, or silicon oxynitride, with a thickness of 50-500 nm; or The thin film layer is a metal layer of titanium, chromium, copper or their alloy, with a thickness of 5-100 nm.
7. The wafer self-alignment method according to claim 1, characterized in that, In step S1, the protrusion structure is formed on the bonding surface of the upper wafer by electroplating, sputtering, screen printing or embossing processes; In step S2, the groove structure is formed on the bonding surface of the lower wafer by anisotropic wet etching, dry etching or laser ablation process, and corresponds to the position of the protrusion structure; In step S3, the thin film layer is formed on the bottom and sidewall surfaces of the groove structure by thermal oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes.
8. The wafer self-alignment method according to claim 1, characterized in that, In step S5, the material is heated to the bonding temperature at a rate of 5-20°C / min in a protective atmosphere or vacuum environment; the bonding temperature is set to a temperature exceeding the melting point of the low-melting-point material, and the bonding temperature range is 150-450°C.
9. The wafer self-alignment method according to claim 1, characterized in that, In step S6, a bonding pressure of 1-20 kN is applied for bonding and continues for 5-60 minutes. After bonding is completed, the temperature is controlled by a program and cooled to below 50°C at a rate of 1-5°C / min, so that the molten material is re-solidified to form a permanent bond.
10. A wafer self-alignment structure based on liquid surface tension, characterized in that, This includes the upper and lower wafers that are bonded together; At least one protrusion structure is disposed on the bonding surface of the upper wafer; the protrusion structure is made of a low melting point material; At least one groove structure is disposed on the bonding surface of the lower wafer, and the groove structure corresponds to and engages with the protrusion structure; the bottom and sidewalls of the groove structure are provided with a thin film layer for enhancing wetting.
Citation Information
Patent Citations
Wafer physical self-alignment process method and wafer bonding structure
CN118231312A