A device resource allocation method and server

Abstract

The application discloses a device resource allocation method and a server, relates to the technical field of servers, and comprises the following steps: judging an extension device hot plug event type; in response to an addition event of an extension device, judging whether the added extension device is a target device; in response to the added extension device being the target device, acquiring resource requirements of a request register of the target device; acquiring a corresponding memory base address according to the resource requirements of the request register; in response to successful sending of the memory base address, setting a lock mark bit of a control register; and in response to starting of an operating system, performing memory resource allocation on the target device according to the lock mark bit of the control register. The application can detect address conflicts and resource shortage problems in real time, support real-time adjustment of BAR13 space in a device hot plug scene, and does not need to restart the system, thereby effectively improving resource utilization and reducing space resource waste.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a device resource allocation method and a server. Background Technology

[0002] With the increasing number and complexity of high-speed expansion devices (PCIe, Peripheral Component Interconnect Express) for AI servers, such as an AI training server needing to be equipped with 8 server graphics cards, 8 storage hard drives, and 8 400G network cards, the existing BAR space allocation scheme cannot meet the current configuration.

[0003] Meanwhile, when allocating resources, the operating system of the relevant technology is unaware that the management space behind a certain BAR requires special handling, which may result in the allocation of an inappropriate address region or an address region that conflicts with other devices, leading to system instability or abnormal device function.

[0004] Furthermore, PCIe devices do not provide a unified configuration method for these non-standard BARs (i.e., resource spaces outside of BAR0-BAR5 used for special purposes). Although bridge device resources or SR-IOV resources are mentioned, using identifiers that go beyond the scope of regular BARs, their allocation and management lack a clear coordination mechanism. Developers may need to use various proprietary methods for configuration, which leads to poor system compatibility and portability. Summary of the Invention

[0005] This application provides a device resource allocation method and server. The method includes: a processor determining the type of a hot-plug event of an extended device; in response to the occurrence of an extended device addition event, determining whether the added extended device is a target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register; in response to the added extended device being a target device, obtaining the resource requirements of the target device's request register; the processor obtaining the corresponding memory base address according to the resource requirements of the request register; sending the memory base address to the target device's base address register; in response to the successful sending of the memory base address, setting the lock flag bit of the control register; sending the resource allocation information of the first register group to the operating system through a configuration and power interface table; and in response to the operating system startup, allocating memory resources to the target device according to the lock flag bit of the control register. This application provides real-time detection of address conflicts and resource shortages, supports real-time adjustment of the BAR13 space in device hot-plug scenarios, without requiring a system restart, effectively improving resource utilization and reducing space resource waste.

[0006] This application provides a device resource allocation method applied to a server processor. The server also includes several expansion devices, and the processor is connected to each expansion device. Each expansion device includes several registers. The method includes:

[0007] The processor determines the type of hot-plug event for the expansion device.

[0008] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device that includes a first register group, the first register group including a request register, a base address register, and a control register;

[0009] In response to the addition of an extended device as the target device, the resource requirements of the target device's request register are obtained;

[0010] The processor obtains the corresponding memory base address based on the resource requirements of the request register;

[0011] Send the memory base address to the base address register of the target device;

[0012] In response to a successful transmission of the memory base address, the lock flag bit of the control register is set;

[0013] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0014] In response to the operating system startup, memory resources are allocated to the target device based on the lock flag bit in the control register.

[0015] This application also provides a server, which includes a processor and several expansion devices. The processor is connected to the expansion devices, and each expansion device includes several registers. The processor is used for:

[0016] Determine the type of hot-plug event for the expansion device;

[0017] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device that includes a first register group, the first register group including a request register, a base address register, and a control register;

[0018] In response to the addition of an extended device as the target device, the resource requirements of the target device's request register are obtained, including the memory space size and resource attributes;

[0019] The processor obtains the corresponding memory base address based on the resource requirements of the request register;

[0020] Send the memory base address to the base address register of the target device;

[0021] In response to a successful transmission of the memory base address, the lock flag bit of the control register is set;

[0022] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0023] In response to the operating system startup, memory resources are allocated to the target device based on the lock flag bit in the control register.

[0024] This application also provides a computer-readable storage medium storing a computer program, wherein when executed by a processor, the computer program implements the steps of a device resource allocation method, the method comprising:

[0025] The processor determines the type of hot-plug event for the expansion device.

[0026] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device that includes a first register group, the first register group including a request register, a base address register, and a control register;

[0027] In response to the addition of an extended device as the target device, the resource requirements of the target device's request register are obtained;

[0028] The processor obtains the corresponding memory base address based on the resource requirements of the request register;

[0029] Send the memory base address to the base address register of the target device;

[0030] In response to a successful transmission of the memory base address, the lock flag bit of the control register is set;

[0031] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0032] In response to the operating system startup, memory resources are allocated to the target device based on the lock flag bit in the control register.

[0033] This application provides a method that includes: a processor determining the type of a hot-plug event for an extended device; in response to a new extended device event, determining whether the new extended device is a target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register; in response to the new extended device being a target device, obtaining the resource requirements of the target device's request register; the processor obtaining the corresponding memory base address based on the resource requirements of the request register; sending the memory base address to the target device's base address register; in response to successful transmission of the memory base address, setting the lock flag bit of the control register; sending the resource allocation information of the first register group to the operating system through a configuration and power interface table; and in response to the operating system startup, allocating memory resources to the target device according to the lock flag bit of the control register. This application provides real-time detection of address conflicts and resource shortages, supports real-time adjustment of the BAR13 space in hot-plug scenarios, eliminates the need to restart the system, effectively improves resource utilization, and reduces space resource waste.

[0034] This application's technical solution ensures that critical functions of whitelisted devices are ready before the operating system loads by completing configuration during the BIOS firmware stage. The BIOS firmware allocates resources to register BAR13 from global memory resources, effectively avoiding conflicts with subsequent OS resource allocation or OS resource allocation to other devices. Through hardware locking mechanisms and standard ACPI information transmission, OS misoperations are avoided, ensuring the overall stability of BIOS and OS configurations, preventing resource conflicts, and enhancing the scalability of complex devices. Furthermore, this application provides a standardized collaborative framework that can flexibly support the complex resource requirements of various future PCIe devices without requiring large-scale modifications to the operating system kernel. Attached Figure Description

[0035] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A first flowchart of the device resource allocation method provided in the embodiments of this application;

[0037] Figure 2 A second flowchart of the device resource allocation method provided in the embodiments of this application;

[0038] Figure 3 This is a structural diagram of the BAR13 register group provided in an embodiment of this application;

[0039] Figure 4 A flowchart of BAR13 collaborative configuration provided for embodiments of this application;

[0040] Figure 5 Target device screening diagram provided for embodiments of this application;

[0041] Figure 6 A flowchart illustrating the dynamic reconfiguration process provided in this application embodiment;

[0042] Figure 7 A third flowchart illustrating the device resource allocation method provided in this application embodiment;

[0043] Figure 8 A fourth flowchart of the device resource allocation method provided in the embodiments of this application;

[0044] Figure 9 Exemplary systems provided for embodiments of this application that can be used to implement the various embodiments of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0046] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0047] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] PCIe is the most mainstream high-speed serial bus standard in current computer systems, used to connect the processor with various peripheral devices, such as graphics cards, memory controllers, and network interface cards. In order for the processor CPU to access the registers and memory on the PCIe device, the PCIe specification defines the base address register (BAR) mechanism. Each PCIe function's configuration space can contain up to 6 BARs (BAR0-BAR5).

[0049] During system startup, the enumeration process of PCIe devices is usually handled by the operating system (OS) or, in some cases, by the system firmware (such as BIOS / UEFI). This process includes allocating system resources for all devices on the bus, including configuring BAR resources.

[0050] However, with the development of technology, modern PCIe devices have become increasingly complex. Many high-end devices, such as smart network cards that support SR-IOV, accelerator cards for artificial intelligence (AI) and high-performance computing (HPC), and new devices based on the CXL.io protocol, integrate independent management processors, complex virtualization structures that require early initialization, or out-of-band management channels, in addition to the standard functions provided to the operating system. These special functions usually require a stable and isolated memory access space before the operating system is fully loaded and takes over hardware management.

[0051] In related technologies, relying entirely on the standard BAR allocation process of the operating system to handle this type of special function space will face the following challenges:

[0052] 1. Resource conflict risk: When allocating resources, the operating system may not know that a certain BAR corresponds to a management space that requires special handling, which may result in the allocation of an inappropriate address region or an address region that conflicts with other devices, leading to system instability or abnormal device function. In large server systems with a large number of PCIe devices, address space resources are already scarce, resulting in an even higher risk of conflict.

[0053] 2. Configuration time is too late: Some device management functions need to be initialized in the very early stage of system startup (firmware execution stage); waiting for the operating system to load before configuring its BAR space will delay the readiness time of these critical functions, affect the overall startup performance or make some functions that depend on early configuration unable to work properly.

[0054] 3. Lack of flexibility and standardization: For these non-standard BARs (i.e. resource spaces outside of BAR0-BAR5 used for special purposes), the PCIe specification does not provide a unified configuration method. Although it mentions that bridge device resources or SR-IOV resources may use identifiers beyond the scope of regular BARs, their allocation and management lack a clear coordination mechanism. Developers may use various private methods for configuration, resulting in poor compatibility and portability.

[0055] 4. Operating system compatibility issues: Some operating systems may not be able to correctly recognize or handle these special BAR spaces, or may even attempt to incorrectly reconfigure them according to standard procedures during the enumeration process, thereby overwriting earlier settings that have already been completed by the firmware.

[0056] For example: 1. The relevant solutions rely on the Basic Input Output System (BIOS) firmware to statically allocate BAR13 space according to "device enumeration order + fixed size" during the system power-on initialization phase, resulting in resource waste (e.g., a server graphics card GPU only needs 2GB, leaving the other 2GB idle) or demand overflow, making it unable to adapt to scenarios where devices are dynamically added or removed, and lacking flexibility; 2. Some PCIe devices (such as self-developed accelerator cards) support independently requesting BAR13 space through hardware registers, but there is no resource coordination mechanism between devices. For example, if a server graphics card GPU (Graphics Processing Unit) and a storage device NVMe (Non-Volatile Memory Express) request address segments at the same time, it will cause PCIe bus enumeration failure, triggering a blue screen or infinite restart, resulting in address allocation conflicts; 3. The BIOS firmware only allocates space during the initialization phase. When adding an NVMe SSD via hot-swapping, the system needs to be restarted to reallocate BAR13 space, causing business interruption (e.g., AI training tasks are forced to pause), and dynamic space allocation by the BIOS firmware cannot be achieved.

[0057] This application describes how, during the development of an AI server, various PCIe devices are connected via a Switch Bridge. For example, the AI ​​server connects to 8 hard drives, 8 network cards, and 8 GPU cards via a Switch Bridge expansion card. Such an AI server has abundant PCIe device resources, and different AI server models have various combinations of PCIe resources. In the complex device configuration of the AI ​​server project, to enable the CPU to access the registers and memory on the PCIe devices, memory resources need to be allocated to the configuration space of each PCIe device. This ensures that the BAR space of the PCIe device can be mapped to the allocated memory address, allowing the CPU to access the PCIe device as if it were memory.

[0058] Devices request contiguous physical memory address space from the host via BAR to implement key functions such as DMA, device register mapping, and high-bandwidth data transfer. BAR13 is a dedicated register for the PCIe device extended configuration space (defined in PCIe 5.0 and later protocols). Its address width supports 64 bits, allowing allocation of GB or even TB-level memory space. It is specifically designed for peripherals with high bandwidth and low latency requirements (e.g., an NVIDIA H100 GPU requires 2GB or more of BAR13 space for data exchange between video memory and host memory, and a 400G network card requires 512MB of space for packet buffering).

[0059] Understandably, this application addresses problems encountered in the development of existing AI servers by proposing a method for allocating BAR13 space resources in PCIe devices through BIOS firmware combined with hardware co-configuration. The hardware module manages the allocation of BAR13 space resources and performs real-time conflict detection, while the BIOS firmware module collects and dynamically adjusts device requirements. Both synchronize information via the PCIe interface, forming a closed-loop configuration process. This method ensures that the special functional space of BAR13 is not misconfigured during the system enumeration process, thus improving system stability, performance, and support for new and complex PCIe devices.

[0060] Here, "BAR13" is a representative name, generally referring to the memory address space used for special functions of the device, which is outside the scope of the regular BAR0-BAR5 and requires early configuration at the firmware level.

[0061] Embodiments of this application provide a device resource allocation method, such as... Figure 1 As shown, the method is applied to the processor of a server, which also includes several expansion devices. The processor is connected to the expansion devices, and each expansion device includes several registers. The method includes:

[0062] The processor determines the type of hot-plug event for the expansion device.

[0063] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device that includes a first register group, the first register group including a request register, a base address register, and a control register;

[0064] In response to the addition of an extended device as the target device, the resource requirements of the target device's request register are obtained;

[0065] The processor obtains the corresponding memory base address based on the resource requirements of the request register;

[0066] Send the memory base address to the base address register of the target device;

[0067] In response to a successful transmission of the memory base address, the lock flag bit of the control register is set;

[0068] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0069] In response to the operating system startup, memory resources are allocated to the target device based on the lock flag bit in the control register.

[0070] It is understood that this application provides a firmware and hardware collaborative configuration method for BAR13 space resource allocation in PCIe devices. The method adjusts the memory resource allocation size according to the actual needs of the device (rather than fixed rules), realizes dynamic allocation of BAR13 space, detects address conflicts and resource shortages in real time, supports real-time adjustment of BAR13 space in hot-swappable scenarios, does not require system restart, effectively improves BAR13 resource utilization, and reduces space resource waste.

[0071] The request register is used to define the size, alignment, and resource attributes of the first register group memory space.

[0072] The base address register is used to store the base address of the memory region corresponding to the resource requirement conditions of the first register group allocated by the global physical memory address mapping table;

[0073] The control register is used to latch and prevent the operating system from modifying the resource configuration of the first register group of the target device in response to the presence of a latch flag in the first register group.

[0074] It is understood that this application discloses a hardware-firmware co-configuration method for PCIe BAR13 space allocation, aiming to solve resource conflicts, inflexible configuration, and operating system compatibility issues that may occur during the allocation of special function address spaces (such as management, virtualization, or out-of-band communication spaces) of complex PCIe devices in the system startup phase. This application pre-defines a dedicated BAR13 configuration interface in the PCIe device hardware, and the system firmware (such as UEFI / BIOS) works in conjunction with this hardware interface before the operating system loads to complete the detection, negotiation, allocation, and locking of the BAR13 space. The firmware then transmits the allocation results to the operating system through standard table interfaces such as ACPI. This method ensures that the special function space of BAR13 is allocated efficiently and conflict-free in the early stages of the system, avoiding erroneous reconfiguration that may be caused by the standard enumeration process of the operating system, and improving the system's stability, performance, and support for new and complex PCIe devices.

[0075] Embodiments of this application provide a device resource allocation method, such as... Figure 2 As shown, the method is applied to the processor of a server, which also includes several expansion devices. The processor is connected to the expansion devices, and each expansion device includes several registers. The method includes:

[0076] The main objective of this application is to provide a hardware-firmware co-configuration method for BAR13 space allocation in PCIe devices to solve the aforementioned problems.

[0077] To achieve the above objectives, this application provides a hardware-firmware collaborative configuration method. The core of this method is to hand over the control of BAR13 space allocation to the system firmware and cooperate with it through a specific hardware interface on the PCIe device, so as to securely transmit a stable and locked configuration result to the operating system.

[0078] Step S01: The processor determines the type of hot-plug event for the expansion device;

[0079] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device. The target device is an extended device that includes a first register group (BAR13), which includes a request register, a base address register, and a control register.

[0080] Specifically, during the initialization phase after the system powers on, the system BIOS firmware enumerates the PCIe bus and uses a predefined whitelist system (which filters PCIe devices by Vendor, Device ID, and PCIe device type) to select the target devices that need to be configured with BAR13.

[0081] For example, target devices include specific smart network interface cards (NICs), GPU graphics cards, and other device types that have special requirements for BAR13.

[0082] Step S02: In response to the addition of an extended device as the target device, obtain the resource requirements of the target device's request register;

[0083] The processor obtains the corresponding memory base address based on the resource requirements of the request register.

[0084] Specifically, such as Figure 3 As shown, the BIOS firmware interacts with the target device; firstly, a set of dedicated registers is predefined in the PCIe device:

[0085] BAR13 Request Register: This register defines the size, alignment, and attributes (such as whether it is prefetchable) of the BAR13 space. The BIOS firmware can obtain the BAR13 configuration requirements of the target device through this register.

[0086] BAR13 Base Address Register: Stores the base address of the memory region allocated by the BIOS;

[0087] BAR13 Control Register: BAR13 latch prevents the operating system from subsequently modifying the BAR13 configuration assigned by the BIOS firmware.

[0088] Step S021: Establish a global physical memory address mapping table in the system resource pool;

[0089] The memory address region that meets the resource requirements of the request register is determined based on the resource requirements of the request register and the global physical memory address mapping table. The resource requirements include memory space size and resource attributes.

[0090] Set the memory address range to the memory base address.

[0091] Step S03, as follows Figure 4 As shown, the memory base address is sent to the base address register of the target device;

[0092] In response to a successful transmission of the memory base address, the lock flag bit of the control register is set.

[0093] Step S04: Send the resource allocation information of the first register group to the operating system by configuring the power interface table;

[0094] In response to the operating system startup, memory resources are allocated to the target device based on the lock flag bit in the control register.

[0095] Specifically, such as Figure 5As shown, during the POST phase of memory resource allocation, the system BIOS firmware adds a new operation on the BAR13 dedicated register of the PCIe target device: 1. Based on the BAR13 request register requirements obtained from the target device hardware, a suitable memory region is safely searched and allocated in the global system physical memory address mapping; this process avoids critical regions that are already occupied, thus ensuring conflict-free allocation; 2. After allocation, the BIOS firmware "writes back" the base address of the allocated memory region to the BAR13 base address register of the PCIe target device; 3. The latch flag of the BAR13 control register is set; this latch flag is a crucial link in the coordination between the PCIe target device and the BIOS firmware, indicating that the PCIe target device has already allocated resources, and any subsequent attempts to modify the BAR configuration from the BIOS firmware or operating system should be rejected.

[0096] Step S041: Obtain the lock flag bit of the control register;

[0097] The configuration status of the memory space of the first register group is determined based on the lock flag bit of the control register;

[0098] In response to the fact that the memory space of the first register group has been pre-configured by the processor, the memory configuration of the first register group of the target device is stopped, and memory resources are allocated to the other registers of the target device.

[0099] Allocate memory resources for other registers of the target device, including:

[0100] The priority strategy for allocating memory resources of other registers in the target device is determined based on the size of the register's resource requirement space.

[0101] Memory resources are allocated to other registers of the target device according to the priority strategy for memory resource allocation;

[0102] Memory resources are allocated to other registers of the target device according to the priority strategy for memory resource allocation, including:

[0103] When the resource space requirement of a register is greater than the first threshold (3-4GB), memory resources are allocated to that register first.

[0104] When the resource space requirement of a register is less than or equal to the first threshold, memory resource allocation for that register is downgraded.

[0105] If the available address space in the system resource pool is insufficient, it will determine whether the physical address space of the operating system is enabled if it is greater than the second threshold (4GB), and allocate memory resources according to the enabled status of the physical address space.

[0106] In response to overlapping physical memory addresses allocated to registers, the register resource allocation problem is diagnosed by cross-validating the results of the display configuration information tool and the memory resource mapping table tool, and the operating system is updated.

[0107] Specifically, the firmware passes the allocation information (base address, space size, etc.) of the BAR13 space to the operating system through the standard ACPI (Advanced Configuration and Power Interface) table or other similar BIOS firmware and operating system standard interfaces. When the operating system starts and begins its regular PCIe device enumeration, the new operating system learns that the BAR13 space has been pre-configured and locked by the firmware by reading the lock flag bit of the BAR13 control register on the PCIe target device. Therefore, the operating system will skip the configuration of the register group BAR13 for this target device and only perform its regular memory resource allocation process for other standard registers BAR (such as BAR0-BAR5) of this device.

[0108] Step S05: In response to the occurrence of an extended device removal event, obtain the resource configuration information of the removed extended device and release the resource configuration space of the removed extended device;

[0109] Update the configuration and power interface table, and send resource release information to the operating system.

[0110] Step S06: In response to the fact that the newly added extended device is not the target device, memory resources are allocated to the extended device according to the register readback value of the newly added extended device.

[0111] Based on the register readback value of the newly added extended device, memory resources are allocated to the extended device, including:

[0112] Write a first preset value (all 1s) to any register of the newly added extended device, and then read back the value of the register of the newly added extended device;

[0113] Analyze the readback values ​​of the registers of the newly added extended device;

[0114] The physical address space size and resource type of the newly added extended device are determined by analyzing the register readback values ​​of the newly added extended device.

[0115] Based on the physical address space size and resource type of the newly added extended device resource request, a physical address space matching the physical address space size of the extended device resource request is allocated from the available addresses in the system resource pool.

[0116] Write the base address of the corresponding matching physical address space into the register of the newly added extended device to complete the physical address mapping of the newly added extended device.

[0117] Specifically, the configuration process of the BAR register for an extended device is as follows: The software (OS kernel driver) first writes all 1s into the BAR register, then reads back the value of the register, and analyzes the read-back value to determine the size of the address space and the type of resources (memory space or I / O space, 32-bit or 64-bit, whether it is prefetchable) requested by the extended device (PCIE); then, the software allocates a block of contiguous physical address space of the corresponding size from the system's available address resource pool, and writes the base address of the space into the BAR register, thereby completing the physical address mapping.

[0118] Step S07: Update the global physical memory address mapping table and the configuration and power interface table, and dynamically adjust the system resource pool according to the memory resource allocation of the target device;

[0119] The system resource pool is dynamically adjusted based on the memory resource allocation of the target device, including:

[0120] The system resource pool is dynamically adjusted based on the system firmware layer;

[0121] The system resource pool is dynamically adjusted based on the system firmware layer, including:

[0122] Record the allocated and free memory areas in the system resource pool;

[0123] Adjust the allocated and free memory areas according to the memory resource allocation of the target device;

[0124] If the system resource pool is insufficient, the system resource pool will be expanded or compressed.

[0125] Update the current resource settings table of the system resource pool through the configuration and power interface notification mechanism;

[0126] The system resource pool is dynamically adjusted based on the operating system layer;

[0127] Dynamically adjust the system resource pool based on the operating system layer, including:

[0128] When the target device is inserted, the PCIe bus address space allocation function is called through the hot-plug driver at the operating system layer.

[0129] The resource requirements of the target device are determined by the address space allocation function of the PCIe bus.

[0130] Based on the resource requirements of the target device, allocate the corresponding physical memory address of the target device from the system resource pool maintained by the operating system kernel;

[0131] The system resource pool is reallocated using the Plug and Play Manager (PNP Manager) and the Configuration Power Interface Driver Stack (ACPI Driver Stack).

[0132] Step S08, as follows Figure 6 As shown, the lock status of the control register is verified;

[0133] Verify the lock status of the control register, including:

[0134] Send an interrupt request for the process of allocating memory resources to the target device based on the lock flag bit of the control register;

[0135] Determine if the lock flag bit of the control register is valid;

[0136] In response to the failure of the lock flag bit of the control register, the lock flag bit of the control register is reset; the resource allocation information of the first register group is sent to the operating system through the configuration and power interface table; in response to the start of the operating system, the memory resources of the target device are reallocated according to the lock flag bit of the control register, and the configuration and power interface table is updated.

[0137] If the lock flag bit of the control register is valid, the process of verifying the lock status of the control register ends.

[0138] Step S09: Optimize memory resource allocation for the target device;

[0139] The optimization of memory resource allocation for the target device includes:

[0140] Obtain the lock flag bit of the control register;

[0141] Determine whether the lock flag bit of the control register is valid and whether the flag bit is in a locked state;

[0142] In response to the lock flag bit being valid and the flag bit being locked in the control register, the memory configuration process for the first register group of the target device is stopped.

[0143] In response to the lock flag bit of the control register being invalid or the flag bit being unlocked, memory resources are allocated to the target device based on the readback value of the first register group of the target device.

[0144] Remove the physical memory address corresponding to the first register group of the target device from the system resource pool to prevent other devices from being mistakenly allocated to this area;

[0145] Record the lock status of the first register group of the target device in the system log.

[0146] Through the above optimizations, the firmware's control over critical resources can be preserved, while the intelligence and compatibility of the operating system's resource management can be improved.

[0147] Here, as Figure 7 , Figure 8 As shown, the BIOS firmware of this application enumerates the PCIe bus and identifies target PCIe devices that support the BAR13 co-configuration function during the system power-on self-test (POST) phase.

[0148] BIOS interacts with the target PCIe device: The system firmware reads the preset BAR13 hardware request register in the target PCIe device to obtain the target device's requirements for the size and attributes of the BAR13 register space;

[0149] BIOS firmware resource allocation: Based on the size and attribute requirements of the obtained BAR13 space, the BIOS firmware searches for and allocates a contiguous, conflict-free memory region in the system physical address space as the BAR13 memory region space.

[0150] BIOS BAR13 configuration write-back: The firmware writes the base address of the allocated memory region into the preset BAR13 base address register in the target PCIe device;

[0151] BAR13 Locking and Information Transmission: The firmware sets the firmware lock flag in the preset BAR13 control register within the target PCIe device to prevent the operating system from modifying the configuration later, and announces the allocated BAR13 space information to the operating system through system tables (such as the ACPI table).

[0152] Understandably, this application addresses the issue of allocating special function space (BAR13 space) for complex PCIe devices. During the POST phase of the system BIOS, devices are enumerated, BAR13 requirements are obtained through the registers built into the PCIe target device, global resource allocation space is performed, and the base address register built into the PCIe target device is written back. A locking flag is set to prevent the OS system from modifying it, and then the OS system is informed through the ACPI table. After the OS system automatically detects the locking flag, it only performs resource configuration for the standard BAR.

[0153] The process involves the system BIOS firmware filtering out target devices, interacting with the target device during the BIOS POST phase to obtain BAR13 requirements, allocating resources and writing back the allocation address, locking the flag bit, and transmitting information through the ACPI table. During firmware allocation, the global planning avoids critical areas. After locking, the OS system recognizes the lock flag bit and skips the configuration of BAR13 for this target device, preventing the OS system from re-allocating resources to the target device's BAR13.

[0154] In addition, setting the lock flag bit of the control register includes:

[0155] The processor allocates a contiguous block of physical memory (e.g., 64GB @ 0x10_0000_0000) from the MMIO resource pool.

[0156] Write consecutive physical memory addresses into the control register of the first register group BAR13 of the target device (e.g., 0x10_0000_0000 | LOCK_BIT).

[0157] Set the LOCK flag in the control register (e.g., bit 31 = 1);

[0158] Write the LOCK flag to the control register via PCIe configuration;

[0159] In response to the operating system startup, enumerate the target devices and read the standard registers BAR0–BAR5 of the target devices;

[0160] When the BAR13 register group is detected, it is determined that the LOCK bit of the control register is set;

[0161] Then skip the reallocation of the BAR13 register group and only map its current value for driver use.

[0162] Set a special "Firmware Lock" flag and write a specific bit into a configuration register of the target device (usually a control register in the extended configuration space) to indicate that the resource has been pre-allocated by the firmware and is prohibited from being modified by the operating system. When the operating system detects the LOCK flag, it skips the reallocation of the BAR13 register group and only performs its normal resource allocation process for other standard BARs (such as BAR0-BAR5) of the target device.

[0163] The device resource allocation method provided in this application embodiment can be improved and optimized in several ways without departing from the technical solution of this application, and these improvements and optimizations should also be considered within the scope of protection of this application.

[0164] The beneficial effects of the technical solutions provided in this application are:

[0165] This application provides real-time detection of address conflicts and resource shortages, and supports real-time adjustment of the BAR13 space in hot-swappable device scenarios without requiring a system restart, effectively improving resource utilization and reducing space resource waste.

[0166] This application's technical solution ensures that critical functions of whitelisted devices are ready before the operating system loads by completing configuration during the BIOS firmware stage. The BIOS firmware allocates resources to register BAR13 from global memory resources, effectively avoiding conflicts with subsequent OS resource allocation or OS resource allocation to other devices. Through hardware locking mechanisms and standard ACPI information transmission, OS misoperations are avoided, ensuring the overall stability of BIOS and OS configurations and enhancing the scalability of complex devices. Furthermore, this application provides a standardized collaborative framework that can flexibly support the complex resource requirements of various new PCIe devices in the future without requiring large-scale modifications to the operating system kernel.

[0167] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0168] Embodiments of this application also provide a server, the server including a processor and a plurality of expansion devices, the processor being connected to the plurality of expansion devices, each expansion device including a plurality of registers, the processor being used for:

[0169] Determine the type of hot-plug event for the expansion device;

[0170] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register;

[0171] In response to the fact that the newly added extended device is a target device, the resource requirements of the request register of the target device are obtained, wherein the resource requirements include memory space size and resource attributes;

[0172] The processor obtains the corresponding memory base address according to the resource requirements of the request register;

[0173] Send the memory base address to the base address register of the target device;

[0174] In response to the successful transmission of the memory base address, the lock flag bit of the control register is set;

[0175] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0176] In response to the startup of the operating system, memory resources are allocated to the target device according to the lock flag bit of the control register.

[0177] The processor is used to: establish a global physical memory address mapping table in the system resource pool;

[0178] The memory address region that satisfies the resource requirements of the request register is determined based on the resource requirements of the request register and the global physical memory address mapping table, wherein the resource requirements include memory space size and resource attributes;

[0179] Set the memory address region as the memory base address.

[0180] The processor is used to: acquire the lock flag bit of the control register;

[0181] The configuration status of the memory space of the first register group is determined based on the lock flag bit of the control register;

[0182] In response to the fact that the memory space of the first register group has been pre-configured by the processor, the memory configuration of the first register group of the target device is stopped, and memory resources are allocated to other registers of the target device.

[0183] The allocation of memory resources for other registers of the target device includes:

[0184] The priority strategy for allocating memory resources of other registers in the target device is determined based on the resource requirement space size of the registers.

[0185] Memory resources are allocated to other registers of the target device according to the priority strategy for memory resource allocation;

[0186] The step of allocating memory resources to other registers of the target device according to the priority strategy for memory resource allocation includes:

[0187] When the resource space requirement of the register is greater than the first threshold, memory resources are allocated to the register first.

[0188] When the resource space requirement of the register is less than or equal to the first threshold, the memory resource allocation for the register is downgraded.

[0189] If the available address space in the system resource pool is insufficient, it is determined whether the physical address space of the operating system is open if it exceeds the second threshold, and memory resources are allocated according to the open status of the physical address space.

[0190] In response to overlapping physical memory addresses allocated to registers, the register resource allocation problem is diagnosed by cross-validating the results of the display configuration information tool and the memory resource mapping table tool, and the operating system is updated.

[0191] The processor is configured to: in response to the fact that the newly added extended device is not the target device, allocate memory resources to the extended device based on the register readback value of the newly added extended device;

[0192] The step of allocating memory resources to the newly added extended device based on the register readback value includes:

[0193] Write a first preset value to any register of the newly added extended device, and then read back the value of the register of the newly added extended device;

[0194] Analyze the readback values ​​of the registers of the newly added extended device;

[0195] The physical address space size and resource type of the newly added extended device are determined by analyzing the register readback values ​​of the newly added extended device.

[0196] Based on the physical address space size and resource type of the newly added extended device resource request, a physical address space matching the physical address space size of the extended device resource request is allocated from the available addresses of the system resource pool.

[0197] Write the base address of the corresponding matching physical address space into the register of the newly added extended device to complete the physical address mapping of the newly added extended device.

[0198] The processor is used to: update the global physical memory address mapping table and the configuration and power interface table, and dynamically adjust the system resource pool according to the memory resource allocation of the target device;

[0199] The step of dynamically adjusting the system resource pool based on the memory resource allocation of the target device includes:

[0200] The system resource pool is dynamically adjusted based on the system firmware layer;

[0201] The dynamic adjustment of the system resource pool based on the system firmware layer includes:

[0202] The system resource pool records the allocated and free memory areas;

[0203] The allocated and free memory areas are adjusted according to the memory resource allocation of the target device;

[0204] If the system resource pool is insufficient, the system resource pool is expanded or compressed.

[0205] The current resource settings table of the system resource pool is updated through the configuration and power interface notification mechanism;

[0206] The system resource pool is dynamically adjusted based on the operating system layer;

[0207] The dynamic adjustment of the system resource pool based on the operating system layer includes:

[0208] When the target device is inserted, the PCIe bus address space allocation function is called through the hot-plug driver at the operating system layer.

[0209] The resource requirements of the target device are determined by the PCIe bus address space allocation function.

[0210] Based on the resource requirements of the target device, the physical memory address corresponding to the target device is allocated from the system resource pool maintained by the operating system kernel.

[0211] The system resource pool is reallocated using a plug-and-play manager and a configured power interface driver stack.

[0212] The processor is used to: verify the lock status of the control register;

[0213] The step of verifying the lock state of the control register includes:

[0214] Send an interrupt request to the process of allocating memory resources to the target device based on the lock flag bit of the control register;

[0215] Determine whether the lock flag bit of the control register is valid;

[0216] In response to the failure of the lock flag bit of the control register, the lock flag bit of the control register is reset; the resource allocation information of the first register group is sent to the operating system through the configuration and power interface table; in response to the startup of the operating system, the memory resources of the target device are reallocated according to the lock flag bit of the control register, and the configuration and power interface table is updated.

[0217] If the lock flag bit of the control register is valid, the process of verifying the lock status of the control register ends.

[0218] Specifically, during the system power-on self-test (POST) phase, the firmware of this application enumerates the PCIe bus and identifies target PCIe devices that support the BAR13 co-configuration function.

[0219] The system firmware obtains the target device's requirements for the size and attributes of the BAR13 register space by reading the preset BAR13 hardware request register in the target PCIe device;

[0220] Based on the obtained space requirements, the system firmware searches for and allocates a contiguous, conflict-free memory region in the system's physical address space as the BAR13 space.

[0221] The system firmware writes the base address of the allocated memory region into the preset BAR13 base address register in the target PCIe device;

[0222] The system firmware sets the firmware lock flag in the preset BAR13 control register within the target PCIe device to prevent the operating system from modifying the configuration later, and announces the allocated BAR13 space information to the operating system through a system table (such as the ACPI table).

[0223] Here, identifying a target PCIe device that supports BAR13 co-configuration is achieved by checking a specific identifier in the device's VendorID, Device ID, or PCIe Extended Capability structure;

[0224] The BAR13 hardware request register not only defines the space size requirement, but also the properties of that space, including whether it is prefetchable or non-prefetchable.

[0225] When allocating BAR13 space, the firmware will reserve critical system resource areas in advance and take into account the standard BAR space requirements of other PCIe devices in the system to avoid address overlap or insufficient resources.

[0226] Once the firmware lock flag is set, the hardware logic of the target PCIe device will prevent write operations from the operating system to the BAR13 base address register and control register.

[0227] After the operating system is loaded, its PCIe bus driver identifies and accepts the BAR13 space allocation that the firmware has completed by reading the firmware lock flag or parsing the system table (such as the ACPI table), and only performs the normal resource allocation process for other standard registers BAR (such as BAR0-BAR5) of the device.

[0228] The beneficial effects of the technical solutions provided in this application are:

[0229] This application provides real-time detection of address conflicts and resource shortages, and supports real-time adjustment of the BAR13 space in hot-swappable device scenarios without requiring a system restart, effectively improving resource utilization and reducing space resource waste.

[0230] This application's technical solution ensures that critical functions of whitelisted devices are ready before the operating system loads by completing configuration during the BIOS firmware stage. The BIOS firmware allocates resources to register BAR13 from global memory resources, effectively avoiding conflicts with subsequent OS resource allocation or OS resource allocation to other devices. Through hardware locking mechanisms and standard ACPI information transmission, OS misoperations are avoided, ensuring the overall stability of BIOS and OS configurations and enhancing the scalability of complex devices. Furthermore, this application provides a standardized collaborative framework that can flexibly support the complex resource requirements of various new PCIe devices in the future without requiring large-scale modifications to the operating system kernel.

[0231] Embodiments of this application also provide an electronic device (server), the server including a processor and a plurality of expansion devices, the processor being connected to the plurality of expansion devices, each expansion device including a plurality of registers.

[0232] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in the device resource allocation method embodiment, the method including:

[0233] The processor determines the type of hot-plug event for the expansion device.

[0234] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register;

[0235] In response to the fact that the newly added extended device is the target device, the resource requirements of the request register of the target device are obtained;

[0236] The processor obtains the corresponding memory base address according to the resource requirements of the request register;

[0237] Send the memory base address to the base address register of the target device;

[0238] In response to the successful transmission of the memory base address, the lock flag bit of the control register is set;

[0239] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0240] In response to the startup of the operating system, memory resources are allocated to the target device according to the lock flag bit of the control register.

[0241] like Figure 9 As shown, embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the device resource allocation method embodiments at runtime, the method including:

[0242] The processor determines the type of hot-plug event for the expansion device.

[0243] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register;

[0244] In response to the fact that the newly added extended device is the target device, the resource requirements of the request register of the target device are obtained;

[0245] The processor obtains the corresponding memory base address according to the resource requirements of the request register;

[0246] Send the memory base address to the base address register of the target device;

[0247] In response to the successful transmission of the memory base address, the lock flag bit of the control register is set;

[0248] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0249] In response to the startup of the operating system, memory resources are allocated to the target device according to the lock flag bit of the control register.

[0250] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0251] Embodiments of this application also provide a computer program product, which includes a computer program. When executed by a processor, the computer program implements the steps in the device resource allocation method embodiment, the method including:

[0252] The processor determines the type of hot-plug event for the expansion device.

[0253] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register;

[0254] In response to the fact that the newly added extended device is the target device, the resource requirements of the request register of the target device are obtained;

[0255] The processor obtains the corresponding memory base address according to the resource requirements of the request register;

[0256] Send the memory base address to the base address register of the target device;

[0257] In response to the successful transmission of the memory base address, the lock flag bit of the control register is set;

[0258] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0259] In response to the startup of the operating system, memory resources are allocated to the target device according to the lock flag bit of the control register.

[0260] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the steps in the device resource allocation method embodiments, the method including:

[0261] The processor determines the type of hot-plug event for the expansion device.

[0262] In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register;

[0263] In response to the fact that the newly added extended device is the target device, the resource requirements of the request register of the target device are obtained;

[0264] The processor obtains the corresponding memory base address according to the resource requirements of the request register;

[0265] Send the memory base address to the base address register of the target device;

[0266] In response to the successful transmission of the memory base address, the lock flag bit of the control register is set;

[0267] The resource allocation information of the first register group is sent to the operating system by configuring the power interface table;

[0268] In response to the startup of the operating system, memory resources are allocated to the target device according to the lock flag bit of the control register.

[0269] This application provides real-time detection of address conflicts and resource shortages, and supports real-time adjustment of the BAR13 space in hot-swappable device scenarios without requiring a system restart, effectively improving resource utilization and reducing space resource waste.

[0270] This application's technical solution ensures that critical functions of whitelisted devices are ready before the operating system loads by completing configuration during the BIOS firmware stage. The BIOS firmware allocates resources to register BAR13 from global memory resources, effectively avoiding conflicts with subsequent OS resource allocation or OS resource allocation to other devices. Through hardware locking mechanisms and standard ACPI information transmission, OS misoperations are avoided, ensuring the overall stability of BIOS and OS configurations and enhancing the scalability of complex devices. Furthermore, this application provides a standardized collaborative framework that can flexibly support the complex resource requirements of various new PCIe devices in the future without requiring large-scale modifications to the operating system kernel.

[0271] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0272] The above provides a detailed description of a device resource allocation method and server provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for allocating equipment resources, characterized in that, The method is applied to a processor of a server, the server further comprising a plurality of expansion devices, the processor being connected to the plurality of expansion devices, each expansion device comprising a plurality of registers, the method comprising: The processor determines the type of hot-plug event for the expansion device. In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register; In response to the fact that the newly added extended device is the target device, the resource requirements of the request register of the target device are obtained; The processor obtains the corresponding memory base address according to the resource requirements of the request register; Send the memory base address to the base address register of the target device; In response to the successful transmission of the memory base address, the lock flag bit of the control register is set; The resource allocation information of the first register group is sent to the operating system by configuring the power interface table; In response to the startup of the operating system, memory resources are allocated to the target device according to the lock flag bit of the control register; The step of obtaining the corresponding memory base address based on the resource requirements of the request register includes: Establish a global physical memory address mapping table in the system resource pool; The memory address region that satisfies the resource requirements of the request register is determined based on the resource requirements of the request register and the global physical memory address mapping table, wherein the resource requirements include memory space size and resource attributes; Set the memory address region as the memory base address.

2. The equipment resource allocation method according to claim 1, characterized in that, The step of allocating memory resources to the target device according to the lock flag bit of the control register includes: Obtain the lock flag bit of the control register; The configuration status of the memory space of the first register group is determined based on the lock flag bit of the control register; In response to the fact that the memory space of the first register group has been pre-configured by the processor, the memory configuration of the first register group of the target device is stopped, and memory resources are allocated to other registers of the target device. The allocation of memory resources for other registers of the target device includes: The priority strategy for allocating memory resources of other registers in the target device is determined based on the resource requirement space size of the registers. Memory resources are allocated to other registers of the target device according to the priority strategy for memory resource allocation; The step of allocating memory resources to other registers of the target device according to the priority strategy for memory resource allocation includes: When the resource space requirement of the register is greater than the first threshold, memory resources are allocated to the register first. When the resource space requirement of the register is less than or equal to the first threshold, the memory resource allocation for the register is downgraded. If the available address space in the system resource pool is insufficient, it is determined whether the physical address space of the operating system is open if it exceeds the second threshold, and memory resources are allocated according to the open status of the physical address space. In response to overlapping physical memory addresses allocated to registers, the register resource allocation problem is diagnosed by cross-validating the results of the display configuration information tool and the memory resource mapping table tool, and the operating system is updated.

3. The equipment resource allocation method according to claim 1, characterized in that, The method includes: In response to an event that an extended device is removed, the resource configuration information of the removed extended device is obtained, and the resource configuration space of the removed extended device is released. Update the configuration and power interface table, and send resource release information to the operating system.

4. The equipment resource allocation method according to claim 1, characterized in that, The method includes: If the newly added extended device is not the target device, then memory resources are allocated to the extended device based on the register readback value of the newly added extended device; The step of allocating memory resources to the newly added extended device based on the register readback value includes: Write a first preset value to any register of the newly added extended device, and then read back the value of the register of the newly added extended device; Analyze the readback values ​​of the registers of the newly added extended device; The physical address space size and resource type of the newly added extended device are determined by analyzing the register readback values ​​of the newly added extended device. Based on the physical address space size and resource type of the newly added extended device resource request, a physical address space matching the physical address space size of the extended device resource request is allocated from the available addresses of the system resource pool. Write the base address of the corresponding matching physical address space into the register of the newly added extended device to complete the physical address mapping of the newly added extended device.

5. The equipment resource allocation method according to claim 1, characterized in that, After allocating memory resources to the target device according to the lock flag bit of the control register, the process includes: Update the global physical memory address mapping table and the configuration and power interface table, and dynamically adjust the system resource pool according to the memory resource allocation of the target device; The step of dynamically adjusting the system resource pool based on the memory resource allocation of the target device includes: The system resource pool is dynamically adjusted based on the system firmware layer; The dynamic adjustment of the system resource pool based on the system firmware layer includes: The system resource pool records the allocated and free memory areas; The allocated and free memory areas are adjusted according to the memory resource allocation of the target device; If the system resource pool is insufficient, the system resource pool is expanded or compressed. The current resource settings table of the system resource pool is updated through the configuration and power interface notification mechanism; The system resource pool is dynamically adjusted based on the operating system layer; The dynamic adjustment of the system resource pool based on the operating system layer includes: When the target device is inserted, the bus address space allocation function is called through the hot-plug driver at the operating system layer. The resource requirements of the target device are determined by the bus address space allocation function. Based on the resource requirements of the target device, the physical memory address corresponding to the target device is allocated from the system resource pool maintained by the operating system kernel. The system resource pool is reallocated using a plug-and-play manager and a configured power interface driver stack.

6. The equipment resource allocation method according to claim 1, characterized in that, The method includes: The lock status of the control register is verified; The step of verifying the lock state of the control register includes: Send an interrupt request to the process of allocating memory resources to the target device based on the lock flag bit of the control register; Determine whether the lock flag bit of the control register is valid; In response to the failure of the lock flag bit of the control register, the lock flag bit of the control register is reset; the resource allocation information of the first register group is sent to the operating system through the configuration and power interface table; in response to the startup of the operating system, the memory resources of the target device are reallocated according to the lock flag bit of the control register, and the configuration and power interface table is updated. If the lock flag bit of the control register is valid, the process of verifying the lock status of the control register ends.

7. The equipment resource allocation method according to claim 1, characterized in that, The method further includes: The memory resource allocation of the target device is optimized. The optimization of memory resource allocation for the target device includes: Obtain the lock flag bit of the control register; Determine whether the lock flag bit of the control register is valid and whether the flag bit is in a locked state; In response to the lock flag bit being valid and the flag bit being locked in the control register, the memory configuration process for the first register group of the target device is stopped. In response to the lock flag bit of the control register being invalid or the flag bit being unlocked, memory resources are allocated to the target device based on the readback value of the first register group of the target device. Remove the physical memory address corresponding to the first register group of the target device from the system resource pool; Record the lock status of the first register group of the target device in the system log.

8. The equipment resource allocation method according to claim 1, characterized in that, The first register group includes a request register, a base address register, and a control register. The request register is used to define the size, alignment, and resource attributes of the memory space of the first register group; The base address register is used to store the base address of the memory region corresponding to the resource requirement conditions of the first register group allocated by the global physical memory address mapping table; The control register is used to latch and prevent the operating system from modifying the resource configuration of the first register group of the target device in response to the presence of a latch flag bit in the first register group.

9. A server, characterized in that, The server includes a processor and several expansion devices. The processor is connected to the expansion devices, and each expansion device includes several registers. The processor is used for: Determine the type of hot-plug event for the expansion device; In response to an event indicating the addition of an extended device, it is determined whether the added extended device is the target device, wherein the target device is an extended device including a first register group, the first register group including a request register, a base address register, and a control register; In response to the fact that the newly added extended device is a target device, the resource requirements of the request register of the target device are obtained, wherein the resource requirements include memory space size and resource attributes; The processor obtains the corresponding memory base address according to the resource requirements of the request register; Send the memory base address to the base address register of the target device; In response to the successful transmission of the memory base address, the lock flag bit of the control register is set; The resource allocation information of the first register group is sent to the operating system by configuring the power interface table; In response to the startup of the operating system, memory resources are allocated to the target device according to the lock flag bit of the control register; The step of obtaining the corresponding memory base address based on the resource requirements of the request register includes: Establish a global physical memory address mapping table in the system resource pool; The memory address region that satisfies the resource requirements of the request register is determined based on the resource requirements of the request register and the global physical memory address mapping table, wherein the resource requirements include memory space size and resource attributes; Set the memory address region as the memory base address.

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