A method for intelligent resource allocation for cognitive subzone energy

Abstract

This invention discloses an intelligent resource allocation method for energy-aware partitions, belonging to the field of computer architecture and operating system task scheduling technology. The method divides computing resources into multiple independent energy-aware partitions based on the processor cores. It then monitors the energy status parameters of each partition in real time. By parsing the instruction code stream of the tasks to be assigned, the proportion of arithmetic and logical instructions is extracted as instruction mixing features, and the address span of memory access instructions is analyzed to obtain cache access density features. Based on the energy status of the partitions and the computation and memory access characteristics of the tasks, a suitability score for the task relative to each partition is generated, comprehensively reflecting the energy matching degree and hardware resource matching degree. Based on the suitability score and the remaining task acceptance capacity of the partitions, a two-dimensional assignment strategy is used to dynamically map tasks to the core execution in the optimal energy-aware partition. This invention achieves fine-grained matching of computing resources and energy status, optimizing system energy utilization efficiency.

Description

Technical Field

[0001] This invention discloses an intelligent resource allocation method for intelligent sensing partition energy, belonging to the field of computer architecture and operating system task scheduling technology. Background Technology

[0002] In traditional multi-core processor task scheduling techniques, the operating system typically treats processor cores as equal computing resources, allocating tasks and balancing load based on core load percentage or utilization. This scheduling approach primarily focuses on the efficiency of computing resource utilization, such as migrating tasks to idle cores to improve throughput or assigning related tasks to cores with shared caches to reduce data access latency. However, with the increasing integration of processors and the growing complexity of computing scenarios, especially the stringent requirements for battery life and thermal management in mobile and edge computing, scheduling strategies based solely on load information are no longer sufficient to meet the optimization needs for system energy efficiency. Existing scheduling methods generally fail to adequately consider the energy consumption distribution of processor cores in physical space, the topology of the power supply network, and the impact of localized heat accumulation on the overall system stability. This can lead to localized power overload, hotspot formation, and uneven battery consumption across physical partitions during concurrent multitasking, thereby limiting the performance release and continuous operation capability of the computing system.

[0003] To address these challenges, some existing technologies attempt to introduce power-aware scheduling mechanisms. For example, they might adjust task execution frequency and voltage by monitoring the overall processor current or temperature, or perform predictive scheduling by collecting historical power consumption data at the operating system level. However, these solutions typically treat the processor as a single power unit, or only allow for coarse-level power control at the package level, failing to delve into the fine-grained resource management at the physical partition level within the chip. Furthermore, the differences in task instruction composition lead to varying degrees of activation of different hardware units within the processor during execution. For instance, the power consumption characteristics of floating-point and integer arithmetic units differ significantly, and different cache access modes also greatly impact the energy consumption of the cache subsystem. Existing technologies lack effective means to correlate and match the micro-instructional characteristics of tasks with the real-time energy state of physical partitions. This disconnect between task characteristics and partition energy state makes it difficult for scheduling decisions to achieve balanced utilization of partition energy and proactive avoidance of local hotspots while ensuring task performance.

[0004] To address the limitations of existing technologies, there is an urgent need for an intelligent method capable of energy-aware partitioning of computing resources at the physical level, and dynamically allocating resources based on the task's instruction mixing characteristics and cache access density characteristics, combined with the real-time status of each partition, such as instantaneous power consumption, temperature, and remaining battery power. This method requires in-depth understanding of the processor's physical layout and power supply topology, dividing computing resources into independent energy management units. It also involves extracting the energy consumption tendencies of task code through static analysis, thereby constructing a multi-dimensional adaptation model between tasks and partitions. By precisely mapping tasks to partitions whose energy states match, it is possible to effectively control local power consumption peaks, balance power consumption between partitions, and suppress hotspots while meeting task computing requirements. This ultimately improves the overall energy utilization efficiency and task execution stability of the computing system, providing a refined resource management solution for high-performance computing and low-power embedded scenarios. Summary of the Invention

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] A method for intelligent resource allocation of energy in intelligent sensing zones includes:

[0007] S1, the physical computing resources of the computing system are divided into multiple energy-aware partitions according to their physical location and power supply topology, and each energy-aware partition includes a processor core and a corresponding local cache.

[0008] S2, monitor the real-time energy status parameters of each energy sensing partition in the current execution cycle, the real-time energy status parameters include the partition's instantaneous power consumption, partition temperature and partition's remaining power;

[0009] S3, parse the current queue of tasks to be assigned, and extract the instruction mixing features and cache access density features of each task to be assigned;

[0010] S4. Based on the real-time energy state parameters of each energy sensing partition and the instruction mixing characteristics and cache access density characteristics of each task to be assigned, generate a partition adaptation score for each task to be assigned.

[0011] S5. Based on the partition adaptation score, the task to be assigned is dynamically mapped to the processor core in the corresponding energy-aware partition for execution.

[0012] Further, S1 includes:

[0013] Obtain the motherboard layout diagram of the computing system, which includes the physical coordinates of the processor core, the power supply domain division of the shared voltage regulation module, and the physical arrangement of the cache.

[0014] At least one processor core connected to the same voltage regulation module output and located within a preset physical proximity range, along with its dedicated L1 cache and shared L2 cache, are divided into an initial energy partition.

[0015] Detect whether there is a power shared path or physical substrate contact area between the initial energy partition and adjacent energy partitions;

[0016] If the power sharing path or physical substrate contact area exists, the two initial energy partitions with a sharing relationship will be merged into a final energy sensing partition.

[0017] Each of the energy sensing partitions is assigned a unique partition identifier, and a mapping relationship between the partition identifier and the physical core bitmap is established in the operating system scheduler.

[0018] Further, S2 includes:

[0019] A current sensing circuit and a voltage sensing circuit are deployed at the power supply inlet of each energy sensing zone. The instantaneous current value and the instantaneous voltage value flowing through the zone are collected by the current sensing circuit and the voltage sensing circuit at a fixed sampling frequency. The product of the instantaneous current value and the instantaneous voltage value is determined as the instantaneous power consumption of the zone.

[0020] Temperature sensing diodes are installed on the substrate surface of the processor cores contained in each energy sensing partition. The real-time junction temperature of the core is obtained by the change of the pn junction voltage of the temperature sensing diodes. The highest real-time junction temperature of all cores in the partition is taken as the partition temperature of the partition.

[0021] In the power management unit of the computing system, an independent power counter is maintained for each energy sensing partition. The power counter records the remaining available power allocated to the partition from the total system battery capacity in a coulomb measurement manner. At the end of each execution cycle, the power counter of the partition is decremented and updated according to the instantaneous power consumption and cycle duration to obtain the remaining power of the partition.

[0022] Further, S3 includes:

[0023] For each task in the current task queue to be assigned, obtain its executable code segment, perform static instruction scanning on the executable code segment, and count the first number of integer arithmetic instructions, the second number of floating-point arithmetic instructions, and the third number of memory access instructions contained in the executable code segment.

[0024] Based on the first number of integer arithmetic instructions and the second number of floating-point arithmetic instructions, the total number of arithmetic logic instructions is calculated, and the ratio of the total number of arithmetic logic instructions to the total number of instructions in the task is determined as the instruction mixing characteristic of the task.

[0025] The executable code segment is divided into basic blocks, the memory access instructions contained in each basic block are identified, and the memory address accessed by each memory access instruction is analyzed. The address difference between adjacent memory access instructions is calculated based on the address access span of the memory access instructions. The address difference is cumulatively distributed and analyzed to count the number of memory access instruction pairs whose address difference is less than the preset cache line size. The ratio of the number of memory access instruction pairs to the total number of memory access instructions in the task is determined as the cache access density feature of the task.

[0026] Further, S4 includes:

[0027] For each task in the task queue to be assigned, calculate the fit score between the task and each energy sensing partition.

[0028] In the compatibility score calculation between a task and a partition, a first component is generated based on the comparison between the partition temperature and a preset temperature threshold, a second component is generated based on the comparison between the remaining power of the partition and the estimated power consumption of the task, and a third component is generated based on the comparison between the instantaneous power consumption of the partition and the rated power consumption of the partition.

[0029] A fourth component is generated based on the degree of matching between the instruction mixing characteristics of the task and the hardware computing unit type of the partition, and a fifth component is generated based on the degree of matching between the cache access density characteristics of the task and the cache capacity of the partition.

[0030] The first component, the second component, the third component, the fourth component, and the fifth component are weighted and accumulated, and the result of the weighted accumulation is used as the fitness score of the task relative to the partition.

[0031] Furthermore, generating the fourth component based on the degree of matching between the instruction mixing characteristics of the task and the hardware computing unit type of the partition includes:

[0032] Obtain the instruction set architecture extension identifiers supported by the processor cores within the energy-aware partition. The instruction set architecture extension identifiers include single instruction multiple data extension identifiers, advanced vector extension identifiers, and floating-point acceleration unit identifiers.

[0033] The degree of dependence of the task on floating-point computing resources and the degree of dependence on vector computing resources are determined based on the instruction mixing characteristics of the task.

[0034] If the task's dependence on floating-point computing resources exceeds the floating-point dependence threshold and the instruction set architecture extension identifier contains the floating-point acceleration unit identifier, then the fourth component is assigned a first positive value.

[0035] If the task's dependence on vector computing resources exceeds the vector dependence threshold and the instruction set architecture extension identifier contains the advanced vector extension identifier, then the fourth component is assigned a second positive value.

[0036] If the task's dependence on integer operation resources exceeds the integer dependence threshold, the fourth component will be assigned a third positive value, regardless of the value of the instruction set architecture extension identifier.

[0037] If the task's dependence on floating-point computing resources exceeds the floating-point dependence threshold, but the instruction set architecture extension identifier does not contain the floating-point acceleration unit identifier, then the fourth component is assigned a first negative value.

[0038] Furthermore, the step of generating a fifth component based on the matching degree between the cache access density characteristics of the task and the cache capacity of the partition includes:

[0039] Obtain the capacity value of the last-level cache shared within this energy sensing partition;

[0040] Based on the numerical range of the cache access density characteristics of the task, the task is classified into high-density access type, medium-density access type, or low-density access type.

[0041] If the task is a high-density access type and the capacity value of the last-level cache is greater than the first cache capacity threshold, then the fifth component is assigned a first positive value.

[0042] If the task is of medium-density access type and the capacity value of the last level cache is between the first cache capacity threshold and the second cache capacity threshold, then the fifth component is assigned a second positive value;

[0043] If the task is a low-density access type and the capacity value of the last level cache is less than the second cache capacity threshold, then the fifth component is assigned a third positive value.

[0044] If the task is a high-density access type and the capacity value of the last-level cache is less than the second cache capacity threshold, then the fifth component is assigned a first negative value.

[0045] Further, S5 includes:

[0046] Based on the fit score of each task to be assigned relative to each energy-aware partition, a task-partition fit matrix is ​​constructed. The row index of the task-partition fit matrix corresponds to the identifier of the task to be assigned, the column index corresponds to the identifier of the energy-aware partition, and the matrix elements are the corresponding fit scores.

[0047] Scan the task-partition fit matrix to initially determine one or more candidate energy-aware partitions for each task to be assigned. The candidate energy-aware partitions refer to partitions with a fit score greater than a preset admission threshold.

[0048] For each energy-sensing partition, obtain the current task load count and the utilization rate of each processor core in that partition, and determine the remaining task acceptance capacity of that partition based on the task load count and the utilization rate of each processor core.

[0049] Based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, a two-dimensional assignment strategy is adopted to determine a unique target energy-aware partition for each task to be assigned. The goal of the two-dimensional assignment strategy is to maximize the sum of fit scores of all assigned tasks under the constraint of not exceeding the remaining task acceptance capacity of each partition.

[0050] Based on the determination result of the two-dimensional assignment strategy, the execution context of each task to be assigned is migrated to the ready queue of the processor core contained in its target energy-aware partition.

[0051] Furthermore, the step of determining a unique target energy-aware partition for each task to be assigned based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, using a two-dimensional assignment strategy, includes:

[0052] All tasks to be assigned are sorted in descending order of suitability score to generate a task processing sequence;

[0053] All energy-sensing partitions are sorted in ascending order of remaining task capacity to generate a partition processing sequence;

[0054] Extract the first task that appears first in the task processing sequence, and obtain the first partition with the highest adaptation score for the first task based on the task-partition adaptation matrix.

[0055] Check if the remaining task acceptance capacity of the first partition is greater than zero;

[0056] If the remaining task acceptance capacity of the first partition is greater than zero, then the first task is assigned to the first partition, and the remaining task acceptance capacity of the first partition is reduced by one.

[0057] If the remaining task acceptance capacity of the first partition is zero, then the second partition with the second highest adaptation score of the first task is obtained from the task-partition adaptation matrix, and the remaining task acceptance capacity of the second partition is checked until a partition with a remaining task acceptance capacity greater than zero is found for the first task, and the partition is determined as the target energy sensing partition of the first task.

[0058] Furthermore, the step of determining a unique target energy-aware partition for each task to be assigned based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, using a two-dimensional assignment strategy, includes:

[0059] The task-partition fit matrix is ​​input to a hardware-implemented assignment decision circuit, which includes multiple parallel comparators and a cross switch matrix.

[0060] The multiple parallel comparators simultaneously compare the fitness scores of each task to be assigned relative to all energy-aware partitions. Each task to be assigned corresponds to one parallel comparator, and each parallel comparator outputs the highest fitness score corresponding to the task and the corresponding partition number.

[0061] The cross switch matrix receives the partition number output by the parallel comparator and the remaining task acceptance capacity counter value of each partition.

[0062] When at least two parallel comparators output the same partition number, the cross switch matrix arbitrates based on the remaining task acceptance capacity counter value of each partition, retains the connection corresponding to the partition with the highest remaining task acceptance capacity counter value, disconnects other connections pointing to the same partition, and triggers the parallel comparator corresponding to the disconnected connection to re-output the second highest fitness score and partition number.

[0063] When the partition numbers output by all parallel comparators are distinct and their respective remaining task acceptance capacity counter values ​​are all greater than zero, the cross-switch matrix establishes a mapping path between each task to be assigned and the energy-sensing partition corresponding to its output partition number.

[0064] This invention discloses an intelligent resource allocation method for energy-aware partitions, belonging to the field of computer architecture and operating system task scheduling technology. The method divides computing resources into multiple independent energy-aware partitions based on the processor cores. It then monitors the energy status parameters of each partition in real time. By parsing the instruction code stream of the tasks to be assigned, the proportion of arithmetic and logical instructions is extracted as instruction mixing features, and the address span of memory access instructions is analyzed to obtain cache access density features. Based on the energy status of the partitions and the computation and memory access characteristics of the tasks, a suitability score for the task relative to each partition is generated, comprehensively reflecting the energy matching degree and hardware resource matching degree. Based on the suitability score and the remaining task acceptance capacity of the partitions, a two-dimensional assignment strategy is used to dynamically map tasks to the core execution in the optimal energy-aware partition. This invention achieves fine-grained matching of computing resources and energy status, optimizing system energy utilization efficiency. Attached Figure Description

[0065] Figure 1 This is a flowchart illustrating the intelligent resource allocation method for intelligent sensing zone energy as claimed in an embodiment of the present invention.

[0066] Figure 2 This is a second flowchart of a method for intelligent resource allocation of energy for intelligent sensing zones, as claimed in an embodiment of the present invention.

[0067] Figure 3 This is a third flowchart of a method for intelligent resource allocation of energy for intelligent sensing zones, as claimed in an embodiment of the present invention.

[0068] Figure 4 This is a fourth flowchart of a smart resource allocation method for intelligent sensing partition energy, as claimed in an embodiment of the present invention. Detailed Implementation

[0069] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0070] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of those features. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications in the embodiments of this application, such as up, down, left, right, front, back, etc., are only used to explain the relative positional relationships and movements between components in a specific orientation as shown in the accompanying drawings. If the specific orientation changes, the directional indications will change accordingly. Furthermore, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0071] References to embodiments herein mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0072] According to the first embodiment of the present invention, referring to Figure 1 This invention claims protection for an intelligent resource allocation method for intelligent sensing zone energy, comprising:

[0073] S1, the physical computing resources of the computing system are divided into multiple energy-aware partitions according to their physical location and power supply topology, and each energy-aware partition includes a processor core and a corresponding local cache.

[0074] S2, monitor the real-time energy status parameters of each energy sensing partition in the current execution cycle, the real-time energy status parameters include the partition's instantaneous power consumption, partition temperature and partition's remaining power;

[0075] S3, parse the current queue of tasks to be assigned, and extract the instruction mixing features and cache access density features of each task to be assigned;

[0076] S4. Based on the real-time energy state parameters of each energy sensing partition and the instruction mixing characteristics and cache access density characteristics of each task to be assigned, generate a partition adaptation score for each task to be assigned.

[0077] S5. Based on the partition adaptation score, the task to be assigned is dynamically mapped to the processor core in the corresponding energy-aware partition for execution.

[0078] In this embodiment, the physical resource partitioning of the computing system is first required. This step is dynamically executed based on the hardware topology during system initialization or runtime. Specifically, the motherboard layout diagram or internal chip layout information of the computing system is obtained. This information can be obtained by reading firmware data on the system management bus, parsing the advanced configuration and power interface table, or directly reading the topology registers integrated inside the chip. Based on the physical coordinates of the processor cores, the power domain partitioning of the shared voltage regulation module, and the physical arrangement of the cache, physically adjacent and power-related processor cores and their associated cache levels are partitioned into the same energy-aware partition. For example, in a multi-core processor, there are usually multiple core clusters, each sharing a voltage regulation module and a slice of the last-level cache. Such a cluster can be partitioned into an independent energy-aware partition. After partitioning, the operating system scheduler maintains a partition mapping table, which records the identifier of each partition and the physical core bitmap contained in that partition, facilitating subsequent task assignment.

[0079] Next, during system operation, the energy status of each energy-sensing partition needs to be monitored in real time. This monitoring task is completed collaboratively by the underlying hardware monitoring unit and power management unit. Current and voltage sensing circuits are deployed on the power supply lines of each partition. These circuits collect the instantaneous current and voltage values ​​flowing through the partition at a fixed sampling frequency, such as 10,000 times per second. The collected analog signals are converted into digital quantities by an analog-to-digital converter, and the power management unit calculates the instantaneous power consumption, which is the product of current and voltage. Simultaneously, temperature-sensing diodes are integrated on or inside the substrate of each processor core. The forward voltage drop of these diodes changes linearly with temperature; by measuring the voltage drop, the real-time junction temperature of the core can be deduced. For partitions containing multiple cores, the maximum value of all core junction temperatures is taken as the temperature value of that partition to reflect the temperature status of the hottest spot. In addition, the power management unit maintains an independent power counter for each partition. This counter tracks the remaining available power allocated to the partition from the total battery capacity of the system in a coulomb measurement manner. At the end of each execution cycle, the power consumed is calculated based on the instantaneous power consumption of the partition and the cycle duration, and the corresponding value is subtracted from the power counter of the partition to obtain the latest remaining power of the partition.

[0080] Then, when the operating system receives a new task or needs to reschedule an existing task, the scheduler retrieves the task to be assigned from the task queue and performs static analysis on each task to extract its execution characteristics. First, it obtains the executable code segment of the task, which is usually done by accessing the code segment pointer in the task's process control block; it then performs an instruction scan on the code segment, parsing the opcode of each instruction to distinguish integer arithmetic instructions, floating-point arithmetic instructions, and memory access instructions; it counts the number of each type of instruction to obtain the number of integer arithmetic instructions, floating-point arithmetic instructions, and memory access instructions; based on these counts, it calculates the total number of arithmetic and logical instructions (ALU) summed up by integer and floating-point instructions, and uses the ratio of the total number of ALU instructions to the total number of instructions in the task as the instruction mixture feature, which reflects the task's dependence on computing units. Next, to analyze the cache access behavior of the task, the code segment is divided into basic blocks. A basic block refers to a sequence of instructions executed sequentially in the program, without branching in or out. Within each basic block, all memory access instructions are identified, and the memory address accessed by each instruction is recorded. By calculating the address difference between adjacent memory access instructions, the locality of memory access can be determined. If the address difference between two consecutive memory access instructions is very small, less than the size of a typical cache line (e.g., 64 bytes), it indicates that these two instructions are likely to access the same cache line, exhibiting high spatial locality. The number of all memory access instruction pairs whose address difference is less than the cache line size is counted, and then divided by the total number of memory access instructions in the task to obtain the cache access density characteristic. The larger this characteristic value, the more the task tends to densely access adjacent addresses when accessing memory, requiring higher cache capacity and hit rate.

[0081] Having obtained the real-time energy status of the partitions and the mixed instruction characteristics and cache access density characteristics of the tasks, the next step is to calculate a suitability score for each task relative to each partition. The suitability score is a comprehensive indicator that integrates energy status matching and hardware characteristic matching; the calculation process uses a weighted summation method. First, a first component is generated based on the relationship between the partition's temperature and a preset temperature threshold. For example, if the partition temperature is below the first temperature threshold, the first component contributes positively; if it is between the first and second thresholds, the contribution is small or zero; if it exceeds the second threshold, it contributes negatively, indicating that tasks should be avoided in overheated areas. Second, a second component is generated based on the relationship between the partition's remaining power and the task's estimated power consumption. The estimated power consumption can be estimated using the task's instruction complexity, such as based on historical statistics or instruction count. If the remaining power is sufficient, the second component is positive; if insufficient, it is negative. Third, a third component is generated based on the comparison between the partition's current instantaneous power consumption and its rated power consumption. The closer the instantaneous power consumption is to the rated power consumption, the lower the contribution; exceeding the rated power consumption results in a negative contribution. The fourth component is based on the matching degree between the task's instruction mixing characteristics and the partition's hardware computing unit type. For example, floating-point intensive tasks assigned to partitions supporting floating-point acceleration units will receive a higher positive score. The fifth component is based on the matching degree between the task's cache access density characteristics and the partition's cache capacity. High-density access tasks assigned to partitions with large-capacity last-level caches will receive a higher score. Finally, these five components are summed according to preset weights to obtain the task's fit score relative to the partition. The scores of all tasks to all partitions constitute a task-partition fit matrix.

[0082] The final step is to dynamically map tasks to processor cores in the corresponding energy-aware partitions based on their fitness scores. The scheduler first constructs a task-partition fitness matrix. Then, considering the limited processing capacity of each partition, a remaining task capacity needs to be set for each partition. This depends on the current task load count within the partition and the core occupancy rate. For example, if a partition has four cores, and each core can run at most one task simultaneously, then the maximum capacity of that partition is four, minus the number of currently assigned tasks, which is the remaining capacity. Next, the scheduler needs to solve a two-dimensional assignment problem: under the constraint of not exceeding the remaining capacity of each partition, select a partition for each task such that the sum of the fitness scores of all tasks is maximized. This can be implemented using a greedy algorithm or the Hungarian algorithm. A simple greedy implementation is as follows: sort all tasks in descending order of their highest fitness score, and sequentially assign each task to the partition with the highest score that still has capacity; if that partition is full, try the next highest score, and so on. After allocation, the task's execution context is migrated to the ready queue of any core contained in the target partition, awaiting core scheduling execution. This dynamic mapping enables energy-aware resource allocation, ensuring that the system can utilize the energy of each partition in a balanced manner when performing tasks, thus avoiding local overload.

[0083] Furthermore, referring to Figure 2 S1 includes:

[0084] Obtain the motherboard layout diagram of the computing system, which includes the physical coordinates of the processor core, the power supply domain division of the shared voltage regulation module, and the physical arrangement of the cache.

[0085] At least one processor core connected to the same voltage regulation module output and located within a preset physical proximity range, along with its dedicated L1 cache and shared L2 cache, are divided into an initial energy partition.

[0086] Detect whether there is a power shared path or physical substrate contact area between the initial energy partition and adjacent energy partitions;

[0087] If the power sharing path or physical substrate contact area exists, the two initial energy partitions with a sharing relationship will be merged into a final energy sensing partition.

[0088] Each of the energy sensing partitions is assigned a unique partition identifier, and a mapping relationship between the partition identifier and the physical core bitmap is established in the operating system scheduler.

[0089] In this embodiment, firstly, it is necessary to obtain the motherboard layout diagram or the internal layout diagram of the chip. This layout diagram can be obtained from the hardware description file during the system design phase or by reading the chip's topology registers at runtime. The layout diagram contains the physical coordinates of the processor cores, such as the X-axis and Y-axis coordinates in the chip grid, which reflect the actual position of the cores on the silicon wafer. Simultaneously, the layout diagram also contains power domain partitioning information, i.e., which cores share the output of the same voltage regulation module. The voltage regulation module is a power conversion unit that provides a stable voltage to the processor cores; multiple cores may be connected to the same voltage regulation module, thus sharing power lines. Furthermore, the layout diagram also shows the physical arrangement of the cache, including the storage locations of the L1 and L2 caches.

[0090] Based on the above information, the initial partitioning is first performed, identifying all processor cores connected to the same voltage regulation module output. At the same time, it is considered whether these cores are physically located within a preset proximity range. The preset proximity range is a distance threshold, such as Euclidean distance in millimeters, used to ensure low thermal coupling between cores or low power supply line loss. These cores, along with their dedicated L1 cache and shared L2 cache, are assigned to an initial energy partition. Each initial partition formed in this step is an independent power supply unit with an independent voltage regulation module and local cache.

[0091] Next, it is necessary to detect whether there are power-shared paths or physical substrate contact areas between adjacent initial energy partitions. Power-shared paths may manifest as two partitions connected by a power gating switch or a shared power grid, allowing the two partitions to share power when the power gating is on. Physical substrate contact areas refer to two partitions that are directly adjacent on the silicon substrate without a clear isolation zone, which can lead to easy heat conduction. These associations can be detected by querying the power management registers in the chip design or reading the adjacency relationships in the layout diagram. If a shared path or contact area is detected, the two initial partitions are merged into a larger final energy-sensing partition. The purpose of merging is to consider this coupling relationship in energy management and avoid energy distribution imbalance caused by actual physical coupling due to independent management.

[0092] Finally, each final energy-aware partition is assigned a unique partition identifier. This identifier can be a number or a string, used to uniquely identify the partition at the software level. In the operating system's scheduler, a mapping relationship needs to be established between the partition identifier and the physical core bitmap. The physical core bitmap is a bitmask, where each bit represents a physical core, and a bit set to 1 indicates that the core belongs to that partition. Thus, when the scheduler decides to assign a task to a partition, it can find all the cores contained in that partition by looking up the mapping relationship, and then assign the task to one of those cores for execution. Through this series of steps, the partitioning of energy-aware partitions is ensured to consider both power supply independence and physical thermal coupling, laying a solid hardware foundation for subsequent energy-aware scheduling.

[0093] Further, S2 includes:

[0094] A current sensing circuit and a voltage sensing circuit are deployed at the power supply inlet of each energy sensing zone. The instantaneous current value and the instantaneous voltage value flowing through the zone are collected by the current sensing circuit and the voltage sensing circuit at a fixed sampling frequency. The product of the instantaneous current value and the instantaneous voltage value is determined as the instantaneous power consumption of the zone.

[0095] Temperature sensing diodes are installed on the substrate surface of the processor cores contained in each energy sensing partition. The real-time junction temperature of the core is obtained by the change of the pn junction voltage of the temperature sensing diodes. The highest real-time junction temperature of all cores in the partition is taken as the partition temperature of the partition.

[0096] In the power management unit of the computing system, an independent power counter is maintained for each energy sensing partition. The power counter records the remaining available power allocated to the partition from the total system battery capacity in a coulomb measurement manner. At the end of each execution cycle, the power counter of the partition is decremented and updated according to the instantaneous power consumption and cycle duration to obtain the remaining power of the partition.

[0097] In this embodiment, current sensing circuits and voltage sensing circuits are deployed at the power supply inlet of each energy sensing zone. The current sensing circuit typically uses a series small-resistance sampling resistor and a differential amplifier to convert the current flowing through the zone into a voltage signal. The voltage sensing circuit directly obtains the supply voltage through a high-impedance voltage divider network. These circuits operate at a fixed sampling frequency, such as 10,000 times per second, to ensure that instantaneous changes in power consumption can be captured. After the analog signal is converted into a digital quantity by an analog-to-digital converter, it is read by the power management unit. The power management unit contains multiple channels of registers to store the instantaneous current and voltage values ​​of each zone. By multiplying the current value and the voltage value, the instantaneous power consumption of the zone can be obtained. This instantaneous power consumption value is recorded in a dedicated register of the power management unit for the scheduler to query at any time.

[0098] Secondly, temperature sensing diodes are installed on the substrate surface of the processor cores contained in each energy-sensing partition. The temperature sensing diodes typically utilize the characteristic that the forward voltage drop of the pn junction changes linearly with temperature. By applying a constant bias current and measuring the voltage across its terminals, the junction temperature can be calculated. Each core has an independent temperature sensing circuit that converts the measured temperature value into a digital value and stores it in the model-specific register of that core. For a partition containing multiple cores, the scheduler reads the temperature register values ​​of all cores in that partition and takes the maximum value as the partition temperature. The reason for this is that the thermal management of the partition should be based on the hottest spot to avoid reliability issues caused by excessively high local temperatures.

[0099] Finally, in the power management unit of the computing system, an independent power counter is maintained for each energy sensing zone. The power counter is essentially an accumulator register, and its initial value is set by the system firmware at startup based on the total battery capacity and the preset weight allocation of each zone. During operation, the power counter is updated in a coulomb measurement manner. Coulomb measurement refers to calculating the consumed power by integrating the current over time. At the end of each execution cycle, the power management unit multiplies the instantaneous power consumption measured in that cycle by the cycle length, i.e., the power consumption integrated over time, to obtain the power consumption value for that cycle. Then, this consumption value is subtracted from the power counter of that zone to update the remaining power. In addition, the power counter can also be implemented through a hardware accumulator. The current value output by the current sensing circuit is directly input into the accumulator. The accumulator accumulates once in each clock cycle, and the accumulated result is the total charge consumed. Combined with the voltage, the energy consumption is calculated. In this way, the remaining power of each zone can always reflect the latest energy usage. These three parameters—instantaneous power consumption, zone temperature, and remaining power of the zone—together constitute the real-time energy status of the zone, providing a key basis for scheduling decisions.

[0100] Further, S3 includes:

[0101] For each task in the current task queue to be assigned, obtain its executable code segment, perform static instruction scanning on the executable code segment, and count the first number of integer arithmetic instructions, the second number of floating-point arithmetic instructions, and the third number of memory access instructions contained in the executable code segment.

[0102] Based on the first number of integer arithmetic instructions and the second number of floating-point arithmetic instructions, the total number of arithmetic logic instructions is calculated, and the ratio of the total number of arithmetic logic instructions to the total number of instructions in the task is determined as the instruction mixing characteristic of the task.

[0103] The executable code segment is divided into basic blocks, the memory access instructions contained in each basic block are identified, and the memory address accessed by each memory access instruction is analyzed. The address difference between adjacent memory access instructions is calculated based on the address access span of the memory access instructions. The address difference is cumulatively distributed and analyzed to count the number of memory access instruction pairs whose address difference is less than the preset cache line size. The ratio of the number of memory access instruction pairs to the total number of memory access instructions in the task is determined as the cache access density feature of the task.

[0104] In this embodiment, for each task in the current task queue to be assigned, the scheduler needs to access the task's process control block to obtain the starting address and length of the executable code segment in memory. Then, the scheduler or a dedicated static analysis module scans the code segment instruction by instruction. During the scan, based on the opcode field of the instruction, integer arithmetic instructions such as addition, subtraction, and logical operations, floating-point arithmetic instructions such as floating-point addition, subtraction, multiplication, and division, transcendental functions, and memory access instructions such as load, store, and prefetch are identified. The number of these three types of instructions is counted and recorded as the number of integer instructions, the number of floating-point instructions, and the number of memory access instructions, respectively. The total number of instructions is the total number of instructions in the code segment. Based on the number of integer instructions and the number of floating-point instructions, the total number of arithmetic and logical instructions is calculated, which is the sum of the two. Then, the total number of arithmetic and logical instructions is divided by the total number of instructions in the task to obtain the proportion of arithmetic and logical instructions. This ratio is the instruction mixing characteristic. The higher the characteristic value, the more computation-oriented the task is, and the greater the demand on the processor core's arithmetic units; conversely, it may be more control-flow or memory-access oriented.

[0105] Next, cache access density features need to be extracted. This analysis is also based on the executable code segment. First, the code segment is divided into basic blocks. The division of basic blocks can be achieved by analyzing control flow instructions such as branches, jumps, calls, and returns. Starting from the code segment entry point, instructions are scanned sequentially. When a control flow instruction is encountered, the instruction ends the current basic block, and a new basic block begins at its target address. After the division, several basic blocks are obtained. For each basic block, all memory access instructions contained therein are identified, and the memory address accessed by each memory access instruction is recorded. It should be noted that since static analysis cannot determine dynamic address values, relative addresses or offsets are usually used for approximation. For example, the offset of the effective address can be calculated based on the base address register and the offset. For each memory access instruction, the difference between the memory address it accesses and the address of the previous memory access instruction is analyzed, and the absolute value of this address difference is calculated. Then, the number of all memory access instruction pairs whose address difference is less than the preset cache line size is counted. The preset cache line size is a basic unit of hardware cache, such as 64 bytes. This statistic reflects whether a task tends to frequently access the same cache line during execution, i.e., the degree of spatial locality. Finally, dividing this statistic by the total number of memory access instructions in the task (note that this is the total number of memory access instructions, not the number of instruction pairs) yields the cache access density feature. The higher this feature value, the more intensive the task's memory access pattern, tending to repeatedly access within a local address range, requiring higher cache capacity and hit rate; conversely, a lower value indicates a sparser memory access pattern, potentially frequently crossing cache lines, leading to a higher cache miss rate. Through these two features, the scheduler can understand the task's demand for computing and cache resources.

[0106] Furthermore, referring to Figure 3 S4 includes:

[0107] For each task in the task queue to be assigned, calculate the fit score between the task and each energy sensing partition.

[0108] In the compatibility score calculation between a task and a partition, a first component is generated based on the comparison between the partition temperature and a preset temperature threshold, a second component is generated based on the comparison between the remaining power of the partition and the estimated power consumption of the task, and a third component is generated based on the comparison between the instantaneous power consumption of the partition and the rated power consumption of the partition.

[0109] A fourth component is generated based on the degree of matching between the instruction mixing characteristics of the task and the hardware computing unit type of the partition, and a fifth component is generated based on the degree of matching between the cache access density characteristics of the task and the cache capacity of the partition.

[0110] The first component, the second component, the third component, the fourth component, and the fifth component are weighted and accumulated, and the result of the weighted accumulation is used as the fitness score of the task relative to the partition.

[0111] In this embodiment, the fit score is a comprehensive indicator, which is a weighted sum of multiple components. In practice, the scheduler maintains a weight table to store the preset weight values ​​of each component. For each combination of task and partition, the following calculation process needs to be performed.

[0112] First, a first component is generated based on the comparison between the partition's temperature and a preset temperature threshold. Two preset temperature thresholds can be set, such as a first temperature threshold and a second temperature threshold, where the first threshold is lower than the second threshold. If the partition temperature is lower than the first threshold, it indicates the partition is in a low-temperature state, ideal for accepting new tasks; therefore, the first component is assigned a high positive value, such as the maximum value of the weighting coefficient. If the partition temperature is between the first and second thresholds, it indicates the partition is in a mild state, capable of accepting tasks but not too many; therefore, the first component is assigned a small positive value or zero. If the partition temperature is higher than the second threshold, it indicates the partition is overheated and tasks should be avoided to prevent thermal runaway; therefore, the first component is assigned a large negative value, equivalent to a penalty.

[0113] Secondly, a second component is generated based on the comparison between the remaining power of the partition and the estimated power consumption of the task. The estimated power consumption of the task can be estimated by combining the task's instruction mixing characteristics and cache access density characteristics with a historical power consumption statistical model. For example, an estimated power value can be calculated based on the task type and the number of instructions. The remaining power of the partition is compared with this estimated power. If the remaining power is much greater than the estimated power, it means that the partition has sufficient power and can safely allocate tasks. The second component is assigned a positive value. If the remaining power is equal to or slightly less than the estimated power, the second component is assigned a zero or a small positive value. If the remaining power is significantly less than the estimated power, it means that the partition's power may not be able to support the complete execution of the task and should be avoided. The second component is assigned a negative value.

[0114] Third, a third component is generated based on the comparison between the instantaneous power consumption and the rated power consumption of the partition. The rated power consumption of the partition refers to the upper limit of long-term stable power consumption allowed by the hardware design of the partition. If the instantaneous power consumption is much lower than the rated power consumption, it means that the partition still has a large power margin and can handle tasks, so the third component is assigned a positive value. If the instantaneous power consumption is close to the rated power consumption, it means that the partition is close to full load, and further task allocation may lead to excessive power consumption, triggering frequency reduction or current limiting. Therefore, the third component is assigned a zero or negative value. If the instantaneous power consumption has exceeded the rated power consumption, the third component is assigned a large negative value.

[0115] The fourth component is generated based on the degree of matching between the instruction mixing characteristics of the task and the hardware computing unit type of the partition. The hardware computing unit type refers to the instruction set extensions supported by the processor core within the partition, such as floating-point acceleration units, single instruction multiple data units, etc. For example, if the instruction mixing characteristics show that the task contains a large number of floating-point operations and the partition supports floating-point acceleration, then the fourth component is positive; if the partition does not support floating-point acceleration, it may be negative.

[0116] The fifth component is generated based on the matching degree between the cache access density characteristics of the task and the cache capacity of the partition. The cache capacity mainly refers to the size of the last-level cache shared within the partition. If the task has a high cache access density and the partition has a large cache capacity, then the fifth component is positive; conversely, if the task has a high density and the partition has a small cache, then it may be negative.

[0117] Finally, each of the five components is multiplied by its corresponding preset weight coefficient, and then summed to obtain the suitability score of the task relative to the partition. The weight coefficients can be dynamically adjusted according to the system design goals. For example, when pursuing performance, the weights of the fourth and fifth components are increased, and when pursuing battery life, the weights of the first and second components are increased. In this way, the suitability score comprehensively reflects the energy state and hardware compatibility, providing a quantitative basis for subsequent task assignment.

[0118] Furthermore, generating the fourth component based on the degree of matching between the instruction mixing characteristics of the task and the hardware computing unit type of the partition includes:

[0119] Obtain the instruction set architecture extension identifiers supported by the processor cores within the energy-aware partition. The instruction set architecture extension identifiers include single instruction multiple data extension identifiers, advanced vector extension identifiers, and floating-point acceleration unit identifiers.

[0120] The degree of dependence of the task on floating-point computing resources and the degree of dependence on vector computing resources are determined based on the instruction mixing characteristics of the task.

[0121] If the task's dependence on floating-point computing resources exceeds the floating-point dependence threshold and the instruction set architecture extension identifier contains the floating-point acceleration unit identifier, then the fourth component is assigned a first positive value.

[0122] If the task's dependence on vector computing resources exceeds the vector dependence threshold and the instruction set architecture extension identifier contains the advanced vector extension identifier, then the fourth component is assigned a second positive value.

[0123] If the task's dependence on integer operation resources exceeds the integer dependence threshold, the fourth component will be assigned a third positive value, regardless of the value of the instruction set architecture extension identifier.

[0124] If the task's dependence on floating-point computing resources exceeds the floating-point dependence threshold, but the instruction set architecture extension identifier does not contain the floating-point acceleration unit identifier, then the fourth component is assigned a first negative value.

[0125] In this embodiment, the scheduler first needs to obtain the instruction set architecture extension identifiers supported by the processor cores in each energy-aware partition. These identifiers are usually obtained by reading the CPUID instruction or architecture configuration register in the processor, such as the Single Instruction Multiple Data Extension identifier, the Advanced Vector Extension identifier, and the Floating Point Acceleration Unit identifier. These identifiers indicate whether the core has specific hardware acceleration units, such as vector processing units, floating point arithmetic units, etc.

[0126] Simultaneously, the scheduler needs to parse the task's dependency on various computing resources from the instruction mixture characteristics. The instruction mixture characteristic itself is a ratio, but it can be further broken down into three sub-features: the proportion of floating-point instructions, the proportion of vector operation instructions, and the proportion of integer operation instructions. Vector operation instructions typically refer to Single Instruction Multiple Data Stream (SID) instructions, such as Advanced Vector Extensions (ADLs). If the proportion of floating-point instructions exceeds a preset floating-point dependency threshold, the task is considered to have a high dependency on floating-point computing resources; similarly, if the proportion of vector operation instructions exceeds a vector dependency threshold, the task is considered to have a high dependency on vector computing resources; and if the proportion of integer operation instructions exceeds an integer dependency threshold, the task is considered to have a high dependency on integer computing resources. These thresholds can be set according to the actual application scenario. For example, a floating-point dependency threshold of 0.3 means that if more than 30% of the instructions in a task are floating-point operations, it is considered floating-point intensive.

[0127] Based on the above judgment, the assignment rules for the fourth component are as follows:

[0128] If the task is highly dependent on floating-point computing resources, and the instruction set architecture extension identifier of the partition contains a floating-point acceleration unit identifier, it means that the hardware of the partition can effectively accelerate floating-point operations. In this case, the fourth component is assigned a large first positive value, and the size of the first positive value can be set according to the system's emphasis on performance.

[0129] If the task is highly dependent on vector computing resources, and the partition's instruction set architecture extension identifier includes an advanced vector extension identifier, it means that the partition's vector processing unit can accelerate such instructions. In this case, the fourth component is assigned a second positive value, which can be equivalent to or slightly different from the first positive value, depending on the design.

[0130] If a task is highly dependent on integer operation resources, integer operations are a fundamental capability of all cores, regardless of whether the partition has a special extended identifier. Therefore, the fourth component is assigned a third positive value, which is usually smaller than the first two positive values, because the acceleration space for integer operations is relatively small.

[0131] If a task is highly dependent on floating-point computing resources, but the instruction set architecture extension identifier of the partition does not include a floating-point acceleration unit identifier, it means that the partition lacks hardware floating-point acceleration. The task will rely entirely on software simulation or basic floating-point units for execution, which is inefficient. In this case, the fourth component is assigned a first negative value to indicate a penalty.

[0132] In other cases, such as when the task blending features are not obvious or the degree of dependence does not exceed the threshold, the fourth component can be assigned a value of zero or a basic positive value.

[0133] This refined assignment allows the suitability score to accurately reflect the matching degree of the task with the hardware acceleration unit, thereby scheduling suitable tasks to partitions with corresponding acceleration capabilities, improving execution efficiency and avoiding energy waste caused by hardware mismatch.

[0134] Furthermore, the step of generating a fifth component based on the matching degree between the cache access density characteristics of the task and the cache capacity of the partition includes:

[0135] Obtain the capacity value of the last-level cache shared within this energy sensing partition;

[0136] Based on the numerical range of the cache access density characteristics of the task, the task is classified into high-density access type, medium-density access type, or low-density access type.

[0137] If the task is a high-density access type and the capacity value of the last-level cache is greater than the first cache capacity threshold, then the fifth component is assigned a first positive value.

[0138] If the task is of medium-density access type and the capacity value of the last level cache is between the first cache capacity threshold and the second cache capacity threshold, then the fifth component is assigned a second positive value;

[0139] If the task is a low-density access type and the capacity value of the last level cache is less than the second cache capacity threshold, then the fifth component is assigned a third positive value.

[0140] If the task is a high-density access type and the capacity value of the last-level cache is less than the second cache capacity threshold, then the fifth component is assigned a first negative value.

[0141] In this embodiment, it is necessary to obtain the capacity value of the last-level cache shared within each energy-aware partition. The last-level cache is usually a cache shared by all cores, and its capacity can be obtained by reading hardware registers or parsing the system device tree. For example, in a typical processor, the last-level cache may be divided into multiple slices, and each partition contains one or more slices. Therefore, the cache capacity corresponding to the partition is the sum of the capacities of these slices.

[0142] The cache access density feature of a task is a value between 0 and 1. Based on the range of this value, tasks can be divided into different access types. Specifically, two thresholds are preset, such as a first density threshold and a second density threshold, where the first density threshold is less than the second density threshold. If the cache access density feature of a task is greater than the second density threshold, it is classified as a high-density access type, indicating that the task's memory access pattern is very localized and the same cache line is frequently accessed. If the cache access density feature of a task is between the first density threshold and the second density threshold, it is classified as a medium-density access type. If it is less than the first density threshold, it is classified as a low-density access type, indicating that the memory access pattern is sparse and the locality is poor.

[0143] At the same time, two thresholds are preset for cache capacity, such as a first cache capacity threshold and a second cache capacity threshold. The first cache capacity threshold is greater than the second cache capacity threshold. The first cache capacity threshold can be set to the size of a typical large-capacity cache, such as 8 megabytes; the second cache capacity threshold is set to the size of a typical small-capacity cache, such as 2 megabytes.

[0144] Based on the above classification, the assignment rules for the fifth component are as follows:

[0145] If the task is a high-density access type and the capacity of the last level cache of the partition is greater than the first cache capacity threshold, it means that the large-capacity cache can effectively accommodate the frequent access of high-density tasks and improve the cache hit rate. In this case, the fifth component is assigned a large first positive value.

[0146] If the task is a medium-density access type, and the last-level cache capacity of the partition is between the first cache capacity threshold and the second cache capacity threshold, it means that the medium-capacity cache matches the medium-density access, which is neither excessive nor insufficient. In this case, the fifth component is assigned the second positive value.

[0147] If the task is a low-density access type and the last-level cache capacity of the partition is less than the second cache capacity threshold, it means that a small-capacity cache is sufficient to handle sparse access and there is no need to waste large-capacity cache resources. In this case, the fifth component is assigned the third positive value.

[0148] If the task is a high-density access type, but the last-level cache capacity of the partition is less than the second cache capacity threshold, it means that the small-capacity cache cannot meet the high-density access requirements, which will lead to a large number of cache misses, increase memory access energy consumption and latency. In this case, the fifth component is assigned the first negative value.

[0149] For other combinations, such as high-density access with medium-capacity cache, or medium-density access with small-capacity cache, appropriate positive or zero values ​​can be assigned based on the specific matching degree to avoid penalties or provide certain rewards.

[0150] By matching cache density with capacity, this ensures that cache resources are used efficiently, avoiding performance degradation and energy waste caused by allocating high-density tasks to small cache partitions, and also avoiding resource idleness caused by allocating low-density tasks to large cache partitions.

[0151] Furthermore, referring to Figure 4 S5 includes:

[0152] Based on the fit score of each task to be assigned relative to each energy-aware partition, a task-partition fit matrix is ​​constructed. The row index of the task-partition fit matrix corresponds to the identifier of the task to be assigned, the column index corresponds to the identifier of the energy-aware partition, and the matrix elements are the corresponding fit scores.

[0153] Scan the task-partition fit matrix to initially determine one or more candidate energy-aware partitions for each task to be assigned. The candidate energy-aware partitions refer to partitions with a fit score greater than a preset admission threshold.

[0154] For each energy-sensing partition, obtain the current task load count and the utilization rate of each processor core in that partition, and determine the remaining task acceptance capacity of that partition based on the task load count and the utilization rate of each processor core.

[0155] Based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, a two-dimensional assignment strategy is adopted to determine a unique target energy-aware partition for each task to be assigned. The goal of the two-dimensional assignment strategy is to maximize the sum of fit scores of all assigned tasks under the constraint of not exceeding the remaining task acceptance capacity of each partition.

[0156] Based on the determination result of the two-dimensional assignment strategy, the execution context of each task to be assigned is migrated to the ready queue of the processor core contained in its target energy-aware partition.

[0157] In this embodiment, the scheduler first creates a two-dimensional matrix based on the number of all tasks to be assigned and the number of all energy-aware partitions. The rows of the matrix correspond to the unique identifier of each task to be assigned, and the columns correspond to the unique identifier of each energy-aware partition. Each element in the matrix is ​​the calculated fitness score of the corresponding task relative to the corresponding partition. This matrix is ​​called the task-partition fitness matrix.

[0158] Next, the scheduler scans this matrix to initially determine one or more candidate energy-aware partitions for each task. The determination of candidate partitions is based on a preset admission threshold. For each task, all partitions are traversed to find those partitions whose fitness scores are greater than or equal to the admission threshold. These partitions are added to the candidate partition list for that task. If a task does not have any partitions with scores exceeding the threshold, the threshold can be appropriately lowered or the partition with the highest score can be directly selected as a candidate to ensure that each task has at least one candidate partition.

[0159] Then, for each energy-aware partition, it is necessary to obtain its current task load count and the utilization rate of each processor core. The task load count refers to the number of tasks queued in the partition's ready queue waiting to be executed. The utilization rate of each core can be obtained by reading the busy time statistics of each core maintained by the operating system. Based on this information, the remaining task acceptance capacity of the partition can be determined. The remaining task acceptance capacity refers to how many more new tasks the partition can accept without significantly affecting performance. For example, a remaining capacity value can be calculated based on the number of cores in the partition, the concurrency capability of each core (such as whether it supports hyper-threading), and the current utilization rate. If the utilization rate of a core is close to 100%, its acceptance capacity is low; conversely, if there are many idle cores, the acceptance capacity is high. A simple method is: the remaining task acceptance capacity of the partition equals the total number of cores in the partition multiplied by the maximum number of tasks per core (such as 1 or 2) minus the current task load count; however, a more refined model can be weighted by combining the utilization rate.

[0160] Based on the task-partition fitness matrix and the remaining task capacity of each partition, the scheduler needs to adopt a two-dimensional assignment strategy to determine a unique target energy-aware partition for each task to be assigned. The goal of the two-dimensional assignment strategy is to maximize the sum of fitness scores of all assigned tasks while satisfying the constraint of the remaining capacity of each partition. This is a typical combinatorial optimization problem. In practical systems, a greedy algorithm can be used to reduce computational overhead. A feasible greedy strategy is as follows: sort tasks according to their highest fitness score, and assign the task with the highest score first. For the current task, select the partition with the highest score in its candidate partition list that still has remaining capacity, assign the task to that partition, and decrement the remaining capacity of that partition by one. If the partition has no capacity, try the next highest score, and so on. If all candidate partitions are full, it may be necessary to downgrade, for example, by selecting a partition with capacity but a lower score from the partitions with the highest global score, or by temporarily increasing the partition's capacity, such as through task preemption. Finally, a target partition is determined for each task.

[0161] Finally, based on the assignment results, the scheduler moves the execution context of each task to be assigned, including the program counter, register state, memory mapping, etc., from the current core to the ready queue of a processor core contained in the target energy-aware partition, if the task is migrated from another core. The migration process involves moving the task control block from one core's queue to another core's queue and updating the relevant scheduling data structures. Subsequently, when the target core is idle, the task will be taken from its ready queue for execution. In this way, the task is dynamically mapped to the partition with the best matching energy state for execution.

[0162] Furthermore, the step of determining a unique target energy-aware partition for each task to be assigned based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, using a two-dimensional assignment strategy, includes:

[0163] All tasks to be assigned are sorted in descending order of suitability score to generate a task processing sequence;

[0164] All energy-sensing partitions are sorted in ascending order of remaining task capacity to generate a partition processing sequence;

[0165] Extract the first task that appears first in the task processing sequence, and obtain the first partition with the highest adaptation score for the first task based on the task-partition adaptation matrix.

[0166] Check if the remaining task acceptance capacity of the first partition is greater than zero;

[0167] If the remaining task acceptance capacity of the first partition is greater than zero, then the first task is assigned to the first partition, and the remaining task acceptance capacity of the first partition is reduced by one.

[0168] If the remaining task acceptance capacity of the first partition is zero, then the second partition with the second highest adaptation score of the first task is obtained from the task-partition adaptation matrix, and the remaining task acceptance capacity of the second partition is checked until a partition with a remaining task acceptance capacity greater than zero is found for the first task, and the partition is determined as the target energy sensing partition of the first task.

[0169] In this embodiment, the scheduler sorts all tasks to be assigned in descending order of fit score to generate a task processing sequence. Here, fit score refers to the highest score of each task relative to its best candidate partition. However, for the sake of fairness in sorting, the maximum value of all scores for each task or the average score can also be used. The purpose of sorting is to give priority to the best matching partition and prevent low-scoring tasks from taking the opportunity of high-scoring tasks.

[0170] Meanwhile, the scheduler sorts all energy-aware partitions in order of their remaining task acceptance capacity from low to high, generating a partition processing sequence. The purpose of this sorting is to prioritize partitions with tight acceptance capacity during the allocation process, ensuring that they can be fully utilized. However, this embodiment does not directly use this partition sequence, but instead adopts another method: when allocating each task, it directly checks whether the partition with the highest score has acceptance capacity. Therefore, in actual implementation, it may not be necessary to explicitly sort the partitions, but the partition sequence may be used for subsequent backup options.

[0171] Next, the first task in the task processing sequence is retrieved. Based on the task-partition fit matrix, the first partition with the highest fit score for this task is obtained. Then, it is checked whether the remaining task acceptance capacity of the first partition is greater than zero. If it is greater than zero, it means that the first partition still has the capacity to accept new tasks, so this first task is assigned to the first partition. After assignment, the remaining task acceptance capacity of the first partition is reduced by one, and the task is removed from the waiting queue. The task-partition fit matrix is ​​updated, for example, by deleting or marking the row containing the assigned task as assigned, and then the next task is processed.

[0172] If the remaining task acceptance capacity of the first partition is zero, it means that the first partition is full and cannot accept any more tasks. At this time, the second partition with the second highest suitability score for the task is obtained from the task-partition suitability matrix. Then, the remaining task acceptance capacity of the second partition is checked. If the second partition has the capacity, the task is assigned to the second partition and updated. If the second partition also has no capacity, the third highest score is tried until a partition with the capacity is found. If no partition has the capacity after traversing all candidate partitions, it may mean that the system resources are insufficient and other measures need to be taken, such as waiting for the existing task to complete, forcibly preempting, or raising the acceptance threshold.

[0173] This strategy of trying the highest-rated partition for each task is simple and efficient, ensuring that each task is assigned to the highest-rated available partition. However, it may not be globally optimal, because the first task assigned may occupy a partition that was originally more suitable for the later task, causing the later task to choose a worse partition. However, in actual operation, since the number of tasks and partitions is limited, this greedy strategy can usually achieve good results and has extremely low computational overhead, making it suitable for real-time execution in the operating system.

[0174] Furthermore, the step of determining a unique target energy-aware partition for each task to be assigned based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, using a two-dimensional assignment strategy, includes:

[0175] The task-partition fit matrix is ​​input to a hardware-implemented assignment decision circuit, which includes multiple parallel comparators and a cross switch matrix.

[0176] The multiple parallel comparators simultaneously compare the fitness scores of each task to be assigned relative to all energy-aware partitions. Each task to be assigned corresponds to one parallel comparator, and each parallel comparator outputs the highest fitness score corresponding to the task and the corresponding partition number.

[0177] The cross switch matrix receives the partition number output by the parallel comparator and the remaining task acceptance capacity counter value of each partition.

[0178] When at least two parallel comparators output the same partition number, the cross switch matrix arbitrates based on the remaining task acceptance capacity counter value of each partition, retains the connection corresponding to the partition with the highest remaining task acceptance capacity counter value, disconnects other connections pointing to the same partition, and triggers the parallel comparator corresponding to the disconnected connection to re-output the second highest fitness score and partition number.

[0179] When the partition numbers output by all parallel comparators are distinct and their respective remaining task acceptance capacity counter values ​​are all greater than zero, the cross-switch matrix establishes a mapping path between each task to be assigned and the energy-sensing partition corresponding to its output partition number.

[0180] In this embodiment, the task-partition fit matrix is ​​input to a hardware-implemented assignment decision circuit. This circuit can be a dedicated hardware accelerator, integrated inside the processor or as a standalone peripheral. Its core includes multiple parallel comparators and a cross switch matrix.

[0181] First, each task to be assigned corresponds to a parallel comparator. The number of parallel comparators is equal to the number of tasks to be assigned. They work simultaneously. Each parallel comparator receives the fitness score of the task relative to all energy-aware partitions as input. The comparator finds the maximum value among the input scores through comparison logic and outputs this maximum value and the corresponding partition number. Therefore, after one round of parallel comparison, the highest fitness score and the corresponding partition number of each task are generated simultaneously.

[0182] These outputs are fed into a cross-switching matrix, a multiplexing network that can establish connections from any input to any output. The cross-switching matrix is ​​also connected to the remaining task acceptance capacity counters of each partition. These counters record the remaining acceptance capacity value of each partition in real time and can be read by the cross-switching matrix.

[0183] When at least two parallel comparators output the same partition number, indicating multiple tasks are vying for the same partition, the cross-switch matrix needs to arbitrate based on the remaining task acceptance capacity counter value of each partition. Specifically, it checks the remaining acceptance capacity value of the conflicting partition. If the remaining acceptance capacity of the partition is greater than or equal to the number of conflicting tasks, all tasks can be accepted. However, the acceptance capacity is usually limited, so it is necessary to decide which connections to retain. The cross-switch matrix compares the comparator outputs corresponding to all tasks vying for the same partition. However, since the partition numbers are the same, they cannot be directly compared. Therefore, it may adopt a priority strategy, such as deciding which to retain based on the score of each task on that partition or the priority of the task itself. In this embodiment, the connection corresponding to the partition with the highest remaining task acceptance capacity counter value is retained. In reality, it should be based on the partition's acceptance capacity to retain a limited number of connections. A more reasonable explanation is that the cross-switch matrix retains a corresponding number of connections for each partition based on its remaining acceptance capacity. That is, if two tasks are vying for a partition with an acceptance capacity of 1, only one connection is retained, and the other connection needs to be disconnected and a reselection is triggered.

[0184] When the connection is broken, the corresponding parallel comparator is triggered to recalculate the second-highest fitness score and partition number. The calculation of the second-highest score can be achieved by masking the selected highest-scoring partition inside the comparator. Then the new result is sent to the cross-switch matrix again for arbitration. This process is repeated until the partition numbers output by all parallel comparators are different and the remaining admission capacity counter value corresponding to each partition is greater than zero, that is, the number of tasks assigned to each partition does not exceed its admission capacity. At this time, all conflicts have been resolved. The cross-switch matrix establishes a mapping path between each task to be assigned and the energy-sensing partition corresponding to its output partition number. These mapping paths can be directly sent to the task distribution unit in the form of electrical signals to trigger the physical migration of the task.

[0185] With this hardware parallel implementation, the task assignment process can be completed within a few clock cycles, which greatly improves scheduling efficiency. It is particularly suitable for scenarios involving the creation and destruction of high-frequency tasks, such as dynamic load management in real-time systems. The hardware circuit avoids the looping and sorting overhead of software algorithms, realizing true real-time energy-aware scheduling.

[0186] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0187] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units. The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0188] The specific embodiments of the invention have been described in detail above, but they are only examples, and this application is not limited to the specific embodiments described above. For those skilled in the art, any equivalent modifications or substitutions to the invention are also within the scope of this application. Therefore, all equivalent changes, modifications, and improvements made without departing from the spirit and principles of this application should be covered within the scope of this application.

Claims

1. A method for intelligent resource allocation of energy in intelligent sensing zones, characterized in that, include: S1, the physical computing resources of the computing system are divided into multiple energy-aware partitions according to their physical location and power supply topology, and each energy-aware partition includes a processor core and a corresponding local cache. S2, monitor the real-time energy status parameters of each energy sensing partition in the current execution cycle, the real-time energy status parameters include the partition's instantaneous power consumption, partition temperature and partition's remaining power; S3, parse the current queue of tasks to be assigned, and extract the instruction mixing features and cache access density features of each task to be assigned; S4. Based on the real-time energy state parameters of each energy sensing partition and the instruction mixing characteristics and cache access density characteristics of each task to be assigned, generate a partition adaptation score for each task to be assigned. S5. Based on the partition adaptation score, the task to be assigned is dynamically mapped to the processor core in the corresponding energy-aware partition for execution.

2. The method according to claim 1, characterized in that, S1 includes: Obtain the motherboard layout diagram of the computing system, which includes the physical coordinates of the processor core, the power supply domain division of the shared voltage regulation module, and the physical arrangement of the cache. At least one processor core connected to the same voltage regulation module output and located within a preset physical proximity range, along with its dedicated L1 cache and shared L2 cache, are divided into an initial energy partition. Detect whether there is a power shared path or physical substrate contact area between the initial energy partition and adjacent energy partitions; If the power sharing path or physical substrate contact area exists, the two initial energy partitions with a sharing relationship will be merged into a final energy sensing partition. Each of the energy sensing partitions is assigned a unique partition identifier, and a mapping relationship between the partition identifier and the physical core bitmap is established in the operating system scheduler.

3. The method according to claim 1, characterized in that, The S2 includes: A current sensing circuit and a voltage sensing circuit are deployed at the power supply inlet of each energy sensing zone. The instantaneous current value and the instantaneous voltage value flowing through the zone are collected by the current sensing circuit and the voltage sensing circuit at a fixed sampling frequency. The product of the instantaneous current value and the instantaneous voltage value is determined as the instantaneous power consumption of the zone. Temperature sensing diodes are installed on the substrate surface of the processor cores contained in each energy sensing partition. The real-time junction temperature of the core is obtained by the change of the pn junction voltage of the temperature sensing diodes. The highest real-time junction temperature of all cores in the partition is taken as the partition temperature of the partition. In the power management unit of the computing system, an independent power counter is maintained for each energy sensing partition. The power counter records the remaining available power allocated to the partition from the total system battery capacity in a coulomb measurement manner. At the end of each execution cycle, the power counter of the partition is decremented and updated according to the instantaneous power consumption and cycle duration to obtain the remaining power of the partition.

4. The method according to claim 1, characterized in that, The S3 includes: For each task in the current task queue to be assigned, obtain its executable code segment, perform static instruction scanning on the executable code segment, and count the first number of integer arithmetic instructions, the second number of floating-point arithmetic instructions, and the third number of memory access instructions contained in the executable code segment. Based on the first number of integer arithmetic instructions and the second number of floating-point arithmetic instructions, the total number of arithmetic logic instructions is calculated, and the ratio of the total number of arithmetic logic instructions to the total number of instructions in the task is determined as the instruction mixing characteristic of the task. The executable code segment is divided into basic blocks, the memory access instructions contained in each basic block are identified, and the memory address accessed by each memory access instruction is analyzed. The address difference between adjacent memory access instructions is calculated based on the address access span of the memory access instructions. The address difference is cumulatively distributed and analyzed to count the number of memory access instruction pairs whose address difference is less than the preset cache line size. The ratio of the number of memory access instruction pairs to the total number of memory access instructions in the task is determined as the cache access density feature of the task.

5. The method according to claim 1, characterized in that, The S4 includes: For each task in the task queue to be assigned, calculate the fit score between the task and each energy sensing partition. In the compatibility score calculation between a task and a partition, a first component is generated based on the comparison between the partition temperature and a preset temperature threshold, a second component is generated based on the comparison between the remaining power of the partition and the estimated power consumption of the task, and a third component is generated based on the comparison between the instantaneous power consumption of the partition and the rated power consumption of the partition. A fourth component is generated based on the degree of matching between the instruction mixing characteristics of the task and the hardware computing unit type of the partition, and a fifth component is generated based on the degree of matching between the cache access density characteristics of the task and the cache capacity of the partition. The first component, the second component, the third component, the fourth component, and the fifth component are weighted and accumulated, and the result of the weighted accumulation is used as the fitness score of the task relative to the partition.

6. The method according to claim 5, characterized in that, The generation of the fourth component based on the degree of matching between the instruction mixing characteristics of the task and the hardware computing unit type of the partition includes: Obtain the instruction set architecture extension identifiers supported by the processor cores within the energy-aware partition. The instruction set architecture extension identifiers include single instruction multiple data extension identifiers, advanced vector extension identifiers, and floating-point acceleration unit identifiers. The degree of dependence of the task on floating-point computing resources and the degree of dependence on vector computing resources are determined based on the instruction mixing characteristics of the task. If the task's dependence on floating-point computing resources exceeds the floating-point dependence threshold and the instruction set architecture extension identifier contains the floating-point acceleration unit identifier, then the fourth component is assigned a first positive value. If the task's dependence on vector computing resources exceeds the vector dependence threshold and the instruction set architecture extension identifier contains the advanced vector extension identifier, then the fourth component is assigned a second positive value. If the task's dependence on integer operation resources exceeds the integer dependence threshold, the fourth component will be assigned a third positive value, regardless of the value of the instruction set architecture extension identifier. If the task's dependence on floating-point computing resources exceeds the floating-point dependence threshold, but the instruction set architecture extension identifier does not contain the floating-point acceleration unit identifier, then the fourth component is assigned a first negative value.

7. The method according to claim 5, characterized in that, The process of generating a fifth component based on the matching degree between the cache access density characteristics of the task and the cache capacity of the partition includes: Obtain the capacity value of the last-level cache shared within this energy sensing partition; Based on the numerical range of the cache access density characteristics of the task, the task is classified into high-density access type, medium-density access type, or low-density access type. If the task is a high-density access type and the capacity value of the last-level cache is greater than the first cache capacity threshold, then the fifth component is assigned a first positive value. If the task is of medium-density access type and the capacity value of the last level cache is between the first cache capacity threshold and the second cache capacity threshold, then the fifth component is assigned a second positive value; If the task is a low-density access type and the capacity value of the last level cache is less than the second cache capacity threshold, then the fifth component is assigned a third positive value. If the task is a high-density access type and the capacity value of the last-level cache is less than the second cache capacity threshold, then the fifth component is assigned a first negative value.

8. The method according to claim 1, characterized in that, The S5 includes: Based on the fit score of each task to be assigned relative to each energy-aware partition, a task-partition fit matrix is ​​constructed. The row index of the task-partition fit matrix corresponds to the identifier of the task to be assigned, the column index corresponds to the identifier of the energy-aware partition, and the matrix elements are the corresponding fit scores. Scan the task-partition fit matrix to initially determine one or more candidate energy-aware partitions for each task to be assigned. The candidate energy-aware partitions refer to partitions with a fit score greater than a preset admission threshold. For each energy-sensing partition, obtain the current task load count and the utilization rate of each processor core in that partition, and determine the remaining task acceptance capacity of that partition based on the task load count and the utilization rate of each processor core. Based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, a two-dimensional assignment strategy is adopted to determine a unique target energy-aware partition for each task to be assigned. The goal of the two-dimensional assignment strategy is to maximize the sum of fit scores of all assigned tasks under the constraint of not exceeding the remaining task acceptance capacity of each partition. Based on the determination result of the two-dimensional assignment strategy, the execution context of each task to be assigned is migrated to the ready queue of the processor core contained in its target energy-aware partition.

9. The method according to claim 8, characterized in that, Based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, a two-dimensional assignment strategy is used to determine a unique target energy-aware partition for each task to be assigned, including: All tasks to be assigned are sorted in descending order of suitability score to generate a task processing sequence; All energy-sensing partitions are sorted in ascending order of remaining task capacity to generate a partition processing sequence; Extract the first task that appears first in the task processing sequence, and obtain the first partition with the highest adaptation score for the first task based on the task-partition adaptation matrix. Check if the remaining task acceptance capacity of the first partition is greater than zero; If the remaining task acceptance capacity of the first partition is greater than zero, then the first task is assigned to the first partition, and the remaining task acceptance capacity of the first partition is reduced by one. If the remaining task acceptance capacity of the first partition is zero, then the second partition with the second highest adaptation score of the first task is obtained from the task-partition adaptation matrix, and the remaining task acceptance capacity of the second partition is checked until a partition with a remaining task acceptance capacity greater than zero is found for the first task, and the partition is determined as the target energy sensing partition of the first task.

10. The method according to claim 8, characterized in that, Based on the task-partition fit matrix and the remaining task acceptance capacity of each partition, a two-dimensional assignment strategy is used to determine a unique target energy-aware partition for each task to be assigned, including: The task-partition fit matrix is ​​input to a hardware-implemented assignment decision circuit, which includes multiple parallel comparators and a cross switch matrix. The multiple parallel comparators simultaneously compare the fitness scores of each task to be assigned relative to all energy-aware partitions. Each task to be assigned corresponds to one parallel comparator, and each parallel comparator outputs the highest fitness score corresponding to the task and the corresponding partition number. The cross switch matrix receives the partition number output by the parallel comparator and the remaining task acceptance capacity counter value of each partition. When at least two parallel comparators output the same partition number, the cross switch matrix arbitrates based on the remaining task acceptance capacity counter value of each partition, retains the connection corresponding to the partition with the highest remaining task acceptance capacity counter value, disconnects other connections pointing to the same partition, and triggers the parallel comparator corresponding to the disconnected connection to re-output the second highest fitness score and partition number. When the partition numbers output by all parallel comparators are distinct and their respective remaining task acceptance capacity counter values ​​are all greater than zero, the cross-switch matrix establishes a mapping path between each task to be assigned and the energy-sensing partition corresponding to its output partition number.

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