Stack overflow detection method, electronic equipment, readable storage medium and program product

Abstract

The invention relates to a stack overflow detection method, electronic equipment, a readable storage medium and a program product. The method comprises the following steps: in response to a read to-be-executed instruction, determining an access address of the to-be-executed instruction based on a decoder, the to-be-executed instruction being used for accessing a memory by using a stack pointer; obtaining a value of a target control state register, wherein the target control state register is configured to store a stack bottom address of a target stack of the to-be-executed instruction; determining a comparison result of the access address and the value of the target control state register based on a comparator; and when the comparison result is that the access address is smaller than the value of the target control state register, determining that the stack overflow detection result is that stack overflow exists. By adopting the method, stack overflow detection with high efficiency, high safety and reduced resource waste can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor design, and in particular, to a stack overflow detection method, an electronic device, a readable storage medium and a program product. BACKGROUND

[0002] Stack overflow is a typical error in program running, which is manifested as when a program writes data into a stack space, if the data volume exceeds the available capacity of the stack, the data will overflow into an adjacent memory area, damaging the stack frame or key data, which not only may cause program crash, but also provides conditions for attackers to execute malicious code using the vulnerability.

[0003] In the conventional technology, common protection methods include: a software protection mechanism that inserts a check value before a return address by a compiler and checks it, which introduces additional instructions and storage overhead, reducing execution efficiency; increasing stack space allocation artificially to reduce the risk of overflow, but the stack usage during program running is difficult to estimate; or using a physical memory protection circuit to trigger an exception when accessing a stack external area, which requires reserving an isolation space between the stack and the program, resulting in waste of memory resources. SUMMARY

[0004] Therefore, it is necessary to provide a stack overflow detection method, an electronic device, a readable storage medium and a program product with high efficiency, high security and reduced resource waste in view of the above technical problems.

[0005] In a first aspect, the present application provides a stack overflow detection method, comprising:

[0006] In response to reading a to-be-executed instruction, determining an access address of the to-be-executed instruction based on a decoder, the to-be-executed instruction being used to access a memory using a stack pointer;

[0007] Obtaining a value of a target control status register configured to store a bottom address of a target stack of the to-be-executed instruction;

[0008] Determining a comparison result of the access address and the value of the target control status register based on a comparator;

[0009] In a case where the comparison result is that the access address is less than the value of the target control status register, determining a stack overflow detection result as existing stack overflow.

[0010] In one of the embodiments, after the step of determining the comparison result of the access address and the value of the target control status register based on the comparator, the method further comprises:

[0011] In a case that the comparison result is that the access address is greater than or equal to the value of the target control state register, it is determined that the stack overflow detection result is that there is no stack overflow.

[0012] In one of the embodiments, the determining the access address of the to-be-executed instruction based on the decoder in response to reading the to-be-executed instruction comprises:

[0013] In response to reading the to-be-executed instruction, the register type of the access address register of the to-be-executed instruction is calculated based on the decoder.

[0014] In a case that the register type is a stack pointer register, the access address of the to-be-executed instruction is determined based on the decoder.

[0015] In one of the embodiments, the determining the access address of the to-be-executed instruction based on the decoder in response to reading the to-be-executed instruction comprises:

[0016] In response to reading the to-be-executed instruction, the instruction type of the to-be-executed instruction is calculated based on the decoder.

[0017] In a case that the instruction type is a memory access instruction, the access address of the to-be-executed instruction is determined based on the decoder.

[0018] In one of the embodiments, the determining the access address of the to-be-executed instruction based on the decoder comprises:

[0019] The offset in the to-be-executed instruction and the value of the stack pointer register are calculated based on the decoder.

[0020] The access address of the to-be-executed instruction is determined based on the offset and the value of the stack pointer register.

[0021] In one of the embodiments, the determining the access address of the to-be-executed instruction based on the offset and the value of the stack pointer register comprises:

[0022] The sum of the offset and the value of the stack pointer register is calculated based on an adder to obtain the access address of the to-be-executed instruction.

[0023] In one of the embodiments, the determining the access address of the to-be-executed instruction based on the decoder in response to reading the to-be-executed instruction comprises:

[0024] In a machine mode, the stack bottom address of a target stack is stored to a target control state register.

[0025] In a second aspect, the application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a program, and the processor implements the steps of the method in any of the above aspects when executing the program.

[0026] In a third aspect, the present application provides a readable storage medium, having a program stored thereon, which, when executed by a processor, implements the steps of the method of any one of the above aspects.

[0027] In a fourth aspect, the present application provides a program product, comprising a program, which, when executed by a processor, implements the steps of the method of any one of the above aspects.

[0028] The stack overflow detection method, the electronic device, the readable storage medium and the program product described above store the stack bottom address by setting a target control state register, and utilize a hardware detection circuit composed of a decoder and a comparator to determine whether the stack access address is lower than the set threshold in real time, so as to accurately identify the stack overflow. The scheme is implemented by pure hardware, without software intervention, without occupying program space and without consuming additional execution time, which significantly improves the detection efficiency and effectively prevents overflow access operations, with high safety. The precise judgment on the stack overflow is realized by monitoring the memory access instruction using the stack pointer. The entire detection mechanism only relies on a special register and a simple comparison circuit, with extremely low hardware resource occupation. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0030] Figure 1 A flowchart of the stack overflow detection method in one embodiment;

[0031] Figure 2 A flowchart of the stack overflow detection method in another embodiment;

[0032] Figure 3 A flowchart of step S110 in one embodiment;

[0033] Figure 4 A flowchart of step S110 in another embodiment;

[0034] Figure 5 A flowchart of the step of determining the access address of the to-be-executed instruction based on the decoder in one embodiment;

[0035] Figure 6 A flowchart of the stack overflow detection method in another embodiment;

[0036] Figure 7 This is a timing diagram of processor pipeline operation in one embodiment;

[0037] Figure 8 This is a structural block diagram of a stack overflow detection device in one embodiment;

[0038] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0041] In one exemplary embodiment, such as Figure 1 As shown, a stack overflow detection method is provided. Taking the application of this method to a processor (e.g., CPU) of an electronic device as an example, the method includes the following steps S110 to S140. Wherein:

[0042] In step S110, in response to reading the instruction to be executed, the access address of the instruction to be executed is determined based on the decoder. The instruction to be executed is used to access memory using the stack pointer.

[0043] The instruction to be executed can refer to a machine instruction that the processor reads from the instruction pipeline (e.g., the fetch stage IF) and is about to enter the decode stage (ID) or the execute stage (EX).

[0044] For example, the control and data paths of the processor hardware can automatically determine the access address of the instruction to be executed based on the decoder during the instruction execution process.

[0045] Step S120: Obtain the value of the target control status register. The target control status register is configured to store the bottom address of the target stack of the instruction to be executed.

[0046] The target control state register can be a special register newly added in a processor architecture, used to define the legal address boundary of the current task stack space. In a possible implementation, the target control state register can be a self-defined special control state register under the RISC-V instruction set architecture, and only allowed to be written through a csr instruction at the highest privilege level to ensure its security and prevent it from being tampered by user programs. The data width of the target control state register can be consistent with the data width of the processor (for example, 32 bits or 64 bits). The target stack can be the current stack corresponding to the stack pointer. The stack is a specific area in the computer memory, used to store local variables, function parameters, return addresses and other information when a function is called, and it complies with the last-in first-out principle. The bottom address of the target stack can be the lower limit address of the stack memory area in logic. Since the stack usually grows in the low address direction, this address is the threshold for stack overflow detection. When the stack pointer tries to access an address lower than this threshold, it is considered to overflow. This address is calculated in advance by the operating system in the machine mode and set in the register during task initialization or context switching.

[0047] In step S130, a comparison result of the access address and the value of the target control state register is determined based on the comparator.

[0048] The comparator is a digital logic circuit that receives the access address and the value of the target control state register (i.e., the bottom address of the target stack) as inputs and compares the numerical values.

[0049] In step S140, in the case where the comparison result is that the access address is less than the value of the target control state register, it is determined that the stack overflow detection result is that there is a stack overflow.

[0050] For example, when the comparator outputs an indication that an overflow occurs, the exception control logic of the processor can be triggered, which can intercept the current illegal memory access request so that it will not be sent to the memory controller, thereby preventing damage to the critical data outside the stack. At the same time, the logic generates a hardware exception, so that the processor enters the exception handling program in the machine mode.

[0051] In the above stack overflow detection method, the bottom address of the stack is stored by setting the target control state register, and a hardware detection circuit composed of the decoder and the comparator is used to determine in real time whether the stack access address is lower than the set threshold, so as to accurately identify the stack overflow. This scheme is implemented purely in hardware, without the need for software intervention, neither occupying program space nor consuming additional execution time, significantly improving the detection efficiency and effectively preventing overflow access operations, with high security; the precise judgment of the stack overflow condition is realized by monitoring the memory access instructions using the stack pointer; the entire detection mechanism only relies on a special register and a simple comparison circuit, with extremely low hardware resource occupation.

[0052] In some embodiments, as shown in Figure 2 The stack overflow detection method can further include:

[0053] At step S150, in the case that the comparison result is that the access address is greater than or equal to the value of the target control state register, it is determined that the stack overflow detection result is that there is no stack overflow.

[0054] Illustratively, when the comparator output indicates that no overflow has occurred (i.e., the access address is greater than or equal to the threshold value), the current memory access request can be allowed to pass normally. The memory access request (e.g., store data sw or load data lw) will be normally sent to the memory subsystem (e.g., cache or memory controller) and executed, and the instruction pipeline will also continue to operate normally.

[0055] In some embodiments, as shown in Figure 3 The step S110 can include:

[0056] At step A1, in response to reading the to-be-executed instruction, the register type of the access address register of the to-be-executed instruction is calculated based on the decoder.

[0057] The register type of the access address register can be the base register number used to specify the memory address calculation in the instruction code. The decoder hardware parses the specific field of the instruction (e.g., in the RISC-V I-Type or S-Type instruction) to extract the base register number.

[0058] At step A2, in the case that the register type is a stack pointer register, the access address of the to-be-executed instruction is determined based on the decoder.

[0059] The stack pointer register can be the general register x2 (also referred to as SP) in the RISC-V architecture.

[0060] Illustratively, the decoder can internally include a comparison logic for judging whether the base register number extracted from the instruction is equal to the number of x2. When the base register is identified as the stack pointer register, the access address calculation logic is enabled, and the subsequent stack overflow detection logic is executed. If the base register is another register, it indicates that this memory access is not related to the stack operation, and the subsequent stack overflow detection logic can be skipped.

[0061] In this embodiment, the register type of the access address is identified by the decoder, and the address calculation and overflow judgment are only started when the register is the stack pointer, thereby realizing targeted monitoring of the stack access behavior, having the characteristics of low resource occupation, and not needing to specially reserve a part of the memory space, without resource waste.

[0062] In some embodiments, as shown in Figure 4 The step S110 can include the following steps.

[0063] Step B1, in response to reading the to-be-executed instruction, calculating the instruction type of the to-be-executed instruction based on the decoder.

[0064] The instruction type of the to-be-executed instruction can be determined by the decoder by parsing the operation code of the instruction.

[0065] Step B2, in the case that the instruction type is a memory access instruction, determining the access address of the to-be-executed instruction based on the decoder.

[0066] The memory access instruction can be an instruction for transferring data between the memory and the register. In the RISC-V architecture, the memory access instruction includes but is not limited to the load instruction and the store instruction.

[0067] For example, the decoder can first determine whether the operation code belongs to the category of the memory access instruction. When the instruction is identified as the memory access instruction, the base address register is further determined and the subsequent address calculation and comparison are performed. When the instruction is identified as a non-memory access instruction, it indicates that the stack memory will not be accessed, and the subsequent stack overflow detection logic can be skipped.

[0068] In this embodiment, by identifying the instruction type in the decoding stage and starting the subsequent address calculation and overflow detection process only when the instruction belongs to the memory access type, the preliminary screening of the instruction is realized, unnecessary hardware actions are avoided, and the detection efficiency is further improved while ensuring that the stack overflow behavior is accurately captured.

[0069] In one of the embodiments, as shown in Figure 5 The step of determining the access address of the to-be-executed instruction based on the decoder can include the following steps.

[0070] Step C1, calculating the offset in the to-be-executed instruction and the value of the stack pointer register based on the decoder.

[0071] Step C2, determining the access address of the to-be-executed instruction based on the offset and the value of the stack pointer register.

[0072] In one possible implementation, the step S110 can include the following steps: in response to reading the to-be-executed instruction, calculating the instruction type of the to-be-executed instruction, the offset in the to-be-executed instruction and the value of the stack pointer register based on the decoder; calculating whether the instruction type of the to-be-executed instruction is a memory access instruction, and in the case that the instruction type of the to-be-executed instruction is a memory access instruction, calculating the access address of the to-be-executed instruction based on the offset and the value of the stack pointer register.

[0073] Specifically, the instruction can be first decoded to parse its opcode and operand to determine whether it belongs to the instruction type that can cause stack access (e.g., store instruction sw, load instruction lw, etc. memory access instruction) and further determine whether the instruction specifies the stack pointer register (usually x2 in RISC-V) as its address base register. If both conditions are met, the instruction is determined to be a stack access instruction. Subsequently, the hardware logic can calculate the actual memory address to be accessed by the current memory access operation in combination with the current stack address read from the stack pointer register and the offset contained in the instruction encoding.

[0074] In one possible implementation, the above step C2 can include: based on the adder, calculating the sum of the offset and the value of the stack pointer register to obtain the access address of the to-be-executed instruction.

[0075] Exemplarily, the address offset obtained from the instruction decoding and the current value of the stack pointer read from the register file can be sent to the adder together. The result output by the adder is the actual physical address to be accessed by the current memory access operation.

[0076] In this embodiment, the calculation of the access address based on the hardware adder avoids the additional overhead of software calculation and improves the address resolution speed.

[0077] In one exemplary embodiment, as shown in Figure 6 The above stack overflow detection method can further include:

[0078] Step S160, in the machine mode, store the bottom address of the target stack to the target control state register.

[0079] The machine mode (M mode) is the running mode with the highest permission in RISC-V.

[0080] Further, the above step S110 can include: in the user mode, in response to reading the to-be-executed instruction, determining the access address of the to-be-executed instruction based on the decoder.

[0081] The user mode (U mode) is used to execute applications in RISC-V and has limited memory address access permission.

[0082] Exemplarily, after the operating system schedules a task and allocates a stack space for a new task or process, the operating system kernel (running in M mode) can calculate the start address (i.e., the bottom address) of the new stack space, and then write the address value into the stack pointer threshold register by executing a dedicated control state register write instruction, so as to set a legal stack boundary for the task to be run. When the processor switches to the user mode to execute the application program, the instruction pipeline thereof continuously fetches, decodes and executes, and automatically executes the stack overflow detection logic through hardware.

[0083] In this embodiment, by limiting the write operation on the target control state register in the machine mode, the safety and reliability of the bottom threshold setting are ensured.

[0084] In one possible implementation, refer to Figure 7 , Figure 7 for a timing diagram of the processor pipeline operation in one embodiment. Wherein, GPR refers to the general-purpose register group (General-Purpose Register). IF (Instruction Fetch) refers to the instruction fetch stage, which reads instructions from the memory. ID (Decode) refers to the instruction decoding stage, which identifies the storage instruction and prepares the operands. EX (Execute) refers to the execution stage. LD (Load) / ST (Store) refers to the memory access stage. If it is a load instruction, data is read from the calculated address; if it is a storage instruction (as shown in Figure 7 ), data is written to the address. WB (Write Back) refers to the write back stage, which writes the operation result back to the register. Specifically, under normal circumstances, the calculated access address is greater than or equal to the value of the target control state register, the instruction continues to enter the LD and WB stages, and the entire operation is completed. Under abnormal circumstances, the calculated access address is less than the value of the target control state register, a fault is detected, and a CPU exception is generated in the EX stage, the subsequent pipeline stages (LD, WB) of the instruction are cancelled; the access request is rejected; the CPU falls into the exception handling process (enters the M mode), the pipeline is interrupted, and the CPU processes the exception.

[0085] In summary, the stack overflow detection method, the electronic device, the readable storage medium and the program product, by setting the target control state register to store the stack bottom address, and using the hardware detection circuit composed of the decoder and the comparator, the stack access address is determined in real time whether it is lower than the set threshold, so as to accurately identify when the stack overflow occurs. The scheme is implemented by pure hardware, without software intervention, without occupying program space, without consuming additional execution time, significantly improving the detection efficiency, and effectively preventing overflow access operation, high safety; by monitoring the memory access instruction using the stack pointer, the accurate judgment of the stack overflow condition is realized; the whole detection mechanism only depends on a special register and a simple comparison circuit, and the hardware resource occupation is extremely low.

[0086] It should be understood that, although each step in the flowchart involved in each embodiment as described above is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps has no strict order limitation, and these steps can be executed in other order. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by combination are within the scope of protection of the present application.

[0087] Based on the same inventive concept, the embodiments of the present application also provide a stack overflow detection device for implementing the above-mentioned stack overflow detection method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more stack overflow detection device embodiments provided below can refer to the limitations of the stack overflow detection method in the foregoing, which will not be repeated here.

[0088] In one exemplary embodiment, as shown in Figure 8 A stack overflow detection device 200 is provided, comprising: an access address determination module 201, a stack bottom address acquisition module 202, an address comparison module 203 and a detection result determination module 204, wherein:

[0089] The access address determination module 201 is configured to determine the access address of the to-be-executed instruction based on the decoder in response to reading the to-be-executed instruction, the to-be-executed instruction being used to access the memory using the stack pointer.

[0090] The stack bottom address obtaining module 202 is configured to obtain a value of a target control status register, the target control status register being configured to store a stack bottom address of a target stack of an instruction to be executed.

[0091] The address comparison module 203 is configured to determine a comparison result of the access address and the value of the target control status register based on a comparator.

[0092] The detection result determination module 204 is configured to determine, in a case where the comparison result is that the access address is less than the value of the target control status register, that a stack overflow detection result is that a stack overflow exists.

[0093] In an embodiment, the detection result determination module 204 is further configured to:

[0094] determine, in a case where the comparison result is that the access address is greater than or equal to the value of the target control status register, that the stack overflow detection result is that a stack overflow does not exist.

[0095] In an embodiment, the access address determination module 201 is further configured to:

[0096] in response to reading the instruction to be executed, determine, based on a decoder, a register type of an access address register of the instruction to be executed;

[0097] in a case where the register type is a stack pointer register, determine, based on the decoder, the access address of the instruction to be executed.

[0098] In an embodiment, the access address determination module 201 is further configured to:

[0099] in response to reading the instruction to be executed, determine, based on a decoder, an instruction type of the instruction to be executed;

[0100] in a case where the instruction type is a memory access instruction, determine, based on the decoder, the access address of the instruction to be executed.

[0101] In an embodiment, the access address determination module 201 is further configured to:

[0102] determine, based on the decoder, an offset in the instruction to be executed and a value of a stack pointer register;

[0103] determine, based on the offset and the value of the stack pointer register, the access address of the instruction to be executed.

[0104] In an embodiment, the access address determination module 201 is further configured to:

[0105] determine, based on a sum of the offset and the value of the stack pointer register calculated by an adder, the access address of the instruction to be executed.

[0106] In an embodiment, the stack overflow detection apparatus 200 further comprises a register configuration module, configured to:

[0107] The offset and the value of the stack pointer register are added based on the adder to obtain an access address of the instruction to be executed.

[0108] The modules in the stack overflow detection apparatus can be implemented by software, hardware, or a combination thereof. The modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so as to be invoked and executed by the processor to perform the operations corresponding to the modules.

[0109] In an exemplary embodiment, an electronic device is provided, comprising a memory storing a program and a processor, wherein the processor implements the steps in the above method embodiments when executing the program. The electronic device can be a computer device or a system on chip.

[0110] In an exemplary embodiment, a computer device is provided, which can be a terminal. The internal structure diagram of the computer device can be as shown in Figure 9 The computer device comprises a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to perform wired or wireless communication with external terminals. The wireless communication can be achieved through WIFI, mobile cellular network, near field communication (NFC), or other technologies. The computer program is executed by the processor to implement a stack overflow detection method.

[0111] In an embodiment, a readable storage medium is provided, which stores a program. The program is executed by a processor to implement the steps in the above method embodiments.

[0112] In an embodiment, a program product is provided, comprising a program. The program is executed by a processor to implement the steps in the above method embodiments.

[0113] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0114] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0115] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A stack overflow detection method, characterized in that, The method includes: In response to reading an instruction to be executed, the access address of the instruction to be executed is determined based on the decoder, and the instruction to be executed is used to access memory using a stack pointer; Obtain the value of the target control status register, which is configured to store the bottom address of the target stack of the instruction to be executed; Based on the comparator, the comparison result between the access address and the value of the target control status register is determined; If the comparison result shows that the access address is less than the value of the target control status register, the stack overflow detection result is determined to be that a stack overflow exists.

2. The method according to claim 1, characterized in that, After determining the comparison result between the access address and the value of the target control status register based on the comparator, the process includes: If the comparison result shows that the access address is greater than or equal to the value of the target control status register, the stack overflow detection result is determined to be that there is no stack overflow.

3. The method according to claim 1, characterized in that, The step of determining the access address of the instruction to be executed based on the decoder in response to reading the instruction to be executed includes: In response to reading the instruction to be executed, the register type of the access address register of the instruction to be executed is calculated based on the decoder; When the register type is a stack pointer register, the access address of the instruction to be executed is determined based on the decoder.

4. The method according to claim 1, characterized in that, The step of determining the access address of the instruction to be executed based on the decoder in response to reading the instruction to be executed includes: In response to reading the instruction to be executed, the instruction type of the instruction to be executed is calculated based on the decoder; When the instruction type is a memory access instruction, the access address of the instruction to be executed is determined based on the decoder.

5. The method according to any one of claims 1 to 4, characterized in that, The process of determining the access address of the instruction to be executed based on the decoder includes: The offset and stack pointer register value in the instruction to be executed are calculated based on the decoder. Based on the offset and the value of the stack pointer register, the access address of the instruction to be executed is determined.

6. The method according to claim 5, characterized in that, Determining the access address of the instruction to be executed based on the offset and the value of the stack pointer register includes: The sum of the offset and the value of the stack pointer register is calculated using the adder to obtain the access address of the instruction to be executed.

7. The method according to claim 1, characterized in that, Before determining the access address of the instruction to be executed based on the decoder in response to reading the instruction to be executed, the following steps are included: In machine mode, the bottom address of the target stack is stored in the target control status register.

8. An electronic device comprising a memory and a processor, wherein the memory stores a program, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 7.

9. A readable storage medium having a program stored thereon, characterized in that, When the program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

10. A program product, comprising a program, characterized in that, When the program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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