Chip inter-core heterogeneous information communication method of two-stage RingBuffer structure

Abstract

The invention provides a chip inter-core heterogeneous information communication method of a two-stage RingBuffer structure, and relates to the technical field of inter-core communication, and the method comprises the following steps: S1, constructing and initializing the two-stage RingBuffer structure which comprises a unit buffer area and a data buffer area; s2, whether write operation is executed or not is determined based on full-write pre-judgment, the initial position of the heterogeneous variable-length information and the actual write-in data length are written into the unit buffer area when the write operation is executed, and original data of the heterogeneous variable-length information are written into the data buffer area; and S3, determining whether to execute a read operation based on the read-out pre-judgment, reading the initial position and the actual write-in data length of the heterogeneous variable-length information based on the unit buffer area when the read operation is executed, and then reading the original data of the heterogeneous variable-length information from the data buffer area based on the actual write-in data length. According to the method, correct transmission of inter-core heterogeneous variable-length information is effectively realized, so that the integrity and correctness of inter-core communication are guaranteed, and the method has the advantages of high space utilization rate and wide application scenarios.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of inter-core communication, and particularly relates to a chip inter-core heterogeneous information communication method based on a two-stage RingBuffer structure. BACKGROUND

[0002] STM32H745BIT6 (referred to as MCU) is a high-performance embedded microcontroller, and a remarkable feature thereof is a powerful dual-core architecture. The microcontroller integrates an ARM Cortex-M7 and a Cortex-M4, two 32-bit RISC cores, which run at frequencies of 480 MHz and 240 MHz respectively, and provides excellent processing capability for complex applications. In application scenarios such as mine personnel positioning systems, the dual-core architecture of the STM32H745BIT6 can efficiently process real-time data collection, processing and communication tasks, and ensure the accuracy and response speed of the positioning system. The Cortex-M7 core can be responsible for high-intensity data processing and algorithm operation, and the Cortex-M4 core can effectively manage peripheral interfaces and communication tasks, and the two cores work together to improve the overall performance and stability of the system.

[0003] Since the STM32H745BIT6 is a dual-core MCU, inter-core communication between the Cortex-M7 core and the Cortex-M4 core is inevitable, but because the transmitted information is different, the information transmission between the two cores is variable-length and heterogeneous, and how to define and segment each message in the transmission of heterogeneous variable-length information is very important.

[0004] In the prior art, the fixed-length protocol or the delimiter protocol is generally used to define and segment the heterogeneous variable-length information, but these methods have certain defects, and the defects are as follows: (1) The fixed-length protocol, which converts the variable-length message into a fixed-length message by taking the maximum length as the criterion, and the length of each message is fixed, and the receiving party reads the defined information data according to the fixed byte number, which is simple and easy to implement, but has a serious problem of space waste, especially in a scenario where short messages are dominant and long messages are less, the waste is particularly serious; (2) The delimiter protocol, which adds a specific delimiter between messages to enable the receiving party to distinguish messages according to the delimiter, which is suitable for variable-length messages, but is only applicable to scenarios where the message content cannot contain the delimiter, for example, using "\n" as the message delimiter, sending "Hello World\n,Hello Everyone\n", and the receiving party segments the message according to "\n", and the application scenario is too limited.

[0005] Therefore, when performing inter-core communication on a multi-core chip such as STM32H745BIT6, there is an urgent need for a chip inter-core heterogeneous information communication method with high space utilization, wide application scenarios, and effective definition of reading heterogeneous variable-length information.

[0006] The above information disclosed in the background section is only intended to enhance the understanding of the background of the present disclosure, and thus it can include information that does not constitute the prior art known to those of ordinary skill in the art. SUMMARY

[0007] The purpose of the present application is to provide a chip inter-core heterogeneous information communication method with a two-stage RingBuffer structure to solve the problems raised in the background.

[0008] To achieve the above-mentioned purpose, the present application provides the following technical solutions: A chip inter-core heterogeneous information communication method with a two-stage RingBuffer structure, comprising the following steps: S1, constructing and initializing a two-stage RingBuffer structure, which is composed of a first ring buffer area including a first ring buffer and a unit buffer area, and a second ring buffer area including a second ring buffer and a data buffer area; S2, determining whether to perform a write operation based on a full write prediction, and when performing a write operation, writing the start position and actual write data length of the heterogeneous variable-length information to the unit buffer area, and writing the original data of the heterogeneous variable-length information to the data buffer area; S3, determining whether to perform a read operation based on an empty read prediction, and when performing a read operation, first reading the start position and actual write data length of the heterogeneous variable-length information based on the unit buffer area, and then reading the original data of the heterogeneous variable-length information from the data buffer area based on the actual write data length of the heterogeneous variable-length information.

[0009] Further, the unit buffer area is used to store the start address and actual write data length of the heterogeneous variable-length information, the actual write data length is determined based on the heterogeneous variable-length information data length and the remaining space of the write operation of the data buffer area, and the first ring buffer is a component for managing the state of the unit buffer area; The data buffer area is used to store the original data of the heterogeneous variable-length information, and the second ring buffer is a component for managing the state of the data buffer area.

[0010] Further, the method for initializing the two-stage RingBuffer structure is to point the write pointer position and the read pointer position of the first ring buffer to the start position of the unit buffer area, and to point the write pointer position and the read pointer position of the second ring buffer to the start position of the data buffer area.

[0011] Further, the logic of performing the full-write prediction is as follows: 1) Determine the remaining space for the write operation of the unit buffer based on the write pointer position and the read pointer position of the first ring buffer; 2) Determine the remaining space for the write operation of the data buffer based on the write pointer position and the read pointer position of the second ring buffer; 3) Perform the full-write prediction based on the remaining space for the write operation of the unit buffer and the remaining space for the write operation of the data buffer. If both are greater than 0, it is determined that the state is not full and the write operation is performed. Otherwise, it is determined that the state is full and the write operation is not performed.

[0012] Further, the logic of performing the read-empty prediction is as follows: 1) Determine the remaining space for the read operation of the unit buffer based on the write pointer position and the read pointer position of the first ring buffer; 2) Determine the remaining space for the read operation of the data buffer based on the write pointer position and the read pointer position of the second ring buffer; 3) Perform the read-empty prediction based on the remaining space for the read operation of the unit buffer and the remaining space for the read operation of the data buffer. If both are greater than 0, it is determined that the state is not empty and the read operation is performed. Otherwise, it is determined that the state is empty and the read operation is not performed.

[0013] Further, the logic of performing the read operation is as follows: 1) Read the actual write data length of the heterogeneous variable-length information requested to be read from the unit buffer, and then read the same length of data from the data buffer based on the actual write data length, as the original data read from the heterogeneous variable-length information; 2) After completing the read of the heterogeneous variable-length information, update the read pointer position of the first ring buffer and the read pointer position of the second ring buffer. Further, the logic of performing the read operation is as follows:

[0014] 1) Read the actual write data length of the heterogeneous variable-length information requested to be read from the unit buffer, and then read the same length of data from the data buffer based on the actual write data length, as the original data read from the heterogeneous variable-length information; 2) After completing the read of the heterogeneous variable-length information, update the read pointer position of the first ring buffer and the read pointer position of the second ring buffer.

[0015] ​Further, during the operation of the two-stage RingBuffer structure, the capacities of the unit buffer or the data buffer are updated in real time based on the remaining space for the write operation of the unit buffer and the remaining space for the write operation of the data buffer, and the specific logic is as follows: 1) During the operation of the two-stage RingBuffer structure, the remaining space for the write operation of the unit buffer and the remaining space for the write operation of the data buffer are collected in real time based on a fixed sampling interval, to determine the unit buffer idle ratio and the data buffer idle ratio at each sampling time, and to calculate the ratio of the two to determine the space utilization balance coefficient at each sampling time; 2) The space utilization balance coefficient and the preset space utilization balance threshold are combined to classify each sampling time into a to-be-positively-adjusted time, a same-direction-adjusted time, or a to-be-negatively-adjusted time; 3) An observation window is set based on the current sampling time, and a dominant adjustment strategy is determined based on the frequency of the to-be-positively-adjusted time, the frequency of the same-direction-adjusted time, and the frequency of the to-be-negatively-adjusted time in the observation window, the dominant adjustment strategy being a positive adjustment strategy, a negative adjustment strategy, or a same-direction adjustment strategy; 4) The dominant adjustment strategy, the first idle ratio threshold, the second idle ratio threshold, the unit buffer idle ratio, and the data buffer idle ratio in the observation window are combined to determine the final adjustment strategy, the first idle ratio threshold being smaller than the second idle ratio threshold.

[0016] Further, the calculation logic of the unit buffer idle ratio and the data buffer idle ratio at each sampling time is as follows: for any sampling time, the ratio of the remaining space for the write operation of the unit buffer to the size of the unit buffer space at the sampling time is calculated as the unit buffer idle ratio at the sampling time, and the ratio of the remaining space for the write operation of the data buffer to the size of the data buffer space at the sampling time is calculated as the data buffer idle ratio at the sampling time; The logic for classifying each sampling time is as follows: the space utilization balance threshold includes a first space utilization balance threshold and a second space utilization balance threshold, and the first space utilization balance threshold is greater than 1 and the second space utilization balance threshold is less than 1, if the space utilization balance coefficient at a sampling time is higher than the first space utilization balance threshold, the sampling time is classified as a to-be-positively-adjusted time, if the space utilization balance coefficient at a sampling time is lower than the second space utilization balance threshold, the sampling time is classified as a to-be-negatively-adjusted time, and if the space utilization balance coefficient at a sampling time is not lower than the second space utilization balance threshold and not higher than the first space utilization balance threshold, the sampling time is classified as a same-direction-adjusted time.

[0017] Further, the logic for determining the dominant adjustment strategy is as follows: Based on the frequency of occurrence of the time to be positively adjusted, the frequency of occurrence of the time to be adjusted in the same direction, and the frequency of occurrence of the time to be negatively adjusted, it is determined whether there is a frequency higher than the frequency threshold. The frequency threshold is a decimal greater than 0.5. If there is no such frequency, the same-direction adjustment strategy is executed. The same-direction adjustment strategy is to either not adjust the capacity of the cell buffer and the data buffer, or to adjust the capacity of the cell buffer and the data buffer proportionally. If the frequency of same-direction adjustment times exceeds the frequency threshold, then the same-direction adjustment strategy is executed; If the frequency of the positive adjustment occurs higher than the frequency threshold, then the positive adjustment strategy is executed. The positive adjustment strategy is to increase the data buffer capacity or decrease the cell buffer capacity. If the frequency of the negative adjustment time exceeds the frequency threshold, the negative adjustment strategy is executed. The negative adjustment strategy is to reduce the data buffer capacity or increase the cell buffer capacity. The logic for determining the final adjustment strategy is as follows: The percentage of idle unit buffers and the percentage of idle data buffers at each sampling time within the observation window are statistically analyzed to determine the average percentage of idle unit buffers and the average percentage of idle data buffers within the observation window. Under the dominant adjustment strategy of same direction adjustment, if the minimum value of the average idle percentage of the unit buffer and the average idle percentage of the data buffer within the observation window is lower than the first idle percentage threshold, the capacity of the unit buffer and the data buffer will be increased proportionally according to a fixed adjustment ratio. If the maximum value of the average idle percentage of the unit buffer and the average idle percentage of the data buffer within the observation window is higher than the second idle percentage threshold, the capacity of the unit buffer and the data buffer will be decreased proportionally according to a fixed adjustment ratio. If neither of the above two conditions is met, the capacity of the unit buffer and the data buffer will not be adjusted. Under the dominant adjustment strategy of positive adjustment, if the average idle percentage of the data buffer within the observation window is lower than the first idle percentage threshold, the capacity of the data buffer is increased by a fixed adjustment ratio, and vice versa. When the dominant adjustment strategy is a negative adjustment strategy, if the average idle percentage of the cell buffer within the observation window is lower than the first idle percentage threshold, the capacity of the cell buffer is increased by a fixed adjustment ratio; otherwise, the capacity of the data buffer is decreased by a fixed adjustment ratio.

[0018] Compared with the prior art, the beneficial effects of the present invention are: The chip core heterogeneous information communication method of the present invention with a two-level RingBuffer structure effectively realizes the correct transmission of heterogeneous variable-length information between cores through the ingenious design of the two-level RingBuffer structure, thereby ensuring the integrity and correctness of inter-core communication. Compared with fixed-length protocols, it has the advantage of high space utilization, and compared with delimiter protocols, it has the advantage of wide application scenarios, effectively solving the pain points and difficulties of existing solutions. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the method flow of the present invention; Figure 2 This is a schematic diagram of the state of the two-level RingBuffer structure after initialization in this invention; Figure 3 This is a schematic diagram of the two-level RingBuffer structure in the present invention in an incomplete state; Figure 4 This is a schematic diagram of the two-level RingBuffer structure in the fully written state (Ⅰ) of this invention; Figure 5 This is a schematic diagram of the two-level RingBuffer structure in the present invention in the state of full (Ⅱ); Figure 6 This is a schematic diagram of the two-level RingBuffer structure in the fully written state (Ⅲ) of this invention; Figure 7 This is a schematic diagram illustrating the state of a write operation performed on the two-level RingBuffer structure in this invention. Figure 8 This is a schematic diagram of the two-level RingBuffer structure in the present invention in an unread, empty state; Figure 9 This is a schematic diagram of the two-level RingBuffer structure in the present invention in the read-empty state (Ⅰ); Figure 10 This is a schematic diagram of the two-level RingBuffer structure in the present invention in the read-empty state (Ⅱ); Figure 11 This is a schematic diagram of the two-level RingBuffer structure in the present invention in the read-empty state (Ⅲ); Figure 12 This is a schematic diagram illustrating the state of a read operation performed on the two-level RingBuffer structure in this invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Example: Please see Figures 1-12 This invention provides a method for heterogeneous information communication between chip cores using a two-level RingBuffer structure, comprising the following steps: S1, construct and initialize a two-level RingBuffer structure, which consists of a first ring buffer including a first ring buffer and a cell buffer, and a second ring buffer including a second ring buffer and a data buffer; The unit buffer is used to store the starting address of the heterogeneous variable-length information and the actual written data length. The actual written data length is determined based on the heterogeneous variable-length information data length and the remaining space of the data buffer for write operations. The first ring buffer is a component used to manage the state of the unit buffer, including information such as read pointer, write pointer, unit buffer size, and data count, so as to control the data read and write operations and ensure the safety and correctness of read and write operations in a concurrent environment. It can also indicate whether the unit buffer is full or empty. The data buffer is used to store the raw data of heterogeneous variable-length information. The second ring buffer is a component used to manage the state of the data buffer, including information such as read pointer, write pointer, cell buffer size, and data count, so as to control the data read and write operations and ensure the safety and correctness of read and write operations in a concurrent environment. It can also indicate the status information such as whether the data buffer is full or empty. As an implementation method, for ease of description, the first circular buffer, the cell buffer, the second circular buffer, the data buffer, and the second circular buffer are respectively labeled as follows: , , , , , And define a for each heterogeneous variable-length information (i.e., data unit), which contains the starting position and size of the heterogeneous information. The size is the data length of the heterogeneous variable length information, and a byte array of type uint8_t is used to store the original data of each heterogeneous variable length information; Taking the STM32H745BIT6 as an example, it includes D1, D2, and D3 domains. The D1 domain, as the core area for high-performance processing, is equipped with a powerful ARM Cortex-M7 core, which can support high-speed and complex data processing and algorithm calculations. The D2 domain focuses on peripheral interface management and communication tasks, driven by an efficient Arm Cortex-M4 core, ensuring real-time and stable interaction with various sensors and communication modules, guaranteeing timely data transmission and rapid system response. The D3 domain, as the foundation of the system, is equipped with SRAM4 memory (i.e., supporting 4-bit wide static random access memory), responsible for reset, clock control, and overall power management, providing a stable operating environment for the D1 and D2 domains. The D1, D2, and D3 domains are tightly interconnected through advanced multi-layer bus matrices such as AXI (Advanced Extensible Interface) and AHB (Advanced High-performance Bus). And in this technical solution , , , All SRAM4s are allocated in the D3 domain, The starting address is defined as LEVEL1_UNIT_START_ADDR, and... The starting address is defined as LEVEL2_DATA_START_ADDR, and in this system design, The space size is set to 1KB, which is 0x400 (1024) bytes (this can be adjusted according to the needs of the scenario and is not unique). The size of the space needs to be determined according to If we perform calculations, for example, setting the size of each heterogeneous variable-length message to 32 bytes (refer to the 32-byte extended CAN message), then... It can accommodate 32 people ,but The space size is 0x20 (32) On a 32-bit system, the starting address and size of heterogeneous variable-length information are typically both 4 bytes. The space size is 256 bytes, while on a 64-bit system, the starting address and size of heterogeneous variable-length information are usually both 8 bytes. The space size is 512 bytes. , , , The specific code for its development is existing technology and will not be elaborated upon here; The method for initializing the two-level RingBuffer structure is as follows: The write and read pointers of the first ring buffer are both set to the start position of the cell buffer, and the write and read pointers of the second ring buffer are both set to the start position of the data buffer. The start position is generally represented by 0. The initialized two-level RingBuffer structure is as follows: Figure 2 As shown, the red arrow represents the write pointer, the blue arrow represents the write pointer, the inner circle represents the cell buffer, and the outer circle represents the data buffer. In this state, read operations cannot be performed, but write operations can be performed. S2, based on the write full prediction, determines whether to perform a write operation, and when performing a write operation, writes the starting position of the heterogeneous variable length information and the actual written data length to the cell buffer, and writes the original data of the heterogeneous variable length information to the data buffer; The logic for executing the full prediction is as follows: 1) Based on the write pointer position and read pointer position of the first ring buffer, determine the remaining space for write operations in the cell buffer. The mathematical expression is as follows: In the formula, This represents the remaining space in the cell buffer after a write operation. , These represent the write pointer position and read pointer position of the first circular buffer, respectively. The setting of 1 ensures that the cell buffer must reserve one cell. The write space, This indicates the size of the unit buffer, in bytes. 2) Based on the write pointer position and read pointer position of the second ring buffer, determine the remaining space for write operations in the data buffer. The mathematical expression is as follows: In the formula, This represents the remaining space in the data buffer after a write operation. , These represent the write pointer position and read pointer position of the second ring buffer, respectively. The setting of 1 ensures that the data buffer must reserve one byte of write space. This indicates the size of the data buffer, in bytes. 3) Based on the remaining space for write operations in the cell buffer and the remaining space for write operations in the data buffer, a write-full pre-judgment is performed. If both are greater than 0, it is judged as not full and a write operation is performed; otherwise, it is judged as full and no write operation is performed. As one implementation method, the above-mentioned full-write prediction can be divided into three full-write states and one non-full-write state, as detailed in Table 1 and below. Figures 3-6 As shown; Table 1, filled with prediction classification table

[0023] It should be noted that the above-mentioned full state (Ⅰ) generally appears in scenarios where heterogeneous variable length information is relatively short and fragmented, while the full state (Ⅱ) generally appears in scenarios where heterogeneous variable length information is relatively long, and the full state (Ⅲ) generally appears in scenarios where heterogeneous variable length information is of moderate length. The logic for performing a write operation is as follows: 1) Select the length of the heterogeneous variable-length information data to be written to the data buffer, and the minimum value of the remaining space in the data buffer for write operations, as the actual write length of the heterogeneous variable-length information. Starting from the first byte of the original data of the heterogeneous variable-length information, extract original data of the same length as the actual write length and write it into the data buffer. The mathematical expression for determining the actual write length is as follows: In the formula, This indicates the actual length of data written, in bytes. This indicates the length of the heterogeneous variable-length information data requested to be written to the data buffer, i.e., the size of the heterogeneous variable-length information, also in bytes. This indicates taking the minimum value; 2) Before the heterogeneous variable-length information to be written is written, the write pointer position of the second ring buffer is used as the starting address of the heterogeneous variable-length information, so as to write the starting address of the heterogeneous variable-length information and the actual written data length into the cell buffer. 3) After writing the heterogeneous variable-length information, update the write pointer positions of the first ring buffer and the second ring buffer. The mathematical expression is as follows: In the formula, This indicates the position of the write pointer after the first ring buffer has been updated. This indicates the write pointer position of the first ring buffer before writing heterogeneous variable-length information; In the formula, This indicates the updated write pointer position of the second ring buffer. This indicates the write pointer position of the second ring buffer before writing heterogeneous variable-length information; As one implementation, after writing three heterogeneous variable-length messages consecutively to the bipolar RingBuffer structure, the write pointer positions of the first and second ring buffers are updated as follows: Figure 7 As shown below, Figure 7 The table below shows the write pointer position update status after writing three heterogeneous variable-length information items in a clockwise direction. Figure 7 The red, cyan, and yellow filled parts represent the written heterogeneous variable-length information, the solid red arrow represents the final update position of the write pointer, and the dashed red arrow represents the intermediate update state of the write pointer during the process of writing three heterogeneous variable-length information one by one. S3 determines whether to perform a read operation based on read empty prediction, and when performing a read operation, first reads the starting position and actual written data length of the heterogeneous variable length information based on the cell buffer, and then reads the original data of the heterogeneous variable length information from the data buffer based on the actual written data length of the heterogeneous variable length information. The logic for performing the read-empty prediction is as follows: 1) Based on the write pointer position and read pointer position of the first ring buffer, determine the remaining space for read operations in the cell buffer. The mathematical expression is as follows: In the formula, This indicates the remaining space in the cell buffer after a read operation. 2) Based on the write pointer position and read pointer position of the second ring buffer, determine the remaining space for read operations in the data buffer. The mathematical expression is as follows: In the formula, This indicates the remaining space in the data buffer after a read operation. 3) Based on the remaining space of the read operation in the cell buffer and the remaining space of the read operation in the data buffer, a read empty pre-judgment is performed. If both are greater than 0, it is judged as not empty and a read operation is performed. Otherwise, it is judged as empty and no read operation is performed. As one implementation method, the above-mentioned read-empty prediction can be divided into three read-empty states and one unread-empty state, as detailed in Table 2 and below. Figures 8-11 As shown; Table 2, Classification Table of Reading Prediction

[0024] It should be noted that the above-mentioned empty state (Ⅰ) generally appears in scenarios where heterogeneous variable length information is relatively short and fragmented, while the empty state (Ⅱ) generally appears in scenarios where heterogeneous variable length information is relatively long, and the empty state (Ⅲ) generally appears in scenarios where heterogeneous variable length information is of moderate length. The logic for performing a read operation is as follows: 1) Read the actual written data length of the requested heterogeneous variable-length information from the cell buffer, and then read data of the same length from the data buffer based on the actual written data length as the original data to be read from the heterogeneous variable-length information. 2) After reading the heterogeneous variable-length information, update the read pointer positions of the first ring buffer and the second ring buffer. The mathematical expression is as follows: In the formula, This indicates the updated read pointer position of the first ring buffer. This indicates the read pointer position of the first ring buffer before reading heterogeneous variable-length information; In the formula, This indicates the updated read pointer position of the second ring buffer. This indicates the read pointer position of the second ring buffer before reading heterogeneous variable-length information. This indicates the length of the original data read from the heterogeneous variable-length information, and its value is the same as the actual length of the data written to the heterogeneous variable-length information. As one implementation, after continuously reading three heterogeneous variable-length messages from the bipolar RingBuffer structure, the read pointer positions of the first and second ring buffers are updated as follows: Figure 12 As shown below, Figure 12 The table below shows the read pointer position update status after reading three heterogeneous variable-length information items in a clockwise direction. Figure 12 The red, cyan, and yellow filled parts represent the read heterogeneous variable-length information, respectively. The solid blue arrow represents the final update position of the read pointer, and the dashed blue arrow represents the intermediate update state of the read pointer during the process of reading three heterogeneous variable-length information one by one. In the application scenario of this embodiment, in order to realize bidirectional communication between the ARM Cortex-M7 core and the Cortex-M4 core in STM32H745BIT6, two sets of two-level RingBuffer structures are designed. One set is used for Cortex-M4 core to send and ARM Cortex-M7 core to receive, and the other set is used for ARM Cortex-M7 core to send and Cortex-M4 core to receive. In practical applications, because the content of STM32H745BIT6 inter-core communication is diverse, such as ASCII streams in string form, uint8 format code streams, or code streams in specific protocol formats, the single-level RingBuffer structure cannot effectively solve the boundary definition of each piece of information. However, after adopting the two-level RingBuffer structure of this technical solution, the correct transmission of heterogeneous variable-length information under different forms can be guaranteed, thereby ensuring the integrity and correctness of inter-core communication. Compared with fixed-length protocols, it has the advantage of high space utilization, and compared with delimiter protocols, it has the advantage of wide application scenarios without restrictions, effectively solving the pain points and difficulties of existing solutions. Furthermore, during the operation of the two-level RingBuffer structure, the capacity of the cell buffer or data buffer is updated in real time based on the remaining space for write operations in the cell buffer and the remaining space for write operations in the data buffer. The specific logic is as follows: 1) During the operation of the two-level RingBuffer structure, the remaining space of the write operation of the unit buffer and the remaining space of the write operation of the data buffer are collected in real time based on a fixed sampling interval to determine the idle proportion of the unit buffer and the idle proportion of the data buffer at each sampling time, and the ratio of the two is calculated to determine the space utilization balance coefficient at each sampling time. Specifically, for any sampling time, the ratio of the remaining space for write operations in the unit buffer to the size of the unit buffer space at that sampling time is calculated as the free proportion of the unit buffer at that sampling time. The larger the value, the more remaining writable space the unit buffer has at that sampling time. Specifically, for any sampling time, the ratio of the remaining space for write operations in the data buffer to the size of the data buffer space at that sampling time is calculated as the free proportion of the data buffer at that sampling time. The larger the value, the more remaining writable space the data buffer has at that sampling time. It should be noted that the closer the free percentage of the cell buffer and the free percentage of the data buffer are at a given sampling time, the closer the free levels of the cell buffer and data buffer in the two-level RingBuffer structure are at that sampling time, the closer the space utilization balance coefficient is to 1, and the better the space utilization balance. Conversely, if the free percentage of the cell buffer is significantly higher than the free percentage of the data buffer at a given sampling time, it indicates that too little data is written to the cell buffer of the two-level RingBuffer structure, while too much data is written to the data buffer. This situation is generally caused by writing heterogeneous variable-length information, and the space utilization balance coefficient is thus larger. The greater the deviation along the direction greater than 1, the worse the space utilization balance. It may be necessary to increase the data buffer capacity or decrease the cell buffer capacity. If the degree to which the free percentage of the cell buffer is lower than the free percentage of the data buffer at a sampling time is greater, it means that at this sampling time, too much data is written in the cell buffer of the two-level RingBuffer structure, while too little data is written in the data buffer. This situation is generally caused by the relatively short and fragmented heterogeneous variable length information being written. The smaller the space utilization balance coefficient, the greater the deviation along the direction less than 1, and the worse the space utilization balance. It may be necessary to decrease the data buffer capacity or increase the cell buffer capacity. 2) Combining the space utilization equalization coefficient and the preset space utilization equalization threshold, each sampling time is classified into times to be adjusted positively, times to be adjusted in the same direction, or times to be adjusted negatively. The specific logic is as follows: The space utilization balancing threshold includes a first space utilization balancing threshold and a second space utilization balancing threshold. The first space utilization balancing threshold is greater than 1, and the second space utilization balancing threshold is less than 1. If the space utilization balancing coefficient at a sampling time is higher than the first space utilization balancing threshold, then this sampling time is designated as the time to be adjusted positively. This indicates that the two-level RingBuffer structure tends to increase the data buffer capacity or decrease the unit buffer capacity at this sampling time. If the space utilization balancing coefficient at a sampling time is lower than the second space utilization balancing threshold, then this sampling time is designated as the time to be adjusted negatively. This indicates that the two-level RingBuffer structure tends to decrease the data buffer capacity or increase the unit buffer capacity at this sampling time. If the space utilization balancing coefficient at a sampling time is not lower than the second space utilization balancing threshold and not higher than the first space utilization balancing threshold, then this sampling time is designated as the time to be adjusted in the same direction. This indicates that at this sampling time, the utilization ratio of the unit buffer and data buffer capacity of the two-level RingBuffer structure is relatively balanced, and it tends not to adjust the capacity of the unit buffer and data buffer, or adjust the capacity of the unit buffer and data buffer proportionally according to the actual situation. It should be noted that the specific values ​​of the first space utilization equalization threshold and the second space utilization equalization threshold are set by the staff according to the actual situation. For example, the value of the first space utilization equalization threshold can be set between 1.2 and 1.4, and the value of the second space utilization equalization threshold can be set between 0.6 and 0.8. This is to classify each sampling time and provide a basis for subsequent analysis of each monitoring window to determine the final adjustment plan. 3) Set an observation window based on the current sampling time, and determine the dominant adjustment strategy based on the frequency of occurrence of the time to be positively adjusted, the frequency of occurrence of the time to be adjusted in the same direction, and the frequency of occurrence of the time to be negatively adjusted in the observation window. The dominant adjustment strategy is a positive adjustment strategy, a negative adjustment strategy, or a same-direction adjustment strategy. It should be noted that the specific value of the sampling interval is set by the staff according to the actual situation, such as 30 minutes, 1 hour, 2 hours, etc., without any restrictions. The current sampling time is the latest sampling time, which is updated in real time as the sampling process proceeds. The capacity of the unit buffer or data buffer is adjusted and updated after each latest sampling, thus achieving the effect of real-time capacity update. The monitoring window ends at the real time, and its time length can generally be set to 6 hours, 12 hours, 24 hours, etc., to encompass the current sampling time and several previous sampling times. The setting of the monitoring window facilitates the observation of the overall trend of the remaining space in the write operation. Compared with analysis based solely on the current sampling time, it effectively suppresses the adverse effects of data fluctuations. The logic for determining the frequency of occurrence of the positive adjustment time, the same-direction adjustment time, and the negative adjustment time is as follows: calculate the ratio of the number of times the positive adjustment time appears in the observation window to the total number of sampling times in the observation window, and use this as the frequency of occurrence of the positive adjustment time; calculate the ratio of the number of times the same-direction adjustment time appears in the observation window to the total number of sampling times in the observation window, and use this as the frequency of occurrence of the same-direction adjustment time; calculate the ratio of the number of times the negative adjustment time appears in the observation window to the total number of sampling times in the observation window, and use this as the frequency of occurrence of the negative adjustment time. The logic for determining the dominant adjustment strategy is as follows: Based on the frequency of occurrence of times to be positively adjusted, times to be adjusted in the same direction, and times to be negatively adjusted, it is determined whether there is a frequency higher than the frequency threshold, which is a decimal greater than 0.5. If not, it means that there is no dominant time type within the observation window, that is, the cell buffer and data buffer of the two-level RingBuffer structure are not significantly unbalanced within the observation window. In this case, the same-direction adjustment strategy is executed, which means either not adjusting the capacity of the cell buffer and the data buffer, or adjusting the capacity of the cell buffer and the data buffer proportionally. If the frequency of same-direction adjustment times is higher than the frequency threshold, it indicates that same-direction adjustment times are the dominant time type within the observation window, and the space utilization of the cell buffer and data buffer of the two-level RingBuffer structure is relatively balanced. In this case, the same-direction adjustment strategy is executed. If the frequency of the positive adjustment time exceeds the frequency threshold, it indicates that the positive adjustment time is the dominant time type within the observation window. The data written to the cell buffer of the two-level RingBuffer structure is too little, while the data buffer is written too much. In this case, the positive adjustment strategy is executed, which is to increase the data buffer capacity or decrease the cell buffer capacity. If the frequency of the negative adjustment time exceeds the frequency threshold, it indicates that the negative adjustment time is the dominant time type within the observation window. Too much data is written to the cell buffer of the two-level RingBuffer structure, while too little data is written to the data buffer. In this case, a negative adjustment strategy is executed, which is to reduce the data buffer capacity or increase the cell buffer capacity. 4) Combining the dominant adjustment strategy, the first idle percentage threshold, the second idle percentage threshold, the idle percentage of the cell buffer within the observation window, and the idle percentage of the data buffer, determine the final adjustment strategy. The first idle percentage threshold is less than the second idle percentage threshold. The logic for determining the final adjustment strategy is as follows: The percentage of idle unit buffers and the percentage of idle data buffers at each sampling time within the observation window are statistically analyzed to determine the average percentage of idle unit buffers and the average percentage of idle data buffers within the observation window. Under the dominant adjustment strategy of unidirectional adjustment, if the minimum value of the average free percentage of the unit buffer and the average free percentage of the data buffer within the observation window is lower than the first free percentage threshold, it indicates that the remaining space for write operations in the unit buffer and data buffer of the two-level RingBuffer structure is small within the observation window. In this case, the capacity of the unit buffer and data buffer is increased proportionally according to a fixed adjustment ratio to avoid the problem of being unable to continue writing heterogeneous variable-length information. If the maximum value of the average free percentage of the unit buffer and the average free percentage of the data buffer within the observation window is higher than the second free percentage threshold, it indicates that the remaining space for write operations in the unit buffer and data buffer of the two-level RingBuffer structure is large within the observation window. In this case, the capacity of the unit buffer and data buffer is decreased proportionally according to a fixed adjustment ratio to avoid the problem of unnecessary memory waste. If neither of the above two conditions is met, it indicates that the remaining space for write operations in the unit buffer and data buffer is moderate, and the capacity of the unit buffer and data buffer is not adjusted. Under the dominant adjustment strategy of positive adjustment, if the average free percentage of the data buffer within the observation window is lower than the first free percentage threshold, it indicates that there is little remaining space for write operations in the data buffer. In this case, the capacity of the data buffer is increased by a fixed adjustment ratio to avoid the problem of being unable to continue writing heterogeneous variable-length information. Conversely, if the average free percentage of the data buffer is higher than the first free percentage threshold, it indicates that the data buffer still has sufficient remaining space for write operations. In this case, the capacity of the unit buffer is reduced by a fixed adjustment ratio to avoid unnecessary memory waste. Under the dominant adjustment strategy of negative adjustment strategy, if the average free percentage of the unit buffer in the observation window is lower than the first free percentage threshold, it means that there is little remaining space for write operations in the unit buffer. In this case, the capacity of the unit buffer is increased by a fixed adjustment ratio to avoid the problem of being unable to continue writing heterogeneous variable length information. Conversely, if the average free percentage of the unit buffer is higher than the threshold, it means that there is still sufficient remaining space for write operations in the unit buffer. In this case, the capacity of the data buffer is reduced by a fixed adjustment ratio to avoid the problem of unnecessary memory waste. It should be noted that the specific value of the frequency threshold is set by the staff according to the actual situation. For example, it can be set between 0.6 and 0.8 to find the dominant time type. The first idle percentage threshold is used to distinguish whether the remaining capacity percentage is urgent, and its value can be set between 5% and 10%. The second idle percentage threshold is used to distinguish whether the remaining capacity percentage is too abundant, and its value can be set between 70% and 90%. The specific value is also set by the staff according to the actual situation, and will not be elaborated here. Since a capacity adjustment is performed every time a new sample is taken, the single adjustment does not need to be too large to avoid the problem of over-adjustment. The adjustment ratio can generally be set between 10% and 20% to make the capacity adjustment more gradual. When increasing the capacity according to a fixed adjustment ratio, the sum of the first value and the adjustment ratio is multiplied by the capacity to obtain the increased capacity. When decreasing the capacity according to a fixed adjustment ratio, the difference between the first value and the adjustment ratio is multiplied by the capacity to obtain the decreased capacity. If the adjusted capacity has a decimal, it is rounded up to avoid the problem of meaningless decimals.

[0025] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0026] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above embodiments can be implemented, in whole or in part, as a computer program product. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution.

[0027] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0028] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for heterogeneous information communication between chip cores using a two-level RingBuffer structure, characterized in that, Includes the following steps: S1, construct and initialize a two-level RingBuffer structure, which consists of a first ring buffer including a first ring buffer and a cell buffer, and a second ring buffer including a second ring buffer and a data buffer; S2, based on the write full prediction, determines whether to perform a write operation, and when performing a write operation, writes the starting position of the heterogeneous variable length information and the actual written data length to the cell buffer, and writes the original data of the heterogeneous variable length information to the data buffer; S3 determines whether to perform a read operation based on read empty prediction. When performing a read operation, it first reads the starting position and actual written data length of the heterogeneous variable length information based on the cell buffer, and then reads the original data of the heterogeneous variable length information from the data buffer based on the actual written data length of the heterogeneous variable length information.

2. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 1, characterized in that: The unit buffer is used to store the starting address of the heterogeneous variable length information and the actual written data length. The actual written data length is determined based on the heterogeneous variable length information data length and the remaining space of the data buffer for write operations. The first ring buffer is a component used to manage the state of the unit buffer. The data buffer is used to store the raw data of heterogeneous variable-length information, and the second ring buffer is a component used to manage the state of the data buffer.

3. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 1, characterized in that, The method for initializing a two-level RingBuffer structure is as follows: both the write pointer and read pointer of the first ring buffer are set to the beginning of the cell buffer, and both the write pointer and read pointer of the second ring buffer are set to the beginning of the data buffer.

4. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 1, characterized in that, The logic for executing the full prediction is as follows: 1) Determine the remaining space for write operations in the cell buffer based on the write pointer position and read pointer position of the first ring buffer; 2) Determine the remaining space for write operations in the data buffer based on the write pointer position and read pointer position of the second ring buffer; 3) Based on the remaining space for write operations in the cell buffer and the remaining space for write operations in the data buffer, a write-full pre-judgment is performed. If both are greater than 0, it is judged as not full and a write operation is performed; otherwise, it is judged as full and no write operation is performed.

5. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 4, characterized in that, The logic for performing a write operation is as follows: 1) Select the length of the heterogeneous variable-length information data to be written to the data buffer, and the minimum value in the remaining space of the data buffer for the write operation, as the actual write length of the heterogeneous variable-length information. Starting from the first byte of the original data of the heterogeneous variable-length information, extract the original data of the same length as the actual write length and write it into the data buffer. 2) Before the heterogeneous variable-length information to be written is written, the write pointer position of the second ring buffer is used as the starting address of the heterogeneous variable-length information, so as to write the starting address of the heterogeneous variable-length information and the actual written data length into the cell buffer. 3) After writing the heterogeneous variable-length information, update the write pointer position of the first ring buffer and the write pointer position of the second ring buffer.

6. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 1, characterized in that, The logic for performing a read-and-predict check is as follows: 1) Determine the remaining space for read operations in the cell buffer based on the write pointer position and read pointer position of the first ring buffer; 2) Based on the write pointer position and read pointer position of the second ring buffer, determine the remaining space for read operations in the data buffer. 3) Based on the remaining space of the read operation in the cell buffer and the remaining space of the read operation in the data buffer, a read empty pre-judgment is performed. If both are greater than 0, it is judged as not empty and a read operation is performed. Otherwise, it is judged as empty and no read operation is performed.

7. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 6, characterized in that, The logic for performing a read operation is as follows: 1) Read the actual written data length of the requested heterogeneous variable-length information from the cell buffer, and then read data of the same length from the data buffer based on the actual written data length as the original data to be read from the heterogeneous variable-length information. 2) After reading the heterogeneous variable-length information, update the read pointer position of the first ring buffer and the read pointer position of the second ring buffer.

8. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 4, characterized in that, During the operation of the two-level RingBuffer structure, the capacity of the cell buffer or data buffer is updated in real time based on the remaining space for write operations in the cell buffer and the remaining space for write operations in the data buffer. The specific logic is as follows: 1) During the operation of the two-level RingBuffer structure, the remaining space of the write operation of the unit buffer and the remaining space of the write operation of the data buffer are collected in real time based on a fixed sampling interval to determine the idle proportion of the unit buffer and the idle proportion of the data buffer at each sampling time, and the ratio of the two is calculated to determine the space utilization balance coefficient at each sampling time. 2) Combining the space utilization equalization coefficient and the preset space utilization equalization threshold, each sampling time is classified into times to be adjusted in the positive direction, times to be adjusted in the same direction, or times to be adjusted in the negative direction. 3) Set an observation window based on the current sampling time, and determine the dominant adjustment strategy based on the frequency of occurrence of the time to be positively adjusted, the frequency of occurrence of the time to be adjusted in the same direction, and the frequency of occurrence of the time to be negatively adjusted in the observation window. The dominant adjustment strategy is a positive adjustment strategy, a negative adjustment strategy, or a same-direction adjustment strategy. 4) Combine the dominant adjustment strategy, the first idle percentage threshold, the second idle percentage threshold, the idle percentage of the cell buffer and the idle percentage of the data buffer within the observation window to determine the final adjustment strategy, where the first idle percentage threshold is less than the second idle percentage threshold.

9. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 8, characterized in that, The calculation logic for the idle percentage of the cell buffer and the idle percentage of the data buffer at each sampling time is as follows: For any sampling time, calculate the ratio of the remaining space of the cell buffer for write operations to the size of the cell buffer at that sampling time, as the idle percentage of the cell buffer at that sampling time; and calculate the ratio of the remaining space of the data buffer for write operations to the size of the data buffer at that sampling time, as the idle percentage of the data buffer at that sampling time. The logic for classifying each sampling time is as follows: the space utilization equalization threshold includes a first space utilization equalization threshold and a second space utilization equalization threshold, and the first space utilization equalization threshold is greater than 1, and the second space utilization equalization threshold is less than 1. If the space utilization equalization coefficient at a sampling time is higher than the first space utilization equalization threshold, then this sampling time is classified as a time to be positively adjusted. If the space utilization equalization coefficient at a sampling time is lower than the second space utilization equalization threshold, then this sampling time is classified as a time to be negatively adjusted. If the space utilization equalization coefficient at a sampling time is not lower than the second space utilization equalization threshold and not higher than the first space utilization equalization threshold, then this sampling time is classified as a time to be adjusted in the same direction.

10. The method for heterogeneous information communication between chip cores using a two-level RingBuffer structure according to claim 8, characterized in that, The logic for determining the dominant adjustment strategy is as follows: Based on the frequency of occurrence of the time to be positively adjusted, the frequency of occurrence of the time to be adjusted in the same direction, and the frequency of occurrence of the time to be negatively adjusted, it is determined whether there is a frequency higher than the frequency threshold. The frequency threshold is a decimal greater than 0.

5. If there is no such frequency, the same-direction adjustment strategy is executed. The same-direction adjustment strategy is to either not adjust the capacity of the cell buffer and the data buffer, or to adjust the capacity of the cell buffer and the data buffer proportionally. If the frequency of same-direction adjustment times exceeds the frequency threshold, then the same-direction adjustment strategy is executed; If the frequency of the positive adjustment occurs higher than the frequency threshold, then the positive adjustment strategy is executed. The positive adjustment strategy is to increase the data buffer capacity or decrease the cell buffer capacity. If the frequency of the negative adjustment time exceeds the frequency threshold, the negative adjustment strategy is executed. The negative adjustment strategy is to reduce the data buffer capacity or increase the cell buffer capacity. The logic for determining the final adjustment strategy is as follows: The percentage of idle unit buffers and the percentage of idle data buffers at each sampling time within the observation window are statistically analyzed to determine the average percentage of idle unit buffers and the average percentage of idle data buffers within the observation window. Under the dominant adjustment strategy of same direction adjustment, if the minimum value of the average idle percentage of the unit buffer and the average idle percentage of the data buffer within the observation window is lower than the first idle percentage threshold, the capacity of the unit buffer and the data buffer will be increased proportionally according to a fixed adjustment ratio. If the maximum value of the average idle percentage of the unit buffer and the average idle percentage of the data buffer within the observation window is higher than the second idle percentage threshold, the capacity of the unit buffer and the data buffer will be decreased proportionally according to a fixed adjustment ratio. If neither of the above two conditions is met, the capacity of the unit buffer and the data buffer will not be adjusted. Under the dominant adjustment strategy of positive adjustment, if the average idle percentage of the data buffer within the observation window is lower than the first idle percentage threshold, the capacity of the data buffer is increased by a fixed adjustment ratio, and vice versa. When the dominant adjustment strategy is a negative adjustment strategy, if the average idle percentage of the cell buffer within the observation window is lower than the first idle percentage threshold, the capacity of the cell buffer is increased by a fixed adjustment ratio; otherwise, the capacity of the data buffer is decreased by a fixed adjustment ratio.

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