Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device. The display panel comprises a gate drive circuit, and the gate drive circuit comprises a shift register. The shift register comprises an output module which responds to a signal of a first output control node and writes a signal of a first clock end into an output end; the first pull-down module responds to the signal of the first control end and writes the signal of the first signal line into the first output control node; the bias voltage transfer module comprises a capacitor unit, a first unit, a second unit and a third unit; the capacitor unit is connected between the first node and the second node; the first unit responds to a signal of a first control end and writes a signal of a second signal line into a first node; the second unit responds to the signal of the first node and writes the signal of the third signal line into the second node; the third unit writes a signal of a fourth signal line to the first output control node in response to a signal of the second node.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display, in particular to a display panel, a driving method thereof and a display device. BACKGROUND

[0002] The in-cell touch display panel can adopt in-frame touch driving, which is also called Long-H driving, that is, adding a pit for touch scanning in the display process of a frame. This driving mode can realize multiple touch sampling in a frame, for example, a display panel with a refresh frequency of 60Hz can realize a touch report rate of 120Hz.

[0003] However, at present, the display panel is prone to horizontal stripe problems in Long-H driving mode, which damages the picture uniformity and further leads to a decrease in display quality. SUMMARY

[0004] The present application provides a display panel, a driving method thereof and a display device, which are used to effectively improve the horizontal stripe phenomenon of the display panel in Long-H driving mode.

[0005] In a first aspect, the present application provides a display panel, comprising a gate drive circuit, the gate drive circuit comprising a plurality of shift registers cascaded; wherein the shift register comprises: an output module, electrically connected with a first output control node, a first clock terminal and an output terminal, for writing the signal of the first clock terminal into the output terminal in response to the signal of the first output control node; a first pull-down module, electrically connected with a first control terminal, a first signal line and the first output control node, for writing the signal of the first signal line into the first output control node in response to the signal of the first control terminal; a bias transfer module, comprising a capacitor unit, a first unit, a second unit and a third unit; wherein the capacitor unit is electrically connected between a first node and a second node; the first unit is electrically connected with the first control terminal, a second signal line and the first node, for writing the signal of the second signal line into the first node in response to the signal of the first control terminal; the second unit is electrically connected with the first node, a third signal line and the second node, for writing the signal of the third signal line into the second node in response to the signal of the first node; the third unit is electrically connected with the second node, a fourth signal line and the first output control node, for writing the signal of the fourth signal line into the first output control node in response to the signal of the second node.

[0006] In a second aspect, based on the same inventive concept, the present application further provides a driving method of a display panel, the display panel comprising a gate drive circuit, the gate drive circuit comprising a plurality of shift registers cascaded; wherein the shift register comprises: an output module, electrically connected with a first output control node, a first clock terminal and an output terminal; The first pull-down module is electrically connected to the first control terminal, the first signal line and the first output control node; The bias transfer module includes a capacitor unit, a first unit, a second unit, and a third unit; wherein, the capacitor unit is electrically connected between the first node and the second node, the first unit is electrically connected to the first control terminal, the second signal line, and the first node, the second unit is electrically connected to the first node, the third signal line, and the second node, and the third unit is electrically connected to the second node, the fourth signal line, and the first output control node; The driving method for the display panel includes controlling the gate driving circuit to output a driving signal, wherein the operation of the shift register in the gate driving circuit includes: The first pull-down module responds to the signal from the first control terminal and writes the signal from the first signal line into the first output control node; The first unit responds to the signal from the first control terminal and writes the signal of the second signal line into the first node; the second unit responds to the signal from the first node and writes the signal of the third signal line into the second node; the third unit responds to the signal from the second node and writes the signal of the fourth signal line into the first output control node. The output module responds to the signal from the first output control node and writes the signal from the first clock terminal to the output terminal.

[0007] Thirdly, based on the same inventive concept, the present invention also provides a display device, including the display panel of the present invention.

[0008] Compared with the prior art, the display panel, driving method, and display device provided by the present invention achieve at least the following beneficial effects: The display panel provided by this invention includes a gate driving circuit, which includes multiple cascaded shift registers. Each shift register includes: an output module electrically connected to a first output control node, a first clock terminal, and an output terminal, used to write the signal from the first clock terminal to the output terminal in response to a signal from the first output control node; a first pull-down module electrically connected to a first control terminal, a first signal line, and the first output control node, used to write the signal from the first signal line to the first output control node in response to a signal from the first control terminal; and a bias transfer module including a capacitor unit, a first unit, a second unit, and a third unit. The capacitor unit is electrically connected between the first node and the second node. The first unit is electrically connected to the first control terminal, the second signal line, and the first node, used to write the signal from the second signal line to the first node in response to a signal from the first control terminal; the second unit is electrically connected to the first node, the third signal line, and the second node, used to write the signal from the third signal line to the second node in response to a signal from the first node; and the third unit is electrically connected to the second node, a fourth signal line, and the first output control node, used to write the signal from the fourth signal line to the first output control node in response to a signal from the second node.

[0009] The display panel provided by this invention can adopt a Long-H driving mode. The display process of one frame includes multiple line scanning periods. The shift register outputs a high level during the line scanning period, and a touch period is inserted between at least some of the adjacent line scanning periods.

[0010] The following explanation uses the example of a touch-enabled period that occurs between the row scan periods corresponding to the (n-1)th level shift register and the nth level shift register.

[0011] During the process of the (n-1)th stage shift register outputting a high level, the first control terminal connected to the first pull-down module in the nth stage shift register provides a high level, the first signal line provides a low level, and the second signal line provides a high level. In the nth stage shift register, the first pull-down module is enabled, writing the low level of the first signal line to the first output control node to prevent the first output control node from being pulled high additionally. Simultaneously, the first cell is enabled, writing the high level of the second signal line to the first node to charge the capacitor cell.

[0012] During the touch period, the first control terminal connected to the first pull-down module in the nth-level shift register is at a low level, and the capacitor unit in the nth-level shift register continues to store the potential.

[0013] After the touch period ends, both the third and fourth signal lines provide a high level. In the nth stage shift register, the signal on the third signal line jumps high. Based on the actions of the second unit and the capacitor unit, the first node bootstraps, and its potential is raised. The second unit writes the high level of the third signal line into the second node, charging the second node. The third unit responds to the high level of the second node by writing the high level of the fourth signal line into the first output control node.

[0014] In the above process, during the high-level output of the (n-1)th stage shift register before touch, the first pull-down module in the nth stage shift register sets the voltage of the first output control node low, and the first unit in the bias transfer module charges the capacitor unit, thus storing the voltage of the first output control node in the bias transfer module. After the touch ends, the bias transfer module releases it back to the first output control node, thereby preparing for the nth stage shift register to output a high level, so that the subsequent nth stage shift register can continue to output a high level, achieving the continuity of the effective output level of the subsequent shift registers.

[0015] Furthermore, in the bias transfer module of the present invention, before touch, the capacitor unit is charged using the first unit. This charging process does not involve the function of the first output control node. Therefore, there is no need to pull the first output control node high before touch, thus eliminating the additional bias voltage of the first output control node before touch. Moreover, after touch ends, by using the third unit to control the high-time of the first output control node, the first output control node will not have any additional bias voltage after touch.

[0016] In summary, this invention can eliminate the additional bias voltage of the first output control node to a greater extent, and the output signal delay of the stop-hole level shift register will not change abruptly. It can more effectively provide the signal consistency between the stop-hole level shift register and other conventional level shift registers, and better improve the horizontal stripe phenomenon. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a shift register in related technologies; Figure 2 This is a timing diagram in related technologies; Figure 3 This is a schematic diagram of the IV curve variation of a transistor. Figure 4 This is another schematic diagram of a shift register in related technologies; Figure 5 This is another timing diagram in related technologies; Figure 6 A schematic diagram of a display panel provided by the present invention; Figure 7 A schematic diagram of a shift register provided by the present invention; Figure 8 Another schematic diagram of the shift register provided by the present invention; Figure 9 This is a schematic diagram illustrating a connection between a shift register and signal lines provided by the present invention. Figure 10 A timing diagram provided by the present invention; Figure 11 Another timing diagram provided by the present invention; Figure 12This is a schematic diagram of a display device provided by the present invention. Detailed Implementation

[0019] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0021] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0023] Before describing the technical solutions provided by the embodiments of the present invention, the present invention first explains the technical problems existing in the related art: The display panel includes a gate driving circuit, which includes multiple cascaded shift registers. The display process of one frame includes multiple line scan periods. The multiple shift registers output scan signals to the pixel circuits line by line to drive the scanning of one line of pixel circuits within one line scan period.

[0024] Figure 1 This is a schematic diagram of a shift register in related technologies, such as... Figure 1 As shown, the shift register 101 includes a control module 102, a pull-up node PU, a pull-down node PD, and an output module 103. The control module 102 is used to write signals to the pull-up node PU and the pull-down node PD, and the output module 103 is used to output an effective level (high level) for at least a portion of the time period when the pull-up node PU is high, and to output an ineffective level (low level) when the pull-down node PD is high.

[0025] When the display panel is in Long-H driving mode, it will add slots for touch scanning during at least part of the adjacent row scanning period.

[0026] The following example illustrates how a touch segment is inserted between the high-level outputs of the (n-1)th level shift register 101(n-1) and the nth level shift register 101(n).

[0027] Figure 2 This is a timing diagram in related technologies, combined with Figure 1 and Figure 2 The display cycle of one frame includes a first time period t1, a touch time period tp, and a second time period t2. In the first time period t1, the (n-1)th level shift register 101(n-1) outputs a high level; the touch time period tp is located between the first time period t1 and the second time period t2, and touch scanning is performed within the touch time period tp; in the second time period t2, the nth level shift register 101(n) outputs a high level.

[0028] When the (n-1)th stage shift register 101(n-1) outputs a high level, the nth stage shift register 101(n) is already in a ready-to-start state, and its pull-up node PU(n) has also completed initial charging. The high potential of the pull-up node PU(n) will be maintained until the touch ends, so that the output module 103 of the nth stage shift register 101(n) can respond to the high level of the pull-up node PU(n) and output a high level in the second time period t2.

[0029] However, this would cause the pull-up node PU(n) in the nth stage shift register 101(n) to remain in the high position for a long time, thus creating an additional bias voltage for an extended period (see...). Figure 2 (Process A in the process). After the display panel has been operating in a high-temperature environment for a long time, this additional bias voltage will cause electrons in the output transistor connected to the pull-up node PU(n) in the nth stage shift register 101(n) to be trapped by oxide layer traps, resulting in an increase in interface trap density. Figure 3 This is a schematic diagram of the IV curve variation of a transistor, such as... Figure 3 As shown, this will further cause the threshold voltage of the output transistor to drift positively, changing its device characteristics. Consequently, the device characteristics of this output transistor in the nth stage shift register 101(n) will differ significantly from those of the output transistors in other stages of shift register 101, resulting in abnormal output of the nth stage shift register 101(n) and causing regular horizontal stripe problems.

[0030] In response to this issue, Figure 4 This is another schematic diagram of a shift register in related technologies, such as... Figure 4As shown, the related technology proposes that a bias transfer module 104 connected to the pull-up node PU can be added to the shift register 101, and the potential of the pull-up node PU can be stored using the capacitor in the bias transfer module 104. For the nth stage shift register 101(n), before entering the touch period tp, the capacitor in the bias transfer module 104 is fully charged. During the touch period tp, the path used to control the charging and discharging of the capacitor in the bias transfer module 104 is cut off. After the touch period tp ends, the capacitor returns the stored potential to the pull-up node PU(n) through the charging and discharging path, pulling the potential of the pull-up node PU(n) high, so that the output module 103 of the nth stage shift register 101(n) can output a high level normally in the second period t2.

[0031] However, based on the existing structure of the bias transfer module 104, before the touch period tp, the charging of the capacitor in the bias transfer module 104 is achieved using the pull-up node PU(n). Figure 5 Another timing diagram in related technologies, such as Figure 5 As shown, this means that the pull-up node PU(n) needs to be pulled high again before touch, resulting in additional bias voltage (see...). Figure 5 (Process B in the process).

[0032] Therefore, the relevant technology cannot completely eliminate the additional bias voltage of the pull-up node PU(n). The device characteristics of the output transistor in the nth stage shift register 101(n) are still different from those of the output transistors in other stages of shift register 101, and the effect on improving the horizontal stripe is not good.

[0033] In response, this invention provides a technical solution that, by improving the structure of the bias transfer module in the shift register, can further eliminate the additional bias voltage of the pull-up node in the stop-level shift register before touch, thereby more effectively improving the horizontal stripe phenomenon.

[0034] This invention provides a display panel. Figure 6 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 6 As shown, the display panel includes a gate driving circuit 1, which can be an amorphous silicon gate (ASG) driving circuit. The gate driving circuit 1 includes multiple cascaded shift registers 2. The shift registers 2 are electrically connected to the pixel circuit 4 via scan lines 3, and are used to output a scan signal with a high effective level to control the pixel circuit 4 to perform operations such as data writing. It should be noted that... Figure 6The scan line 3 and pixel circuit 4 shown in the diagram are only for illustrating their connection relationship and are not a limitation on their relative positions. The scan line 3 may overlap with the middle or both sides of the pixel circuit 4, or it may not overlap with the pixel circuit 4.

[0035] Figure 7 This is a schematic diagram of a shift register provided in an embodiment of the present invention, such as... Figure 7 As shown, shift register 2 includes output module 5, first pull-down module 6, and bias transfer module 7.

[0036] The output module 5 is electrically connected to the first output control node PU, the first clock terminal CKB, and the output terminal Gout. It responds to signals from the first output control node PU by writing the signal from the first clock terminal CKB to the output terminal Gout. For example, during at least a portion of the time period when the first output control node PU is high, the first clock terminal CKB provides a high level. The output module 5 responds to the high level of the first output control node PU by writing the high level of the first clock terminal CKB to the output terminal Gout, thus causing the output terminal Gout to output a valid high level.

[0037] The first pull-down module 6 is electrically connected to the first control terminal Ctrl1, the first signal line DIR1, and the first output control node PU. It is used to respond to the signal from the first control terminal Ctrl1 by writing the signal from the first signal line DIR1 into the first output control node PU. For example, when the first control terminal Ctrl1 is high, the first signal line DIR1 provides a low level. The first pull-down module 6 responds to the high level of the first control terminal Ctrl1 by writing the low level of the first signal line DIR1 into the first output control node PU.

[0038] The bias transfer module 7 includes a capacitor unit 8, a first unit 9, a second unit 10, and a third unit 11.

[0039] Among them, capacitor unit 8 is electrically connected between the first node PT and the second node PA.

[0040] The first unit 9 is electrically connected to the first control terminal Ctrl1, the second signal line DIR1-SP, and the first node PT. It is used to respond to the signal of the first control terminal Ctrl1 and write the signal of the second signal line DIR1-SP into the first node PT. For example, when the first control terminal Ctrl1 is high, the second signal line DIR1-SP provides a high level, and the first unit 9 responds to the high level of the first control terminal Ctrl1 by writing the high level of the second signal line DIR1-SP into the first node PT.

[0041] The second unit 10 is electrically connected to the first node PT, the third signal line PAchar, and the second node PA, and is used to respond to the signal of the first node PT and write the signal of the third signal line PAchar into the second node PA.

[0042] The third unit 11 is electrically connected to the second node PA, the fourth signal line PUchar, and the first output control node PU, and is used to respond to the signal of the second node PA and write the signal of the fourth signal line PUchar into the first output control node PU.

[0043] This invention can employ a Long-H driving mode. The display process of one frame includes multiple line scanning periods. Shift register 2 outputs a high level during the line scanning period, and touch periods are inserted between at least some of the adjacent line scanning periods.

[0044] For clarity, the i-th stage shift register is represented by reference numeral 2(i). Correspondingly, the first control terminal of the i-th stage shift register 2(i) is represented by reference numeral Ctrl1(i), the first output control node is represented by reference numeral PU(n), the first node is represented by reference numeral PT(n), and the second node is represented by reference numeral PA(n), where i = 1, 2, 3, 4, ... k, and k is the number of shift registers in the gate drive circuit 1.

[0045] Combination Figures 7-10 The following explanation will be based on the example of a touch-enabled period between the row scan periods corresponding to the (n-1)th level shift register 2 (n-1) and the nth level shift register 2 (n).

[0046] During the process of the (n-1)th stage shift register 2 (n-1) outputting a high level, the first control terminal Ctrl1 (n) connected to the first pull-down module 6 in the nth stage shift register 2 (n) provides a high level, the first signal line DIR1 provides a low level, and the second signal line DIR1-SP provides a high level. In the nth stage shift register 2 (n), the first pull-down module 6 is turned on, writing the low level of the first signal line DIR1 to the first output control node PU (n) to prevent the first output control node PU (n) from generating an additional pull-up. At the same time, the first unit 9 is turned on, writing the high level of the second signal line DIR1-SP to the first node PT (n) to charge the capacitor unit 8.

[0047] During the touch period, the first control terminal Ctrl1(n) connected to the first pull-down module 6 in the nth shift register 2(n) is at a low level, and the capacitor unit 8 in the nth shift register 2(n) continues to store the potential.

[0048] After the touch period ends, the third signal line PAchar provides a high level, and the fourth signal line PUchar provides a high level. In the nth stage shift register 2(n), the signal of the third signal line PAchar jumps high. Based on the action of the second unit 10 and the capacitor unit 8, the first node PT(n) bootstraps, and its potential is raised. The second unit 10 writes the high level of the third signal line PAchar into the second node PA(n), charging the second node PA(n). The third unit 11 responds to the high level of the second node PA(n) and writes the high level of the fourth signal line PUchar into the first output control node PU(n).

[0049] In the above process, before the touch is applied, when the (n-1)th stage shift register 2(n-1) outputs a high level, in the nth stage shift register 2(n), the first pull-down module 6 lowers the voltage of the first output control node PU(n), and the first unit 9 in the bias transfer module 7 charges the capacitor unit 8, thus storing the voltage of the first output control node PU(n) in the bias transfer module 7, where the devices bear the effects of the long-term positive bias. After the touch ends, the bias transfer module 7 releases the voltage to the first output control node PU(n), preparing for the nth stage shift register 2(n) to output a high level, ensuring that the subsequent nth stage shift register 2(n) can continue to output a high level, thus achieving continuity of the effective output level of the subsequent shift register 2.

[0050] Furthermore, in the bias transfer module 7 of this embodiment, before touch, the capacitor unit 8 is charged using the first unit 9. This charging process does not involve the function of the first output control node PU(n), so there is no need to pull the first output control node PU(n) high before touch, thus eliminating the extra bias voltage of the first output control node PU(n) before touch. Moreover, after the touch ends, by using the third unit 11 to control the high-time of the first output control node PU(n), the first output control node PU(n) will not have any extra bias voltage after touch.

[0051] In summary, the embodiments of the present invention can eliminate the additional bias voltage of the first output control node PU(n) to a greater extent, and the output signal delay of the stop-hole level shift register will not change abruptly. This provides more effective signal consistency between the stop-hole level shift register and other conventional level shift registers, and better improves the horizontal stripe phenomenon.

[0052] In one feasible implementation, Figure 8 This is another schematic diagram of a shift register provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of a connection between a shift register and signal lines provided in an embodiment of the present invention, in conjunction with...Figure 8 and Figure 9 In the two adjacent shift registers 2 of the gate drive circuit 1, the first control terminal Ctrl1 of the latter shift register 2 is electrically connected to the output terminal Gout of the former shift register 2.

[0053] For example, the first control terminal Ctrl1(n) corresponding to the nth stage shift register 2(n) is electrically connected to the output terminal Gout(n-1) corresponding to the (n-1)th stage shift register 2(n-1). This connection method allows the first control terminal Ctrl1(n) connected to the first pull-down module 6 in the nth stage shift register 2(n) to provide a high level while the (n-1)th stage shift register 2(n-1) outputs a high level. Furthermore, it improves the synchronization of the high levels in the two signals and enhances the reliability of the coordinated operation between the (n-1)th stage shift register 2(n-1) and the nth stage shift register 2(n).

[0054] Figure 10 A timing diagram provided in an embodiment of the present invention, combined with Figure 8 and Figure 10 The driving cycle of the display panel includes a first time period t1, a second time period t2, and a touch time period tp located between the first time period t1 and the second time period t2.

[0055] Shift register 2 includes an adjacent first shift register 2-1 and a second shift register 2-2. The first shift register 2-1 outputs a high level in the first time period t1, and the second shift register 2-2 outputs a high level in the second time period t2.

[0056] In this system, the first shift register 2-1 is the last shift register 2 to output a high level before the touch event begins, and the second shift register 2-2 is the first shift register 2 to output a high level after the touch event ends. The specific shift registers that the first shift register 2-1 and the second shift register 2-2 represent can be determined based on the insertion position of the touch event period. For example, based on the aforementioned illustration, when a touch event period is inserted between the high-level outputs of the (n-1)th shift register 2(n-1) and the nth shift register 2(n), then the first shift register 2-1 includes the (n-1)th shift register 2(n-1), and the second shift register 2-2 includes the nth shift register 2(n).

[0057] It should be noted that, in this embodiment of the invention, touch time periods tp can be inserted between multiple adjacent shift registers 2. Therefore, in the gate driving circuit 1, there can be multiple first shift registers 2-1 and multiple second shift registers 2-2. This embodiment of the invention only uses two adjacent shift registers 2, the (n-1)th level shift register 2 (n-1) and the nth level shift register 2 (n), as examples for illustration.

[0058] The following explanation uses the example of shift register 2(n-1) as the first shift register 2-1 and shift register 2(n) as the second shift register 2-2.

[0059] Combination Figures 8-10 During the first time period t1, the output terminal Gout(n-1) of the (n-1)th stage shift register 2(n-1) outputs a high level, correspondingly making the first control terminal Ctrl1(n) of the nth stage shift register 2(n) high. The first signal line DIR1 provides a low level, the third signal line PAchar provides a low level, and the second signal line DIR1-SP provides a high level. In the nth stage shift register 2(n), the first pull-down module 6 responds to the high level of the first control terminal Ctrl1(n) by writing the low level of the first signal line DIR1 into the first output control node PU(n), the first unit 9 responds to the high level of the first control terminal Ctrl1(n) by writing the high level of the second signal line DIR1-SP into the first node PT(n) to charge the first node PT(n), and the second unit 10 responds to the high level of the first node PT(n) by writing the low level of the third signal line PAchar into the second node PA(n).

[0060] During this period, the nth shift register 2(n) charges the first node PT(n) through the first unit 9. As analyzed above, this charging does not depend on the first output control node PU(n), thus eliminating the extra bias voltage of the first output control node PU(n) before touch.

[0061] The driving cycle of the display panel also includes a third time period t3, which is located between the touch time period tp and the second time period t2.

[0062] During the third time period t3, the third signal line PAchar provides a high level, and the fourth signal line PUchar provides a high level. In the nth stage shift register 2(n), after the signal of the third signal line PAchar is pulled high, based on the function of the second unit 10 and the capacitor unit 8, the first node PT(n) bootstraps to a high level. The second unit 10 writes the high level of the third signal line PAchar into the second node PA(n) to charge the second node PA(n). The third unit 11 responds to the high level of the second node PA(n) by writing the high level of the fourth signal line PUchar into the first output control node PU(n).

[0063] In the third time period t3, in the nth stage shift register 2(n), the bias register module 7 releases the voltage stored before the touch to the first output control node PU(n), thereby enabling the first output control node PU(n) to prepare for the subsequent control output module 5 to output a high level to the output terminal Gout(n) in the second time period t2, so that the subsequent shift register can be shifted normally after the touch ends.

[0064] In one feasible implementation, combined with Figure 7 , Figure 8 and Figure 10 The shift register 2 also includes a control module 12, which is electrically connected to the reset line RESET, the low potential line VGL, and the first output control node PU.

[0065] The driving cycle of the display panel also includes a fourth time period t4 and a fifth time period t5. The fourth time period t4 is located between the first time period t1 and the touch time period tp, and the fifth time period t5 is located between the touch time period tp and the third time period t3.

[0066] During the fourth time period t4, the reset line RESET provides a high level. At least in the first shift register 2-1, the control module 12 responds to the high level of the reset line RESET by writing the low level of the low potential line VGL into the first output control node PU.

[0067] During the fifth time period t5, the RESET signal on the reset line jumps to a low level.

[0068] The following explanation uses the example of shift register 2(n-1) as the first shift register 2-1 and shift register 2(n) as the second shift register 2-2.

[0069] In the fourth time period t4, the reset line RESET signal is set high, and all control modules 12 in all shift registers 2 will respond to the high level of the reset line RESET, writing the low level of the low potential line VGL into the first output control node PU. Specifically, for the (n-1)th stage shift register 2 (n-1), in the first time period t1, its first output control node PU (n-1) is at a high potential. Pulling its potential low in the fourth time period t4 avoids additional bias voltage on the first output control node PU (n-1) of the (n-1)th stage shift register 2 (n-1), for example, compared to related technologies... Figure 2 and Figure 5In this embodiment of the invention, the first output control node PU(n-1) has no additional bias voltage during and before and after touch. The waveform of the signal of the first output control node PU(n-1) is consistent with that of other stages, thereby avoiding the bias voltage difference between the output transistor connected to the first output control node PU(n-1) in the (n-1)th stage shift register 2(n-1) and the output transistors of other stages of shift register 2. This makes the signals output by the (n-1)th stage shift register 2(n-1) and other stages of conventional shift register 2 consistent, thus greatly improving the horizontal stripe problem.

[0070] In the fifth time period t5 after the touch ends, the RESET signal jumps to low level again, and the control module 12 cuts off the signal path between the low potential line VGL and the first output control node PU to prevent it from affecting the normal signal state of the first output control node PU in each level shift register 2.

[0071] Furthermore, the signal of the fourth signal line PUchar can jump to a high level in advance during the fifth time period t5, in preparation for the charging of the first output control node PU(n) in the subsequent third time period t3.

[0072] In one feasible implementation, Figure 11 Another timing diagram provided for an embodiment of the present invention, such as Figure 11 As shown, the signal output by the second shift register 2-2 jumps low at the first time p1, which means the signal output by Gout(n) of the nth stage shift register 2(n) jumps low at the first time p1. The signal of the first output control node PU in the second shift register 2-2 jumps low at the second time p2, which means the first output control node PU(n) in the nth stage shift register 2(n) jumps low at the second time p2. There is a first time interval between the second time p2 and the first time p1.

[0073] The signal output by the first shift register 2-1 goes low at the third time p3. That is, the signal output by the output terminal Gout(n-1) of the (n-1)th stage shift register 2(n-1) goes low at the third time p3. The reset line RESET goes high at the fourth time p4. There is a second time interval between the fourth time p4 and the third time p3.

[0074] The second time interval is equal to the first time interval.

[0075] By controlling the signal jump time of the RESET line, the second time interval is made equal to the first time interval. This ensures that the waveform of the signal of the first output control node PU in the first shift register 2-1 is consistent with the waveform of the signal of the first output control node PU in the second shift register 2-2, thus completely eliminating the extra bias voltage of the first output control node PU in the first shift register 2-1 before touch.

[0076] In one feasible implementation, combined with Figure 8 and Figure 10 During the fourth time period t4, the signal on the second signal line DIR1-SP jumps to a low level.

[0077] During the fourth time period t4, the signal jump of the second signal line DIR1-SP can prevent the first node PT of other stage shift registers 2 from leaking to a high level, thus maintaining potential stability.

[0078] Furthermore, there can be a certain interval between the low-level jump of the signal on the second signal line DIR1-SP and the time when the (n-1)th stage shift register 2 (n-1) stops outputting a high level. For example, the signal on the second signal line DIR1-SP can be pulled low again at the end of the fourth time period t4. This ensures that the first unit 9 in the nth stage shift register 2 (n) is closed when the signal on the second signal line DIR1-SP is low, preventing any impact on the potential of the first node PT (n).

[0079] In one feasible implementation, combined with Figure 8 and Figure 10 During the fifth time period t5, the signal on the first signal line DIR1 jumps to a high level.

[0080] In the first time period t1, the signal of the first signal line DIR1 is pulled low to set the first output control node PU(u) low. In the fifth time period t5, the signal of the first signal line DIR1 is pulled high to restore it to the potential of the normal working stage and to prepare for pulling it low again in the future.

[0081] In one feasible implementation, combined with Figure 8 and Figure 10 In the third time period t3, the signal of the third signal line PAchar changes from high level to low level, and in the second time period t2, the signal of the fourth signal line PUchar changes to low level.

[0082] As mentioned earlier, during the third time period t3, the third signal line PAchar provides a high level to charge the second node PA(n), thereby enabling the third unit 11 to charge the first output control node PU(n) and raise its voltage level. Similarly, during the third time period t3, after the third signal line PAchar provides a high level for a certain period of time, its signal jumps low, thereby setting the second node PA(n) low and stopping the charging of the first output control node PU(n), so that the first output control node PU(n) can complete its bootstrap function normally during the second time period t2.

[0083] In the second time period t2, the signal of the fourth signal line PUchar can also be set low to prepare for the subsequent signal transition. Since the second node PA(n) has been set low in the previous third time period t3, the third unit 11 is turned off when the signal of the fourth signal line PUchar is set low, and the level of the fourth signal line PUchar will not be written to the first output control node PU(n).

[0084] In one feasible implementation, combined with Figure 7 , Figure 8 and Figure 10 The bias transfer module 7 also includes a fourth unit 13. The fourth unit 13 is electrically connected to the second control terminal Ctrl2, the fifth signal line DIR2-SP and the first node PT, and is used to respond to the signal of the second control terminal Ctrl2 and write the signal of the fifth signal line DIR2-SP into the first node PT.

[0085] In the two adjacent shift registers 2 of the gate drive circuit 1, the second control terminal Ctrl2 of the previous shift register 2 is electrically connected to the output terminal Gout of the next shift register 2. For example, the output terminal Gout(n) of the nth shift register 2(n) is electrically connected to the second control terminal Ctrl2(n-1) of the (n-1)th shift register 2(n-1).

[0086] Shift register 2 also includes a third shift register 2-3 adjacent to the second shift register 2-2. The third shift register 2-3 is the adjacent shift register 2 that outputs a high level after the second shift register 2-2. For example, based on the above schematic analysis, when the second shift register 2-2 includes the nth stage shift register 2(n), the third shift register 2-3 includes the (n+1)th stage shift register 2(n+1).

[0087] The drive cycle of the display panel also includes a sixth period t6, which is located after the second period t2. The third shift register 2-3 outputs a high level in the sixth period t6.

[0088] During the sixth time period t6, the fifth signal line DIR2-SP provides a low level. In the second shift register 2-2, the fourth unit 13 responds to the high level of the second control terminal Ctrl2 and writes the low level of the fifth signal line DIR2-SP into the first node PT.

[0089] In the sixth time period t6, the (n+1)th stage shift register 2 (n+1) outputs a high level. In the nth stage shift register 2 (n), the fourth unit 13 responds to the high level of the second control terminal Ctrl2 (n) and writes the low level of the fifth signal line DIR2-SP to the first node PT (n), causing the second unit 10 to turn off. After that, it is the normal output stage of shift register 2. The (n+2)th stage, the (n+3)th stage, and so on, shift register 2 outputs a high level in sequence.

[0090] In one feasible implementation, combined with Figure 7 , Figure 8 and Figure 10 The bias transfer module 7 also includes a fifth unit 14, which is electrically connected to the first clock terminal CKB, the low potential line VGL, and the second node PA.

[0091] During the second time period t2, in the second shift register 2-2, the fifth unit 14 responds to the high level of the first clock terminal CKB and writes the low level of the low potential line VGL into the second node PA.

[0092] During the second time period t2, for the nth shift register 2(n), its first clock terminal CKB is high. The fifth unit 14 writes a low level to the second node PA(n), which works together with the second unit 10 to set the second node PA(n) low, thereby controlling the third unit 11 to turn off and stop charging the first output control node PU(n), so that the first output control node PU(n) can complete the bootstrap function normally during the second time period t2.

[0093] In one feasible implementation, combined with Figure 8 and Figure 10 The output module 5 is also electrically connected to the low potential line VGL and is also used to respond to the signal of the second output control node PD by writing the low level of the low potential line VGL to the output terminal Gout.

[0094] Furthermore, the output module 5 is also electrically connected to the second clock terminal CK, and is also used to respond to the signal of the second clock terminal CK by writing the low level of the low potential line VGL to the output terminal Gout.

[0095] The shift register 2 also includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 is electrically connected between the output terminal Gout and the first output control node PU, and the second capacitor C2 is electrically connected between the first clock terminal CKB and the second output control node PD.

[0096] The shift register 2 also includes a second pull-down module 15, which is electrically connected to the second control terminal Ctrl2, the sixth signal line DIR2, and the first output control node PU. The second pull-down module 15 responds to the signal from the second control terminal Ctrl2 by writing the signal from the sixth signal line DIR2 into the first output control node PU. For example, if the sixth signal line DIR2 provides a high level, and the second control terminal Ctrl2 is high, the second pull-down module 15 opens, writing the low level of the sixth signal line DIR2 into the first output control node PU. The shift register 2 also includes a control module 12, which is electrically connected to the reset line RESET, the low potential line VGL, the first output control node PU, and the second output control node PD, and is used to write signals to the first output control node PU and the second output control node PD.

[0097] The following is combined Figures 7-10 The working process of shift register 2 is explained below: The first pull-down module 6 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the first control terminal Ctrl1, the first electrode is electrically connected to the first signal line DIR1, and the second electrode is electrically connected to the first output control node PU.

[0098] The control module 12 includes a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. Specifically, the gate of the second transistor T2 is electrically connected to the reset line RESET, its first terminal is electrically connected to the low-potential line VGL, and its second terminal is electrically connected to the first output control node PU. The gate of the third transistor T3 is electrically connected to the reset line RESET, its first terminal is electrically connected to the low-potential line VGL, and its second terminal is electrically connected to the output terminal Gout. The gate of the fourth transistor T4 is electrically connected to the second output control node PD, its first terminal is electrically connected to the low-potential line VGL, and its second terminal is electrically connected to the first output control node PU. The gate of the fifth transistor T5 is electrically connected to the first output control node PU, its first terminal is electrically connected to the low-potential line VGL, and its second terminal is electrically connected to the second output control node PD.

[0099] In the bias transfer module 7: Capacitor unit 8 includes a third capacitor C3, which is electrically connected between the first node PT and the second node PA. First unit 9 includes a sixth transistor T6, whose gate is electrically connected to the first control terminal Ctrl1, its first terminal is electrically connected to the second signal line DIR1-SP, and its second terminal is electrically connected to the first node PT. Second unit 10 includes a seventh transistor T7, whose gate is electrically connected to the first node PT, its first terminal is electrically connected to the third signal line PAchar, and its second terminal is electrically connected to the second node PA. Third unit 11 includes an eighth transistor T8, whose gate is electrically connected to the second node PA, its first terminal is electrically connected to the fourth signal line PUchar, and its second terminal is electrically connected to the first output control node PU. Fourth unit 13 includes a ninth transistor T9, whose gate is electrically connected to the second control terminal Ctrl2, its first terminal is electrically connected to the fifth signal line DIR2-SP, and its second terminal is electrically connected to the first node PT. The fifth unit 14 includes a tenth transistor T10. The gate of the tenth transistor T10 is electrically connected to the first clock terminal CKB, the first terminal is electrically connected to the low potential line VGL, and the second terminal is electrically connected to the second node PA.

[0100] The second pull-down module 15 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is electrically connected to the second control terminal Ctrl2, the first terminal is electrically connected to the sixth signal line DIR2, and the second terminal is electrically connected to the first output control node PU.

[0101] Output module 5 includes a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. Specifically, the gate of the twelfth transistor T12 is electrically connected to the first output control node PU, its first terminal is electrically connected to the first clock terminal CKB, and its second terminal is electrically connected to the output terminal Gout. The gate of the thirteenth transistor T13 is electrically connected to the second output control node PD, its first terminal is electrically connected to the low-potential line VGL, and its second terminal is electrically connected to the output terminal Gout. The gate of the fourteenth transistor T14 is electrically connected to the second clock terminal CK, its first terminal is electrically connected to the low-potential line VGL, and its second terminal is electrically connected to the output terminal Gout.

[0102] In two adjacent shift registers 2, the first control terminal Ctrl1 of the latter shift register 2 is electrically connected to the output terminal Gout of the former shift register 2; and in two adjacent shift registers 2, the second control terminal Ctrl2 of the former shift register 2 is electrically connected to the output terminal Gout of the latter shift register 2.

[0103] See Figure 9In two adjacent shift registers 2, the first clock terminal CKB of the first shift register 2 is electrically connected to the first clock line ck1, and the second clock terminal CK is electrically connected to the second clock line ck2. In the other shift register 2, the second clock terminal CK is electrically connected to the first clock line ck1, and the first clock terminal CKB is electrically connected to the second clock line ck2.

[0104] Combination Figures 6-10 The driving cycle of the display panel includes the seventh time period t7, the first time period t1, the fourth time period t4, the touch time period tp, the fifth time period t5, the third time period t3, the second time period t2, and the sixth time period t6.

[0105] During the seventh time period t7, the shift registers from level i to level n-2 output high levels in sequence, where i can be equal to 1 or greater than 1.

[0106] During the first time period t1, the (n-1)th stage shift register 2 outputs a high level. The first signal line DIR1 provides a low level, the third signal line PAchar provides a low level, and the second signal line DIR1-SP provides a high level. In the nth stage shift register 2, the first transistor T1 responds to the high level of the first control terminal Ctrl1(n) and conducts, writing the low level of the first signal line DIR1 to the first output control node PU(n). The sixth transistor T6 responds to the high level of the first control terminal Ctrl1(n) and conducts, writing the high level of the second signal line DIR1-SP to the first node PT(n). The seventh unit responds to the high level of the first node PT(n) and conducts, writing the low level of the third signal line PAchar to the second node PA(n). During the fourth time period t4, the reset line RESET provides a high level. In each stage of shift register 2, the second transistor T2 turns on in response to the high level of the reset line RESET, writing the low level of the low potential line VGL into the first output control node PU(n). During or at the end of the fourth time period t4, the signal on the second signal line DIR1-SP jumps low to prevent leakage to the high level of the first node PT of other stages of shift register 2.

[0107] During the touch period, tp performs touch scanning detection.

[0108] During the fifth time period t5, the signal on the fourth signal line PUchar can jump to a high level, preparing for the subsequent charging of the first output control node PU(n). The signal on the reset line RESET jumps to a low level. The signal on the first signal line DIR1 jumps to a high level, restoring it to its normal operating potential and preparing for a subsequent pull-down.

[0109] During the third time period t3, the third signal line PAchar provides a high level, and the fourth signal line PUchar remains high. In the nth stage shift register 2, after the signal of the third signal line PAchar is pulled high, based on the action of the seventh transistor T7 and the third capacitor C3, the first node PT(n) bootstraps to a high level. The seventh transistor T7 writes the high level of the third signal line PAchar to the second node PA(n), charging the second node PA(n). The eighth transistor T8 responds to the high level of the second node PA(n) by writing the high level of the fourth signal line PUchar to the first output control node PU(n). Then, the signal of the third signal line PAchar goes low, setting the second node PA(n) low and stopping the charging of the first output control node PU(n).

[0110] During the second time period t2, in the nth stage shift register 2, the first clock terminal CKB provides a high level, the first output control node PU(n) bootstraps to a higher potential, and the tenth transistor T10 turns on, writing the high level of the first clock terminal CKB to the output terminal Gout(n). The signal on the fourth signal line PUchar is pulled low to prepare for subsequent signal transitions.

[0111] During the sixth time period t6, the (n+1)th stage shift register 2 outputs a high level. The fifth signal line DIR2-SP provides a low level. In the nth stage shift register 2, the ninth transistor T9 turns on in response to the high level of the second control terminal Ctrl2(n), writing the low level of the fifth signal line DIR2-SP into the first node PT(n).

[0112] Based on the same inventive concept, embodiments of the present invention also provide a method for driving a display panel, combined with Figures 7-10 The display panel includes a gate drive circuit 1, which includes multiple cascaded shift registers 2.

[0113] The shift register 2 includes an output module 5, a first pull-down module 6, and a bias transfer module 7.

[0114] The output module 5 is electrically connected to the first output control node PU, the first clock terminal CKB, and the output terminal Gout.

[0115] The first drop-down module 6 is electrically connected to the first control terminal Ctrl1, the first signal line DIR1, and the first output control node PU.

[0116] The bias transfer module 7 includes a capacitor unit 8, a first unit 9, a second unit 10, and a third unit 11. The capacitor unit 8 is electrically connected between the first node PT and the second node PA. The first unit 9 is electrically connected to the first control terminal Ctrl1, the second signal line DIR1-SP, and the first node PT. The second unit 10 is electrically connected to the first node PT, the third signal line PAchar, and the second node PA. The third unit 11 is electrically connected to the second node PA, the fourth signal line PUchar, and the first output control node PU.

[0117] The driving method for the display panel includes controlling the gate driving circuit 1 to output a driving signal. The operation of the shift register 2 in the gate driving circuit 1 includes: the first pull-down module 6 responds to the signal from the first control terminal Ctrl1 and writes the signal from the first signal line DIR1 into the first output control node PU. The first unit 9 responds to the signal from the first control terminal Ctrl1 and writes the signal from the second signal line DIR1-SP into the first node PT; the second unit 10 responds to the signal from the first node PT and writes the signal from the third signal line PAchar into the second node PA; the third unit 11 responds to the signal from the second node PA and writes the signal from the fourth signal line PUchar into the first output control node PU. The output module 5 responds to the signal from the first output control node PU and writes the signal from the first clock terminal CKB into the output terminal Gout.

[0118] More specifically, embodiments of the present invention may employ a Long-H driving mode. The display process of one frame includes multiple line scanning periods. Shift register 2 outputs a high level during the line scanning period, and touch periods are inserted between at least some of the adjacent line scanning periods.

[0119] For clarity, the i-th stage shift register is represented by reference numeral 2(i). Correspondingly, the first control terminal of the i-th stage shift register 2(i) is represented by reference numeral Ctrl1(i), the first output control node is represented by reference numeral PU(n), the first node is represented by reference numeral PT(n), and the second node is represented by reference numeral PA(n), where i = 1, 2, 3, 4, ... k, and k is the number of shift registers in the gate drive circuit 1.

[0120] Combination Figure 8 The following explanation will be based on the example of a touch-enabled period between the row scan periods corresponding to the (n-1)th level shift register 2 (n-1) and the nth level shift register 2 (n).

[0121] During the process of the (n-1)th stage shift register 2 (n-1) outputting a high level, the first control terminal Ctrl1 (n) connected to the first pull-down module 6 in the nth stage shift register 2 (n) provides a high level, the first signal line DIR1 provides a low level, and the second signal line DIR1-SP provides a high level. In the nth stage shift register 2 (n), the first pull-down module 6 is turned on, writing the low level of the first signal line DIR1 to the first output control node PU (n) to prevent the first output control node PU (n) from generating an additional pull-up. At the same time, the first unit 9 is turned on, writing the high level of the second signal line DIR1-SP to the first node PT (n) to charge the capacitor unit 8.

[0122] During the touch period, the first control terminal Ctrl1(n) connected to the first pull-down module 6 in the nth shift register 2(n) is at a low level, and the capacitor unit 8 in the nth shift register 2(n) continues to store the potential.

[0123] After the touch period ends, the third signal line PAchar provides a high level, and the fourth signal line PUchar provides a high level. In the nth stage shift register 2(n), the signal of the third signal line PAchar jumps high. Based on the action of the second unit 10 and the capacitor unit 8, the first node PT(n) bootstraps, and its potential is raised. The second unit 10 writes the high level of the third signal line PAchar into the second node PA(n), charging the second node PA(n). The third unit 11 responds to the high level of the second node PA(n) and writes the high level of the fourth signal line PUchar into the first output control node PU(n).

[0124] In the above process, before the touch is applied, the (n-1)th stage shift register 2 (n-1) outputs a high level. In the nth stage shift register 2 (n), the first pull-down module 6 sets the voltage of the first output control node PU (n) low. The first unit 9 in the bias transfer module 7 charges the capacitor unit 8, so that the voltage of the first output control node PU (n) is stored in the bias transfer module 7. After the touch is applied, the bias transfer module 7 releases it to the first output control node PU (n), thus preparing for the nth stage shift register 2 (n) to output a high level. This ensures that the subsequent nth stage shift register 2 (n) can continue to output a high level, achieving the continuity of the effective output level of the subsequent shift register 2.

[0125] Furthermore, in the bias transfer module 7 of this embodiment, before touch, the capacitor unit 8 is charged using the first unit 9. This charging process does not involve the function of the first output control node PU(n), so there is no need to pull the first output control node PU(n) high before touch, thus eliminating the extra bias voltage of the first output control node PU(n) before touch. Moreover, after the touch ends, by using the third unit 11 to control the high-time of the first output control node PU(n), the first output control node PU(n) will not have any extra bias voltage after touch.

[0126] In summary, the embodiments of the present invention can eliminate the additional bias voltage of the first output control node PU(n) to a greater extent, and the output signal delay of the stop-hole level shift register will not change abruptly. This provides more effective signal consistency between the stop-hole level shift register and other conventional level shift registers, and better improves the horizontal stripe phenomenon.

[0127] In one feasible implementation, combined with Figure 9 and Figures 8-10 In the two adjacent shift registers 2 of the gate drive circuit 1, the first control terminal Ctrl1 of the latter shift register 2 is electrically connected to the output terminal Gout of the former shift register 2.

[0128] For example, the first control terminal Ctrl1(n) corresponding to the nth stage shift register 2(n) is electrically connected to the output terminal Gout(n-1) corresponding to the (n-1)th stage shift register 2(n-1). This connection method allows the first control terminal Ctrl1(n) connected to the first pull-down module 6 in the nth stage shift register 2(n) to provide a high level while the (n-1)th stage shift register 2(n-1) outputs a high level. Furthermore, it improves the synchronization of the high levels in the two signals and enhances the reliability of the coordinated operation between the (n-1)th stage shift register 2(n-1) and the nth stage shift register 2(n).

[0129] The driving cycle of the display panel includes a first time period t1, a second time period t2, and a touch time period tp located between the first time period t1 and the second time period t2.

[0130] Shift register 2 includes an adjacent first shift register 2-1 and a second shift register 2-2. The first shift register 2-1 outputs a high level in the first time period t1, and the second shift register 2-2 outputs a high level in the second time period t2.

[0131] In this system, the first shift register 2-1 is the last shift register 2 to output a high level before the touch event begins, and the second shift register 2-2 is the first shift register 2 to output a high level after the touch event ends. The specific shift registers that the first shift register 2-1 and the second shift register 2-2 represent can be determined based on the insertion position of the touch event period. For example, based on the aforementioned illustration, when a touch event period is inserted between the high-level outputs of the (n-1)th shift register 2(n) and the nth shift register 2(n), then the first shift register 2-1 includes the (n-1)th shift register 2(n), and the second shift register 2-2 includes the nth shift register 2(n).

[0132] It should be noted that, in this embodiment of the invention, touch time periods tp can be inserted between multiple adjacent shift registers 2. Therefore, in the gate driving circuit 1, there can be multiple first shift registers 2-1 and multiple second shift registers 2-2. This embodiment of the invention only uses two adjacent shift registers 2, the (n-1)th level shift register 2 (n-1) and the nth level shift register 2 (n), as examples for illustration.

[0133] The driving method for the display panel includes: in the first time period t1, the first signal line DIR1 and the third signal line PAchar provide a low level, and the second signal line DIR1-SP provides a high level; in the second shift register 2-2, the first pull-down module 6 responds to the high level of the first control terminal Ctrl1 and writes the low level of the first signal line DIR1 to the first output control node PU; the first unit 9 responds to the high level of the first control terminal Ctrl1 and writes the high level of the second signal line DIR1-SP to the first node PT; and the second unit 10 responds to the high level of the first node PT and writes the low level of the third signal line PAchar to the second node PA.

[0134] The following explanation uses the example of shift register 2(n-1) as the first shift register 2-1 and shift register 2(n) as the second shift register 2-2.

[0135] Combination Figure 7During the first time period t1, the output terminal Gout(n-1) of the (n-1)th stage shift register 2(n-1) outputs a high level, correspondingly making the first control terminal Ctrl1(n) of the nth stage shift register 2(n) high. The first signal line DIR1 provides a low level, the third signal line PAchar provides a low level, and the second signal line DIR1-SP provides a high level. In the nth stage shift register 2(n), the first pull-down module 6 responds to the high level of the first control terminal Ctrl1(n) by writing the low level of the first signal line DIR1 into the first output control node PU(n), the first unit 9 responds to the high level of the first control terminal Ctrl1(n) by writing the high level of the second signal line DIR1-SP into the first node PT(n) to charge the first node PT(n), and the second unit 10 responds to the high level of the first node PT(n) by writing the low level of the third signal line PAchar into the second node PA(n).

[0136] During this period, the nth shift register 2(n) charges the first node PT(n) through the first unit 9. As analyzed above, this charging does not depend on the first output control node PU(n), thus eliminating the extra bias voltage of the first output control node PU(n) before touch.

[0137] The driving cycle of the display panel also includes a third time period t3, which is located between the touch time period tp and the second time period t2.

[0138] The driving method for the display panel also includes: during the third time period t3, the third signal line PAchar and the fourth signal line PUchar provide a high level; in the second shift register 2-2, the first node PT is at a high level, the second unit 10 responds to the high level of the first node PT by writing the high level of the third signal line PAchar to the second node PA, and the third unit 11 responds to the high level of the second node PA by writing the high level of the fourth signal line PUchar to the first output control node PU.

[0139] In the third time period t3, in the nth stage shift register 2(n), the bias register module 7 releases the voltage stored before the touch to the first output control node PU(n), thereby enabling the first output control node PU(n) to prepare for the subsequent control output module 5 to output a high level to the output terminal Gout(n) in the second time period t2, so that the subsequent shift register can be shifted normally after the touch ends.

[0140] In one feasible implementation, combined with Figure 8 , Figure 10 and Figure 2 The shift register 2 also includes a control module 12, which is electrically connected to the reset line RESET, the low potential line VGL, and the first output control node PU.

[0141] The driving cycle of the display panel also includes a fourth time period t4 and a fifth time period t5. The fourth time period t4 is located between the first time period t1 and the touch time period tp, and the fifth time period t5 is located between the touch time period tp and the third time period t3.

[0142] The driving method for the display panel also includes: during the fourth time period t4, the reset line RESET provides a high level, and at least in the first shift register 2-1, the control module 12 responds to the high level of the reset line RESET by writing the low level of the low potential line VGL into the first output control node PU; during the fifth time period t5, the signal of the reset line RESET jumps to a low level.

[0143] The following explanation uses the example of shift register 2(n-1) as the first shift register 2-1 and shift register 2(n) as the second shift register 2-2.

[0144] In the fourth time period t4, the reset line RESET signal is set high, and all control modules 12 in all shift registers 2 will respond to the high level of the reset line RESET, writing the low level of the low potential line VGL into the first output control node PU. Specifically, for the (n-1)th stage shift register 2 (n-1), in the first time period t1, its first output control node PU (n-1) is at a high potential. Pulling its potential low in the fourth time period t4 avoids additional bias voltage on the first output control node PU (n-1) of the (n-1)th stage shift register 2 (n-1), for example, compared to related technologies... Figure 5 and Figure 11 In this embodiment of the invention, the first output control node PU(n-1) has no additional bias voltage during and before and after touch. The waveform of the signal of the first output control node PU(n-1) is consistent with that of other stages, thereby avoiding the bias voltage difference between the output transistor connected to the first output control node PU(n-1) in the (n-1)th stage shift register 2(n-1) and the output transistors of other stages of shift register 2. This makes the signals output by the (n-1)th stage shift register 2(n-1) and other stages of conventional shift register 2 consistent, thus greatly improving the horizontal stripe problem.

[0145] In the fifth time period t5 after the touch ends, the RESET signal jumps to low level again, and the control module 12 cuts off the signal path between the low potential line VGL and the first output control node PU to prevent it from affecting the normal signal state of the first output control node PU in each level shift register 2.

[0146] Furthermore, the signal of the fourth signal line PUchar can jump to a high level in advance during the fifth time period t5, in preparation for the charging of the first output control node PU(n) in the subsequent third time period t3.

[0147] In one feasible implementation, see Figure 8 The signal output by the second shift register 2-2 jumps to a low level at the first moment p1, and the signal of the first output control node PU in the second shift register 2-2 jumps to a low level at the second moment p2. There is a first time interval between the second moment p2 and the first moment p1.

[0148] The signal output by the first shift register 2-1 jumps to low level at the third time p3, and the RESET signal jumps to high level at the fourth time p4. There is a second time interval between the fourth time p4 and the third time p3.

[0149] The second time interval is equal to the first time interval.

[0150] By controlling the signal jump time of the RESET line, the second time interval is made equal to the first time interval. This ensures that the waveform of the signal of the first output control node PU in the first shift register 2-1 is consistent with the waveform of the signal of the first output control node PU in the second shift register 2-2, thus completely eliminating the extra bias voltage of the first output control node PU in the first shift register 2-1 before touch.

[0151] In one feasible implementation, combined with Figure 10 and Figure 8 During the fourth time period t4, the signal on the second signal line DIR1-SP jumps to a low level.

[0152] During the fourth time period t4, the signal jump of the second signal line DIR1-SP can prevent the first node PT of other stage shift registers 2 from leaking to a high level, thus maintaining potential stability.

[0153] Furthermore, there can be a certain interval between the low-level jump of the signal on the second signal line DIR1-SP and the time when the (n-1)th stage shift register 2 (n-1) stops outputting a high level. For example, the signal on the second signal line DIR1-SP can be pulled low again at the end of the fourth time period t4. This ensures that the first unit 9 in the nth stage shift register 2 (n) is closed when the signal on the second signal line DIR1-SP is low, preventing any impact on the potential of the first node PT (n).

[0154] And / or, during the fifth time period t5, the signal on the first signal line DIR1 jumps to a high level.

[0155] In the first time period t1, the signal of the first signal line DIR1 is pulled low to set the first output control node PU(u) low. In the fifth time period t5, the signal of the first signal line DIR1 is pulled high to restore it to the potential of the normal working stage and to prepare for pulling it low again in the future.

[0156] In one feasible implementation, combined with Figure 10 and Figure 7 In the third time period t3, the signal of the third signal line PAchar changes from high level to low level; in the second time period t2, the signal of the fourth signal line PUchar changes to low level.

[0157] As mentioned earlier, during the third time period t3, the third signal line PAchar provides a high level to charge the second node PA(n), thereby enabling the third unit 11 to charge the first output control node PU(n) and raise its voltage level. Similarly, during the third time period t3, after the third signal line PAchar provides a high level for a certain period of time, its signal jumps low, thereby setting the second node PA(n) low and stopping the charging of the first output control node PU(n), so that the first output control node PU(n) can complete its bootstrap function normally during the second time period t2.

[0158] In the second time period t2, the signal of the fourth signal line PUchar can also be set low to prepare for the subsequent signal transition. Since the second node PA(n) has been set low in the previous third time period t3, the third unit 11 is turned off when the signal of the fourth signal line PUchar is set low, and the level of the fourth signal line PUchar will not be written to the first output control node PU(n).

[0159] In one feasible implementation, combined with Figure 8 , Figure 10 and Figure 7 The bias transfer module 7 also includes a fourth unit 13, which is electrically connected to the second control terminal Ctrl2, the fifth signal line DIR2-SP and the first node PT. It is used to respond to the signal of the second control terminal Ctrl2 and write the signal of the fifth signal line DIR2-SP into the first node PT.

[0160] In the two adjacent shift registers 2 of the gate drive circuit 1, the second control terminal Ctrl2 of the previous shift register 2 is electrically connected to the output terminal Gout of the next shift register 2. For example, the output terminal Gout(n) of the nth shift register 2(n) is electrically connected to the second control terminal Ctrl2(n-1) of the (n-1)th shift register 2(n-1).

[0161] Shift register 2 also includes a third shift register 2-3 adjacent to the second shift register 2-2. The third shift register 2-3 is the adjacent shift register 2 that outputs a high level after the second shift register 2-2. For example, based on the above schematic analysis, when the second shift register 2-2 includes the nth stage shift register 2(n), the third shift register 2-3 includes the (n+1)th stage shift register 2(n+1).

[0162] The drive cycle of the display panel also includes a sixth period t6, which is located after the second period t2. The third shift register 2-3 outputs a high level in the sixth period t6.

[0163] The driving method for the display panel also includes: during the sixth time period t6, the fifth signal line DIR2-SP provides a low level, and in the second shift register 2-2, the fourth unit 13 responds to the high level of the second control terminal Ctrl2 and writes the low level of the fifth signal line DIR2-SP into the first node PT.

[0164] In the sixth time period t6, the (n+1)th stage shift register 2 (n+1) outputs a high level. In the nth stage shift register 2 (n), the fourth unit 13 responds to the high level of the second control terminal Ctrl2 (n) and writes the low level of the fifth signal line DIR2-SP to the first node PT (n), causing the second unit 10 to turn off. After that, it is the normal output stage of shift register 2. The (n+2)th stage, the (n+3)th stage, and so on, shift register 2 outputs a high level in sequence.

[0165] In one feasible implementation, combined with Figure 8 , Figure 10 and Figure 12 The bias transfer module 7 also includes a fifth unit 14, which is electrically connected to the first clock terminal CKB, the low potential line VGL, and the second node PA.

[0166] The driving method for the display panel also includes: in the second time period t2, in the second shift register 2-2, the fifth unit 14 responds to the high level of the first clock terminal CKB and writes the low level of the low potential line VGL into the second node PA.

[0167] During the second time period t2, for the nth shift register 2(n), its first clock terminal CKB is high. The fifth unit 14 writes a low level to the second node PA(n), which works together with the second unit 10 to set the second node PA(n) low, thereby controlling the third unit 11 to turn off and stop charging the first output control node PU(n), so that the first output control node PU(n) can complete the bootstrap function normally during the second time period t2.

[0168] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 12This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 12 As shown, the display device includes the aforementioned display panel 100. Of course, Figures 7-10 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0169] Combination ​ As mentioned earlier, in the display panel, based on the design of the bias transfer module 7 of the shift register 2 in the gate drive circuit 1, the capacitor unit 8 can be charged using the first unit 9 before touch. This charging process does not involve the function of the first output control node PU(n), so there is no need to pull the first output control node PU(n) high before touch, thereby eliminating the extra bias voltage of the first output control node PU(n) before touch. Moreover, after the touch ends, by using the third unit 11 to control the high-time of the first output control node PU(n), the first output control node PU(n) will not have an extra bias voltage after touch. This panel design can eliminate the extra bias voltage of the first output control node PU(n) to a greater extent, so that the output signal delay of the stop-hole shift register will not change abruptly.

[0170] Therefore, when the display device includes the aforementioned display panel, the signal consistency output by the stop-level shift register and other conventional-level shift registers is better when the display device adopts the Long-H driving mode, which can effectively avoid the appearance of horizontal stripes and greatly improve the display quality of the display device.

[0171] As can be seen from the above embodiments, the display panel, its driving method, and the display device provided by the present invention achieve at least the following beneficial effects: The display panel provided by this invention includes a gate driving circuit, which includes multiple cascaded shift registers. Each shift register includes: an output module electrically connected to a first output control node, a first clock terminal, and an output terminal, used to write the signal from the first clock terminal to the output terminal in response to a signal from the first output control node; a first pull-down module electrically connected to a first control terminal, a first signal line, and the first output control node, used to write the signal from the first signal line to the first output control node in response to a signal from the first control terminal; and a bias transfer module including a capacitor unit, a first unit, a second unit, and a third unit. The capacitor unit is electrically connected between the first node and the second node. The first unit is electrically connected to the first control terminal, the second signal line, and the first node, used to write the signal from the second signal line to the first node in response to a signal from the first control terminal; the second unit is electrically connected to the first node, the third signal line, and the second node, used to write the signal from the third signal line to the second node in response to a signal from the first node; and the third unit is electrically connected to the second node, a fourth signal line, and the first output control node, used to write the signal from the fourth signal line to the first output control node in response to a signal from the second node.

[0172] The display panel provided by this invention can adopt a Long-H driving mode. The display process of one frame includes multiple line scanning periods. The shift register outputs a high level during the line scanning period, and a touch period is inserted between at least some of the adjacent line scanning periods.

[0173] The following explanation uses the example of a touch-enabled period that occurs between the row scan periods corresponding to the (n-1)th level shift register and the nth level shift register.

[0174] During the process of the (n-1)th stage shift register outputting a high level, the first control terminal connected to the first pull-down module in the nth stage shift register provides a high level, the first signal line provides a low level, and the second signal line provides a high level. In the nth stage shift register, the first pull-down module is enabled, writing the low level of the first signal line to the first output control node to prevent the first output control node from being pulled high additionally. Simultaneously, the first cell is enabled, writing the high level of the second signal line to the first node to charge the capacitor cell.

[0175] During the touch period, the first control terminal connected to the first pull-down module in the nth-level shift register is at a low level, and the capacitor unit in the nth-level shift register continues to store the potential.

[0176] After the touch period ends, both the third and fourth signal lines provide a high level. In the nth stage shift register, the signal on the third signal line jumps high. Based on the actions of the second unit and the capacitor unit, the first node bootstraps, and its potential is raised. The second unit writes the high level of the third signal line into the second node, charging the second node. The third unit responds to the high level of the second node by writing the high level of the fourth signal line into the first output control node.

[0177] In the above process, during the high-level output of the (n-1)th stage shift register before touch, the first pull-down module in the nth stage shift register sets the voltage of the first output control node low, and the first unit in the bias transfer module charges the capacitor unit, thus storing the voltage of the first output control node in the bias transfer module. After the touch ends, the bias transfer module releases it back to the first output control node, thereby preparing for the nth stage shift register to output a high level, so that the subsequent nth stage shift register can continue to output a high level, achieving the continuity of the effective output level of the subsequent shift registers.

[0178] Furthermore, in the bias transfer module of the present invention, before touch, the capacitor unit is charged using the first unit. This charging process does not involve the function of the first output control node. Therefore, there is no need to pull the first output control node high before touch, thus eliminating the additional bias voltage of the first output control node before touch. Moreover, after touch ends, by using the third unit to control the high-time of the first output control node, the first output control node will not have any additional bias voltage after touch.

[0179] In summary, this invention can eliminate the additional bias voltage of the first output control node to a greater extent, and the output signal delay of the stop-hole level shift register will not change abruptly. It can more effectively provide the signal consistency between the stop-hole level shift register and other conventional level shift registers, better improve the horizontal stripe phenomenon, and enhance the display quality.

[0180] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The circuit includes a gate drive circuit, which includes multiple cascaded shift registers; wherein the shift registers include: An output module is electrically connected to a first output control node, a first clock terminal, and an output terminal, and is used to respond to the signal of the first output control node and write the signal of the first clock terminal into the output terminal. The first pull-down module is electrically connected to the first control terminal, the first signal line and the first output control node, and is used to respond to the signal of the first control terminal and write the signal of the first signal line into the first output control node. A bias transfer module includes a capacitor unit, a first unit, a second unit, and a third unit. The capacitor unit is electrically connected between a first node and a second node. The first unit is electrically connected to a first control terminal, a second signal line, and the first node, and is used to write the signal from the second signal line to the first node in response to a signal from the first control terminal. The second unit is electrically connected to the first node, a third signal line, and the second node, and is used to write the signal from the third signal line to the second node in response to a signal from the first node. The third unit is electrically connected to the second node, a fourth signal line, and the first output control node, and is used to write the signal from the fourth signal line to the first output control node in response to a signal from the second node.

2. The display panel according to claim 1, characterized in that, In the two adjacent shift registers of the gate drive circuit, the first control terminal of the latter shift register is electrically connected to the output terminal of the former shift register. The driving cycle of the display panel includes a first time period, a second time period, and a touch time period between the first time period and the second time period; The shift register includes an adjacent first shift register and a second shift register. The first shift register outputs a high level during the first time period, and the second shift register outputs the high level during the second time period. During the first time period, the first signal line and the third signal line provide a low level, and the second signal line provides a high level; in the second shift register, the first pull-down module responds to the high level of the first control terminal by writing the low level of the first signal line into the first output control node, the first unit responds to the high level of the first control terminal by writing the high level of the second signal line into the first node, and the second unit responds to the high level of the first node by writing the low level of the third signal line into the second node; The driving cycle of the display panel also includes a third time period, which is located between the touch time period and the second time period; During the third time period, the third signal line and the fourth signal line provide a high level; in the second shift register, the first node is at a high level, the second unit responds to the high level of the first node by writing the high level of the third signal line into the second node, and the third unit responds to the high level of the second node by writing the high level of the fourth signal line into the first output control node.

3. The display panel according to claim 2, characterized in that, The shift register also includes a control module, which is electrically connected to the reset line, the low potential line and the first output control node; The driving cycle of the display panel further includes a fourth time period and a fifth time period, wherein the fourth time period is located between the first time period and the touch time period, and the fifth time period is located between the touch time period and the third time period; During the fourth time period, the reset line provides a high level, and at least in the first shift register, the control module responds to the high level of the reset line by writing the low level of the low potential line into the first output control node; During the fifth time period, the signal of the reset line transitions to the low level.

4. The display panel according to claim 3, characterized in that, The signal output by the second shift register jumps to the low level at the first moment, and the signal of the first output control node in the second shift register jumps to the low level at the second moment. There is a first time interval between the second moment and the first moment. The signal output by the first shift register jumps to the low level at the third time, and the signal of the reset line jumps to the high level at the fourth time, with a second time interval between the fourth time and the third time; The second time interval is equal to the first time interval.

5. The display panel according to claim 3, characterized in that, During the fourth time period, the signal on the second signal line transitions to the low level.

6. The display panel according to claim 3, characterized in that, During the fifth time period, the signal on the first signal line transitions to the high level.

7. The display panel according to claim 2, characterized in that, During the third time period, the signal of the third signal line changes from high level to low level, while during the second time period, the signal of the fourth signal line changes to the low level.

8. The display panel according to claim 2, characterized in that, The bias transfer module further includes a fourth unit, which is electrically connected to the second control terminal, the fifth signal line and the first node, and is used to respond to the signal of the second control terminal and write the signal of the fifth signal line into the first node. In the two adjacent shift registers of the gate drive circuit, the second control terminal of the previous shift register is electrically connected to the output terminal of the next shift register. The shift register also includes a third shift register adjacent to the second shift register, and the driving cycle of the display panel also includes a sixth period after the second period, during which the third shift register outputs the high level. During the sixth time period, the fifth signal line provides the low level, and in the second shift register, the fourth unit responds to the high level of the second control terminal by writing the low level of the fifth signal line into the first node.

9. The display panel according to claim 2, characterized in that, The bias transfer module further includes a fifth unit, which is electrically connected to the first clock terminal, the low potential line and the second node. During the second time period, in the second shift register, the fifth unit responds to the high level of the first clock terminal by writing the low level of the low potential line into the second node.

10. The display panel according to claim 1, characterized in that, The output module is also electrically connected to the second output control node and the low potential line, and is also used to respond to the signal of the second output control node by writing the low level of the low potential line into the output terminal; The shift register also includes: The first capacitor is electrically connected between the output terminal and the first output control node; The second capacitor is electrically connected between the first clock terminal and the second output control node; The second pull-down module is electrically connected to the second control terminal, the sixth signal line and the first output control node, and is used to respond to the signal of the second control terminal and write the signal of the sixth signal line into the first output control node. The control module is electrically connected to the reset line, the low potential line, the first output control node, and the second output control node, and is used to write signals to the first output control node and the second output control node.

11. A driving method for a display panel, characterized in that, The display panel includes a gate driving circuit, which includes a plurality of cascaded shift registers; wherein the shift registers include: The output module is electrically connected to the first output control node, the first clock terminal, and the output terminal. The first pull-down module is electrically connected to the first control terminal, the first signal line and the first output control node; The bias transfer module includes a capacitor unit, a first unit, a second unit, and a third unit; wherein the capacitor unit is electrically connected between a first node and a second node, the first unit is electrically connected to the first control terminal, a second signal line, and the first node, the second unit is electrically connected to the first node, a third signal line, and the second node, and the third unit is electrically connected to the second node, a fourth signal line, and the first output control node; The driving method for the display panel includes controlling the gate driving circuit to output a driving signal, wherein the operation of the shift register in the gate driving circuit includes: The first pull-down module responds to the signal from the first control terminal and writes the signal from the first signal line into the first output control node; The first unit responds to the signal from the first control terminal and writes the signal of the second signal line into the first node; the second unit responds to the signal from the first node and writes the signal of the third signal line into the second node; the third unit responds to the signal from the second node and writes the signal of the fourth signal line into the first output control node. The output module responds to the signal from the first output control node and writes the signal from the first clock terminal into the output terminal.

12. The driving method for a display panel according to claim 11, characterized in that, In the two adjacent shift registers of the gate drive circuit, the first control terminal of the latter shift register is electrically connected to the output terminal of the former shift register. The driving cycle of the display panel includes a first time period, a second time period, and a touch time period between the first time period and the second time period; The shift register includes an adjacent first shift register and a second shift register. The first shift register outputs a high level during the first time period, and the second shift register outputs the high level during the second time period. The driving method for the display panel includes: During the first time period, the first signal line and the third signal line provide a low level, and the second signal line provides a high level; in the second shift register, the first pull-down module responds to the high level of the first control terminal by writing the low level of the first signal line into the first output control node, the first unit responds to the high level of the first control terminal by writing the high level of the second signal line into the first node, and the second unit responds to the high level of the first node by writing the low level of the third signal line into the second node; The driving cycle of the display panel also includes a third time period, which is located between the touch time period and the second time period; The driving method for the display panel further includes: During the third time period, the third signal line and the fourth signal line provide a high level; in the second shift register, the first node is at a high level, the second unit responds to the high level of the first node by writing the high level of the third signal line into the second node, and the third unit responds to the high level of the second node by writing the high level of the fourth signal line into the first output control node.

13. The driving method for a display panel according to claim 12, characterized in that, The shift register also includes a control module, which is electrically connected to the reset line, the low potential line and the first output control node; The driving cycle of the display panel further includes a fourth time period and a fifth time period, wherein the fourth time period is located between the first time period and the touch time period, and the fifth time period is located between the touch time period and the third time period; The driving method for the display panel further includes: During the fourth time period, the reset line provides a high level, and at least in the first shift register, the control module responds to the high level of the reset line by writing the low level of the low potential line into the first output control node; During the fifth time period, the signal of the reset line transitions to the low level.

14. The driving method for a display panel according to claim 13, characterized in that, The signal output by the second shift register jumps to the low level at the first moment, and the signal of the first output control node in the second shift register jumps to the low level at the second moment. There is a first time interval between the second moment and the first moment. The signal output by the first shift register jumps to the low level at the third time, and the signal of the reset line jumps to the high level at the fourth time, with a second time interval between the fourth time and the third time; The second time interval is equal to the first time interval.

15. The driving method for a display panel according to claim 13, characterized in that, During the fourth time period, the signal of the second signal line transitions to the low level, and / or, during the fifth time period, the signal of the first signal line transitions to the high level.

16. The driving method for a display panel according to claim 12, characterized in that, During the third time period, the signal of the third signal line changes from high level to low level; during the second time period, the signal of the fourth signal line changes to the low level.

17. The driving method for a display panel according to claim 12, characterized in that, The bias transfer module further includes a fourth unit, which is electrically connected to the second control terminal, the fifth signal line and the first node, and is used to respond to the signal of the second control terminal and write the signal of the fifth signal line into the first node. In the two adjacent shift registers of the gate drive circuit, the second control terminal of the previous shift register is electrically connected to the output terminal of the next shift register. The shift register also includes a third shift register adjacent to the second shift register, and the driving cycle of the display panel also includes a sixth period after the second period, during which the third shift register outputs the high level. The driving method for the display panel further includes: during the sixth time period, the fifth signal line provides the low level, and in the second shift register, the fourth unit responds to the high level of the second control terminal by writing the low level of the fifth signal line into the first node.

18. The driving method for a display panel according to claim 12, characterized in that, The bias transfer module further includes a fifth unit, which is electrically connected to the first clock terminal, the low potential line and the second node. The driving method for the display panel further includes: during the second time period, in the second shift register, the fifth unit responds to the high level of the first clock terminal and writes the low level of the low potential line into the second node.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 10.

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