Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a substrate and a word line structure. The substrate includes a source / drain region. The word line structure is disposed in the substrate and adjacent to the source / drain region. The character line structure comprises a character line metal layer, a covering layer, a first sealing layer and a first air gap. The capping layer is disposed on the word line metal layer. The first sealing layer is disposed between the word line metal layer and the capping layer. The first air gap is disposed between the word line metal layer and the first sealing layer. According to the semiconductor structure comprising the word line structure with the air gap and the manufacturing method of the semiconductor structure, parasitic capacitance can be effectively reduced.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor structure and a method of manufacturing a semiconductor structure. More particularly, the present invention relates to a semiconductor structure having an air gap and a method of manufacturing the same. BACKGROUND

[0002] Dynamic random access memories (DRAMs) can provide more storage cells per unit wafer area than other types of memory (e.g., static random access memories (SRAMs)) due to their simple structure. A dynamic random access memory is composed of a plurality of DRAM cells, where each dynamic random access memory cell includes a capacitor to store information and a transistor coupled to the capacitor to regulate when the capacitor is charged or discharged. During a read operation, a word line (WL) is asserted, turning on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor through a bit line (BL). During a write operation, the data to be written is provided on the bit line while the word line is asserted.

[0003] To meet the demand for greater storage capacity, the size of dynamic random access memory storage cells continues to shrink, resulting in a significant increase in the packing density of these dynamic random access memories. However, as the size of DRAM storage cells is continually reduced, the problem of capacitive coupling becomes increasingly prominent, resulting in increased parasitic capacitance. As a result, the read and write speed of the DRAM storage cells is reduced, which in turn negatively impacts the overall performance of the device.

[0004] The discussion of background art does not constitute an admission that any of the art SUMMARY

[0005] One aspect of the present invention provides a semiconductor structure including a substrate and a word line structure. The substrate includes a source / drain region. The word line structure is disposed in the substrate and adjacent to the source / drain region. The word line structure includes a word line metal layer, a capping layer, a first encapsulation layer, and a first air gap. The capping layer is disposed on the word line metal layer. The first encapsulation layer is disposed between the word line metal layer and the capping layer. The first air gap is disposed between the word line metal layer and the first encapsulation layer.

[0006] In some embodiments, a bottom of the source / drain region is lower than a top surface of the word line metal layer.

[0007] In some embodiments, the word line structure further comprises an insulating layer surrounding the word line metal layer, the cap layer, the first sealing layer, and the first air gap.

[0008] In some embodiments, the first air gap is between the insulating layer and the word line metal layer.

[0009] In some embodiments, the first sealing layer has a flat surface.

[0010] In some embodiments, the word line metal layer has a lower portion and an upper portion on the lower portion, and the upper portion has a trapezoidal profile.

[0011] In some embodiments, the upper portion is surrounded by the first air gap.

[0012] In some embodiments, a bottom of the first air gap is flush with a bottom of the source / drain region.

[0013] In some embodiments, the first sealing layer further extends upward and surrounds the cap layer.

[0014] In some embodiments, the first sealing layer has a thickness between 5 nm and 10 nm.

[0015] In some embodiments, the semiconductor structure further comprises a polysilicon layer, a second sealing layer, and a second air gap. The polysilicon layer is disposed between the first sealing layer and the cap layer. The second sealing layer is disposed between the polysilicon layer and the cap layer. The second air gap is disposed between the polysilicon layer and the second sealing layer.

[0016] In some embodiments, the second sealing layer has a thickness between 5 nm and 10 nm.

[0017] In some embodiments, a bottom of the second air gap is flush with a bottom of the source / drain region.

[0018] In some embodiments, the polysilicon layer has a lower portion and an upper portion on the lower portion, and the upper portion has a trapezoidal profile.

[0019] In some embodiments, the second sealing layer has a flat surface.

[0020] Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes the following steps. A source / drain region is formed in a substrate. A trench is formed in the substrate. An insulating layer is formed in the trench to cover an inner surface of the trench. A wordline metal layer is formed in the trench and on the insulating layer. An upper portion of a sidewall of the wordline metal layer is removed to form a first recess. A first sealing layer is formed on the wordline metal layer such that the first recess is sealed to form a first air gap. A capping layer is formed on the first sealing layer.

[0021] In some embodiments, forming the first sealing layer on the wordline metal layer further includes forming the first sealing layer to cover the insulating layer.

[0022] In some embodiments, the method further includes the following steps. Before forming the capping layer on the first sealing layer, a polysilicon layer is formed on the first sealing layer. A top portion of a sidewall of the polysilicon layer is removed to form a second recess. A second sealing layer is formed on the polysilicon layer such that the second recess is sealed to form a second air gap.

[0023] In some embodiments, forming the wordline metal layer in the trench and on the insulating layer includes: conformally depositing a metal nitride layer in the trench and on the insulating layer; forming a metal layer in the trench and on the metal nitride layer; and recessing the metal nitride layer and the metal layer.

[0024] In some embodiments, a material of the first sealing layer is the same as a material of the capping layer, and a parameter of forming the first sealing layer is different from a parameter of forming the capping layer.

[0025] Accordingly, the parasitic capacitance between the bitline structure and the adjacent conductive element (e.g., the bitline structure and / or the capacitor contact) can be reduced. As a result, the overall performance of the device can be improved, and the yield of the semiconductor device structure can also be increased.

[0026] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the present application, as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0027] The present application can be more fully understood with reference to the following detailed description when read in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a schematic cross-sectional view of a semiconductor structure according to a comparative example of the present disclosure.

[0029] Figure 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

[0030] Figure 3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure.

[0031] Figure 4 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention.

[0032] Figures 5 to 8 is a schematic cross-sectional view of an intermediate stage of manufacturing a word line structure according to various embodiments of the present invention. DETAILED DESCRIPTION

[0033] Embodiments or examples of the disclosure shown in the drawings are described in specific language. It is to be understood that the invention is not intended to be limited to the specific embodiments described. Any alterations and / or modifications of the described embodiments, and any further applications of the principles of the described embodiments are contemplated with respect to the scope and spirit of the invention. Element(s) shown in the drawings can be repeated in each embodiment, but even if they have the same element number, features in one embodiment are not necessarily used in another embodiment.

[0034] It is to be understood that the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers or sections, however, these elements, components, regions, layers or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Therefore, a first element, component, region, layer or section described below can be called a second element, component, region, layer or section without departing from the teachings of the inventive concept of the present invention.

[0035] As used herein, the singular forms "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be understood that the term "comprises" as used in the specification, particularly in the claims, specifies the presence of stated features, integers, steps, operations, elements, or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0036] Due to the simplicity of the structure, dynamic random access memories (DRAMs) can provide more memory cells per unit wafer area than other types of memory such as static random access memories (SRAMs). A DRAM is composed of a plurality of DRAM cells, each including a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line (WL) is asserted, turning on the transistor. The turned-on transistor allows a sense amplifier to read the voltage across the capacitor through a bit line (BL). During a write operation, data to be written is provided on the BL when the WL is asserted.

[0037] To meet the increasing demand for memory storage, the size of DRAM memory cells continues to shrink, significantly increasing the packaging density of these DRAMs. However, the shrinking size requirements of DRAM memory cells have led to an increasing problem of capacitive coupling due to parasitic capacitance. For example, as the spacing between adjacent word lines continues to decrease, parasitic capacitance between word lines can become an issue. Consequently, the speed of DRAM memory cells decreases, negatively impacting the overall performance of the device.

[0038] According to some embodiments of the present invention, a semiconductor structure embodiment is provided. This semiconductor structure includes a word line structure with an air gap. Therefore, by employing an air gap with a low dielectric constant, the parasitic capacitance between word line structures and / or between a word line structure and a capacitor junction can be reduced, thereby improving the operating speed of the semiconductor device.

[0039] Figure 1 This is a schematic cross-sectional view of a semiconductor structure 10 according to a comparative example of the present invention. The semiconductor structure 10 includes a gapless word line structure 110 disposed in a substrate 120 and a source / drain region 130 disposed in the substrate 120 and adjacent to the word line structure 110.

[0040] It is understood that the word line structure is used to control the switching state of channels during DRAM operation. Generally, the word line structure 110 includes a word line metal layer 112, which is surrounded by an insulating layer 114, and a source / drain region 130 adjacent to the word line structure 110. Due to the relatively large overlap area between the word line metal layer 112 and the source / drain region 130, the parasitic capacitance between the word line metal layer 112 and the source / drain region 130 is relatively high, thus affecting the retention time of the DRAM cell.

[0041] To address the aforementioned problems, this invention provides embodiments of semiconductor structures that can effectively reduce parasitic capacitance. In this disclosure, semiconductor structure generally refers to a structure capable of operating using semiconductor characteristics, and optoelectronic devices, light-emitting display devices, semiconductor circuits, and electronic devices all fall within the scope of semiconductor structures.

[0042] Figure 2This is a schematic cross-sectional view of a semiconductor structure 20 according to an embodiment of the present invention. The semiconductor structure 20 includes a substrate 220 and a word line structure 210. Specifically, the substrate 220 includes source / drain regions 230, and the word line structure 210 is disposed in the substrate 220 and adjacent to the source / drain regions 230. The semiconductor structure 20 can be applied to, for example, a cell array of dynamic random access memory (DRAM), but the present invention is not limited thereto.

[0043] According to one example embodiment, the disclosed semiconductor structure 20 is formed on one or more wafers made of semiconductor material, wherein the semiconductor structure is constructed or formed thereon by conventional semiconductor manufacturing techniques, including but not limited to photolithography, such as applying a photoresist layer, patterning the photoresist layer, developing, etching, planarizing and cleaning the photoresist layer, to apply a pattern / structure in a given layer. For completeness, the following is a general description of the semiconductor manufacturing process.

[0044] Generally, photoresist layers can be applied using methods such as spin coating, spray coating, roll coating, dip coating, or extrusion coating. Typically, in spin coating, the substrate 220 is placed on a rotating platen, which may include a vacuum chuck for securing the substrate 220 to the plate. The photoresist composition is then applied to the center of the substrate 220. The speed of the rotating platen is then increased to distribute the photoresist evenly from the center of the substrate 220 to its periphery. The rotation speed of the platen is then fixed to control the final thickness of the photoresist layer.

[0045] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, the baking temperature is approximately 90°C to 110°C. Baking can be performed using a heating plate, oven, or similar equipment. Finally, a photoresist layer is formed on substrate 220.

[0046] The photoresist layer is then patterned by radiation exposure. The radiation can be any wavelength of light with the desired masking pattern. In a particular embodiment, EUV light with a wavelength of about 13.5 nm is used for patterning because this allows for a smaller feature size. This results in some portions of the photoresist layer being exposed to radiation while others are not. This exposure causes some portions of the photoresist to be soluble in the developer, while others are insoluble.

[0047] An additional photoresist baking step (post-exposure bake, or PEB) may be performed after photoresist exposure. For example, this may help release acid leaving groups (ALGs) or other molecules that play an important role in chemically amplified photoresists.

[0048] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. The soluble portions of the photoresist layer dissolve and are washed away during the development step, leaving the photoresist pattern. A common example of a developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developing agents may include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate, propylene glycol monomethyl ether acetate, n-pentyl acetate, n-butyl propionate, n-hexyl acetate, n-butylbutyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propylisobutyrate, or isobutyl... (propionate). Generally, any suitable developer can be used. Sometimes, post-development baking or "hard baking" can be performed to stabilize the developed photoresist pattern, thereby obtaining optimal performance in subsequent steps.

[0049] Continuing, a portion of the layer beneath the patterned photoresist layer is now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. Afterward, the patterned photoresist layer can be removed, for example, using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other strippers at high temperatures, or by dry etching using oxygen plasma.

[0050] Generally, any etching step used in this article can be performed using wet etching, dry etching, or plasma etching processes, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or a combination of both (as the case may be). Etching can be anisotropic. Depending on the material, etchants can include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), carbon fluorides, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), and hydrofluoric acid. Hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), or similar substances, or combinations thereof in various proportions. For example, silicon dioxide can be wet-etched with hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can also be dry-etched with various mixtures of CHF3, O2, CF4, and / or H2.

[0051] Planarization can be performed to obtain a flat surface. For example, planarization can be achieved using a chemical mechanical polishing (CMP) process. Typically, CMP is performed using a rotating platen with polishing pads mounted on it. The substrate 220 is fixed on a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pads or the wafer substrate. During polishing, both the polishing pads and the carrier rotate, which creates mechanical and chemical effects on the surface of the wafer substrate and / or its top layer, removing unwanted material and forming a highly flat surface. A post-CMP cleaning step is then performed, using a rotating brush and cleaning solution to clean one or both sides of the wafer substrate.

[0052] Finally, cleaning steps, such as wet cleaning, can be performed between each process step. The cleaning solution depends on the etching formulation and the exposed layer. Examples of cleaning solutions include deionized water, dilute hydrofluoric acid (HF), and other conventional solutions.

[0053] In some embodiments, substrate 220 may be a semiconductor wafer, such as a silicon wafer. Alternatively, substrate 220 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0054] In some embodiments, substrate 220 includes an epitaxial layer. For example, substrate 220 has an epitaxial layer covering a bulk semiconductor. In some embodiments, substrate 220 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer covering the substrate, and a semiconductor layer covering the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated by separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0055] To manufacture integrated circuits (ICs) and / or IC wafers, lines are first scribed onto a substrate to mark multiple semiconductor wafer regions between wafer areas. The substrate then undergoes a series of cleaning, stacking, patterning, etching, and doping steps to ultimately form the integrated circuit.

[0056] In some embodiments, substrate 220 may further include an isolation structure (not shown). According to some embodiments, this isolation structure is shallow trench isolation (STI). Furthermore, the isolation structure may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials, and the formation of the isolation structure may include: forming a patterned mask (not shown) on substrate 220; etching substrate 220 using the patterned mask to form an opening (not shown); depositing a dielectric material within the opening and on substrate 220; and polishing the dielectric material until substrate 220 is exposed.

[0057] In some embodiments, substrate 220 includes at least two source / drain regions 230 adjacent to word line structures 210. The source / drain regions 230 include source / drain regions 230a and 230b. According to some embodiments, bit lines (not shown) are electrically connected to source / drain regions 230a via conductive vias (not shown) and conductive contacts (not shown). In this embodiment, semiconductor structure 20 is dynamic random access memory (DRAM), and source / drain regions 230b are electrically connected to individual capacitors (not shown).

[0058] In some embodiments, source / drain regions 230 (e.g., source / drain regions 230a and 230b) can be formed by one or more ion implantation processes, whereby a P-type dopant (e.g., boron (B), gallium (Ga), or indium (In)) or an N-type dopant (e.g., phosphorus (P) or arsenic (As)) can be implanted into the substrate 220 to form the source / drain regions 230. In this invention, source / drain region 230 may refer to either a source or a drain, depending on the context, either individually or jointly. Sources and drains are used interchangeably, and their structures are substantially the same.

[0059] Please continue reading. Figure 2 The character line structure 210 includes a character line metal layer 212, a cover layer 214, a first sealing layer 216, a first air gap 217, and an insulating layer 218. More specifically, the cover layer 214 is disposed on the character line metal layer 212. The first sealing layer 216 is disposed between the character line metal layer 212 and the cover layer 214. The first air gap 217 is disposed between the character line metal layer 212 and the first sealing layer 216. The character line metal layer 212 and the substrate 220 are separated by the insulating layer 218. In some embodiments, the insulating layer 218 surrounds the character line metal layer 212, the cover layer 214, the first sealing layer 216, and the first air gap 217. In some embodiments, the first air gap 217 is disposed between the insulating layer 218 and the character line metal layer 212.

[0060] The material of the insulating layer 218 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant (high k) dielectric material, or a combination thereof. Furthermore, the insulating layer 218 may be formed by a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-coating, or other suitable processes.

[0061] The character line metal layer 212 may include a conductive material. Any conductive material discussed herein can generally be any conductive metal or conductive oxide. Suitable examples of metals include copper (Cu), aluminum (Al), nickel (Ni), chromium (Cr), gold (Au), germanium (Ge), silver (Ag), titanium (Ti), tungsten (W), platinum (Pt), tantalum (Ta), ruthenium (Ru), cobalt (Co), rhenium (Re), palladium (Pd), or zirconium (Zr); composite materials such as TiN, WN, or TaN; or alloys thereof, such as AlCu. Suitable examples of conductive oxides include indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO), aluminum-zinc oxide (AlZnO), indium oxide (InO), or cadmium oxide (CdO). Metallic or oxide materials can be deposited by evaporation or sputtering, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods. In other embodiments, the character line metal layer 212 may comprise a single layer or multiple layers. In some embodiments, the character line metal layer 212 has a lower portion 212a and an upper portion 212b situated above the lower portion 212a, and the upper portion 212b has a trapezoidal profile. In some embodiments, the upper portion 212b is surrounded by a first air gap 217.

[0062] The materials of the capping layer 214 and the first sealing layer 216 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Furthermore, the capping layer 214 and the first sealing layer 216 can each be formed by a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-coating, or other suitable processes. However, the deposition process parameters for forming the capping layer 214 differ from those for forming the first sealing layer 216. In some embodiments, the first sealing layer 216 has a flat surface. In some embodiments, the thickness of the first sealing layer 216 is 5 nanometers to 10 nanometers.

[0063] Furthermore, the character line structure 210 can be formed by patterning and deposition processes. In some embodiments, the character line structure 210 is formed after the source / drain region 230. In some embodiments, the bottom 230c of the source / drain region 230 is lower than the top surface 212s of the character line metal layer 212. In some embodiments, the bottom of the first air gap 217 is substantially flush with the bottom 230c of the source / drain region 230.

[0064] To facilitate comparison with the above embodiments and to simplify the explanation, the same symbols are used to label the same elements in the following embodiments, and the explanation mainly focuses on the differences between the embodiments, without repeating the same parts.

[0065] Figure 3 This is a schematic cross-sectional view of a semiconductor structure 30 according to another embodiment of the present invention. The difference between semiconductor structure 30 and semiconductor structure 20 is that the first sealing layer 316 of semiconductor structure 30 extends further upward and surrounds the cover layer 214.

[0066] Figure 4 This is a schematic cross-sectional view of a semiconductor structure 40 according to yet another embodiment of the present invention. The difference between semiconductor structure 40 and semiconductor structure 30 is that semiconductor structure 40 further includes a polysilicon layer 412, a second sealing layer 416, and a second air gap 417. Specifically, the polysilicon layer 412 is disposed between the first sealing layer 216 and the capping layer 214. The second sealing layer 416 is disposed between the polysilicon layer 412 and the capping layer 214. The second air gap 417 is disposed between the polysilicon layer 412 and the second sealing layer 416. Furthermore, the second sealing layer 416 may extend further upward and surround the capping layer 214.

[0067] In some embodiments, the thickness of the second sealing layer 416 is 5 nanometers to 10 nanometers. In some embodiments, the bottom of the second air gap 417 is flush with the bottom 230c of the source / drain region 230. In some embodiments, the polysilicon layer 412 has a lower portion 412a and an upper portion 412b located above the lower portion 412a, and the upper portion 412b has a trapezoidal profile. In some embodiments, the upper portion 412b is surrounded by the second air gap 417. In some embodiments, the second sealing layer 416 has a substantially flat surface.

[0068] Another aspect of the present invention is to provide a method for manufacturing a semiconductor structure 20. This method includes the following steps: First, a source / drain region 230 is formed in a substrate 220, such as... Figure 1 As shown. Next, the character line structure 210 is formed in the substrate 220 and located between the two source / drain regions 230, as shown. Figure 2 As shown.

[0069] Figures 5 to 8 This is a schematic cross-sectional view of an intermediate stage in the manufacturing of a character line structure according to various embodiments of the present invention. The specific method for forming the character line structure 210 is as follows: Figures 5 to 8 As shown. See also Figure 5 First, a trench 510 is formed in the substrate 220. Then, an insulating layer 218 is formed in the trench 510 to cover the inner surface of the trench 510, thereby defining the opening 520 by the insulating layer 218.

[0070] Then, a character line metal layer 212 is formed in the trench 510 and on the insulating layer 218. More specifically, the character line metal layer 212 is formed in the opening 520 and on the insulating layer 218. In some embodiments, forming the character line metal layer 212 in the opening 520 includes conformally depositing a metal nitride layer 2121 in the opening 520 and on the insulating layer 218; forming a metal layer 2122 in the opening 520 and on the metal nitride layer 2121; and recessing the metal nitride layer 2121 and the metal layer 2122.

[0071] The metal layer 2122 may include copper (Cu), aluminum (Al), nickel (Ni), chromium (Cr), gold (Au), germanium (Ge), silver (Ag), titanium (Ti), tungsten (W), platinum (Pt), tantalum (Ta), ruthenium (Ru), cobalt (Co), rhenium (Re), palladium (Pd), zirconium (Zr), or combinations thereof.

[0072] See Figure 6 The upper portion of the sidewall of the character line metal layer 212 is removed to form the first recess 530. In some embodiments, the first recess 530 may be formed by any suitable etching step, such as wet etching, dry etching, or plasma etching processes.

[0073] See Figure 7 Then, a first sealing layer 216 is formed on the word line metal layer 212, sealing the first recess 530 to form a first air gap 217. Since the first air gap 217 is filled with air, its dielectric constant is much lower than that of a capping layer 214, such as one composed of silicon nitride. Accordingly, the first air gap 217 can significantly reduce the parasitic capacitance between the bottom contacts of the high-level bit lines (and / or the bottom contacts of the high-level capacitors) and the word line metal layer 212 of the word line structure 210. In other words, the first air gap 217 can significantly mitigate the interference effect between the electrical signal applied to the bottom contacts of the high-level bit lines (and / or the bottom contacts of the high-level capacitors) and the word line metal layer 212 of the word line structure 210.

[0074] In some embodiments, forming a first sealing layer 216 on the character line metal layer 212 further includes forming a first sealing layer 216 to cover the insulating layer 218. In other words, the first sealing layer 216 extends further upward and contacts the insulating layer 218. The step of removing the first sealing layer 216 that contacts the insulating layer 218 is optional.

[0075] See Figure 8 A covering layer 214 is formed on the first sealing layer 216, thereby forming a... Figure 2 The semiconductor structure 20 is shown. In some embodiments, the material of the first sealing layer 216 is the same as that of the capping layer 214, and the parameters for forming the first sealing layer 216 are different from those for forming the capping layer 214. For example, the deposition rate of the first sealing layer 216 is faster than that of the capping layer 214.

[0076] In other embodiments, a polysilicon layer 412 is formed on the first sealing layer 216 before the capping layer 214 is formed on it. Next, the top of the sidewalls of the polysilicon layer 412 is removed to form a second recess (not shown). A second sealing layer 416 is formed on the polysilicon layer 412, sealing the second recess to form a second air gap 417. Finally, a capping layer 214 is formed on the second sealing layer 416, thereby forming a... Figure 4 The semiconductor structure 40 shown.

[0077] Therefore, the present invention provides a semiconductor structure including a word line structure with an air gap and a method for manufacturing the same, which can effectively reduce parasitic capacitance. More specifically, it can reduce the parasitic capacitance between the bit line structure and adjacent conductive elements (e.g., bit line structures and / or capacitor contacts). This improves the overall performance of the device and increases the yield of the semiconductor device structure.

[0078] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0079] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from its scope or spirit. In view of the foregoing, the present invention is intended to cover modifications and variations falling within the appended claims.

[0080] [Symbol Explanation] 10: Semiconductor Structure 20: Semiconductor Structure 30: Semiconductor Structure 40: Semiconductor Structure 110: Character line structure 112: Character line metal layer 114: Insulation layer 120: Substrate 130: Source / Drain Region 210: Character Line Structure 212: Character line metal layer 2121: Metal nitride layer 2122: Metal layer 212a: Lower part 212b: Upper part 212s: Top surface 214: Overlay 216: First sealing layer 217: First air gap 218: Insulation layer 220: Substrate 230: Source / Drain Region 230a: Source / Drain Region 230b: Source / Drain Region 230c: Bottom 316: First sealing layer 412: Polycrystalline silicon layer 412a : lower part 412b : upper part 416: Second sealing layer 417: Second air gap 510: Trench 520: Opening 530: First depression.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, including source / drain regions; as well as A character line structure is disposed in the substrate and adjacent to the source / drain region, wherein the character line structure includes: Character line metal layer; An overlay layer is disposed on the metal layer of the character line; A first sealing layer is disposed between the character line metal layer and the cover layer; and The first air gap is located between the character line metal layer and the first sealing layer.

2. The semiconductor structure of claim 1, wherein the bottom of the source / drain region is lower than the top surface of the word line metal layer.

3. The semiconductor structure according to claim 1, wherein the character line structure further includes an insulating layer surrounding the character line metal layer, the cover layer, the first sealing layer, and the first air gap.

4. The semiconductor structure according to claim 3, wherein the first air gap is located between the insulating layer and the character line metal layer.

5. The semiconductor structure according to claim 1, wherein the first sealing layer has a flat surface.

6. The semiconductor structure of claim 1, wherein the character line metal layer has a lower portion and an upper portion located on the lower portion, and the upper portion has a trapezoidal profile.

7. The semiconductor structure of claim 6, wherein the upper portion is surrounded by the first air gap.

8. The semiconductor structure of claim 1, wherein the bottom of the first air gap is flush with the bottom of the source / drain region.

9. The semiconductor structure of claim 1, wherein the first sealing layer extends further upward and surrounds the cover layer.

10. The semiconductor structure of claim 1, wherein the first sealing layer has a thickness between 5 nanometers and 10 nanometers.

11. The semiconductor structure according to claim 1, wherein, Further includes: A polycrystalline silicon layer is disposed between the first sealing layer and the cover layer; A second sealing layer is disposed between the polysilicon layer and the cover layer; and The second air gap is disposed between the polysilicon layer and the second sealing layer.

12. The semiconductor structure of claim 11, wherein the second sealing layer has a thickness between 5 nanometers and 10 nanometers.

13. The semiconductor structure of claim 11, wherein the bottom of the second air gap is flush with the bottom of the source / drain region.

14. The semiconductor structure of claim 11, wherein the polysilicon layer has a lower portion and an upper portion located on the lower portion, and the upper portion has a trapezoidal profile.

15. The semiconductor structure of claim 11, wherein the second sealing layer has a flat surface.

16. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Source / drain regions are formed in the substrate; Trenches are formed in the substrate; An insulating layer is formed in the trench to cover the inner surface of the trench; A character line metal layer is formed in the trench and on the insulating layer; Remove the upper part of the sidewall of the character line metal layer to form the first recess; A first sealing layer is formed on the character line metal layer, thereby sealing the first recess to form a first air gap; and A covering layer is formed on the first sealing layer.

17. The method of claim 16, wherein forming the first sealing layer on the character line metal layer further comprises forming the first sealing layer to cover the insulating layer.

18. The method according to claim 16, wherein, Further includes: Before forming the cover layer on the first sealing layer, a polysilicon layer is formed on the first sealing layer; Remove the top of the sidewall of the polysilicon layer to form a second recess; and A second sealing layer is formed on the polysilicon layer, thereby sealing the second recess to form a second air gap.

19. The method of claim 16, wherein forming the character line metal layer in the trench and on the insulating layer comprises: A metal nitride layer is conformally deposited in the trench and on the insulating layer; A metal layer is formed in the trench and on the metal nitride layer; as well as The metal nitride layer and the metal layer are recessed.

20. The method of claim 16, wherein the material of the first sealing layer is the same as the material of the covering layer, and the parameters for forming the first sealing layer are different from the parameters for forming the covering layer.

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